WO2022046055A1

WO2022046055A1 - Latency durations of peripheral devices

Info

Publication number: WO2022046055A1
Application number: PCT/US2020/048143
Authority: WO
Inventors: Tsue-Yi HUANG; Chia-Cheng Lin; Kang-Ning Feng; Shao-Yu CHIANG
Original assignee: Hewlett-Packard Development Company, L.P.
Priority date: 2020-08-27
Filing date: 2020-08-27
Publication date: 2022-03-03

Abstract

In some examples, a host device comprises a first controller having a first latency duration and a second controller coupled to the first controller. The second controller is to receive data from an electronic device coupled to the host device, the data indicating a type of a peripheral device coupled to the electronic device. The second controller is to replace the first latency duration with a second latency duration based on the data. The first and second latency durations are indicative of respective delays that are to elapse prior to servicing signals received from the electronic device. The second latency duration is shorter than the first latency duration.

Description

LATENCY DURATIONS OF PERIPHERAL DEVICES

BACKGROUND

[0001] A battery-operated host device may perform any of a variety of actions to preserve battery life. For example, the host device may be programmed with a particular latency duration, which determines how long the host device may wait before servicing a signal (e.g., an interrupt signal) received from a peripheral device connected to the host device. Battery life may be preserved by longer latency durations and may be diminished by shorter latency durations.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Various examples will be described below referring to the following figures:

[0003] FIG. 1 is a schematic diagram of a system for adjusting a latency duration of a peripheral device in accordance with various examples;

[0004] FIG. 2 is a schematic diagram of a host device for adjusting a latency duration of a peripheral device in accordance with various examples;

[0005] FIG. 3 is a schematic diagram of a host device for adjusting a latency duration of a peripheral device in accordance with various examples; and

[0006] FIG. 4 is a schematic diagram of a host device for adjusting a latency duration of a peripheral device in accordance with various examples.

DETAILED DESCRIPTION

[0007] As described above, to preserve battery life, a host device may be programmed with a relatively long latency duration. The latency duration may be a Latency Tolerance Reporting (LTR) duration, for example. Although relatively long latency durations help to preserve battery life, they can often result in a diminished user experience. For instance, when a peripheral device (e.g., a full high definition (FHD) Universal Serial Bus (USB) camera) is connected to the host device (either directly or through a docking station), the peripheral device may send signals to the host device and may expect the host device to rapidly service those signals. With a long latency duration, however, the host device may take an undesirably long time to service the signals from the peripheral device. For example, an audio controller in the host device may have been programmed with a relatively long latency duration, and in response to a user headset being connected to the host device, the audio controller may instruct a central processing unit (CPU) of the host device to wait an undesirably long time before servicing signals from the headset. As a result of this undesirable delay in servicing the signals from the peripheral device, the user experience is diminished.

[0008] Such delays may be compounded even further by latency durations that are so long that they allow the CPU to enter a low-power mode (e.g., a sleep mode) due to low activity levels. When the CPU is in such a low-power mode, signals from the peripheral device are serviced even more slowly than when the CPU is not in a low-power mode because the CPU may not be able to service the signals until it has exited the low-power mode and resumed normal operations. Attempting to improve the user experience by indiscriminately decreasing the latency duration is also disadvantageous, as this may result in a higher rate of battery drain.

[0009] This disclosure describes examples of a host device that dynamically adjusts a latency duration in response to a peripheral device, such as a highspeed peripheral device, being connected to the host device, either directly or indirectly (e.g., through an electronic device such as a docking station). In particular, in response to a peripheral device being connected to the host device, the host device may determine what type of peripheral device has been connected; store, for later use, a first latency duration present in a register of a device controller for the peripheral device; and then adjust the first latency duration in the register to a second latency duration. The type of peripheral device may indicate a function performed by the peripheral device (e.g., input device, output device, storage device), a particular form of the peripheral device (e.g., touch screen device, audio device, mouse, keyboard, display device), a method by which the peripheral device couples to another electronic device (e.g., USB, Thunderbolt), or a speed of the peripheral device (e.g., high speed). In some examples, the second latency duration may be a programmed latency duration that prevents the CPU from entering the low-power mode. After the peripheral device has been disconnected from the host device, the host device may re-write the register with the first latency duration and discard the second latency duration. [0010] By adjusting a latency duration in this manner, the experience for the user of the peripheral device is improved because signals from the peripheral device to the CPU are serviced quickly. In addition, the user experience is further improved because decreasing the latency duration of a device controller prevents the CPU from entering a low-power mode while the peripheral device is connected to and communicating with the host device. In addition to improving the user experience, the host device described herein continues to preserve battery life because it includes a selective and dynamic adjustment (e.g., reduction) to a latency duration when doing so would result in an improved user experience. By adjusting latency durations selectively and dynamically instead of indiscriminately and permanently, battery life is still preserved. For example, the host device may decrease the latency duration in the register of an audio controller but may leave the latency durations in other device controllers (e.g., USB controller, local area network (LAN) controller) unchanged, thus preserving battery life while making a temporary accommodation for a high-speed headset peripheral device. Battery life preservation is further improved by restoring the prior latency duration, as described above, in response to the peripheral device being disconnected from the host device.

[0011] In one example in accordance with the present disclosure, a host device is provided. The host device comprises a first controller having a first latency duration; and a second controller coupled to the first controller. The second controller is to receive data from an electronic device coupled to the host device. The data indicates a type of a peripheral device coupled to the electronic device. The second controller is to replace the first latency duration with a second latency duration based on the data. The first and second latency durations are indicative of respective delays that are to elapse prior to servicing signals received from the electronic device. The second latency duration is shorter than the first latency duration.

[0012] In another example, a non-transitory computer-readable medium is provided. The non-transitory computer-readable medium stores computer- readable instructions. When executed by a first controller of a host device, the computer-readable instructions cause the first controller to determine a type of a peripheral device coupled to the host device, store a first latency duration of a second controller for the peripheral device, replace the first latency duration of the second controller with a second latency duration based on the type, and, after a signal from the peripheral device has been serviced, replace the second latency duration of the second controller with the stored first latency duration.

[0013] In another example, a host device is provided. The host device comprises a first controller and a second controller coupled to the first controller. The second controller is to determine a type of a peripheral device coupled to the host device and to replace a first latency duration of the first controller with a second latency duration based on the type. The second latency duration is indicative of a delay that is to elapse prior to servicing a signal received from the peripheral device. The first latency duration is sufficiently long to allow a processor of the host device to enter a low-power mode and the second latency duration is sufficiently short to prevent the processor from entering the low-power mode.

[0014] Referring now to FIG. 1 , a schematic diagram of a system 100 for adjusting a latency duration of a peripheral device is depicted, in accordance with various examples. The system 100 comprises a host device 102, an electronic device 104, and a peripheral device 106. The host device 102 may be a notebook, laptop, tablet, smartphone, wearable electronic device, or other electronic computing device, for example. The electronic device 104 may be a docking station, a hub, a cable converter, or another suitable device for coupling a host device to a peripheral device. The electronic device 104 may facilitate communication between the host device 102 and the peripheral device 106. In some examples, the host device 102 may be communicate with the electronic device 104 or the peripheral device 106 wirelessly utilizing BLUETOOTH®, WIFI®, or utilizing any other suitable wireless technology standard. In other examples, the host device 102 may communicate with the electronic device 104 or the peripheral device 106 utilizing a cable (e.g., universal serial bus (USB), Ethernet, or any other suitable wired technology standard). [0015] In various examples, the host device 102 comprises a communication bus 126 coupled to a processor 108, a storage device 110, controllers 112, 114, 116, and 118. Ports 120 and 122 and a wireless transceiver 124 couple to the controller 112. The communication bus 126 facilitates the communication of data between components that are coupled to the communication bus 126. The communication bus 126 may be Inter-Integrated Circuit (I2C), Peripheral Component Interconnect Express (PCI-E®), or any other suitable bus that allows data transfers, for example.

[0016] The processor 108 and the controllers 112, 114, 116, 118 may each be a microprocessor, a microcomputer, a microcontroller, a programmable integrated circuit, a programmable gate array, or another suitable device for controlling operations of a component or multiple components, for example. The processor 108 may be the central processing unit (CPU) of the host device 102, for example. In some examples, the controller 112 may be a controller for a communications bus. The communications bus may be the communications bus 126, for example. The bus may be I2C, PCI-E®, or any other suitable bus that allows data transfers, for example. The controller 112 may be a PCI-E controller. In other examples, the controllers 112, 114, 116, 118 may each be a device controller for a different type of peripheral device. For example, the controller 114 may control a USB device, the controller 116 may control an audio device, and the controller 118 may control a storage device. In another example, the controller 112 may be an embedded controller of a wireless transceiver module (not expressly shown) that includes the wireless transceiver 124. In another example, the controller 112 may be a USB Power Delivery (PD) controller. The wireless transceiver 124 transmits and receives signals. The wireless transceiver 124 may transmit or receive signals from the electronic device 104 or the peripheral device 106, for example.

[0017] The storage device 110 may include a hard drive, solid state drive (SSD), flash memory, random access memory (RAM), or other suitable memory. In some examples, the storage device 110 may store the computer-readable instructions 132. The computer-readable instructions 132, when executed by the processor 108, may cause the processor 108 to perform some or all of the actions attributed herein to the processor 108. In some examples, the controller 112 includes an embedded processor 128 and a storage device 130. The storage device 130 may store the computer-readable instructions 134. The computer- readable instructions 134, when executed by the embedded processor 128, may cause the embedded processor 128 to perform some or all of the actions attributed herein to the controller 112.

[0018] In various examples, the electronic device 104 comprises a controller 136 coupled to a wireless transceiver 138 and ports 140, 142, and 144. The controller 136 may be a microprocessor, a microcomputer, a microcontroller, a programmable integrated circuit, a programmable gate array, or another suitable device for controlling operations of a component or multiple components, for example. In some examples, the controller 136 may be a controller for a communication bus carrying data transferred to and from the ports 140, 142, 144 and the wireless transceiver 138. For example, the controller 136 may be a PCI-E controller. In other examples, the controller 136 may be a device controller for a peripheral device. For example, the controller 136 may be a USB Power Delivery (PD) controller. In another example, the controller 136 may be an embedded controller of a wireless transceiver module (not expressly shown) that includes the wireless transceiver 138. The wireless transceiver 138 transmits and receives signals. The wireless transceiver 138 may transmit or receive signals from the host device 102 or the peripheral device 106, for example. In some examples, the controller 136 includes an embedded processor 146 and a storage device 148. The storage device 148 may store the computer-readable instructions 150. The computer-readable instructions 150, when executed by the embedded processor 146, may cause the embedded processor 146 to perform some or all of the actions attributed herein to the controller 136.

[0019] As discussed above, in some examples, the host device 102 dynamically adjusts a latency duration in response to the peripheral device 106 being connected to the electronic device 104. In some examples, the peripheral device 106 may be coupled to the host device 102 utilizing the port 120, the port 122, or the wireless transceiver 124. In other examples, the peripheral device 106 may be coupled to the electronic device 104 utilizing the port 140, the port 142, the port 144, or the wireless transceiver 138, and, in turn, the electronic device 104 may be coupled to the host device 102 utilizing the port 120, the port 122, or the wireless transceiver 124. In response to the peripheral device 106 being coupled, either directly or indirectly, to the host device 102, the controller 112 of the host device 102 may determine what type of peripheral device has been connected, store a first latency duration present in a register for a device controller for the peripheral device (e.g., controller 114, controller 116, controller 118) for later use, and then adjust (e.g., decrease) the first latency duration in the register to a second latency duration. The controller 112 may determine the type based on data received from the electronic device 104, based on a port to which the peripheral device is connected, or based on a signal received from the peripheral device 106, for example. The register may be stored on the storage device 110 or a storage device of the device controller. The second latency duration may be a programmed latency duration that is sufficiently short so that it prevents the processor 108 from entering a low-power mode. In some examples, instead of saving the register value before updating the register, the controller 112 may notify the basic input/output system (BIOS) that the register is to be updated and provide the relevant value(s), and the BIOS may save the register value, update the register, and subsequently re-write the register using the saved register value. [0020] As used herein, a basic input/output system (BIOS) refers to hardware or hardware and instructions to initialize, control, or operate a computing device prior to execution of an operating system (OS) of the computing device. Instructions included within a BIOS may be software, firmware, microcode, or other programming that defines or controls functionality or operation of a BIOS. The instructions may be stored on the storage device 110, for example. In one example, a BIOS may be implemented using instructions, such as platform firmware of a computing device, executable by the processor 108. A BIOS may operate or execute prior to the execution of the OS of a computing device. A BIOS may initialize, control, or operate components such as hardware components of a computing device and may load or boot the OS of computing device. In some examples, a BIOS may provide or establish an interface between hardware devices or platform firmware of the computing device and an OS of the computing device, via which the OS of the computing device may control or operate hardware devices or platform firmware of the computing device. In some examples, a BIOS may implement the Unified Extensible Firmware Interface (UEFI) specification or another specification or standard for initializing, controlling, or operating a computing device.

[0021] In various examples, after the peripheral device 106 has been disconnected from the host device 102 (e.g., from one of the ports 120, 122, or after the peripheral device 106 has ceased communicating wirelessly with the wireless transceiver 124 for a programmed threshold amount of time), the controller 112 may re-write the register with the first latency duration and discard the second latency duration. For example, an audio controller of the host device 102 may include a register storing a latency duration of 10 milliseconds (ms), which may be too large for a high-speed peripheral such as a headset. Thus, upon connection of a headset to the host device 102, the controller 112 may store the 10 ms latency duration for later use and then re-write the audio controller register with a 2 ms latency duration. This 2 ms latency duration may cause the processor 108 to service signals from the headset more quickly, thus resulting in an improved user experience. After the headset is disconnected from the host device 102, the 2 ms latency duration is discarded from the register and the register is re-written with the 10 ms latency duration. By adjusting the latency duration as described above, the host device 102 may improve the user experience by quickly servicing signals from the peripheral device 106 and by preventing the processor 108 from entering a low-power mode while the peripheral device 106 is connected to and communicating with the host device 102. By rewriting the register value to a higher latency duration after the peripheral device 106 is disconnected, the host device 102 preserves battery life.

[0022] Referring now to FIG. 2, a schematic diagram of the host device 102 for adjusting a latency duration of a peripheral device is depicted, in accordance with various examples. The peripheral device may be the peripheral device 106, for example. As discussed above with respect to FIG. 1 , the host device 102 may include the controllers 112, 114, 116, 118 coupled to the communications bus 126. The controller 112 may include the embedded processor 128 and the storage device 130. The storage device 130 may store the computer-readable instructions 200 and 202. The computer-readable instructions 200, 202 may be the computer-readable instructions 134, for example. The computer-readable instructions 200, 202, when executed by the embedded processor 128, may cause the embedded processor 128 to perform some or all of the actions attributed herein to the controller 112.

[0023] In various examples, when executed by the embedded processor 128, the computer-readable instructions 200, 202 cause the controller 112 to replace a latency duration based on a type of a peripheral device coupled to an electronic device that is coupled to the host device 102. The peripheral device may be the peripheral device 106, for example. The electronic device may be the electronic device 104, for example. For example, the computer-readable instruction 200 may cause the controller 112 to receive data from the electronic device 104, the data indicating a type of the peripheral device 106 coupled to the electronic device 104. The computer-readable instruction 202 may cause the controller 112 to replace a first latency duration of a device controller with a second latency duration based on the data. The device controller may be the controller 114, 116, or 118, for example. The first and second latency durations are indicative of respective delays that are to elapse prior to servicing signals received from the electronic device 104.

[0024] In some examples, the second latency duration is shorter than the first latency duration. For example, in response to the data indicating the peripheral device 106 is a high-speed type of peripheral device, the second latency duration may be set to a programmed latency duration that is sufficiently short to prevent the processor 108 from entering a low-power mode. In other examples, the second latency duration is longer than the first latency duration. For example, in response to the data indicating no peripheral device is coupled to the electronic device 104, the second latency duration may be set to a programmed latency duration that is sufficiently long to allow the processor 108 to enter a low-power mode.

[0025] In various examples, the electronic device 104 may transmit data indicating types for multiple peripheral devices coupled to the electronic device 104. For example, the electronic device 104 may transmit a table of data indicating a type of peripheral device for multiple peripheral devices. In response to the data, the controller 112 may replace a latency duration of a device controller associated with each type of peripheral device based on the data. For example, the electronic device 104 may transmit a table indicating that a first and a third type of peripheral devices are high-speed peripheral devices and a second type of peripheral device is not a high-speed peripheral device. In response to the data, the controller 112 may replace a latency duration of the device controller 114 and 118 with the second latency duration and may not be able to replace a latency duration of the device controller 116, for example.

[0026] In some examples, the electronic device 104 may transmit data indicating a Latency Tolerance Reporting (LTR) duration for the type of the peripheral device. In various examples, the controller 112 may utilize the LTR duration as the second latency duration. In other examples, the controller 112 may determine whether the LTR duration is less than a programmed latency duration that is sufficiently short to prevent the processor 108 from entering a low- power mode. In response to the LTR duration being less than the programmed latency duration, the controller 112 may set the second latency duration to the LTR duration. In response to the LTR duration being greater than the programmed latency duration, the controller 112 may set the second latency duration to the programmed latency duration.

[0027] By adjusting the latency duration from a first latency duration to a second latency duration that is less than the first latency duration, the controller 112 may improve the user experience by quickly servicing signals from a high-speed peripheral device and preventing the processor 108 from entering a low-power mode while the high-speed peripheral device is connected to and communicating with the electronic device 104. Additionally, by adjusting the latency duration from a first latency duration to a second latency duration that is greater than the first latency duration, the controller 112 preserves battery life.

[0028] FIG. 3 depicts a schematic diagram of a host device 300 for adjusting a latency duration of a peripheral device 302 in accordance with various examples. The host device 300 may be the host device 102, for example. The peripheral device 302 may be the peripheral device 106, for example. The host device 300 may comprise a controller 304, a storage device 306, a port 308 (e.g., for coupling to the peripheral device 302), a wireless transceiver 310 (e.g., for communicating with the peripheral device 302), and a device controller 312 coupled to a communications bus 314. The controllers 304 and 312 may each be a microprocessor, a microcomputer, a microcontroller, a programmable integrated circuit, a programmable gate array, or another suitable device for controlling operations of a component or multiple components, for example. The controller 304 may be the processor 108 or the controller 112, for example. In another example, the controller 304 may be an embedded controller of a wireless transceiver module (not expressly shown) that includes the wireless transceiver 310. In another example, the controller 312 may be a device controller for a type of peripheral device. For example, the controller 312 may be for a Thunderbolt type peripheral device, for a local area network (LAN) type peripheral device, or for a USB type peripheral device. The controller 312 may be the controller 114, 116, or 118, for example. The wireless transceiver 310 transmits and receives signals. The wireless transceiver 310 may transmit or receive signals from an electronic device (not expressly shown) or the peripheral device 302, for example. The storage device 306 may be a non-transitory computer-readable medium. The non-transitory computer-readable medium may include any electronic, magnetic, optical, or other physical storage device for storing information such as computer-readable instructions and data. The storage device 306 may be the storage device 110 or 130, for example. In some examples, the storage device 306 may store the computer-readable instructions 316, 318, 320, and 322. The computer-readable instructions 316, 318, 320, 322 may be the computer- readable instructions 132 or 134, for example. The computer-readable instructions 316, 318, 320, 322, when executed by the controller 304, may cause the controller 304 to perform some or all of the actions attributed herein to the controller 304.

[0029] In various examples, when executed by the controller 304, the computer- readable instructions 316, 318, 320, 322 cause the controller 304 to replace a latency duration based on a type of the peripheral device 302 coupled to the host device 300. For example, the computer-readable instruction 316 may cause the controller 304 to determine a type of the peripheral device 302 coupled to the host device 300 (e.g., via a physical connection to the port 308 or a wireless connection to the wireless transceiver 310). The computer-readable instruction 318 may cause the controller 304 to store a first latency duration of a device controller for the peripheral device 302. The device controller for the peripheral device 302 may be the device controller 312, for example. The controller 304 may store the first latency duration on the storage device 306 or on a storage device of the device controller for the peripheral device 302, for example. The computer- readable instruction 320 may cause the controller 304 to replace the first latency duration of the device controller with a second latency duration based on the type. The computer-readable instruction 322 may cause the controller 304 to, after a signal from the peripheral device 302 has been serviced, replace the second latency duration of the device controller with the stored first latency duration.

[0030] In various examples, the computer-readable instructions may cause the controller 304 to determine the peripheral device 302 has been removed (e.g., is no longer coupled) from the host device 300. For example, the peripheral device 302 may no longer be coupled to the port 308 or may no longer be wirelessly communicating with the wireless transceiver 310 (e.g., a lack of communication for a programmed threshold length of time). In response to the determination, the computer-readable instructions may case the controller 304 to replace the second latency duration of the device controller with the stored first latency duration. In some examples, the computer-readable instructions may cause the controller 304 to notify a BIOS of the host device 300 each time the latency duration is replaced. [0031] In various examples, the computer-readable instructions may cause the controller 304 to determine a second type of a second peripheral device (not expressly shown) coupled to the host device 300. The computer-readable instructions may cause the controller 304 to store a third latency duration of a device controller (not expressly shown) for the second peripheral device. The computer-readable instructions may cause the controller 304 to replace the third latency duration of the device controller for the second peripheral device with a fourth latency duration based on the second type. In some examples, the fourth latency duration is the same as the second latency duration. In other examples, the fourth latency duration is different than the second latency duration and the fourth and the second latency durations are sufficiently short to prevent the host device 300 from entering a low-power mode.

[0032] By adjusting the latency duration, the host device 300 may improve the user experience for a high-speed peripheral device 302 by quickly servicing signals from the peripheral device 302. The user experience is further improved because decreasing the latency duration of the high-speed peripheral device controller (e.g., controller 312) prevents the host device 300 from entering a low- power mode while the high-speed peripheral device 302 is connected to and communicating with the host device 300. Additionally, the host device 300 preserves battery life by selectively and dynamically adjusting the latency duration to enable the host device 300 to enter a low-power mode when the highspeed peripheral device 302 is no longer coupled to the host device 300.

[0033] FIG. 4 depicts a schematic diagram of the host device 102 for adjusting a latency duration of a peripheral device, in accordance with various examples. The host device 102 may be the host device 300, for example. The peripheral device may be the peripheral device 106 or 302, for example. As described above with respect to FIGS. 1 and 3, the host device 102 may include the controllers 112, 114, 116, 118 coupled to the communications bus 126. The controller 112 may also couple to the communications bus 126 and may include the embedded processor 128 and the storage device 130. The storage device 130 may be the storage device 306, for example. The storage device 130 may store the computer-readable instructions 400 and 402. The computer-readable instructions 400, 402 may be the computer-readable instructions 134, for example. The computer-readable instructions 400, 402, when executed by the embedded processor 128, may cause the embedded processor 128 to perform some or all of the actions attributed herein to the controller 112.

[0034] In various examples, when executed by the embedded processor 128, the computer-readable instructions 400, 402 cause the controller 112 to replace a latency duration based on a type of a peripheral device coupled to the host device 102. For example, the computer-readable instruction 400 may cause the controller 112 to determine a type of a peripheral device coupled to the host device 102. The computer-readable instruction 402 may cause the controller 112 to replace a first latency duration of a device controller for the peripheral device with a second latency duration based on the type, where the first latency duration is longer than the second latency duration. The device controller for the peripheral device may be the device controller 114, 116, or 118, for example. The second latency duration is indicative of a delay that is to elapse prior to servicing a signal received from the peripheral device. The first latency duration is sufficiently long to allow the processor 108 to enter a low-power mode, and the second latency duration is sufficiently short to prevent the processor 108 from entering the low- power mode.

[0035] By adjusting a latency duration as described above, a host device may improve the experience for the user of a high-speed peripheral device by quickly servicing signals from the peripheral device. The user experience is further improved because decreasing the latency duration of the high-speed peripheral device controller prevents the CPU from entering a low-power mode while the high-speed peripheral device is connected to and/or communicating with the host device. Additionally, the host device described herein preserves battery life by selectively and dynamically adjusting a latency duration.

[0036] The above discussion is meant to be illustrative of the principles and various examples of the present disclosure. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

[0037] In the figures, certain features and components disclosed herein may be shown exaggerated in scale or in somewhat schematic form, and some details of certain elements may not be shown in the interest of clarity and conciseness. In some of the figures, in order to improve clarity and conciseness, a component or an aspect of a component may be omitted. [0038] In the above discussion and in the claims, the term "comprising" is used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to...." Also, the term "couple" or "couples" is intended to be broad enough to encompass both indirect and direct connections. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices, components, and connections. As used herein, including in the claims, the word “or” is used in an inclusive manner. For example, “A or B” means any of the following: “A” alone, “B” alone, or both “A” and “B.”

Claims

What is claimed is: A host device, comprising: a first controller having a first latency duration; and a second controller coupled to the first controller, the second controller to: receive data from an electronic device coupled to the host device, the data indicating a type of a peripheral device coupled to the electronic device; and replace the first latency duration with a second latency duration based on the data, the first and second latency durations indicative of respective delays that are to elapse prior to servicing signals received from the electronic device, the second latency duration shorter than the first latency duration. The host device of claim 1 , wherein the second controller is to: receive second data from the electronic device, the second data indicating the peripheral device is removed from the electronic device; and replace the second latency duration with the first latency duration. The host device of claim 1 , comprising: a third controller having a third latency duration, and wherein the second controller is to: receive second data from the electronic device, the second data indicating a type of a second peripheral device coupled to the electronic device; and replace the third latency duration with the second latency duration based on the second data, the second latency duration shorter than the third latency duration.

4. The host device of claim 1 , wherein the data indicates a Latency Tolerance Reporting (LTR) duration for the type of the peripheral device, and wherein the LTR duration is the second latency duration.

5. The host device of claim 1 , wherein the data indicates a Latency Tolerance Reporting (LTR) duration for the type of the peripheral device, and wherein the second controller is to: determine whether the LTR duration is less than a programmed latency duration, the programmed latency duration sufficiently short to prevent a processor of the host device from entering a low-power mode; and set the second latency duration to the LTR duration in response to the LTR duration being less than the programmed latency duration and set the second latency duration to the programmed latency duration in response to the LTR duration being more than the programmed latency duration.

6. A non-transitory computer-readable medium storing computer-readable instructions which, when executed by a first controller of a host device, cause the first controller to: determine a type of a peripheral device in communication with the host device; store a first latency duration of a second controller for the peripheral device; replace the first latency duration of the second controller with a second latency duration based on the type; and after a signal from the peripheral device has been serviced, replace the second latency duration of the second controller with the stored first latency duration. 18

7. The non-transitory computer-readable medium of claim 6, wherein the computer-readable instructions, when executed by the first controller, cause the first controller to: determine that the peripheral device is disconnected from the host device; and replace the second latency duration of the second controller with the stored first latency duration.

8. The non-transitory computer-readable medium of claim 6, wherein the second latency duration is shorter than the first latency duration.

9. The non-transitory computer-readable medium of claim 6, wherein the computer-readable instructions, when executed by the first controller, cause the first controller to replace the second latency duration of the second controller with the stored first latency duration responsive to a determination that the peripheral device has not wirelessly communicated with the host device for a threshold amount of time.

10. The non-transitory computer-readable medium of claim 6, wherein the computer-readable instructions, when executed by the first controller, cause the first controller to: determine a second type of a second peripheral device coupled to the host device; store a third latency duration of a third controller for the second peripheral device; and replace the third latency duration of the third controller with a fourth latency duration based on the second type. 19

11. A host device, comprising: a first controller; and a second controller coupled to the first controller, the second controller to: determine a type of a peripheral device coupled to the host device; and replace a first latency duration of the first controller with a second latency duration based on the type, the second latency duration indicative of a delay that is to elapse prior to servicing a signal received from the peripheral device, wherein the first latency duration is longer than the second latency duration.

12. The host device of claim 11 , comprising: a third controller; and wherein the second controller is to: determine a second type of a second peripheral device coupled to the host device; and replace a third latency duration of the third controller with the second latency duration based on the second type.

13. The host device of claim 11 , comprising: a third controller; and wherein the second controller is to: determine a second type of a second peripheral device coupled to the host device; and replace a third latency duration of the third controller with a fourth latency duration based on the second type, the fourth latency duration having a different duration than the second latency duration.

14. The host device of claim 13, wherein the type of the peripheral device is different than the second type of the second peripheral device. 20

15. The host device of claim 13, wherein the fourth latency duration is sufficiently short to prevent a processor from entering a low-power mode.