WO2013140985A1 - Hall sensor - Google Patents

Hall sensor Download PDF

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Publication number
WO2013140985A1
WO2013140985A1 PCT/JP2013/055429 JP2013055429W WO2013140985A1 WO 2013140985 A1 WO2013140985 A1 WO 2013140985A1 JP 2013055429 W JP2013055429 W JP 2013055429W WO 2013140985 A1 WO2013140985 A1 WO 2013140985A1
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hall
impurity region
voltage
depletion layer
type impurity
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French (fr)
Japanese (ja)
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孝明 飛岡
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セイコーインスツル株式会社
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
    • G01R33/06—Measuring direction or magnitude of magnetic fields or magnetic flux using galvano-magnetic devices
    • G01R33/07—Hall effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00—Hall-effect devices
    • H10N52/101—Semiconductor Hall-effect devices

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  • the present invention relates to a semiconductor Hall sensor, and relates to a Hall sensor with high sensitivity and capable of removing an offset voltage.
  • an output voltage is generated even when no magnetic field is applied.
  • the voltage output when the magnetic field is 0 is referred to as an offset voltage.
  • the cause of the offset voltage is considered to be due to an imbalance in potential distribution inside the device such as mechanical stress applied to the device from the outside or misalignment during the manufacturing process.
  • the method for compensating the offset voltage is generally performed by the following method.
  • the Hall element 100 has a symmetrical shape, and has four terminals T1, T2, T3, and T4 that allow a control current to flow through a pair of input terminals and obtain an output voltage from the other pair of output terminals.
  • the other pair of terminals T3 and T4 is a Hall voltage output terminal.
  • Vh + Vos is generated at the output terminal.
  • Vh represents a Hall voltage proportional to the magnetic field of the Hall element
  • Vos represents an offset voltage.
  • the hall element is represented by an equivalent circuit shown in FIG.
  • the Hall element is represented as a bridge circuit in which four terminals are connected by four resistors R1, R2, R3, and R4. As described above, the offset voltage is canceled by subtracting the output voltage when a current is passed in two directions.
  • Vouta (R2 * R4-R1 * R3) / (R1 + R4) / (R2 + R3) * Vin Is output.
  • Voutb (R1 * R3-R2 * R4) / (R3 + R4) / (R1 + R2) * Vin Is output.
  • Vouta-Voutb (R1-R3) * (R2-R4) * (R2 * R4-R1 * R3) / (R1 + R4) / (R2 + R3) / (R3 + R4) / (R1 + R2) * Vin It becomes. Therefore, the offset voltage can be offset canceled even when the resistors R1, R2, R3, and R4 of the equivalent circuits are different. However, when the values of the resistors R1, R2, R3, and R4 change depending on the current application direction and the applied voltage, the above equation does not hold, and therefore offset cancellation cannot be performed.
  • FIG. 5 is a cross-sectional view of a general Hall element (see, for example, Patent Document 1).
  • a peripheral portion of the N-type impurity region that becomes the Hall element magnetic sensing portion is surrounded by a P-type impurity region for isolation.
  • a depletion layer spreads at the boundary between the Hall element magnetic sensing part and its peripheral part. Since no hole current flows in the depletion layer, the hole current is suppressed and the resistance increases in the region where the depletion layer extends.
  • the depletion layer width depends on the applied voltage. Therefore, since the values of the resistors R1, R2, R3, and R4 of the equivalent circuit shown in FIG. 4 change depending on the voltage application direction, the magnetic offset cannot be canceled by the offset cancel circuit.
  • the depletion layer width can be controlled by the depletion layer control electrode, and the offset voltage can be removed by using the offset cancel circuit.
  • the depletion layer control electrode since a plurality of depletion layer control electrodes are used and a complicated control circuit is required, there is a problem that the chip size increases and the cost increases.
  • an object of the present invention is to provide a Hall sensor in which the depletion layer width is difficult to change and the offset voltage can be removed without using a complicated control circuit.
  • the present invention has the following configuration.
  • the Hall sensor is characterized in that the control current flowing in the Hall element can be separated and flown from the junction between the Hall element magnetic sensing portion, which is an N-type impurity region, and the peripheral portion of the P-type substrate.
  • the Hall sensor is characterized in that the first N-type impurity region which is a depletion layer suppression region is deeper than the second N-type impurity region of the magnetic sensing portion and has a low concentration.
  • control current input terminal and the hall voltage output terminal are the hall sensors characterized by having the same depth as the hall magnetic sensing part.
  • the Hall sensor is characterized in that the offset voltage can be removed by spinning current.
  • the control current flowing in the Hall element can flow separately from the junction between the Hall element magnetic sensing part which is an N-type impurity region and the peripheral part of the P-type substrate. For this reason, the depletion layer is prevented from extending into the Hall element magnetic sensing portion, and the resistance between the terminals does not change depending on the applied voltage and its direction. Therefore, the offset voltage can be removed by the spinning current.
  • the depletion layer suppression region is placed under the Hall element magnetic sensing part, the resistance voltage change due to the depletion layer can be suppressed without using a depletion layer suppression electrode or a complicated circuit, eliminating the offset voltage. It is possible to reduce the chip size and the cost.
  • FIG. 1 It is a figure which shows the structure of the Hall element of this invention.
  • (A) is a top view and
  • (B) is a side view. It is a figure for demonstrating the principle of an ideal Hall effect. It is a figure for demonstrating the removal method of the offset voltage by a spinning current. It is a figure of the equivalent circuit for demonstrating the offset voltage of a Hall element. It is a figure of the cross-sectional structure of a general Hall element.
  • FIG. 1 is a diagram showing the configuration of the Hall element of the present invention.
  • the second N-type impurity region 121 having a square shape with a side of 50 to 150 ⁇ m has a magnetic sensing portion having a lower impurity concentration than the second N-type impurity region 121 below the magnetic sensing portion.
  • the depletion layer suppression region of one N-type impurity region 122 and the control current input terminal and Hall voltage output terminals 11, 12, 13, and 14 of the N-type high concentration impurity region are provided at each apex thereof.
  • the N-type impurity region of the magnetic sensing portion has a depth of about 300 to 500 nm, the impurity concentration is 1 ⁇ 10 16 (atoms / cm 3 ) ⁇ N ⁇ 5 ⁇ 10 16 (atoms / cm 3 ), and is a depletion layer suppression region.
  • 2 N-type impurity region 121 has a depth of about 2 to 3 ⁇ m, a concentration of 8 ⁇ 10 14 (atoms / cm 3 ) ⁇ N ⁇ 3 ⁇ 10 15 (atoms / cm 3 ), a control current input terminal and a hall voltage output terminal
  • the depth of the high-concentration N-type impurity region is preferably about 300 nm. That is, the depletion layer suppression region is deeper than the magnetic sensing portion, and the impurity concentration is lowered.
  • the control current input terminal and the Hall voltage output terminal have the same depth as the Hall magnetic sensor.
  • the control current can be passed to the Hall magnetic sensing portion without being affected by the depletion layer generated at the junction between the depletion layer suppressing region and the P-type substrate region in the periphery thereof. Therefore, when the Hall voltage output terminals are 11, 13 and the control current input terminals are 12, 14, the resistance value between the terminals and the Hall voltage output terminals are 12, 14, and the control current input terminals are 11, 13. The resistance value between the terminals is constant. Thereby, the offset voltage can be erased by the spinning current.
  • a first N-type impurity region 122 serving as a depletion layer suppressing layer is formed on a P-type substrate.
  • the first N-type impurity region 122 had a depth of 2 to 3 ⁇ m and an impurity concentration of 8 ⁇ 10 14 (atoms / cm 3 ) ⁇ N ⁇ 3 ⁇ 10 15 (atoms / cm 3 ). This is the same concentration and depth as the n-well.
  • the first N-type impurity region 122 is used as a depletion layer suppression region, even if the manufacturing variation of the n-well is large, the sensitivity and other characteristics of the Hall element are not affected. Therefore, it can be formed in common with n-wells of other elements.
  • the first N-type impurity region 122 has a depth of 300 to 500 nm and a concentration of 1 ⁇ 10 16 (atoms / cm 3 ) ⁇ N ⁇ 5 ⁇ 10 16 (atoms / cm 3 ).
  • the impurity region having this depth and concentration can be formed by a normal ion implantation apparatus, and variation in concentration and depth can be made smaller than that of the n well.
  • the Hall element sensing part By forming the Hall element sensing part by ion implantation, a Hall element having a small variation in sensitivity is formed.
  • the high-concentration impurity region that becomes a control current input terminal and a Hall voltage output terminal is formed.
  • the high-concentration impurity region has a depth of 300 nm, and can be formed in common without requiring a separate process from other elements.
  • a square magnetic sensing portion, a depletion layer suppression region, and a Hall element shape having a control current input terminal and a Hall voltage output terminal at each vertex thereof are taken as an example, but the shape is not limited thereto.
  • Any symmetrical Hall element having a control current input terminal and a Hall voltage output terminal in a high concentration impurity region and having a shape capable of erasing an offset voltage due to spinning current may be used.
  • the first N-type impurity region of the cross-shaped depletion layer suppressing region inclined by 45 °, the second N-type impurity region of the Hall element magnetic sensing portion, and the hole current of the N-type high-concentration impurity region at each end thereof can be obtained even when the control electrode and the Hall voltage output terminal are arranged other than the square shape.
  • the structure as shown in FIG. 1 eliminates the need for a complicated circuit or a complicated structure, and it is not necessary to add a special process.
  • the influence of the depletion layer on the control current is suppressed, and the spinning current is used.
  • An offset voltage can be erased, a chip size is small, and an inexpensive Hall sensor can be realized.

Abstract

A Hall sensor readily produced and capable of readily removing off-set voltage, without increasing chip size, as a result of having a magnetically sensitive receptor for a square or cross-shaped second n-type impurity region, and a control current input terminal and a Hall voltage output terminal for n-type high-density impurity regions at a first n-type impurity region for a depletion layer suppressing layer and at each peak and end section thereof.

Description

ホールセンサHall sensor
　本発明は、半導体ホールセンサに関し、高感度でかつ、オフセット電圧の除去が可能なホールセンサに関する。 The present invention relates to a semiconductor Hall sensor, and relates to a Hall sensor with high sensitivity and capable of removing an offset voltage.
　ホール素子の磁気検出原理について説明する。物質中に流れる電流に対して垂直な磁界を印加するとその電流と磁界の双方に対して垂直な方向に電界（ホール電圧）が生じる。 The magnetic detection principle of the Hall element will be explained. When a magnetic field perpendicular to the current flowing in the material is applied, an electric field (Hall voltage) is generated in a direction perpendicular to both the current and the magnetic field.
　図３のようなホール素子を考えたとき、ホール素子磁気感受部１の幅Ｗ、長さＬ、電子移動度μ、電流を流すための電源２の印加電圧Ｖｄｄ、印加磁場をＢとしたとき、電圧計３から出力されるホール電圧は
ＶＨ＝μＢ（Ｗ／Ｌ）Ｖｄｄ
とあらわされ、このホール素子の磁気感度Ｋｈは、
Ｋｈ＝μ（Ｗ／Ｌ）Ｖｄｄ
と表される。この関係式より高感度化するための方法の１つはＷ／Ｌ比を大きくすることであることがわかる。 When considering the Hall element as shown in FIG. 3, when the width W, the length L, the electron mobility μ, the applied voltage Vdd of the power source 2 for flowing current, and the applied magnetic field are B, the Hall element magnetic sensing unit 1 The Hall voltage output from the voltmeter 3 is VH = μB (W / L) Vdd
It is expressed that the magnetic sensitivity Kh of this Hall element is
Kh = μ (W / L) Vdd
It is expressed. From this relational expression, it can be seen that one of the methods for increasing the sensitivity is to increase the W / L ratio.
　一方、実際のホール素子では磁界が印加されていないときでも、出力電圧が生じている。この磁場０のときに出力される電圧をオフセット電圧という。オフセット電圧が生じる原因は、外部から素子に加わる機械的な応力や製造過程でのアライメントずれなどの素子内部の電位分布の不均衡によるものであると考えられている。 On the other hand, in the actual Hall element, an output voltage is generated even when no magnetic field is applied. The voltage output when the magnetic field is 0 is referred to as an offset voltage. The cause of the offset voltage is considered to be due to an imbalance in potential distribution inside the device such as mechanical stress applied to the device from the outside or misalignment during the manufacturing process.
　オフセット電圧を補償する方法は、一般的に以下の方法で行っている。 The method for compensating the offset voltage is generally performed by the following method.
　図３に示すようなスピニングカレントによるオフセットキャンセル回路である。ホール素子１００は対称的な形状で、１対の入力端子に制御電流を流し、他の１対の出力端子から出力電圧を得る４端子Ｔ１、Ｔ２、Ｔ３、Ｔ４を有している。ホール素子の一方の一対の端子Ｔ１、Ｔ２が制御電流入力端子となる場合、他方の一対の端子Ｔ３、Ｔ４がホール電圧出力端子となる。このとき、入力端子に電圧Ｖｉｎを印加すると、出力端子には出力電圧Ｖｈ＋Ｖｏｓが発生する。ここでＶｈはホール素子の磁場に比例したホール電圧、Ｖｏｓはオフセット電圧を示している。次に、Ｔ３、Ｔ４を制御電流出力端子、Ｔ１、Ｔ２をホール電圧出力端子として、Ｔ３、Ｔ４間に入力電圧Ｖｉｎを印加すると、出力端子に電圧－Ｖｈ＋Ｖｏｓが発生する。 This is an offset cancellation circuit with spinning current as shown in FIG. The Hall element 100 has a symmetrical shape, and has four terminals T1, T2, T3, and T4 that allow a control current to flow through a pair of input terminals and obtain an output voltage from the other pair of output terminals. When one pair of terminals T1 and T2 of the Hall element is a control current input terminal, the other pair of terminals T3 and T4 is a Hall voltage output terminal. At this time, when the voltage Vin is applied to the input terminal, an output voltage Vh + Vos is generated at the output terminal. Here, Vh represents a Hall voltage proportional to the magnetic field of the Hall element, and Vos represents an offset voltage. Next, when the input voltage Vin is applied between T3 and T4 using T3 and T4 as control current output terminals and T1 and T2 as Hall voltage output terminals, a voltage −Vh + Vos is generated at the output terminal.
　以上の２方向に電流を流したときの出力電圧を減算することによりオフセット電圧Ｖｏｓはキャンセルされ、磁場に比例した出力電圧２Ｖｈを得ることができる。 By subtracting the output voltage when the current flows in the above two directions, the offset voltage Vos is canceled and an output voltage 2Vh proportional to the magnetic field can be obtained.
　しかし、このオフセットキャンセル回路でオフセット電圧を完全にキャンセルすることができない。その理由を以下で説明する。 However, this offset cancel circuit cannot cancel the offset voltage completely. The reason will be described below.
　ホール素子は、図４に示す等価回路で表される。ホール素子は、４つの端子を、４つの抵抗Ｒ１、Ｒ２、Ｒ　３、Ｒ４で接続したブリッジ回路として表される。前記のとおり２方向に電流を流したときの出力電圧を減算することによりオフセット電圧をキャンセルする。 The hall element is represented by an equivalent circuit shown in FIG. The Hall element is represented as a bridge circuit in which four terminals are connected by four resistors R1, R2, R3, and R4. As described above, the offset voltage is canceled by subtracting the output voltage when a current is passed in two directions.
　ホール素子の一方の一対の端子Ｔ１、Ｔ２に電圧Ｖｉｎを印加すると、他方の一対の端子Ｔ３、Ｔ４間には、ホール電圧
Vouta = (R2*R4-R1*R3)/(R1+R4)/(R2+R3)*Vin
が出力される。一方、端子Ｔ３、Ｔ４に電圧Ｖｉｎを印加すると、Ｔ１、Ｔ２にはホール電圧
Voutb = (R1*R3-R2*R4)/(R3+R4)/(R1+R2)*Vin
が出力される。
２方向の出力電圧の差をとると、
Vouta-Voutb = (R1-R3)*(R2-R4)*(R2*R4-R1*R3)/(R1+R4)/(R2+R3)/(R3+R4)/(R1+R2)*Vin
となる。したがって、オフセット電圧は各々の等価回路の抵抗Ｒ１、Ｒ２、Ｒ３、Ｒ４が異なる場合でもオフセットキャンセルできる。しかし、抵抗Ｒ１、Ｒ２、Ｒ３、Ｒ４が電流印加方向、印加電圧により値が変化する場合、前記の式が成り立たないため、オフセットキャンセルできない。 When the voltage Vin is applied to one pair of terminals T1 and T2 of the Hall element, the Hall voltage is applied between the other pair of terminals T3 and T4.
Vouta = (R2 * R4-R1 * R3) / (R1 + R4) / (R2 + R3) * Vin
Is output. On the other hand, when the voltage Vin is applied to the terminals T3 and T4, the Hall voltage is applied to T1 and T2.
Voutb = (R1 * R3-R2 * R4) / (R3 + R4) / (R1 + R2) * Vin
Is output.
Taking the difference in output voltage in two directions,
Vouta-Voutb = (R1-R3) * (R2-R4) * (R2 * R4-R1 * R3) / (R1 + R4) / (R2 + R3) / (R3 + R4) / (R1 + R2) * Vin
It becomes. Therefore, the offset voltage can be offset canceled even when the resistors R1, R2, R3, and R4 of the equivalent circuits are different. However, when the values of the resistors R1, R2, R3, and R4 change depending on the current application direction and the applied voltage, the above equation does not hold, and therefore offset cancellation cannot be performed.
　図５は一般的なホール素子の断面図である（例えば、特許文献１参照）。ホール素子磁気感受部となるＮ型の不純物領域の周辺部は分離のためＰ型の不純物領域に囲まれている。ホール電流印加端子に電圧を印加すると、ホール素子磁気感受部とその周辺部の境界では空乏層が広がる。空乏層中にはホール電流は流れないため、空乏層が広がっている領域ではホール電流は抑制され、抵抗は増加する。また、空乏層幅は印加電圧に依存する。そのため、図４で示す等価回路の抵抗Ｒ１、Ｒ２、Ｒ３、Ｒ４が電圧印加方向により値が変化するためオフセットキャンセル回路で磁気オフセットキャンセルができない。 FIG. 5 is a cross-sectional view of a general Hall element (see, for example, Patent Document 1). A peripheral portion of the N-type impurity region that becomes the Hall element magnetic sensing portion is surrounded by a P-type impurity region for isolation. When a voltage is applied to the Hall current application terminal, a depletion layer spreads at the boundary between the Hall element magnetic sensing part and its peripheral part. Since no hole current flows in the depletion layer, the hole current is suppressed and the resistance increases in the region where the depletion layer extends. The depletion layer width depends on the applied voltage. Therefore, since the values of the resistors R1, R2, R3, and R4 of the equivalent circuit shown in FIG. 4 change depending on the voltage application direction, the magnetic offset cannot be canceled by the offset cancel circuit.
　素子周辺及び素子上部に空乏層制御電極を配置し、空乏層がホール素子内へ延びることを各々の電極に印加する電圧を調節することにより空乏層を抑制する方法が採られている場合もある（例えば、特許文献２参照）。 There is a case where a depletion layer control electrode is arranged around the element and at the top of the element, and a method of suppressing the depletion layer by adjusting a voltage applied to each electrode is extended so that the depletion layer extends into the Hall element. (For example, refer to Patent Document 2).
国際公開ＷＯ２００７／１１６８２３号公報International Publication WO2007 / 116823 特開平０８－３３０６４６号公報Japanese Patent Laid-Open No. 08-330646
　特許文献１の方法では、ホール素子に電圧を印加すると、薄いＮ型不純物領域であるホール素子磁気感受部とＰ型基板である周辺部及び底面部との接合部で空乏層が広がる。空乏層がホール素子中に流れる電流を抑制し、抵抗値が変化する。印加電圧及びその方向により、空乏層幅が変化する。このため、前記のオフセットキャンセル回路によるスピニングカレントによるオフセット電圧除去ができない。 In the method of Patent Document 1, when a voltage is applied to the Hall element, a depletion layer spreads at the junction between the Hall element magnetic sensing part, which is a thin N-type impurity region, and the peripheral part and the bottom part, which are P-type substrates. The depletion layer suppresses the current flowing in the Hall element, and the resistance value changes. The depletion layer width varies depending on the applied voltage and its direction. For this reason, the offset voltage cannot be removed by the spinning current by the offset cancel circuit.
　また、特許文献２の方法では、空乏層制御電極により、空乏層幅を制御し、オフセットキャンセル回路を用いてオフセット電圧を除去可能である。しかしながら、複数の空乏層制御電極を用い、複雑な制御回路も必要とするため、チップサイズが大きくなり、コストアップにつながる等といった難点がある。 In the method of Patent Document 2, the depletion layer width can be controlled by the depletion layer control electrode, and the offset voltage can be removed by using the offset cancel circuit. However, since a plurality of depletion layer control electrodes are used and a complicated control circuit is required, there is a problem that the chip size increases and the cost increases.
　そこで、本願発明は、空乏層幅が変化しにくく、複雑な制御回路を使わずにオフセット電圧が除去できるホールセンサを提供することを課題とする。 Therefore, an object of the present invention is to provide a Hall sensor in which the depletion layer width is difficult to change and the offset voltage can be removed without using a complicated control circuit.
　　　上記の課題を解決するため、本発明は以下のような構成をした。 In order to solve the above problems, the present invention has the following configuration.
　まず、ホール素子中を流れる制御電流をＮ型不純物領域であるホール素子磁気感受部とＰ型基板のその周辺部との接合部と分離して流すことができることを特徴とするホールセンサとした。 First, the Hall sensor is characterized in that the control current flowing in the Hall element can be separated and flown from the junction between the Hall element magnetic sensing portion, which is an N-type impurity region, and the peripheral portion of the P-type substrate.
　また、正方形もしくは十字型の第２のＮ型不純物領域の磁気感受部と空乏層抑制層の第１のＮ型不純物領域及びその各頂点及び端部にＮ型高濃度不純物領域の制御電流入力端子及びホール電圧出力端子を有することを特徴とするホールセンサとした。 In addition, a magnetic sensing portion of the square or cross-shaped second N-type impurity region, a first N-type impurity region of the depletion layer suppression layer, and a control current input terminal of the N-type high-concentration impurity region at each vertex and end thereof And a hall voltage output terminal.
　また、空乏層抑制領域である第１のＮ型不純物領域は磁気感受部の第２のＮ型不純物領域よりも深く、濃度が薄いことを特徴とするホールセンサとした。 In addition, the Hall sensor is characterized in that the first N-type impurity region which is a depletion layer suppression region is deeper than the second N-type impurity region of the magnetic sensing portion and has a low concentration.
　また、制御電流入力端子及びホール電圧出力端子は、ホール磁気感受部と深さを同程度であることを特徴とするホールセンサとした。 Further, the control current input terminal and the hall voltage output terminal are the hall sensors characterized by having the same depth as the hall magnetic sensing part.
　また、スピニングカレントによりオフセット電圧を除去できることを特徴とするホールセンサとした。 Also, the Hall sensor is characterized in that the offset voltage can be removed by spinning current.
　上記手段を用いることにより、ホール素子中を流れる制御電流をＮ型不純物領域であるホール素子磁気感受部とＰ型基板のその周辺部との接合部と分離して流すことができる。そのため、ホール素子磁気感受部内へ空乏層が伸びることが抑制され、印加電圧及びその方向により各々の端子間の抵抗が変化しない。したがって、スピニングカレントによりオフセット電圧を除去することができる。 By using the above means, the control current flowing in the Hall element can flow separately from the junction between the Hall element magnetic sensing part which is an N-type impurity region and the peripheral part of the P-type substrate. For this reason, the depletion layer is prevented from extending into the Hall element magnetic sensing portion, and the resistance between the terminals does not change depending on the applied voltage and its direction. Therefore, the offset voltage can be removed by the spinning current.
　また、ホール素子磁気感受部下に空乏層抑制領域を配置する構造のため、空乏層抑制電極や複雑な回路を用いることなく、空乏層による抵抗値変化を抑制することができるため、オフセット電圧が除去可能でかつ、チップサイズを小さく、コストを抑制することができる。 In addition, because the depletion layer suppression region is placed under the Hall element magnetic sensing part, the resistance voltage change due to the depletion layer can be suppressed without using a depletion layer suppression electrode or a complicated circuit, eliminating the offset voltage. It is possible to reduce the chip size and the cost.
本発明のホール素子の構成を示す図である。（Ａ）は上面図であり、（Ｂ）は側面図である。It is a figure which shows the structure of the Hall element of this invention. (A) is a top view and (B) is a side view. 理想的なホール効果の原理について説明するための図である。It is a figure for demonstrating the principle of an ideal Hall effect. スピニングカレントによるオフセット電圧の除去方法を説明するための図である。It is a figure for demonstrating the removal method of the offset voltage by a spinning current. ホール素子のオフセット電圧を説明するための等価回路の図である。It is a figure of the equivalent circuit for demonstrating the offset voltage of a Hall element. 一般的なホール素子の断面構造の図である。It is a figure of the cross-sectional structure of a general Hall element.
　図１は本発明のホール素子の構成を示した図である。本発明のホール素子は１辺が５０～１５０μｍの正方形の第２のＮ型不純物領域１２１の磁気感受部とその磁気感受部の下部に第２のＮ型不純物領域１２１よりも不純物濃度が低い第１のＮ型不純物領域１２２の空乏層抑制領域及びその各頂点にＮ型高濃度不純物領域の制御電流入力端子及びホール電圧出力端子１１，１２，１３，１４を有する。磁気感受部のＮ型不純物領域は深さ３００～５００ｎｍ程度、不純物濃度は１×１０１６（ａｔｏｍｓ／ｃｍ３）≦Ｎ≦５×１０１６（ａｔｏｍｓ／ｃｍ３）、空乏層抑制領域である第２のＮ型不純物領域１２１は深さ２～３μｍ程度、濃度は８×１０１４（ａｔｏｍｓ／ｃｍ３）≦Ｎ≦３×１０１５（ａｔｏｍｓ／ｃｍ３）、制御電流入力端子及びホール電圧出力端子となる高濃度Ｎ型不純物領域の深さは３００ｎｍ程度にすることが好ましい。つまり、空乏層抑制領域は磁気感受部よりも深く、不純物濃度を低くする。また、制御電流入力端子及びホール電圧出力端子は、ホール磁気感受部と深さを同程度にする。 FIG. 1 is a diagram showing the configuration of the Hall element of the present invention. In the Hall element of the present invention, the second N-type impurity region 121 having a square shape with a side of 50 to 150 μm has a magnetic sensing portion having a lower impurity concentration than the second N-type impurity region 121 below the magnetic sensing portion. The depletion layer suppression region of one N-type impurity region 122 and the control current input terminal and Hall voltage output terminals 11, 12, 13, and 14 of the N-type high concentration impurity region are provided at each apex thereof. The N-type impurity region of the magnetic sensing portion has a depth of about 300 to 500 nm, the impurity concentration is 1 × 10 16 (atoms / cm 3 ) ≦ N ≦ 5 × 10 16 (atoms / cm 3 ), and is a depletion layer suppression region. 2 N-type impurity region 121 has a depth of about 2 to 3 μm, a concentration of 8 × 10 14 (atoms / cm 3 ) ≦ N ≦ 3 × 10 15 (atoms / cm 3 ), a control current input terminal and a hall voltage output terminal The depth of the high-concentration N-type impurity region is preferably about 300 nm. That is, the depletion layer suppression region is deeper than the magnetic sensing portion, and the impurity concentration is lowered. In addition, the control current input terminal and the Hall voltage output terminal have the same depth as the Hall magnetic sensor.
　以上の関係を保つことにより空乏層抑制領域とその周辺部のＰ型基板領域との間の接合部で生じる空乏層に影響されず、制御電流をホール磁気感受部に流すことができる。したがって、ホール電圧出力端子を１１、１３、制御電流入力端子を１２、１４としたときの各々の端子間の抵抗値とホール電圧出力端子を１２、１４、制御電流入力端子を１１、１３としたときの各々の端子間の抵抗値は一定となる。これによりスピニングカレントによりオフセット電圧を消去できる。 By maintaining the above relationship, the control current can be passed to the Hall magnetic sensing portion without being affected by the depletion layer generated at the junction between the depletion layer suppressing region and the P-type substrate region in the periphery thereof. Therefore, when the Hall voltage output terminals are 11, 13 and the control current input terminals are 12, 14, the resistance value between the terminals and the Hall voltage output terminals are 12, 14, and the control current input terminals are 11, 13. The resistance value between the terminals is constant. Thereby, the offset voltage can be erased by the spinning current.
　また、本発明のホール素子の製造方法も容易である。まず、Ｐ型基板に空乏層抑制層となる第１のＮ型不純物領域１２２を形成する。このとき、第１のＮ型不純物領域１２２は深さ２～３μｍ、不純物濃度８×１０１４（ａｔｏｍｓ／ｃｍ３）≦Ｎ≦３×１０１５（ａｔｏｍｓ／ｃｍ３）であった。これはｎウェルと同程度の濃度、深さである。さらに、第１のＮ型不純物領域１２２は空乏層抑制領域として用いるため、ｎウェルの製造ばらつきが大きくてもホール素子の感度やその他の特性に影響しない。そのため、他の要素のｎウェルと共通して形成することができる。 Moreover, the manufacturing method of the Hall element of the present invention is also easy. First, a first N-type impurity region 122 serving as a depletion layer suppressing layer is formed on a P-type substrate. At this time, the first N-type impurity region 122 had a depth of 2 to 3 μm and an impurity concentration of 8 × 10 14 (atoms / cm 3 ) ≦ N ≦ 3 × 10 15 (atoms / cm 3 ). This is the same concentration and depth as the n-well. Further, since the first N-type impurity region 122 is used as a depletion layer suppression region, even if the manufacturing variation of the n-well is large, the sensitivity and other characteristics of the Hall element are not affected. Therefore, it can be formed in common with n-wells of other elements.
　次にホール磁気感受部である第２のＮ型不純物領域１２１を形成する。このとき、第１のＮ型不純物領域１２２は深さ３００～５００ｎｍ、濃度１×１０１６（ａｔｏｍｓ／ｃｍ３）≦Ｎ≦５×１０１６（ａｔｏｍｓ／ｃｍ３）とする。この深さ、濃度の不純物領域は通常のイオン注入装置で形成可能で、ｎウェルよりも濃度、深さのばらつきを小さくすることができる。ホール素子感受部をイオン注入で形成することにより、感度のばらつきの小さいホール素子を形成する。 Next, a second N-type impurity region 121 which is a Hall magnetic sensing part is formed. At this time, the first N-type impurity region 122 has a depth of 300 to 500 nm and a concentration of 1 × 10 16 (atoms / cm 3 ) ≦ N ≦ 5 × 10 16 (atoms / cm 3 ). The impurity region having this depth and concentration can be formed by a normal ion implantation apparatus, and variation in concentration and depth can be made smaller than that of the n well. By forming the Hall element sensing part by ion implantation, a Hall element having a small variation in sensitivity is formed.
　最後に、制御電流入力端子及びホール電圧出力端子となる高濃度不純物領域を形成する。高濃度不純物領域は深さ３００ｎｍであり、特に他の要素と別の工程を必要とせず、共通して形成可能である。 Finally, a high-concentration impurity region that becomes a control current input terminal and a Hall voltage output terminal is formed. The high-concentration impurity region has a depth of 300 nm, and can be formed in common without requiring a separate process from other elements.
　さらに、実施例として正方形の磁気感受部、空乏層抑制領域及びその各頂点に制御電流入力端子とホール電圧出力端子を有するホール素子形状を例にとったがこの形状に限らない。第２のＮ型不純物領域の磁気感受部とその磁気感受部の下部に第２のＮ型不純物領域よりも不純物濃度が低い第１のＮ型不純物領域の空乏層抑制領域及びその各頂点にＮ型高濃度不純物領域の制御電流入力端子及びホール電圧出力端子を有する、スピニングカレントによるオフセット電圧を消去できる形状の対称型ホール素子であればよい。例えば、４５°傾けた十字型の空乏層抑制領域の第１のＮ型不純物領域、ホール素子磁気感受部の第２のＮ型不純物領域及びその各端部にＮ型高濃度不純物領域のホール電流制御電極及びホール電圧出力端子を配置した形状など正方形状以外のでも同様の効果が得られる。 Furthermore, as an example, a square magnetic sensing portion, a depletion layer suppression region, and a Hall element shape having a control current input terminal and a Hall voltage output terminal at each vertex thereof are taken as an example, but the shape is not limited thereto. A depletion layer suppression region of the first N-type impurity region having an impurity concentration lower than that of the second N-type impurity region at the magnetic sensing portion of the second N-type impurity region, and N at each apex thereof. Any symmetrical Hall element having a control current input terminal and a Hall voltage output terminal in a high concentration impurity region and having a shape capable of erasing an offset voltage due to spinning current may be used. For example, the first N-type impurity region of the cross-shaped depletion layer suppressing region inclined by 45 °, the second N-type impurity region of the Hall element magnetic sensing portion, and the hole current of the N-type high-concentration impurity region at each end thereof The same effect can be obtained even when the control electrode and the Hall voltage output terminal are arranged other than the square shape.
　以上より図１のような構造をとることにより複雑な回路や複雑な構造をとる必要もなく、特別な工程を追加する必要もせず、制御電流への空乏層の影響を抑制し、スピニングカレントによりオフセット電圧を消去でき、チップサイズが小さく、安価なホールセンサが実現できる。 As described above, the structure as shown in FIG. 1 eliminates the need for a complicated circuit or a complicated structure, and it is not necessary to add a special process. The influence of the depletion layer on the control current is suppressed, and the spinning current is used. An offset voltage can be erased, a chip size is small, and an inexpensive Hall sensor can be realized.
１０、１２０　ホール素子
１００　Ｐ型基板
１１０　Ｎ型高濃度不純物領域
１２１　第２のＮ型不純物領域
１２２　第１のＮ型不純物領域
１１、１２、１３、１４　ホール電圧出力端子及び制御電流入力端子
２、１２　電源
３、１３　電圧計
１１　切替信号発生器
Ｓ１、Ｓ２、Ｓ３、Ｓ４　センサー端子切替手段
Ｔ１、Ｔ２、Ｔ３、Ｔ４　端子
Ｒ１、Ｒ２、Ｒ３、Ｒ４　抵抗 10, 120 Hall element 100 P-type substrate 110 N-type high concentration impurity region 121 Second N-type impurity region 122 First N- type impurity region 11, 12, 13, 14 Hall voltage output terminal and control current input terminal 2, 12 power supply 3, 13 voltmeter 11 switching signal generator S1, S2, S3, S4 sensor terminal switching means T1, T2, T3, T4 terminals R1, R2, R3, R4 resistance

Claims (3)

  1. 　ホール素子中を流れる制御電流が、Ｎ型不純物領域である磁気感受部とＰ型基板である前記磁気感受部の周辺部とが形成する接合部から離れて流れるように
    　前記磁気感受部は、より深く拡散された、不純物濃度の低いＮ型不純物領域である空乏層抑制領域によって周囲を覆われており、
    　制御電流入力端子及びホール電圧出力端子は、前記磁気感受部に配置されており、前記制御電流入力端子及び前記ホール電圧出力端子は、前記磁気感受部と同じ深さを有していることを特徴とするホールセンサ。     The magnetic susceptor is more controlled so that a control current flowing in the Hall element flows away from a joint formed by a magnetic susceptor that is an N-type impurity region and a peripheral part of the magnetic susceptor that is a P-type substrate. The periphery is covered by a depletion layer suppression region that is an N-type impurity region that is deeply diffused and has a low impurity concentration,
    The control current input terminal and the Hall voltage output terminal are disposed in the magnetic sensing part, and the control current input terminal and the Hall voltage output terminal have the same depth as the magnetic sensing part. Hall sensor.
  2. 　前記磁気感受部が正方形もしくは十字型であり、その各頂点及び端部にＮ型高濃度不純物領域の制御電流入力端子及びホール電圧出力端子を有することを特徴とする請求項１記載のホールセンサ。 The Hall sensor according to claim 1, wherein the magnetic sensing portion is square or cross-shaped, and has a control current input terminal and a Hall voltage output terminal of an N-type high concentration impurity region at each apex and end thereof.
  3. 　スピニングカレントによりオフセット電圧を除去できることを特徴とする請求項１記載のホールセンサ。 The Hall sensor according to claim 1, wherein the offset voltage can be removed by spinning current.
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JPH06186103A (en) * 1992-12-21 1994-07-08 Taisee:Kk Sensor-terminal changeover means and magnetism measuring method or pressure measuring method
JP2012032382A (en) * 2010-07-05 2012-02-16 Seiko Instruments Inc Hall sensor
JP2012032383A (en) * 2010-07-05 2012-02-16 Seiko Instruments Inc Hall sensor

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Publication number Priority date Publication date Assignee Title
JPH06186103A (en) * 1992-12-21 1994-07-08 Taisee:Kk Sensor-terminal changeover means and magnetism measuring method or pressure measuring method
JP2012032382A (en) * 2010-07-05 2012-02-16 Seiko Instruments Inc Hall sensor
JP2012032383A (en) * 2010-07-05 2012-02-16 Seiko Instruments Inc Hall sensor

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