WO2013133593A1 - Light-emitting diode having improved light-extraction efficiency, and production method therefor - Google Patents

Abstract

Provided is a light-emitting diode. The light-emitting diode has a first electrically-conductive cladding layer. A light-scattering pattern having a refractive index different from that of the first electrically-conductive cladding layer is positioned in the first electrically-conductive cladding layer. An active layer is positioned below the first electrically-conductive cladding layer. A second electrically-conductive cladding layer is positioned below the active layer. An electrically connecting first electrode is positioned on the first electrically-conductive cladding layer. An electrically connecting second electrode is positioned on the second electrically-conductive cladding layer.

Description

Light emitting diode with improved light extraction efficiency and manufacturing method thereof

The present invention relates to a semiconductor device, and more particularly to a light emitting diode.

The light emitting diode includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer positioned between the n-type and p-type semiconductor layers, and a forward electric field is applied to the n-type and p-type semiconductor layers. Electrons and holes are injected into the active layer, and electrons and holes injected into the active layer recombine to emit light.

In such a light emitting diode, a device in which n-type and p-type electrodes electrically connected to each of the n-type and p-type semiconductor layers is positioned in a vertical direction is called a vertical light-emitting diode. Such vertical light emitting diodes are known to have excellent heat dissipation characteristics and light output. However, there is still a problem that the light output is not sufficient.

The problem to be solved by the present invention is to provide a light emitting diode with improved light extraction efficiency.

One aspect of the present invention to achieve the above object provides a light emitting diode. The light emitting diode includes a first conductive cladding layer. A light scattering pattern having a refractive index different from that of the first conductive clad layer is disposed in the first conductive clad layer. An active layer is positioned below the first conductivity type clad layer. A second conductive cladding layer is positioned below the active layer. A first electrode electrically connected to the first conductive cladding layer is positioned. A second electrode is electrically connected to the second conductive cladding layer.

The light scattering pattern may be positioned to overlap the first electrode. In detail, the light scattering pattern may be located in a region overlapping with the first electrode and in a region adjacent thereto. The first electrode may include a bonding pad and an extension, and the light scattering pattern may be located below the bonding pad but not below the extension.

The width of the opening defined by the light scattering pattern may be smaller than that of the region not overlapping with the first electrode in the region overlapping with the first electrode. The light scattering pattern may be a film having a plurality of dots, a plurality of lines, or a plurality of through holes. The light scattering pattern may be an insulating layer having a smaller refractive index than that of the first conductive cladding layer. The light scattering pattern may be formed by alternately stacking films having different refractive indices.

The first conductive clad layer may have a plurality of grooves etched along a defect in an upper surface thereof. The concentration of impurities in the protrusions defined by the grooves may be higher than the concentration of impurities in the first conductive clad layer. The impurity may be a first conductivity type dopant.

Levels of the bottom portions of the grooves may be lowered in the outward direction at the center of the upper surface of the first conductive clad layer. An upper surface of the first conductive clad layer includes a portion where the grooves are formed and a portion where the grooves are not formed, and the first electrode is formed on a portion where the grooves of the first conductive clad layer are not formed. Can be located. Alternatively, the first electrode may be located on a portion where the grooves are formed. An insulating pattern may be located between the first conductive clad layer and the first electrode.

The first conductive cladding layer may include a main first conductive cladding layer and an auxiliary first conductive cladding layer. An intrinsic clad layer may be positioned between the main first conductive cladding layer and the auxiliary first conductive cladding layer. The grooves may be formed in the auxiliary first conductive clad layer. At least some of the bottoms of the grooves may abut the intrinsic clad layer.

One aspect of the present invention to achieve the above object provides another embodiment of the light emitting diode. The light emitting diode according to the present embodiment includes a first conductive cladding layer. An active layer may be located under the first conductive clad layer. A second conductive cladding layer may be positioned below the active layer. A first electrode electrically connected to the first conductive clad layer may be positioned. A second electrode may be arranged to be electrically connected to the second conductive clad layer. An insulator pattern may be disposed in the first conductive cladding layer, and a width of an opening defined by the dielectric pattern may be smaller than a region in which the first electrode overlaps with the first electrode.

One aspect of the present invention to achieve the above object provides another embodiment of the light emitting diode. The light emitting diode according to the present embodiment includes a one-conductive cladding layer having a plurality of grooves in the upper surface and protrusions defined by the grooves. An active layer is positioned below the first conductivity type clad layer. A second conductive cladding layer is positioned below the active layer. The concentration of impurities in the protrusions is higher than the concentration of impurities in the first conductive clad layer.

Another aspect of the present invention to achieve the above object provides a method of manufacturing a light emitting diode. First, the auxiliary first conductivity type clad layer is formed. A light scattering pattern having a refractive index different from that of the auxiliary first conductive clad layer is formed on the auxiliary first conductive clad layer. The main first conductive cladding layer is formed on the light scattering pattern. An active layer is formed on the main first conductive clad layer. A second conductive cladding layer is formed on the active layer. An electrode electrically connected to the auxiliary first conductive cladding layer is formed.

The light scattering pattern may be formed to overlap with the electrode. The light scattering pattern may be formed to be limited in a region overlapping with the electrode and a region adjacent thereto. The electrode may include a bonding pad and an extension, and the light scattering pattern may be located in an area overlapping the bonding pad but not in an area overlapping the extension. The width of the opening defined by the light scattering pattern may be narrower than a region in the region overlapping with the electrode does not overlap the electrode. The light scattering pattern may be a film having a plurality of dots, a plurality of lines, or a plurality of through holes.

The light scattering pattern may be an insulating layer having a smaller refractive index than the first conductive clad layers. The light scattering pattern may be formed by alternately stacking films having different refractive indices.

The auxiliary first conductive cladding layer may be formed on a growth substrate. Before forming the electrode, the growth substrate may be removed to expose the auxiliary first conductive clad layer. The growth substrate may be a GaN substrate, and the auxiliary first conductive clad layer may be a GaN layer.

Prior to forming the electrode, a defect may be created in an upper surface of the auxiliary first conductive clad layer. The defect may be etched to form a plurality of grooves in an upper surface of the auxiliary first conductive clad layer. Generating a defect in the surface of the auxiliary first conductive cladding layer may be performed by implanting impurities into the surface of the auxiliary first conductive cladding layer. The impurity may be a first conductivity type dopant. Forming the plurality of grooves may be performed using a wet etching method. The wet etching method may be a photo-enhanced chemical etching method.

Depth of the defect may be deepened from the central portion of the upper surface of the auxiliary first conductive clad layer toward the outer portion. The defect is generated by impurity implantation, and the projected range Rp of the implanted impurity may be deepened from the central portion of the surface of the auxiliary first conductive clad layer to the outer portion. To this end, before implanting the impurity, a mask layer having a reduced thickness in the outer direction from the center of the surface of the auxiliary first conductive clad layer may be formed on the upper surface of the auxiliary first conductive clad layer.

The electrode may be formed on the surface of the auxiliary first conductive clad layer before or after the grooves are formed. Before forming the electrode, an insulating pattern may be formed on the surface of the auxiliary first conductive clad layer. The electrode may be formed on the insulating pattern.

Before forming the light scattering pattern, an intrinsic cladding layer may be formed on the auxiliary first conductive cladding layer. At this time, at least some of the bottoms of the grooves may contact the intrinsic clad layer.

The auxiliary first conductive cladding layer, the light scattering pattern, the main first conductive cladding layer, the active layer, and the second conductive cladding layer may be sequentially formed on a growth substrate. Before generating the defect, the growth substrate may be removed to expose the top surface of the auxiliary first conductive clad layer. The growth substrate may be a GaN substrate, and the auxiliary first conductive clad layer may be a GaN layer.

According to the present invention, a light scattering pattern is formed in the first conductive clad layer to scatter light generated from the active layer, thereby improving light extraction efficiency. The light scattering pattern may be disposed in an area overlapping the first electrode. In this case, light emitted from a region located vertically below the first electrode of the active layer may be scattered by the light scattering pattern to be emitted to a region where the first electrode is not formed. Accordingly, the light extraction efficiency can be further improved.

In addition, the width of the opening defined by the light scattering pattern may be smaller than an area not overlapping the first electrode in an area overlapping the first electrode. As a result, current crowding in the region overlapping with the first electrode can be alleviated, so that horizontal current spreading in the light emitting structure can be improved. In addition, the light scattering pattern may be disposed to be limited to an area overlapping with the first electrode and an area adjacent to the first electrode, in which case the flow of current overlaps with the first electrode rather than in an area overlapping with the first electrode. It can be larger in areas that do not. Thus, the current spreading in the horizontal direction can be further improved.

In addition, when the growth substrate is a GaN substrate and the first conductive cladding layer is a GaN layer, the light emitting structure including the first conductive cladding layer may be formed of a high quality epitaxial layer having almost no crystal defects.

Furthermore, the probability that photons generated from the active layer can escape to the outside due to the grooves and the protrusions defined therein, that is, the roughness, can be increased. As a result, the light extraction efficiency can be improved.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects that are not mentioned will be clearly understood by those skilled in the art from the following description.

1A to 1C are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.

2A through 2E are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.

3A to 3C are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention.

4A to 4C are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention.

5A to 5C are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention.

6 is a layout diagram illustrating a light emitting diode according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view taken along cut line III-III ′ of FIG. 6.

8 is a layout diagram illustrating a portion of a light emitting diode according to another embodiment of the present invention.

9 is a layout diagram illustrating a light emitting diode according to another embodiment of the present invention.

10 is a layout diagram illustrating a portion of a light emitting diode according to another embodiment of the present invention.

11 is a layout diagram illustrating a light emitting diode according to another embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to describe the present invention in more detail. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms.

Where a layer is referred to herein as being "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. In addition, in the present specification, the directional expression of the upper portion, the upper portion, and the upper surface may be understood as the meaning of the lower portion, the lower portion, the lower surface, and the like. In other words, the expression of the spatial direction should be understood in the relative direction and not limitedly as it means the absolute direction. In addition, the "first" or "second" is not intended to limit any of the components herein, but should be understood as a term for distinguishing the components.

In addition, in the drawings herein, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

1A to 1C are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 1A, the auxiliary first conductive cladding layer 13a, the light scattering pattern 14, and the main first conductive cladding layer 13b are formed on the growth substrate 10. The auxiliary first conductive cladding layer 13a and the main first conductive cladding layer 13b form a first conductive cladding layer 13. Thereafter, the active layer 15 and the second conductive cladding layer 17 are sequentially formed on the first conductive cladding layer 13. The first conductive cladding layer 13, the active layer 15, and the second conductive cladding layer 17 may form the light emitting structure LS.

The growth substrate 10 includes sapphire (Al ₂ O ₃ ), silicon carbide (SiC), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium oxide (Ga ₂ O ₃ ), or a silicon substrate. Specifically, the growth substrate 10 may be a GaN substrate.

The main and auxiliary first conductive cladding layers 13a and 13b, that is, the first conductive cladding layer 13 may be a nitride based semiconductor layer and may be a layer doped with an n-type dopant. As an example, the first conductive cladding layer 13 may be formed of Si as an n-type dopant in an In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1) layer. May be a doped layer. Specifically, the first conductive cladding layer 13 may be a GaN layer doped with Si. Alternatively, the first conductivity type cladding layer 13 has a plurality of In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1) layers having different compositions. You may. In the case where the growth substrate 10 is a GaN substrate and the first conductivity type cladding layer 13 is a GaN layer, the first conductivity type having higher quality than the case where other types of growth substrates 10 are used has no lattice defects. The clad layer 13 can be obtained.

The light scattering pattern 14 may be a material pattern having a refractive index different from that of the first conductive cladding layer 13, for example, a material pattern having a lower refractive index than the first conductive cladding layer 13. The light scattering pattern 14 may be formed using a deposition method and a photolithography etching method. The light scattering pattern 14 may include, for example, SiO ₂ (n = 1.4), Al ₂ O ₃ (n = 1.6), SiN _x (0.5 <x <1.8, n = 2.05 to 2.25), and TiO ₂ (n A single layer, or a pair of material layers thereof, may be a distributed bragg reflector (DBR), which is an alternately laminated film. The material and thickness forming the light scattering pattern 14 may be appropriately selected depending on the wavelength characteristics of the light emitted from the active layer 15. Although the cross section of the light scattering pattern 14 is illustrated as a quadrangle, the light scattering pattern 14 is not limited thereto and may be various polygons such as a circle or a triangle.

The light scattering pattern 14 defines a region where the light scattering pattern 14 is not formed, that is, a plurality of openings 14h. The main first conductive cladding layer 13b may be epitaxial lateral overgrowth from the auxiliary first conductive cladding layer 13a through the openings 14h of the light scattering pattern 14. Thus, lattice defects in the main first conductivity type cladding layer 13b can be further alleviated.

The active layer 15 may be an In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) layer, and may have a single quantum well structure or a multi quantum well structure (multi -quantum well (MQW). As an example, the active layer 15 may have a single quantum well structure of an InGaN layer or an AlGaN layer, or a multi-quantum well structure that is a multilayer structure of InGaN / GaN, AlGaN / (In) GaN, or InAlGaN / (In) GaN. have.

The second conductive cladding layer 17 may also be a nitride-based semiconductor layer or a layer doped with a p-type dopant. As an example, the second conductivity type cladding layer 17 may be a p-type dopant in an In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) layer. It may be a layer doped with Mg or Zn as. Specifically, the second conductivity type cladding layer 17 may be a GaN layer doped with Mg. In contrast, the second conductive cladding layer 17 has a plurality of In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) layers having different compositions. It may be provided. The first conductive cladding layer 13, the active layer 15, and the second conductive cladding layer 17 may be formed using a MOCVD method or an MBE method.

Before forming the auxiliary first conductive cladding layer 13a, a buffer layer (not shown) may be formed on the growth substrate 10. The buffer layer may be a ZnO layer, an Al _x Ga _1-x N (0 ≦ x ≦ 1) layer, or a CrN layer. When the growth substrate 10 is a GaN substrate and the first conductive cladding layer 13 is a GaN layer, the buffer layer may be omitted.

An ohmic contact layer 19 in ohmic contact with the second conductive cladding layer 17 is formed on the second conductive cladding layer 17. To this end, a conductive layer may be laminated and heat treated on the second conductive cladding layer 17. The ohmic contact layer 19 may be a Pt layer, a Pt alloy layer, a Ni layer, a Ni alloy layer, or multiple layers thereof.

The support substrate 20 may be bonded to the ohmic contact layer 19. Before bonding the support substrate 20, a bonding layer such as a thermo-compressive bonding layer or an eutectic bonding layer is formed between the ohmic contact layer 19 and the support substrate 20. can do. The support substrate 20 may be a semiconductor substrate such as Si, GaAs, GaP, or InP, or a metal substrate such as Cu or W. Alternatively, the support substrate 20 may be a plated substrate formed on the ohmic contact layer 19 by using an electroplating method.

Referring to FIG. 1B, the growth substrate 10 may be removed to expose the first conductive clad layer 13. As an example, when the growth substrate 10 is a sapphire substrate, the growth substrate 10 may be removed by using a laser lift-off (LLO) method. As another example, when the growth substrate 10 is a GaN substrate, the GaN substrate may be removed by grinding.

Referring to FIG. 1C, the first electrode 12 may be formed on the first conductive cladding layer 13 exposed by removing the growth substrate 10. The first electrode 12 may be an Al layer, a Pt layer, a Ni layer, or an Au layer. In addition, a second electrode (not shown) may be formed under the support substrate 20. However, even when the second electrode is not formed, the supporting substrate 20 itself may serve as the second electrode.

2A through 2E are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention. The light emitting diode manufacturing method according to the present embodiment is similar to the light emitting diode manufacturing method described with reference to FIGS. 1A to 1C except as described below.

Referring to FIG. 2A, the auxiliary first conductive cladding layer 13a, the intrinsic cladding layer 12, the light scattering pattern 14, and the main first conductive cladding layer 13b are sequentially formed on the growth substrate 10. Form. The auxiliary first conductive cladding layer 13a and the main first conductive cladding layer 13b form a first conductive cladding layer 13. Thereafter, the active layer 15 and the second conductive cladding layer 17 are sequentially formed on the first conductive cladding layer 13. The first conductive cladding layer 13, the active layer 15, and the second conductive cladding layer 17 may form the light emitting structure LS. The growth substrate 10, the main and auxiliary first conductive cladding layers 13a and 13b, the light scattering pattern 14, the active layer 15, and the second conductive cladding layer 17 will be described with reference to FIG. 1A. Reference is made to the parts described with reference.

The intrinsic cladding layer 12 may be a nitride-based semiconductor layer as a dopant-doped cladding layer, and specifically, In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1) may be a layer, for example, a GaN layer. Specifically, the intrinsic clad layer 12 may have the same composition as the first conductive clad layer 13 except for the dopant. In some cases, the intrinsic clad layer 12 may be omitted. The first conductive cladding layer 13, the intrinsic cladding layer 12, the active layer 15, and the second conductive cladding layer 17 may be formed using a MOCVD method or an MBE method.

A buffer layer (not shown) may be formed on the growth substrate 10 before the auxiliary first conductive cladding layer 13a is formed. In the case where the growth substrate 10 is a GaN substrate and the first conductive cladding layer 13 is a GaN layer, the buffer layer may be omitted. An ohmic contact layer 19 in ohmic contact with the second conductive cladding layer 17 is formed on the second conductive cladding layer 17. To this end, a conductive layer may be laminated and heat treated on the second conductive cladding layer 17. The support substrate 20 may be bonded to the ohmic contact layer 19. Before bonding the support substrate 20, a bonding layer such as a thermo-compressive bonding layer or an eutectic bonding layer is formed between the ohmic contact layer 19 and the support substrate 20. can do. Detailed descriptions of the buffer layer, the ohmic contact layer 19, and the support substrate 20 will be described with reference to FIG. 1A.

Referring to FIG. 2B, the growth substrate 10 may be removed to expose the surface of the first conductive clad layer 13. As an example, when the growth substrate 10 is a sapphire substrate, the growth substrate 10 may be removed by using a laser lift-off (LLO) method. As another example, when the growth substrate 10 is a GaN substrate, the GaN substrate may be removed by grinding.

Referring to FIG. 2C, the mask layer M may be formed on the upper surface of the first conductive clad layer 13 exposed by removing the growth substrate 10. The mask layer M may be an insulating film such as a silicon oxide film, a silicon nitride film, or a photoresist film.

Impurity can be implanted into the surface of the first conductivity type cladding layer 13 using the mask layer M as a mask. To this end, the mask layer M has a thick thickness such that the impurities may not be transmitted. As a result, defects can be created in the surface of the first conductivity type clad layer 13. However, other methods besides impurity implantation may be used to create defects in the surface of the first conductivity type cladding layer 13. Defects may be formed in the auxiliary first conductivity type clad layer 13a.

The impurities may be used as long as they can generate defects in the surface of the first conductivity type cladding layer 13. As an example, the impurity may be a first conductivity type dopant and may be the same as the first conductivity type dopant doped in the first conductivity type clad layer 13. As an example, the first conductivity type dopant may be Si (silicon) or H (hydrogen).

Referring to FIG. 2D, the mask layer M is removed. Thereafter, the defects are etched to form a plurality of grooves H in the surface of the first conductive cladding layer 13. Lattice defects such as dislocations are thermodynamically unstable and can be preferentially etched during the etching process. Since defects are not generated in the portion of the first conductive clad layer 13 that has been masked by the mask layer M, the grooves H may be hardly formed. The probability that photons generated from the active layer 15 can escape to the outside due to the grooves H and the protrusions P defined therein, that is, the roughness, may be increased. As a result, the light extraction efficiency can be further improved.

The grooves H may be formed using a wet etching method. At this time, the etching solution may penetrate along the defects and preferentially etch the defects. As an example, the wet etching method may be a photo-enhanced chemical etching method. Specifically, the resultant after removing the mask layer (M) in the electrolyte solution is injected into the light by etching to proceed.

In the case where the growth substrate (10 in FIG. 1A) is a GaN substrate and the first conductivity type cladding layer 13 is a GaN layer, there may be almost no defect in the first conductivity type cladding layer 13. Therefore, in order to form grooves formed by etching the defect in the surface of the first conductivity type clad layer, it is advantageous to additionally generate the defect as described above.

The etching can be stopped by reaching the intrinsic clad layer 12. Since the intrinsic cladding layer 12 is a thin film having almost no defects because it does not contain impurities, the etching proceeding along the defect may be stopped in the intrinsic cladding layer 12. At this time, at least some of the bottoms of the grooves H may be in contact with the intrinsic clad layer 12. In this case, the grooves H may be prevented from reaching the light emitting layer 15 due to an unexpected excessive progress of etching, thereby preventing deterioration of device efficiency.

In addition, when the grooves H are formed by implanting impurities into the surface of the first conductive cladding layer 13, specifically, the auxiliary first conductive cladding layer 13a, the grooves H are defined by the grooves H. The concentration of impurities in the protruding portions P may be higher than the concentration of impurities in the first conductive clad layer 13, specifically, the main first conductive clad layer 13b.

Referring to FIG. 2E, the first electrode 32 may be formed on the first conductive clad layer 13 in which the grooves H are formed. Specifically, the first electrode 32 may be formed on the portion where the grooves H are not formed by being masked by the mask M. FIG. The first electrode 32 may be an Al layer, a Pt layer, a Ni layer, or an Au layer. In addition, a second electrode (not shown) may be formed under the support substrate 20. However, even when the second electrode is not formed, the supporting substrate 20 itself may serve as the second electrode.

Before forming the first electrode 32, the insulating pattern 31 may be formed on the first conductive cladding layer 13, specifically, the mask M to form a portion where the grooves H are not formed. Can be. The width of the insulating pattern 31 may be equal to or smaller than the width of the first electrode 32. In this case, when voltage is applied to the first electrode 32, the voltage is cut in the vertical downward direction of the insulating pattern 31, so that current crowding can be alleviated and current spreading can be improved. The insulating pattern 31 may be a distributed bragg reflector (DBR), in which a pair of insulating films having different refractive indices are alternately stacked. In this case, since the probability that the light emitted from the active layer 15 is emitted to the region where the first electrode 32 is not formed increases, the light extraction efficiency may be further improved.

3A to 3C are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention. The light emitting diode manufacturing method according to the present embodiment is similar to the light emitting diode manufacturing method described with reference to FIGS. 2A to 2E except for the following description.

Referring to FIG. 3A, impurities may be implanted into the entire surface of the first conductive clad layer 13 exposed by removing the growth substrate 10 (FIG. 2B). As a result, defects may be created in the entire surface of the first conductivity type clad layer 13. However, other methods besides impurity implantation may be used to create defects in the surface of the first conductivity type cladding layer 13. The defects may be formed in the auxiliary first conductivity type clad layer 13a.

Referring to FIG. 3B, the defects are etched to form a plurality of grooves H in the surface of the first conductive clad layer 13. The grooves H may be formed using a wet etching method. As an example, the wet etching method may be a photochemical chemistry (PEC) etching method. The etching may be stopped by reaching the intrinsic clad layer 12 which is a thin film having almost no defects due to no impurities. Therefore, at least some of the bottoms of the grooves H may be in contact with the intrinsic clad layer 12.

Referring to FIG. 3C, the first electrode 32 may be formed on the first conductive clad layer 13 having the grooves H formed therein. Before forming the first electrode 32, the insulating pattern 31 may be formed on the first conductive cladding layer 13. The width of the insulating pattern 31 may be equal to or smaller than the width of the first electrode 32.

When the insulating pattern 31 is not formed or its width is smaller than the width of the first electrode 32, the first electrode 32 may contact the protrusions P defined by the grooves H. Meanwhile, when the grooves H are formed by injecting a first conductivity type dopant into the surface of the first conductivity type cladding layer 13, the protrusions P remaining after etching to form the grooves H remain. The concentration of the first conductivity type dopant in c) may be increased due to the first conductivity type dopant implantation. At this time, the ohmic junction between the first electrode 32 and the protrusions P may be improved.

4A to 4C are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention. The light emitting diode manufacturing method according to the present embodiment is similar to the light emitting diode manufacturing method described with reference to FIGS. 2A to 2E except for the following description.

Referring to FIG. 4A, a mask layer M may be formed on the surface of the first conductive cladding layer 13. The mask layer M may be an insulating film such as a silicon oxide film, a silicon nitride film, or a photoresist film. An impurity may be implanted onto the resultant product on which the mask layer M is formed.

At this time, impurities may be injected into the surface of the first conductive clad layer 13 through the mask layer M. However, the thickness M _h1 of the mask layer M in the region where the electrode will be described later is formed to a thickness such that the impurity cannot penetrate. Although the mask layer M is illustrated as having the thickest portion in the center thereof, the mask layer M may have the thickest thickness in the region where the electrode to be described later is formed. Except for the region where the electrode is to be described later, the mask layer M may have a thickness M _h2 , M _h3 , M _h4 reduced from the center of the surface of the first conductive clad layer 13 to the outer portion. Can be. In this case, Rp (Projected Range) of the implanted impurity may be deepened from the center of the surface of the first conductive clad layer 13 toward the outer portion. To this end, a specific thickness of the mask layer M and the impurity implantation energy may be controlled.

Impurities injected into the surface of the first conductivity type clad layer 13 may generate defects. Since the Rp of the implanted impurities deepens from the center of the surface of the first conductive clad layer 13 to the outer direction, the depth of defects also deepens from the center of the surface of the first conductive clad layer 13 to the outer direction. Can be. The defects may be formed in the auxiliary first conductive cladding layer 13a.

Referring to FIG. 4B, the mask layer M is removed. Thereafter, the defects are etched to form a plurality of grooves H in the surface of the first conductive cladding layer 13. Since the depths of the defects are formed to be deep in the outer direction from the center of the surface of the first conductivity type cladding layer 13, the levels of the bottom portions of the grooves H are the center of the surface of the first conductivity type cladding layer 13. Can be lowered in the outward direction. In this case, the upper surface of the light emitting diode may have an inclination from the center portion to the outer portion. Thus, light diffusion can be increased, which is suitable for illumination.

Since defects were not generated in the portion that was masked by the portion of the mask layer M having the largest thickness, the grooves H may hardly be formed. The grooves H may be formed using a wet etching method. As an example, the wet etching method may be a photochemical chemistry (PEC) etching method. The etching may be stopped by reaching the intrinsic clad layer 12 which is a thin film having almost no defects due to no impurities. Thus, at least some of the bottoms of the grooves H, specifically, the bottoms of the grooves H formed in the region where the depths of the defects are deepest, may contact the intrinsic clad layer 14.

Referring to FIG. 4C, the first electrode 32 may be formed on a portion where the grooves H are not formed by being masked by the thickest portion of the mask layer M. Referring to FIG. Before forming the first electrode 32, the insulating pattern 31 is formed on the first conductive clad layer 13, specifically, masked by the mask M to form the grooves H not formed. Can be formed. The width of the insulating pattern 31 may be equal to or smaller than the width of the first electrode 32.

5A to 5C are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention. The light emitting diode manufacturing method according to the present embodiment is similar to the light emitting diode manufacturing method described with reference to FIGS. 2A to 2E except for the following description.

Referring to FIG. 5A, a mask layer M may be formed on the surface of the first conductive cladding layer 13. The mask layer M may be an insulating film such as a silicon oxide film, a silicon nitride film, or a photoresist film. An impurity may be implanted onto the resultant product on which the mask layer M is formed. The mask layer M may decrease in thickness M _h2 , M _h3 , M _h4 from the surface center portion of the first conductive clad layer 13 toward the outer portion, but the thickest portion M of the mask layer M may be reduced. _{Also in h2} ), impurities may be penetrated and injected into the surface of the first conductivity-type cladding layer 13. In this case, Rp (Projected Range) of the implanted impurity may be deepened from the central portion of the surface of the first conductive clad layer 13 toward the outer portion. To this end, the specific thickness of the mask layer M and the impurity implantation energy may be controlled.

Impurities injected into the surface of the first conductivity type clad layer 13 may generate defects. Since the implanted impurity Rp deepens from the surface center portion of the first conductive clad layer 13 toward the outer portion, the depth of defects may also deepen from the surface center portion of the first conductive clad layer 13 toward the outer portion. The defects may be formed in the auxiliary first conductivity type clad layer 13a.

Referring to FIG. 5B, the mask layer M is removed. Thereafter, the defects are etched to form a plurality of grooves H in the surface of the first conductive cladding layer 13. Since the depths of the defects are formed to be deep in the outer direction from the center of the surface of the first conductivity-type cladding layer, the levels of the bottom portions of the grooves H are the outer portion of the surface of the first conductivity-type cladding layer 13. Direction can be gradually lowered. In this case, the upper surface of the light emitting diode may have an inclination from the center portion to the outer portion. Thus, light diffusion can be increased, such a light emitting diode may be suitable for illumination.

The grooves H may be formed using a wet etching method. As an example, the wet etching method may be a photo-enhanced chemical etching method. The etching may be stopped by reaching the intrinsic clad layer 12 which is a thin film having almost no defects due to no impurities. Therefore, at least some of the bottoms of the grooves H, in particular, the bottoms of the grooves H formed in the region where the depth of the defects are deepest may contact the intrinsic clad layer 12.

Referring to FIG. 5C, a first electrode 32 may be formed on the first conductive cladding layer 13 on which the grooves H are formed. Before forming the first electrode 32, the insulating pattern 31 may be formed on the first conductive cladding layer 13. The width of the insulating pattern 31 may be equal to or smaller than the width of the first electrode 32.

When the insulating pattern 31 is not formed or its width is smaller than the width of the first electrode 32, the first electrode 32 may contact the protrusions P defined by the grooves H. . Meanwhile, when the grooves H are formed by injecting a first conductivity type dopant into the surface of the first conductivity type cladding layer 13, the protrusions P remaining after etching to form the grooves H remain. The concentration of the first conductivity type dopant in c) may be increased by implantation of the first conductivity type dopant. At this time, the ohmic junction between the first electrode 32 and the protrusions P may be improved.

6 is a layout diagram illustrating a light emitting diode according to an embodiment of the present invention. FIG. 7 is a cross-sectional view taken along cut line III-III ′ of FIG. 6. The light emitting diode according to the present embodiment is similar to the light emitting diode described with reference to FIGS. 1A to 1C except as described below.

6 and 7, the first conductive cladding layer 13, the second conductive cladding layer 17 disposed under the first conductive cladding layer 13, and the cladding layers 13 and 17. There is provided a light emitting structure (LS) having an active layer (15) positioned between. The first electrode 32 electrically connected to the first conductive cladding layer 13 is disposed on the first conductive cladding layer 13. The first electrode 32 may include a bonding pad 32a and an extension part 32e extending from the bonding pad 32a. On the other hand, the support substrate 20 is disposed under the second conductive cladding layer 17, and the second conductive cladding layer 17 is ohmic between the second conductive cladding layer 17 and the supporting substrate 20. An ohmic contact layer 19 in contact may be arranged. In addition, a second electrode (not shown) may be disposed below the support substrate 20. However, even when the second electrode is not formed, the supporting substrate 20 itself may serve as the second electrode.

The first conductive cladding layer 13 has a light scattering pattern 14 therein. The light scattering pattern 14 may scatter light generated from the active layer 15 to improve light extraction efficiency. The light scattering pattern 14 may be a dielectric film having a refractive index different from that of the first conductive cladding layer 13. In addition, the plurality of openings 14h may be defined by the light scattering pattern 14. When an electric field is applied between the first electrode 12 and the second electrode, the light scattering pattern 14 may block the flow of current. In other words, the flow of current can be defined in the openings 14h defined by the light scattering pattern 14.

The width or area of the opening 14h in the region R overlapping the first electrode 12 may be smaller than that in the region not overlapping the first electrode 32. At this time, the current flow in the light emitting structure LS may be greater in the region not overlapping with the first electrode 32 than in the region R overlapping with the first electrode 32. Therefore, current crowding in the region R overlapping the first electrode 32 can be alleviated, so that horizontal current spreading in the light emitting structure LS can be improved. . In addition, the light generation efficiency in the active layer 15, that is, the internal quantum efficiency may be improved, and the reliability may also be improved.

Further, the region R having a smaller width or area of the opening 14h may coincide with the region overlapping the first electrode 32, that is, the vertical lower region of the first electrode 32, but misalignment. In consideration of this, it may be wider than the vertical lower region of the first electrode 32. In other words, the region R having a small width or area of the opening 14h may be limited to the region overlapping with the first electrode 32 and the region adjacent thereto. In addition, unlike shown, the region R having a small width or area of the opening 14h may overlap only the bonding pad 32a except for the extension portion 32e.

Specifically, the light scattering pattern 14 may be a plurality of dots as shown. The dots may have a diameter of 0.5 μm or more and a height of 0.1 μm or more. The area between the dots corresponds to the opening 14h defined by the light scattering pattern 14. The widths S1 and S2 of the intervals between the dots located in the region R overlapping the first electrode 32 are the widths S3 of the intervals between the dots located in the region not overlapping the first electrode 32. May be smaller than

8 is a layout diagram illustrating a portion of a light emitting diode according to another embodiment of the present invention. The light emitting diode according to the present embodiment may be similar to the light emitting diode described with reference to FIGS. 6 and 7 except for the following description.

Referring to FIG. 8, the light scattering pattern 14 may be disposed in the region R overlapping the first electrode 32. When the light scattering pattern 14 was not formed, the light emitted from the region located vertically below the first electrode 32 of the active layer (FIG. 1C or 15 of FIG. 7) was blocked by the first electrode 32. On the other hand, by forming the light scattering pattern 14, light emitted from the region located vertically below the first electrode 32 of the active layer (FIG. 1C or 15 of FIG. 7) is scattered by the light scattering pattern 14 The first electrode 32 may be emitted to a region where the electrode 32 is not formed. Accordingly, the light extraction efficiency can be improved.

In addition, the flow of current may be limited to the openings 14h which are regions in which the light scattering pattern 14 is not formed. At this time, the light scattering pattern 14 is disposed only in the region R overlapping with the first electrode 32, so that the current flows first than in the region R overlapping with the first electrode 32. It may be larger in an area not overlapping with the electrode 32. Thus, current spreading in the horizontal direction can be improved. Further, the region R in which the light scattering pattern 14 is formed may coincide with the vertical lower region of the first electrode 32, but is wider than the vertical lower region of the first electrode 32 in consideration of misalignment. It may have an area. In other words, the region R in which the light scattering pattern 14 is formed may be limited to the region overlapping with the first electrode 32 and the region adjacent thereto.

Although the light scattering pattern 14 is illustrated as overlapping with the bonding pad 32a and the extension part 32e, the light scattering pattern 14 is not limited thereto, and the light scattering pattern 14 is not formed below the extension part 32e, and the bonding pad 32a is provided. It can also be located at the bottom.

9 is a layout diagram illustrating a light emitting diode according to another embodiment of the present invention. The light emitting diode according to the present embodiment is similar to the light emitting diode described with reference to FIGS. 1A to 1C, 6, and 7 except for the following description.

Referring to FIG. 9, the light scattering pattern 14 may be a film having a plurality of through holes 14h. At this time, the through holes 14h are openings defined by the light scattering pattern 14.

The openings in the region R overlapping with the first electrode 32, that is, the width or area of the through holes 14h may be smaller than those in the region not overlapping with the first electrode 32. At this time, the current flow in the light emitting structure can be limited to the through-holes (14h), a region that does not overlap with the first electrode 32 than in the region (R) overlapping with the first electrode (32) The current flow can be greater at. Therefore, the horizontal current spreading in the light emitting structure can be improved. The widths S1 and S2 of the through holes located in the region R overlapping the first electrode 32 may be smaller than the widths S3 of the through holes located in the region not overlapping the first electrode 32.

Furthermore, the region R having a smaller width or area of the through holes 14h may coincide with the vertical lower region of the first electrode 32, but considering misalignment, the region of the first electrode 32 It may have a larger area than the vertical lower region. In other words, the region R having a small width or area of the through holes 14h may be limited to the region overlapping with the first electrode 32 and the region adjacent thereto. In addition, unlike the illustrated embodiment, the region R having a small width or area of the through holes 14h may overlap only the bonding pads 32a except for the extension portion 32e.

10 is a layout diagram illustrating a portion of a light emitting diode according to another embodiment of the present invention. The light emitting diode according to the present embodiment may be similar to the light emitting diode described with reference to FIG. 9 except for the following description.

Referring to FIG. 10, the light scattering pattern 14 having the through holes 14h may be limited to the region R overlapping the first electrode 32. A region that does not overlap the first electrode 32 may be opened without the light scattering pattern 14. At this time, the light emitted from the region located vertically below the first electrode 32 of the active layer (FIG. 1C or 15 of FIG. 7) is scattered by the light scattering pattern 14 so that the first electrode 32 is not formed. May be released to the non-area. Accordingly, the light extraction efficiency can be improved.

In addition, by arranging the light scattering pattern 14 to be limited to the region R overlapping the first electrode 32, the flow of current is first compared to the region R overlapping the first electrode 32. It may be larger in an area not overlapping with the electrode 12. Thus, current spreading in the horizontal direction can be improved. Further, the region R in which the light scattering pattern 14 is formed may coincide with the vertical lower region of the first electrode 32, but has a larger area than the vertical lower region of the first electrode 32 in view of misalignment. Can be. In other words, the region R in which the light scattering pattern 14 is formed may be limited to the region overlapping with the first electrode 32 and the region adjacent thereto.

Although the light scattering pattern 14 is illustrated as being limited to the region overlapping the bonding pad 32a and the extension part 32e and the region R adjacent thereto, the light scattering pattern 14 is not limited thereto. 32e) may not be formed below and may be located only below the bonding pads 32a.

11 is a layout diagram illustrating a light emitting diode according to another embodiment of the present invention. The light emitting diode according to the present embodiment is similar to the light emitting diode described with reference to FIGS. 1A to 1C, 6 and 7 except for the following description.

Referring to FIG. 11, the light scattering pattern 14 may be a line pattern. In this case, the regions 14h between the line patterns are openings defined by the light scattering pattern 14.

The width or area of the opening 14 in the region R overlapping the first electrode 12, that is, the region 14h between the line patterns, may be smaller than that in the region not overlapping the first electrode 32. . At this time, the current flow in the light emitting structure may be greater in the region not overlapping with the first electrode 32 than in the region R overlapping with the first electrode 32. Therefore, the horizontal current spreading in the light emitting structure can be improved. Further, the region R having a smaller width or area of the region 14h between the line patterns may coincide with the vertical lower region of the first electrode 32, but considering the misalignment, the first electrode It may be wider than the vertical lower region of 32. In other words, the region R having a small width or area of the region 14h between the line patterns may be limited to the region overlapping with the first electrode 32 and the region adjacent thereto. In addition, unlike the illustrated embodiment, the region R having a small width or area of the through holes 14h may overlap only the bonding pads 32a except for the extension part 32e.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes by those skilled in the art within the spirit and scope of the present invention. This is possible.

Claims (43)

1. A first conductivity type clad layer;

   A light scattering pattern having a refractive index different from that of the first conductive clad layer in the first conductive clad layer;

   An active layer under the first conductive clad layer;

   A second conductive clad layer disposed under the active layer;

   A first electrode electrically connected to the first conductive clad layer; And

   A light emitting diode comprising a second electrode electrically connected to the second conductive cladding layer.
2. The method of claim 1,

   The light scattering pattern overlaps with the first electrode.
3. The method of claim 2,

   The light scattering pattern is a light emitting diode positioned in a region overlapping with the first electrode and a region adjacent thereto.
4. The method of claim 1,

   The first electrode has a bonding pad and an extension,

   The light scattering pattern is positioned below the bonding pad but not below the extension.
5. The method of claim 1,

   The light emitting diode having a width of the opening defined by the light scattering pattern is smaller than a region in which the first electrode overlaps with the first electrode.
6. The method of claim 1,

   The light scattering pattern is a light emitting diode having a plurality of dots, a plurality of lines, or a plurality of through holes.
7. The method of claim 1,

   The light scattering pattern is a light emitting diode having a refractive index smaller than that of the first conductive cladding layer.
8. The method of claim 1,

   The light scattering pattern is a light emitting diode in which films having different refractive indices are alternately stacked.
9. The method of claim 1,

   The first conductive cladding layer has a plurality of grooves etched along a defect in an upper surface thereof.
10. The method of claim 9,

    The concentration of impurities in the protrusions defined by the grooves is higher than the concentration of impurities in the first conductive type clad layer.
11. The method of claim 10,

    The impurity is a light emitting diode of the first conductivity type dopant.
12. The method of claim 9,

    And the levels of the bottom portions of the grooves are lowered toward the outer portion from the center of the upper surface of the first conductive clad layer.
13. The method of claim 9,

    An upper surface of the first conductive cladding layer has a portion where the grooves are formed and a portion where the grooves are not formed,

    The first electrode is on the portion where the grooves of the first conductive clad layer are not formed.
14. The method of claim 9,

    The first electrode is a light emitting diode located on a portion where the grooves are formed.
15. The method according to claim 13 or 14,

    The light emitting diode of claim 1, further comprising an insulating pattern disposed between the first conductive cladding layer and the first electrode.
16. The method of claim 9,

    The first conductive cladding layer includes a main first conductive cladding layer and an auxiliary first conductive cladding layer.

    The light emitting diode further includes an intrinsic clad layer positioned between the main first conductive clad layer and the auxiliary first conductive clad layer.

    The grooves are formed in the auxiliary first conductive cladding layer.
17. The method of claim 16,

    At least a portion of the bottoms of the grooves abut the intrinsic clad layer.
18. A first conductivity type clad layer;

    An active layer under the first conductive clad layer;

    A second conductive clad layer disposed under the active layer;

    A first electrode electrically connected to the first conductive clad layer; And

    A second electrode electrically connected to the second conductive cladding layer,

    A light emitting diode in which a dielectric pattern is located in the first conductive cladding layer, and a width of an opening defined by the dielectric pattern is smaller than a region in which an area overlapping with the first electrode does not overlap with the first electrode.
19. A one-conductive cladding layer having a plurality of grooves and protrusions defined by the grooves in an upper surface thereof;

    An active layer under the first conductive clad layer; And

    A second conductive cladding layer disposed under the active layer;

    The concentration of impurities in the protrusions is higher than the concentration of impurities in the interior of the first conductive clad layer.
20. Forming an auxiliary first conductive clad layer;

    Forming a light scattering pattern having a refractive index different from that of the auxiliary first conductive clad layer on the auxiliary first conductive clad layer;

    Forming a main first conductive clad layer on the light scattering pattern;

    Forming an active layer on the main first conductive clad layer;

    Forming a second conductive cladding layer on the active layer;

    And forming an electrode electrically connected to the auxiliary first conductive cladding layer.
21. The method of claim 20,

    The light scattering pattern is a light emitting diode manufacturing method formed so as to overlap with the electrode.
22. The method of claim 21,

    The light scattering pattern is a light emitting diode manufacturing method to be formed so as to be limited to the region overlapping with the electrode adjacent to the region.
23. The method of claim 20,

    The electrode has a bonding pad and an extension,

    The light scattering pattern is positioned in an area overlapping with the bonding pad but not in an area overlapping the extension.
24. The method of claim 20,

    The width of the opening defined by the light scattering pattern is narrower than the region in the region overlapping with the electrode does not overlap with the electrode.
25. The method of claim 20,

    The light scattering pattern is a light emitting diode manufacturing method of forming a film having a plurality of dots, a plurality of lines, or a plurality of through holes.
26. The method of claim 20,

    The light scattering pattern is a light emitting diode manufacturing method of the refractive index is smaller than the first conductive type cladding layer.
27. The method of claim 20,

    The light scattering pattern is a light emitting diode manufacturing method in which the films having different refractive indexes are alternately stacked.
28. The method of claim 20,

    The auxiliary first conductive cladding layer is formed on a growth substrate,

    And forming the auxiliary first conductive clad layer by removing the growth substrate before forming the electrode.
29. The method of claim 28,

    Wherein the growth substrate is a GaN substrate and the auxiliary first conductive clad layer is a GaN layer.
30. The method of claim 20,

    Before forming the electrode,

    Creating a defect in the top surface of the auxiliary first conductivity type clad layer; And

    Etching the defect to form a plurality of grooves in an upper surface of the auxiliary first conductive cladding layer.
31. The method of claim 30,

    The method of manufacturing a light emitting diode in which a defect is generated in the surface of the auxiliary first conductive cladding layer is implanted with impurities in the surface of the auxiliary first conductive cladding layer.
32. The method of claim 31, wherein

    The impurity is a light emitting diode manufacturing method of the first conductivity type dopant.
33. The method of claim 30,

    Forming the plurality of grooves is a light emitting diode manufacturing method using a wet etching method.
34. The method of claim 33, wherein

    The wet etching method is a light-emitting diode manufacturing method of photo-enhanced chemical etching (Photo-Enhanced Chemical etching) method.
35. The method of claim 30,

    In creating a defect in the surface of the auxiliary first conductive cladding layer,

    The depth of the defect from the central portion of the upper surface of the auxiliary first conductivity-type cladding layer toward the outer portion of the light emitting diode manufacturing method.
36. 36. The method of claim 35 wherein

    The defect is created by impurity implantation,

    And a projected range (Rp) of the implanted impurity is deepened from the center of the surface of the auxiliary first conductive clad layer toward the outer portion.
37. The method of claim 36,

    Before injecting the impurities,

    And forming a mask layer on the upper surface of the auxiliary first conductive cladding layer, the mask layer having a reduced thickness in the outward direction from the center of the surface of the auxiliary first conductive cladding layer.
38. The method of claim 30,

    And the electrode is formed on the surface of the auxiliary first conductive clad layer before or after the grooves are formed.
39. The method of claim 38,

    Before forming the electrode, further comprising forming an insulating pattern on the surface of the auxiliary first conductive cladding layer;

    The electrode is a light emitting diode manufacturing method formed on the insulating pattern.
40. The method of claim 30,

    Before forming the light scattering pattern,

    A method of manufacturing a light emitting diode further comprising forming an intrinsic clad layer on the auxiliary first conductive cladding layer.
41. The method of claim 40,

    At least some of the bottoms of the grooves abut the intrinsic clad layer.
42. The method of claim 30,

    The auxiliary first conductive cladding layer, the light scattering pattern, the main first conductive cladding layer, the active layer, and the second conductive cladding layer are sequentially formed on a growth substrate.

    And removing the growth substrate to expose the top surface of the auxiliary first conductive clad layer before producing the defect.
43. The method of claim 42, wherein

    Wherein the growth substrate is a GaN substrate and the auxiliary first conductive clad layer is a GaN layer.

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