WO2013120247A1 - Procédé, dispositif et système pour faire correspondre des mots de code de correction d'erreur sans voie de retour avec une structure de trame - Google Patents

Procédé, dispositif et système pour faire correspondre des mots de code de correction d'erreur sans voie de retour avec une structure de trame Download PDF

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Publication number
WO2013120247A1
WO2013120247A1 PCT/CN2012/071100 CN2012071100W WO2013120247A1 WO 2013120247 A1 WO2013120247 A1 WO 2013120247A1 CN 2012071100 W CN2012071100 W CN 2012071100W WO 2013120247 A1 WO2013120247 A1 WO 2013120247A1
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Prior art keywords
fec
frame structure
frame
signal
length
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PCT/CN2012/071100
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English (en)
Chinese (zh)
Inventor
金丽丽
李扬
赵羽
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华为技术有限公司
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Priority to PCT/CN2012/071100 priority Critical patent/WO2013120247A1/fr
Priority to CN201280000070.6A priority patent/CN102754378B/zh
Publication of WO2013120247A1 publication Critical patent/WO2013120247A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a method, apparatus, and system for matching a frame structure of a Forward Error Correction (FEC) codeword into a frame structure.
  • FEC Forward Error Correction
  • FEC Forward Error Correction
  • the frame structure in which the FEC codeword is matched refers to an operation of performing FEC encoding after the FEC encoding of the signal to form an FEC encoded signal, and then matching the FEC encoded signal to a frame structure of another format, for example, FEC encoding
  • the post signal is matched to the operation of the optical channel transport unit k (OTUk, Optical Channel Transport Unit k) for transmission, and so on.
  • FIG. 1a is a schematic diagram of a format of a conventional OTUk frame, where 1 to 3824 bytes are a frame header portion and a payload portion of an Optical Channel Transport Unit (OTU).
  • the information bits for storing the FEC are called FEC information bits, and the 3824 ⁇ 4080 bytes are FEC parts, which are used to store the FEC overhead bits, and the cartridge is called the FEC overhead bit.
  • the signal transmitting end generally performs the FEC overhead after the FEC information bits are transmitted.
  • the transmission of the bit at the same time, a large amount of random access memory (RAM) is used to store the FEC information bits at the signal receiving end, waiting for the arrival of the FEC overhead bit, and the FEC information bit and the FEC overhead bit are After the modulo, the decoder will take the corresponding FEC information bits and FEC overhead bits from the RAM to restore the FEC encoded signal, and then decode the restored FEC encoded signal to obtain the original signal.
  • RAM random access memory
  • the inventors of the present invention have found that in the existing method of matching the FEC codeword into a frame structure, since it is necessary to wait for the FEC information bit and the FEC overhead bit to be aligned, In order to decode, the delay is large, and a large amount of RAM is needed to store the FEC information bits and the FEC overhead bits, which wastes RAM resources.
  • Embodiments of the present invention provide a method for matching an FEC codeword into a frame structure, a method for de-matching a frame structure into an FEC codeword, and a corresponding apparatus and system, which can reduce delay and save RAM resources.
  • a method of matching FEC codewords into a frame structure comprising:
  • the FEC encoded signal is matched to the OTU frame structure in accordance with the number of FEC codewords that can be carried.
  • a method for dematching a frame structure into a FEC codeword comprising:
  • An apparatus for matching FEC codewords into a frame structure comprising:
  • a coding unit configured to perform FEC encoding on the received optical signal to obtain an FEC encoded signal
  • a determining unit configured to determine a code length of the FEC codeword, and a frame length of the OTU frame structure
  • a calculating unit configured to Code length and frame length calculate the number of FEC codewords that can be carried in each row of the OTU frame structure
  • a matching unit configured to match the FEC encoded signal into the OTU frame structure according to the number of the bearable FEC codewords.
  • An apparatus for deserializing a frame structure into a FEC codeword comprising:
  • a receiving unit configured to receive a signal after the frame structure is matched, where the signal matched by the frame structure is a signal transmitted through an OTU frame structure;
  • a determining unit configured to determine a frame length of an OTU frame structure used by the frame structure matched signal, and determine a code length of the FEC codeword;
  • a calculating unit configured to calculate, according to the frame length and the code length, a quantity of FEC codewords that can be carried in each row in the OTU frame structure;
  • a de-matching unit configured to extract the matched signal of the frame structure according to the number of the FEC codewords that can be carried, to obtain a FEC encoded signal.
  • a communication system comprising any of the means for matching a forward error correction codeword into a frame structure and any means for dematching a frame structure into a forward error correction codeword.
  • the embodiment of the present invention uses the FEC coded signal to match the FEC encoded signal to the OTU frame structure, the information bit and the overhead bit of the FEC codeword need to be separately separated from the prior art.
  • the signal receiving end receives the signal matched by the frame structure, it does not need to use a large amount of RAM to store the FEC information bit and the FEC overhead bit, so as to wait for the FEC information bit and the FEC overhead bit to be aligned before decoding, but directly It is possible to decode, because in this scheme, the FEC information bit and the FEC overhead bit can arrive at the receiving end together, that is to say, by adopting this scheme, not only the delay can be reduced, but also the RAM resource can be saved.
  • the embodiment of the present invention further provides a corresponding method and device for de-matching a frame structure into an FEC codeword, and the solution matching method and device have the same beneficial effects as the above matching method and device, that is, not only Reduce latency and save RAM resources.
  • Figure la is a schematic diagram of the format of a conventional OTUk frame
  • FIG. 2 is a flowchart of a method for matching FEC to a frame structure according to an embodiment of the present invention
  • FIG. 2 is a flowchart of a method for dematching a frame structure into an FEC codeword according to an embodiment of the present invention
  • FIG. 3b is another flowchart of a method for matching FEC codewords into a frame structure according to an embodiment of the present invention
  • FIG. 3c is a schematic diagram of a format of a structure-matched OTUk frame (frame length is 4080 bytes) according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a first bit width conversion module according to an embodiment of the present invention.
  • FIG. 3e is another flow chart of a method for dematching a frame structure into an FEC codeword according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a second bit width conversion module according to an embodiment of the present disclosure
  • FIG. 4a is still another flowchart of a method for matching FEC codewords into a frame structure according to an embodiment of the present invention
  • 4b is a schematic diagram of a format of a structure-matched OTUk frame (frame length of 4600 bytes) according to an embodiment of the present invention
  • 4c is a schematic structural diagram of a third bit width conversion module according to an embodiment of the present invention.
  • 4d is still another flowchart of a method for de-matching a frame structure into an FEC codeword according to an embodiment of the present invention
  • 4e is a schematic structural diagram of a third bit width conversion module according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of an apparatus for matching an FEC codeword into a frame structure according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of an apparatus for de-matching a frame structure into an FEC codeword according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of a communication system according to an embodiment of the present invention.
  • Embodiments of the present invention provide a method for matching a FEC codeword into a frame structure, a method for dematching a frame structure into a FEC codeword, and a corresponding apparatus and system. The details are described below separately.
  • Embodiment 1
  • a method for matching an FEC codeword into a frame structure comprising: performing FEC encoding on the received optical signal to obtain a FEC encoded signal; determining a code length of the FEC codeword, and a frame length of the OTU frame structure; The length and frame length are calculated by the number of FEC codewords that can be carried in each row of the OTU frame structure; the FEC encoded signal is matched into the OTU frame structure according to the number of FEC codewords that can be carried.
  • Each FEC codeword may specifically include an FEC information bit and a FEC overhead bit, and the FEC codeword code length refers to a total bit width of the FEC information bit and the FEC overhead bit. That is, the step "determining the code length of the FEC codeword" can be:
  • the number of FEC codewords that can be carried in each row in the OTU frame structure is calculated based on the total bit width determined in step 102 and the frame length of the OTU frame structure.
  • the FEC codewords RS take 7% of the FEC codewords RS (255, 239) as an example.
  • RS Random-Solomon codes
  • BCH Bose-Chaudhuri-Hocquengham
  • the optical signal may be accelerated before encoding, which may be as follows:
  • the received optical signal is matched to the frame structure before encoding, so that 1 byte to 3824 bytes in the frame are payloads, and the bytes after 3824 bytes are all zero; that is, 1 ⁇ 3824 bytes in the frame are used as FEC
  • the information bits, and the bytes after 3824 bytes are filled with zeros. For example, taking OTUk with a frame length of 4080 bytes as an example, at this time, 1 ⁇ 3824 bytes in the frame can be used as information bits of FEC, and 3824 ⁇ 4080 bytes are filled with zero, and so on, etc. .
  • the frame length of the frame structure used in the pre-encoding frame structure matching is equal to the frame length of the OTU frame structure used in the frame structure matching performed in step 102.
  • the frame structure used in step 102 is also an OTUk with a frame length of 4080 bytes; if an OTUk with a frame length of 4600 bytes is used here, Then, the frame structure adopted in step 102 is also an OTUk with a frame length of 4600 bytes.
  • the FEC encoded signal is matched into the OTU frame structure in a manner of one FEC codeword. Therefore, the information bits and overhead bits of the FEC codeword need to be separated from the prior art.
  • the signal receiving end receives the signal matched by the frame structure, it does not need to use a large amount of RAM to store the FEC information bit and the FEC overhead bit, waiting for the FEC information bit and the FEC overhead bit to be aligned.
  • Decoding but directly can be decoded, because in this solution, the FEC information bit and the FEC overhead bit can arrive at the receiving end together, that is to say, the scheme can not only reduce the delay but also save RAM resources.
  • a method for de-matching a frame structure into an FEC codeword comprising: receiving a signal with a frame structure matching, wherein the signal matched by the frame structure is a signal transmitted through an OTU frame structure; determining a signal structure after the frame structure is matched The frame length of the adopted OTU frame structure, and determining the code length of the FEC codeword; calculating the number of FEC codewords that can be carried in each row of the OTU frame structure according to the determined frame length and code length; The frame-matched signal is extracted according to the number of FEC codewords that can be carried, to obtain an FEC-encoded signal.
  • the signal matched by the frame structure is an optical signal obtained by using the method of “matching the FEC codeword into a frame structure” in the first embodiment, that is, the signal matched by the frame structure is transmitted through the OTU frame structure.
  • Each FEC codeword may specifically include an FEC information bit and an FEC overhead bit
  • the FEC codeword code length refers to a total bit width of the FEC information bit and the FEC overhead bit, that is, the step "determines the code of the FEC codeword.
  • the length can be:
  • the number of FEC codewords that can be carried in each row in the optical transport unit frame structure is calculated based on the frame length and total bit width of the OTU frame structure confirmed in step 202.
  • the FEC codewords RS take 7% of the FEC codewords RS (255, 239) as an example.
  • step 201 According to the number of FEC codewords that can be carried in each row in the OTU frame structure, in step 201.
  • the received frame structure matched signal is extracted to obtain an FEC encoded signal.
  • the FEC-encoded signal is obtained (ie, step 202), and may further include:
  • the FEC encoded signal is FEC decoded to obtain the FEC decoded signal; the FEC overhead bit is truncated for each FEC codeword in the FEC decoded signal to obtain the FEC information bit.
  • the code length of the FEC codeword needs to be truncated by 16 bits to obtain 239 bits of information bits.
  • the present embodiment is a de-matching method corresponding to the method for matching the forward error correction codeword into a frame structure provided in Embodiment 1, because in this solution, the FEC information bit and the FEC overhead bit can be together.
  • the frame format de-matching device then de-interleaves the received frame structure-matched signals in units of one FEC codeword, so that a large amount of RAM is not required to store the FEC information bits and the FEC overhead bits.
  • the decoding can be performed directly, that is to say, the scheme can not only reduce the delay but also save the RAM resources.
  • the OTU will be exemplified below, and will be further described in detail in Embodiments 3 and 4.
  • FIG. 3a the figure is a schematic diagram of a scene structure matching system of an FEC.
  • a device for matching an FEC codeword into a frame structure and a device for dematching a frame structure into an FEC codeword are as follows:
  • the device for matching the FEC codeword into the frame structure may include a frame structure matching transmitting end (wdm_frame_match_tx) on the wavelength division side, and may further include a frame structure matching receiving end (cli_frame_match_rx) on the client side, and a demultiplexing module.
  • wdm_frame_match_tx a frame structure matching transmitting end
  • cli_frame_match_rx a frame structure matching receiving end
  • demultiplexing module Multi-lane Distributor
  • FEC coding module Fec_Encoder
  • Multiplexer module Multi-lane Plexer
  • Inter leaver Inter leaver
  • the apparatus for de-matching the frame structure to the FEC codeword may include a frame structure matching receiving end (wdm_frame_match_rx) on the wavelength division side, and may further include a frame structure matching transmitting end (cli_frame_match_tx) on the client side, and a multiplexing module.
  • FEC decoding module, demultiplexing module and de-interleaving module (De-Inter leaver).
  • the functions of the above modules can be as follows:
  • the frame structure of the client side matches the receiving end: mainly realizes the conversion of the bit width of the OTUk frame to the information bit length of the FEC;
  • the frame structure of the client side matches the transmitting end: mainly realizes the conversion of the information bit length of the FEC to the parallel processing bit width of the OTUk frame;
  • the frame structure of the wavelength division side matches the transmitting end: mainly realizes the conversion of the code length of the FEC code word to the parallel processing bit width of the OTUk frame;
  • the frame structure of the wavelength division side matches the receiving end: mainly realizes the conversion of the bit width of the OTUk frame to the code length of the FEC code word;
  • FEC coding module mainly used for encoding the signal by FEC
  • FEC decoding module mainly used for decoding FEC signals
  • Multiplexing module mainly used to multiplex signals
  • Demultiplexing module mainly used for demultiplexing signals
  • Interleaving module mainly used for signal interleaving
  • the following describes the specific execution flow of the FEC frame structure matching system by taking the 7% FEC codeword RS (255, 239) in the 10G optical communication system as an example.
  • the process of matching the FEC codewords into a frame structure may be as follows:
  • the frame structure on the client side matches the receiving end to receive the optical signal, where the optical signal is transmitted in the form of an OTUk frame.
  • the frame structure matching on the client side performs the conversion of the OTUk frame parallel processing bit width m to the FEC information bit length k on the received optical signal, and then the converted optical signal is sent to the FEC encoding module.
  • the frame length of the OTUk frame is 4080 bytes, and the parallel processing bit width m of the OTUk frame is 64 bits, and the FEC information bit length k is 239 bits.
  • the received OTUk frame may be processed to achieve a coding precondition, for example, 1 to 3824 bytes in the OTUk frame may be used as the FEC information. Bits, and 3824 ⁇ 4080 bytes are filled with zero.
  • the converted optical signal may be multiplexed by the multiplexing module, and then the multiplexed optical signal is transmitted to the FEC encoding module.
  • the A303 and the FEC encoding module perform FEC encoding on the optical signal sent in step A302 to obtain a FEC encoded signal, and transmit the FEC encoded signal to the frame structure of the wavelength division side to match the transmitting end.
  • the FEC encoded signal needs to be demultiplexed by the demultiplexing module at this time, and the interleaving module may also be used.
  • the demultiplexed optical signal is interleaved to achieve anti-burst error.
  • the frame structure matching on the wavelength division side receives the FEC encoded signal transmitted in step A303, determines the code length of the FEC codeword, and determines the frame length of the OTUk.
  • the code length of the FEC codeword is 255 bits
  • the frame length of the OTUk is 4080 bytes.
  • the frame structure matching transmitter on the wavelength division side calculates the number of FEC codewords that can be carried in each row in the OTUk frame according to the determined code length of the FEC codeword and the frame length of the OTUk.
  • Each row can carry 128 codewords, that is, every 128 FEC codewords form a row of an OTUk frame.
  • the frame structure matching on the wavelength division side matches the FEC encoded signal to the OTUk frame according to the number of FEC codewords that can be carried in each row of the OTUk frame, that is, the FEC is encoded according to the 128 FEC codewords in each row.
  • the signal is matched into the OTUk frame, as shown in Figure 3c.
  • the FEC information bits and the FEC overhead bits are not placed separately, but the FEC information bits and the FEC overhead bits are placed together as a whole, so that when the OTUk frame is transmitted, the FEC information bits and the FEC are placed.
  • the overhead bits will arrive at the signal receiver together.
  • the following method may be used to match the FEC encoded signal to the OTUk frame, and: 3 ⁇ 4 port:
  • the code length of the FEC codeword can be first matched to the parallel processing bit width of the OTUk, and then the FEC codeword is sequentially filled into the OTUk frame, wherein each row of the OTUk frame can carry 128 FEC codewords.
  • the operation may be implemented by a first bit width conversion module, the first bit width conversion module package.
  • Four shift registers D with a bit width of 255 bits are included, as well as a thread counter (Line_cnt), a match counter (Match_Ctrl), and two signal selectors. This saves 4 shifts compared to the prior art requiring 8 shift registers D with a bit width of 255 bits, and a thread counter (Line_cnt), two match counters (Match_Ctrl), and two signal selectors.
  • Bit register D which saves 4 RAMs (because the prior art requires separate processing of information bits and overhead bits, it requires duplicate devices).
  • the process of the method for de-matching the frame structure into the FEC codeword may be as follows: B301.
  • the frame structure on the wavelength division side matches the signal received by the receiving end to receive the frame structure, where the frame structure is matched.
  • the frame structure of the wavelength division side matches the receiving end to determine the code length of the FEC codeword, and determines the frame length of the OTUk.
  • the code length of the FEC codeword is 255 bits
  • the frame length of the OTUk is 4080 bytes.
  • the frame structure matching receiving end of the wavelength division side calculates the number of FEC codewords that can be carried in each row of the OTUk frame according to the determined code length of the FEC codeword and the frame length of the OTUk.
  • a row can carry 128 codewords, that is, every 128 FEC codewords form a row of an OTUk frame.
  • the receiving end extracts the OTUk frame received in step B301 according to the number of FEC codewords that can be carried in each row of the OTUk frame, and obtains the FEC encoded signal, that is, 128 FEC codes per row.
  • the manner of the word extracts the signal matched by the frame structure received in step B301, and obtains the FEC encoded signal.
  • the parallel processing bit width of the OTUk can be first matched to the code length of the FEC codeword, and then the corresponding signal is extracted from the OTUk frame to obtain the FEC encoded signal.
  • the operation may be specifically implemented by the second bit width conversion module, and the second bit width conversion module may include 4 A shift register D with a bit width of 255 bits, and a thread counter (Line_cnt), a match counter (Match_Ctrl), and two signal selectors.
  • the decoder since the overhead bit is received when the information bit is received, the decoder does not need to wait any more, but can directly decode the signal every time 255 bits are received, so compared with the prior art, It also saves about 10 microseconds ( ) and, since the decoder does not need to wait any longer, it does not require RAM for storage, saving up to 6 RAMs, which means a total of about 10 RAM can be saved.
  • the B305 and FEC decoding modules perform FEC decoding on the FEC encoded signal to obtain a FEC decoded signal, and transmit the FEC decoded signal to the client side frame structure matching transmitting end.
  • the frame structure matching on the client side intercepts the signal after the FEC decoding, and obtains the FEC information bit, that is, the Fbit code length of 255 bits is truncated after 16 bits of the overhead bit, and the information bit of the first 239 bits is obtained, and then the information of 239 bits is obtained.
  • the bit is converted into an OTUk frame with a processing bit width of 64 bits, that is, in the OTUk frame, only the information bits of the FEC are reserved, and the overhead bits of the FEC are discarded, and the positions of 3824 to 4080 bytes are still filled in, so that A signal having the same structure as the optical signal received in step A301 is obtained.
  • the FEC encoded signal needs to be deinterleaved by the deinterleaving module.
  • the deinterleaved optical signal can also be multiplexed by the multiplexing module, and then sent to the FEC decoding module for decoding, and then the FEC decoded signal is demultiplexed by the demultiplexing module, and finally The frame structure delivered to the client side matches the transmitting end for processing.
  • the FEC encoded signal is matched to the OTUk frame in a manner of one FEC codeword. Therefore, the information bit and the overhead bit of the FEC codeword need to be separately placed in the prior art.
  • the signal receiving end when receiving the OTUk frame, the signal receiving end does not need to use a large amount of RAM to store the FEC information bits and the FEC overhead bits, so as to wait for the FEC information bits and the FEC overhead bits to be aligned before decoding, It can be decoded directly, because in this scheme, the FEC information bit and the FEC overhead bit can reach the receiving end together, that is to say, by adopting this scheme, not only the delay can be reduced, but also the RAM resource can be saved. Further, Since the amount of RAM can be reduced, the structure of the FEC frame structure matching system is relatively relatively compact. Embodiment 4
  • the embodiment also takes the FEC frame structure matching system shown in FIG. 3a as an example, except that in this embodiment, it will be used for the 20% FEC code in the 10G submarine cable system.
  • the word BCH ( 336, 280 ) is taken as an example for explanation.
  • the process of matching the FEC codewords into a frame structure may be specifically as follows:
  • the frame structure on the client side matches the receiving end to receive the optical signal, where the optical signal is transmitted in the form of an OTUk frame.
  • the frame structure on the client side matches the receiving end and performs OTUk frame parallel processing on the received optical signal to convert the bit width m to the FEC information bit length k, and then delivers the converted optical signal to the FEC encoding module.
  • the frame length of the OTUk is 4600 bytes, and the parallel processing bit width m of the OTUk is 64 bits, and the FEC information bit length k is 280 bits.
  • the received optical signal may be processed to achieve a coding precondition, for example, 1 to 3824 bytes in the OTUk may be used as the FEC information bit. , and 3824 ⁇ 4600 bytes are filled with zero.
  • the converted optical signal may be multiplexed by the multiplexing module, and then the multiplexed optical signal is transmitted to the FEC encoding module.
  • the FEC encoding module performs FEC encoding on the optical signal sent in step A402 to obtain a FEC encoded signal, and transmits the FEC encoded signal to the frame structure of the wavelength division side to match the transmitting end.
  • the FEC encoded signal needs to be demultiplexed by the demultiplexing module at this time, and the interleaving module may also be used.
  • the demultiplexed optical signal is interleaved to achieve anti-burst error.
  • the frame structure matching on the wavelength division side receives the FEC encoded signal transmitted in step A402, determines the code length of the FEC codeword, and determines the frame length of the OTUk.
  • the code length of the FEC code word is 336 bits
  • the frame length of the OTUk is 4600 bytes.
  • the frame structure of the wavelength division side matches the transmitting end according to the determined code length of the FEC codeword and the OTUk
  • the frame length calculates the number of FEC codewords that can be carried in each row of the OTUk frame.
  • a row can carry about 110 codewords, that is, every 110 FEC codewords form a row of an OTUk frame.
  • the frame length of the OTUk is not an integer multiple of the code length of the FEC codeword
  • the last codeword that is, the code length of the FEC codeword of the 110th codeword
  • each row of OTUk The last 48 bits of the frame are fixedly padded to zero.
  • the frame structure matching on the wavelength division side matches the FEC encoded signal in the OTUk frame according to the number of FEC codewords that can be carried in each row of the OTUk frame, that is, the FEC is encoded according to the manner of 110 FEC codewords per row.
  • the signal is matched into the OTUk frame. See Figure 4b for details.
  • the FEC information bits and the FEC overhead bits are not placed separately, but the FEC information bits and the FEC overhead bits are placed together as a whole, so that when the OTUk frame is transmitted, the FEC information bits and the FEC are placed.
  • the overhead bits will arrive at the signal receiver together.
  • the following method may be used to match the FEC encoded signal to the OTUk frame, and: 3 ⁇ 4 port:
  • the code length of the FEC codeword can be first matched to the parallel processing bit width of the OTUk, and then the FEC codeword is sequentially filled into the OTUk frame, wherein each row of the OTUk frame can carry 110 FEC codewords.
  • the operation may be specifically implemented by a third bit width conversion module, and the third bit width conversion module may include 6 A shift register D having a bit width of 336 bits, and a thread counter (Line_cnt), a matching counter (Match_Ctrl), and two signal selectors.
  • the third bit width conversion module may include 6 A shift register D having a bit width of 336 bits, and a thread counter (Line_cnt), a matching counter (Match_Ctrl), and two signal selectors.
  • it requires 12 shift registers D with a bit width of 255 bits, and one thread counter (Line_cnt ), two matching counters ( Match_Ctrl ) and two signal selectors, which can save 6 shifts.
  • Bit register D which saves 6 RAMs (because the prior art requires separate processing of information bits and overhead bits, it requires duplicate devices).
  • the process of the method for de-matching the frame structure into the FEC codeword may be as follows: B401, the frame structure on the wavelength division side matches the signal received by the receiving end to receive the frame structure, where the signal after the frame structure is matched is The OTUk frame output after the processing in step A405. B402. The frame structure of the wavelength division side matches the receiving end to determine the code length of the FEC codeword, and determines the frame length of the OTUk.
  • the code length of the FEC code word is 336 bits
  • the frame length of the OTUk is 4600 bytes.
  • the frame structure matching receiving end of the wavelength division side calculates the number of FEC codewords that can be carried in each row of the OTUk frame according to the determined code length of the FEC codeword and the frame length of the OTUk.
  • a row can carry 128 codewords, that is, every 128 FEC codewords form a row of an OTUk frame.
  • the receiving end extracts the OTUk frame received in step B401 according to the number of FEC codewords that can be carried in each row of the OTUk frame, and obtains the FEC encoded signal, that is, 110 FEC codes per row.
  • the word mode is extracted from the OTUk frame received in step B401 to obtain an FEC encoded signal.
  • the parallel processing bit width of the OTUk can be first matched to the code length of the FEC codeword, and then the corresponding signal is extracted from the OTUk frame to obtain the FEC encoded signal.
  • the operation may be specifically implemented by a fourth bit width conversion module, and the fourth bit width conversion module may include 6 A shift register D having a bit width of 336 bits, and a thread counter (Line_cnt), a matching counter (Match_Ctrl), and two signal selectors.
  • the fourth bit width conversion module may include 6 A shift register D having a bit width of 336 bits, and a thread counter (Line_cnt), a matching counter (Match_Ctrl), and two signal selectors.
  • it requires 12 shift registers D with a bit width of 336 bits, and one thread counter (Line_cnt ), two matching counters ( Match_Ctrl ) and two signal selectors, which can save 6 shifts.
  • Bit register D which saves 6 RAMs (because the prior art requires separate processing of information bits and overhead bits, a duplicate device is required).
  • the decoder since the overhead bit is received when the information bit is received, the decoder does not need to wait any more, but can directly decode the signal every time it receives the 336 bits, so compared with the prior art, It also saves about 10 microseconds ( ) and, since the decoder does not need to wait, it does not require RAM for storage, saving up to 6 RAMs, which means a total of about 12 RAM can be saved.
  • the B405 and the FEC decoding module perform FEC decoding on the FEC encoded signal to obtain a FEC decoded signal, and transmit the FEC decoded signal to the client side frame structure matching transmitting end.
  • the frame structure matching on the client side intercepts the FEC decoded signal, and obtains the FEC information bit, which is the 56 bits overhead bit after the FEC code length is 336 bits, and obtains the information bits of the first 280 bits, and then the information of 280 bits.
  • the bit is converted into an OTUk frame with a processing bit width of 64 bits, that is, in the OTUk frame, only the information bits of the FEC are reserved, and the overhead bits of the FEC are discarded, and the position of 3824 ⁇ 4600 bytes is still filled with zero, so that A signal having the same structure as the optical signal received in step A401 is obtained.
  • the FEC encoded signal needs to be deinterleaved by the deinterleaving module.
  • the deinterleaved optical signal can also be multiplexed by the multiplexing module, and then sent to the FEC decoding module for decoding, and then the FEC decoded signal is demultiplexed by the demultiplexing module, and finally The frame structure delivered to the client side matches the transmitting end for processing.
  • the FEC encoded signal is matched to the OTUk frame in a manner of one FEC codeword. Therefore, the information bits and overhead bits of the FEC codeword need to be separately placed in the prior art.
  • the signal receiving end does not need to use a large amount of RAM to store the FEC information bits and the FEC overhead bits, so as to wait for the FEC information bits and the FEC overhead bits to be aligned before decoding, but directly Capable of decoding, because in this scheme, the FEC information bit and the FEC overhead bit can arrive at the receiving end together, that is, using this scheme can not only reduce the delay but also save RAM resources.
  • an apparatus for matching an FEC codeword into a frame structure is provided. , determining unit 502, calculating unit 503 and matching unit 504;
  • the encoding unit 501 is configured to perform FEC encoding on the received optical signal to obtain a FEC encoded signal
  • a determining unit 502 configured to determine a code length of the FEC codeword, and a frame length of the OTU frame structure;
  • the frame length of the OTUk frame may be 4080 bytes, or may be 4600 bytes, and so on;
  • the calculating unit 503 is configured to calculate each line in the OTU frame structure according to the code length and the frame length determined by the determining unit 502. The number of FEC codewords carried;
  • the matching unit 504 is configured to match the FEC encoded signal into the OTU frame structure according to the number of FEC codewords that can be carried in each row in the OTU frame structure obtained by the computing unit 503.
  • Each FEC codeword may specifically include a FEC information bit and a FEC overhead bit, and the FEC codeword code length refers to a total bit width of the FEC information bit and the FEC overhead bit, that is,
  • the determining unit 502 is specifically configured to determine a total bit width of the FEC information bit and the FEC overhead bit, and a frame length of the OTU frame structure;
  • the calculating unit 503 is specifically configured to calculate the number of FEC codewords that can be carried in each row in the OTU frame structure according to the total bit width determined by the determining unit 502 and the frame length of the OTU frame structure.
  • the FEC codewords RS take 7% of the FEC codewords RS (255, 239) as an example.
  • the encoding unit 501 performs FEC encoding on the received optical signal, and before the FEC encoded signal is obtained, the optical signal may be accelerated before encoding, that is, the FEC codeword is matched into
  • the frame structure device may further include a speed increasing unit;
  • the speed increasing unit is configured to match the received optical signal to the frame structure before encoding, so that 1 byte to 3824 bytes in the frame are payloads, and the bytes after 3824 bytes are all zero; that is, 1 ⁇ in the frame 3824 bytes are used as information bits for FEC, and bytes after 3824 bytes are filled with zeros.
  • 1 ⁇ in the frame 3824 bytes are used as information bits for FEC, and bytes after 3824 bytes are filled with zeros.
  • an OTUk with a frame length of 4080 bytes is taken as an example.
  • 1 ⁇ 3824 bytes in the frame can be used as the information bit of the FEC.
  • 3824 ⁇ 4080 bytes are filled with zeros, and so on.
  • the frame length of the OTU frame structure is equal to the frame length of the frame structure used in the matching of the pre-encoding frame structure. For example, if an OTUk with a frame length of 4080 bytes is used, the frame structure used in step 102 is also an OTUk with a frame length of 4080 bytes; if the OTUk with a frame length of 4600 bytes is used here, Then, the frame structure adopted in step 102 is also an OTUk with a frame length of 4600 bytes.
  • each of the foregoing units may be implemented as an independent entity, or may be implemented in any combination, as the same entity or multiple entities.
  • the coding unit 501 may be implemented by implementing FEC coding modules in three and four, and matching.
  • the unit 504 can be implemented by implementing a frame structure matching matching component on the wavelength division side of the third and fourth sides, and a frame structure matching receiving end and the like on the client side, and the like.
  • the apparatus for matching the FEC codewords into the frame structure in this embodiment adopts the frame structure matching of the FEC encoded signals in a unit of one FEC codeword. Therefore, the FEC code is required in comparison with the prior art.
  • the signal receiving end does not need to use a large amount of RAM to store the FEC information bits and the FEC overhead bits when receiving the signal matched by the frame structure, waiting for the FEC information bits and the FEC.
  • the decoding is performed, but the decoding can be performed directly, so that not only the delay can be reduced, but also the RAM resources can be saved.
  • the embodiment of the present invention further provides an apparatus for de-matching a frame structure into an FEC codeword.
  • the apparatus for de-matching a frame structure into an FEC codeword includes a receiving unit 601, a determining unit 602, Computing unit 603 and dematching unit 604;
  • the receiving unit 601 is configured to receive a signal that is matched by the frame structure, where the matched signal of the frame structure is a signal transmitted by using an OTU frame structure;
  • a determining unit 602 configured to determine a frame length of an OTU frame structure used by the frame structure matched signal, and determine a code length of the FEC codeword;
  • the calculating unit 603 is configured to calculate, according to the frame length and the code length determined by the determining unit 602, the number of FEC codewords that can be carried in each row in the OTU frame structure;
  • the de-matching unit 604 is configured to perform, according to the number of FEC codewords that can be carried in each row in the OTU frame structure calculated by the calculating unit 603, the signal that is matched by the frame structure received by the receiving unit 601. Extract, get the FEC encoded signal.
  • Each FEC codeword may specifically include a FEC information bit and a FEC overhead bit, and the FEC codeword code length refers to a total bit width of the FEC information bit and the FEC overhead bit, that is,
  • the determining unit 602 is specifically configured to determine a frame length of an OTU frame structure used by the frame structure matched signal, and determine a total bit width of the FEC information bit and the FEC overhead bit;
  • the calculating unit 603 is specifically configured to calculate, according to the frame length and the total bit width determined by the determining unit 602, the number of FEC codewords that can be carried in each row in the OTU frame structure.
  • the FEC codewords RS take 7% of the FEC codewords RS (255, 239) as an example.
  • the de-matching unit 604 extracts the frame-matched signal according to the number of FEC codewords that can be carried in each row of the OTU frame structure, and after obtaining the FEC-encoded signal, the FEC-encoded signal can also be FEC-decoded and intercepted.
  • Bits, to obtain FEC information bits that is, the apparatus for de-matching the frame structure to the FEC codeword may further include an FEC decoding unit and a truncation unit;
  • the FEC decoding unit is configured to perform FEC decoding on the FEC encoded signal to obtain a FEC decoded signal
  • the truncation unit is configured to perform a truncation of the FEC overhead bit for each FEC codeword in the FEC decoded signal obtained by the FEC decoding unit, to obtain an FEC information bit. For example, taking 7% of the FEC codewords RS (255, 239) as an example, the code length of the FEC codeword is 255 bits, and 16 bits are cut off to obtain 239 bits of information bits.
  • each of the above units may be implemented as an independent entity, or may be any group.
  • the receiving unit 601 and the frame format de-matching unit 502 can be implemented by implementing the frame structure matching receiving end of the wavelength division side in the third and fourth, and the FEC decoding unit is implemented by The FEC decoding module is implemented, the truncation unit is implemented by the frame format transmitting end of the client side, and the like.
  • the FEC decoding module is implemented
  • the truncation unit is implemented by the frame format transmitting end of the client side, and the like.
  • the apparatus for de-matching the frame structure into the FEC codeword in this embodiment can perform the solution matching on the received frame structure matching signal in units of one FEC codeword, since it can be stored without using a large amount of RAM.
  • the FEC information bit and the FEC overhead bit are decoded after waiting for the FEC information bit and the FEC overhead bit to be aligned, but are directly decoded, so that not only the delay is greatly reduced, but also the RAM resource is saved.
  • the embodiment of the present invention further provides a communication system, including any device for matching a FEC codeword into a frame structure and any device for dematching a frame structure into an FEC codeword.
  • a communication system including any device for matching a FEC codeword into a frame structure and any device for dematching a frame structure into an FEC codeword.
  • the device for matching the FEC codewords into the frame structure refer to the fifth embodiment, and the device for de-matching the frame structure to the FEC codeword can be referred to in the sixth embodiment, and details are not described herein again.
  • the communication system may specifically be a frame structure matching system of the FEC, including means 701 for matching the FEC codewords into a frame structure and means 702 for de-matching the frame structure to the FEC codewords;
  • the apparatus 701 for matching the FEC codeword into a frame structure is configured to perform FEC encoding on the received optical signal to obtain a FEC encoded signal; determining a code length of the FEC codeword, and a frame length of the OTU frame structure, according to the code length And calculating the number of FEC codewords that can be carried in each row in the OTU frame structure, and matching the FEC encoded signal to the OTU frame structure according to the number of FEC codewords that can be carried, to obtain a signal after the frame structure is matched. Transmitting the frame structure matched signal to the device 702 that de-frames the frame structure into the FEC code word;
  • the apparatus 702 for dematching the frame structure into the FEC codeword is configured to receive a frame structure matched signal sent by the apparatus 701 that de-matches the frame structure into the FEC codeword, and determine an OTU frame structure used by the frame structure matched signal. Frame length, and determining the code length of the FEC codeword, calculating the number of FEC codewords that can be carried in each row of the OTU frame structure according to the determined frame length and code length, according to the number of FEC codewords that can be carried The signal after the structure matching is extracted to obtain the FEC encoded signal.
  • Each FEC codeword may specifically include an FEC information bit and an FEC overhead bit, and the FEC The codeword length refers to the total bit width of the FEC information bit and the FEC overhead bit.
  • the apparatus 701 for matching the FEC codewords into the frame structure of the communication system of the present embodiment performs frame structure matching on the FEC encoded signals in units of one FEC codeword. Therefore, compared with the prior art, In order to match the information bits and the overhead bits of the FEC codeword for matching, the signal receiving end does not need to use a large amount of RAM to store the FEC information bits and the FEC overhead bits when receiving the matched signal of the frame structure, waiting for the FEC. After the information bits and the FEC overhead bits are aligned, the decoding is performed. After the frame format de-matching device de-matches the signals, the decoding can be directly performed. Therefore, the scheme can not only reduce the delay but also reduce the delay.
  • the program may be stored in a computer readable storage medium, and the storage medium may include: Read Only Memory (ROM), Random Access Memory (RAM), disk or optical disk.
  • ROM Read Only Memory
  • RAM Random Access Memory

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne un procédé permettant de faire correspondre des mots de code de correction d'erreur sans voie de retour (FEC) avec une structure de trame. Ledit procédé comprend les étapes suivantes : mettre en oeuvre un codage FEC pour des signaux optiques reçus afin d'obtenir des signaux codés FEC ; déterminer la longueur de code des mots de code FEC et la longueur de trame d'une structure de trame d'OTU (unité de transport optique) ; selon la longueur de code et la longueur de trame, calculer le nombre des mots de code FEC transportés dans chaque ligne de la structure de trame d'OTU ; selon le nombre des mots de code FEC transportés, faire correspondre les signaux codés FEC avec la structure de trame d'OTU. Les modes et formes de réalisation de l'invention concernent en outre un procédé, un dispositif et un système correspondants permettant de faire correspondre inversement une structure de trame avec des mots de code FEC.
PCT/CN2012/071100 2012-02-14 2012-02-14 Procédé, dispositif et système pour faire correspondre des mots de code de correction d'erreur sans voie de retour avec une structure de trame WO2013120247A1 (fr)

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PCT/CN2012/071100 WO2013120247A1 (fr) 2012-02-14 2012-02-14 Procédé, dispositif et système pour faire correspondre des mots de code de correction d'erreur sans voie de retour avec une structure de trame
CN201280000070.6A CN102754378B (zh) 2012-02-14 2012-02-14 将前向纠错码字匹配成帧结构的方法、装置和系统

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CN101159495A (zh) * 2006-10-08 2008-04-09 华为技术有限公司 无源光纤网络中信号传送系统及方法
CN101667887A (zh) * 2009-09-02 2010-03-10 中兴通讯股份有限公司 编码方法及其装置、解码方法及其装置
CN102130742A (zh) * 2010-01-14 2011-07-20 三菱电机株式会社 纠错编码装置和方法、及纠错解码装置和方法

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CN101159495A (zh) * 2006-10-08 2008-04-09 华为技术有限公司 无源光纤网络中信号传送系统及方法
CN101667887A (zh) * 2009-09-02 2010-03-10 中兴通讯股份有限公司 编码方法及其装置、解码方法及其装置
CN102130742A (zh) * 2010-01-14 2011-07-20 三菱电机株式会社 纠错编码装置和方法、及纠错解码装置和方法

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