WO2013116273A1

WO2013116273A1 - Graphene-graphene oxide resistive random access memory

Info

Publication number: WO2013116273A1
Application number: PCT/US2013/023750
Authority: WO
Inventors: Igor Pavlovsky
Original assignee: Applied Nanotech Holdings, Inc.
Priority date: 2012-01-30
Filing date: 2013-01-30
Publication date: 2013-08-08

Abstract

An electronic memory device based on the reversible changes in a resistance of graphene when it is oxidized to graphene oxide or reduced back to graphene by voltage application. The redox chemical reactions are enabled by access of the graphene to a source of oxygen. The device is ionizing radiation tolerant and immune to single event effects.

Description

GRAPHENE-GRAPHENE OXIDE RESISTIVE RANDOM ACCESS MEMORY

This application claims priority to U.S. Provisional. Patent Application Serial No. 61/592,223, which is hereby incorporated by reference herein.

Technical Field

The present invention relates in general to electronic memory devices. Background Information

The availability of .radiation hardened memory devices with high total dose tolerance and single event effects immunity is important for the success of long-term space missions. One of the primary causes of fkiliires in memory device is the formation of conducting channels by energetic ions or photons in dielectric layers isolating the charge storage layers, which results in the loss of data storage reliability. Regardless, a more reliable information, storage memory device is needed.

A number of alternative technologies have been proposed to mitigate this effect. These include magnetoresistive random access memory ("MRAM") and resistive random acces memory ("ReRAM") technologies, while many other approaches are still under development. ReRAM has the potential to become the front runner among other non-volatile memories. Compared to a Phase Change R AM, ReRA operates on a faster timescale (switching time can be less than 10 nanoseconds). Compared to RAM, ReRAM has a simpler and smaller cell structure (less than a stack of metal-insulator-metai memory cells with a typical 8P cell layout).

The basic idea behind ReRAM is that a dielectric can be made to conduct through a filament or conduction path, formed after application of a sufficiently high voltage. The conduction path, formation can arise from different mechanisms, including defects, diffusion, metal migration, etc. Once the filament is formed, it may he reset (broken, resulting in high resistance) or set (re-formed, resulting in lower resistance) by an appropriately applied voltage.

It was recently demonstrated that graphene oxide ("GO") thin, films prepared by spin- casting and sandwiched between two aluminum ("At") layers can be successfully utilized in a novel nonvolatile flexible crossbar .memory device. This device exhibited a typical, bipolar resistive switching (^uBRS^,y) with a set/reset voltage of approximately -2.5/4-2.5 volts and. a high ON/OFF ratio greater than 100. Both O and OFF states were stable for more than. 10^s seconds alter removal of the external, voltage stimulus. No degradation of memory performance was observed for approximately 100 cycles. The microscopic origin of the BRS in such Al/GO/AS devices is likely due to the formation an rupture of conducting filaments in the insulating barrier at the top interface. However, these changes in the film structure can result in permanent damage to the device structure, leading to limited memory endurance.

Brief Description of the. Drawings

Figures 1A~!B illustrate an electronic memory cell m accordance with embodiments of the present invention.

figures 2A-2D illustrate operation of the memory cell of Figures tA-lB in accordance with embodiments of the present invention.

Figure 3 illustrates an electronic memory device configured in accordance with embodiments of the present in vention.

Detailed Description

A nonvolatile resistive graphene- graphene oxide memory device having advantages of resistive memory technologies is disclosed, which uses reversible non-destructive nanoscal.e oxidation and reduction of graphene mediated by an electric current.

Embodiments of the present invention address major deficiencies of charge storage- based memory devices, such as the complexity of memory cell structures, limited access time, and vulnerability to ionizing radiation, in a two-terminal configuration, the graphene can be oxidized to graphene oxide and revers y reduced to graphene through application of a low voltage potential The voltage required to reduce or oxidize graphene is more that 1 volt but less than 4 volts. No oxidation was observed for biases under 0.5 volts; however, irreversible reduction took place at potentials of 4.5 volts and above. As a result, a non-volatile memory device may be fabricated with a low voltage suppl (one or more) (e.g., less than or equal to 3.3 volts), which is important for .many electronic applications.

The reduction takes place at the cathode, and oxidation at the anode, in the presence of small amounts of oxygen, which, may be provided through an application-specific chip design and as further described hereinafter. Changing the polarity of the terminals can reverse the reduction-oxidation process. Since the resistivity of graphene oxide is several orders of magnitude higher than that of graphene, even small changes in the redox state (i.e., the oxidized and. reduced, states of the graphene) of graphene can be easily detected. For example, a 5 μιη thick GO film has a sheet resistance of 1.3 MQ/pm, while a fully reduced graphene film of substantially similar thickness has a sheet resistance of 25 Ω/μ η. Thus, low 0*Lo") and high ΓΉΓ) states of a memory cell ma be characterized by an ON/OFF ratio of approximately 50,000, which can be easily discerned using simple electronic circuitry design. This change may occur within, seconds or less.

The fast access time of a memor device based on reversible graphene oxidation is certainly achievable for READ LO and READ H i operations, but it should be significantly lower than the reported values for graphene/graphene oxide to implement fast WRITE operations. Reducing access time may mclude implementing the following; (i) reduction i graphene memory element size; (ii) use of catalyst-plated electrodes to facilitate oxygen transfer reactions, and (iii) use of partial redox instead of full redox of graphene.

In a simplest design approach, the graphene/graphene oxide memory element may be used as a basic memory cell with an example configuration where parallel wordSines are crossed, by perpendicular bitJmes, with the graphene GO material placed, between wordlme and bitline at. a cross-point The state of the basic memory cell depends on the oxidation state of the graphene crystallite bridging the electrodes at the cross-point. Since a. two-electrode configuration of reduction-oxidation of graphene is symmetric, i.e., graphene is reduced at one electrode and oxidized, at the other electrode, the final resistance of graphene/graphene oxide crystallite may not significantly change after the polarity of the electrodes is switched and. the reduction/oxidation process is reversed. Moreover, the resistivit of the graphene may not change much at all towards the center of the graphene crystallite.

As a result, referring to Figures 1 A-I B, a three -electrode scheme is implemented in embodiments of the present invention, which is .more sensitive to the changes in the resistivity and the oxidatio state of the graphene, A bitl ine 102 crosses the graphene electrode 101 , which may be made from a graphene crystallite, near its center, where the oxidation, state of graphene is nearly constant. The resistance i thus measured between the middle part of the graphene electrode 101 (near the bitline electrode position) and the edge of the crystallite electrode 101 that is connected to the wordlme electrode 103.

The other edge of the graphene electrode 1 1 is connected to a counter to a counter electrode ("CE") 1 4. Though not shown for the sake of brevity, such wordiines and counter electrode lines may he controlled to apply various voltage potentials to the memory cells 1.01, including being permitted to float without an applied potential

Basic designs of a graphene memory cell in accordance with embodiment of the present invention may include access of a surface of the graphene crystallite 101 to a source of oxygen 105, which may be provided to the graphene surface as oxygen in a gaseous form (e.g.,, air) trapped under the electronic package lid encasing the memory cells, or oxygen dissolved in a liquid in contact with the surface of the graphene crystallite 101. For example, embodiments of the present invention may contain the memory elements inside a hermetic package wherein an oxygen containing gas mixture is trapped inside the package and in contact with the elements (i.e. the elements would be exposed to the gas): one example of the oxygen containing gas mixture can be ambient air. The access to oxygen provides for proper graphene oxidation to graphene oxide. The graphene structures may be open to ambient air for redox reactions occurring during WRITE operations. Reversible oxidation may utilize an oxygen content less than 100%. One of ordinary skill i electronic packaging design will be able to design the memory device packaging in order to provide the graphene surfaces with access to the oxygen.

During WRITE/ERASE cycles,, the counter electrode 104 may be connected to the memory ceil ground potential (or H-3 volts potential) (not shown) with the bit!me potential floating, while a READ cycle may be completed with the CE 1 4 floating.

The diagrams in Figures 2A-2D further depict exemplary WRITE and READ cycles. The basic memory cell uses bipolar resistive switching. Referring to Figure 2 A, during a WRITE HI cycle, a positive potential (e.g., +3 volts) Is applied from a wordlme to the wordlme electrode 103, and the CE 104 is connected to a memory cell ground potential. The graphene

101 will to oxidize to GO, resulting in high resistance at the cross-point. Referring to Figure 2B, during a WRITE TO cycle, a zero potential (ground) is applied to the wordline .103, and a positive potential (e.g., +3 volts) is applied to the CE i 04, resulting in the reduction of GO to graphene, which has very low resistance.

Figures .2C-2D further depict exemplary READ cycles. For example, with the counter electrode 104 floating, the bitline 102 may READ a HI bit due to the high resistance in the cross-point portion of the graphene crystallite bridging the wordline electrode 103 and the bitline electrode 102. which is sensed by the bitline electrode 102 as a low current.. The bitline 102 may READ a LO bit due to the low resistance in the portion of the graphene crystallite bridging the wordline electrode 103 and the bitline electrode 102, which is sensed by the bitline electrode

1 2 as a high current

In alternative embodiments, utilization of asymmetric electrode configuration, electrode patterning, or patterning of the graphene crystallite, or an asymmetric reduction/o idation timing diagram may be utilized to implement a two-terminal device memory, wherein changes in a polarity of the applied voltage results in preferential reduction or oxidatio of a part of the graphene that bridges the two electrodes. Figure 3 illustrates an exemplary electronic memory device configured in accordance with embodiments of the present invention. Such a memory storage device may operate in a typical manner as random access memory devices in which the hitlines 102, wordhnes 103, and counter electrode lines 104 are utilized to programm.ahly select specified memor cells 101 for storage and access of bits of information, such as described above with respect to Figures 2A- 2D.

Such a basic memory device in accordance with embodiments of the present inventio may be implemented on a glass substrate with Pt(Pd)/Au/Cr bitirae and wordlsne electrodes and patterned single-layer graphene structures. The patterning may be completed using spin, casting of an aqueous graphene oxide dispersion, a photoresist coating, and a dry etch (RJE) process.

Oxidation and reduction of graphene may depend on the rates of related reactions and the concentration of oxygen and other gases that may interfere with the oxidation/reduction processes. Thus, b measuring the rate of change of the resistance of the graphene crystallite during reduction or oxidation, or final resistance if the reduction/oxidation process has reached equilibrium, it is possible to assess the concentration of oxygen, or other gas or liquid components that interfere with the reduction or oxidation process. This approach of electric current mediated oxidation or reduction of graphene in oxygen containing gas or liquid environment may be used in making a chemical sensor device. The sensor device may use a design approach and architecture similar to embodiments of the memory device disclosed, herein, where the environment to be sensed, is exposed to the graphene electrode 101.

Claims

WHAT IS CLAIMED IS;

1. A memory device comprising:

a bitline electrode;

a wordiine electrode; and

a graphene crystallite bridging the bitline and wordiine electrodes, wherein the graphene crystallite is exposed io ¾ source of oxygen.

2. The memory device as recited in claim ! , further comprising a counter electrode, wherein the graphene crystallite bridges the bitline and counter electrodes

3. The memory device as recited in claim 1, wherein the source of oxygen provides the oxygen to the graphene crystallite .hi a gaseous form.

4. The memory device as recited in claim 1_» wherein the source of oxygen provides the oxygen to the graphene crystallite in a liquid form as oxygen dissolved in a liquid.

5. The -memory device, as recited in claim .1, wherein the memory device has a storage of at least a bit of information when a voltage applied to the wordiine electrode results in a chemical oxidation of at least a portion of the graphene crystallite,

6. The memory device as recited i claim 2, wherein the memory device has a storage of at least a bit of information when a voltage applied to the counter electrode results in a chemical oxidation of at least a portion of the graphene crystallite.

7. The memory device as recited in claim 2, wherein the memory device has a storage of at least a bit of information whe a voltage applied to either the wordiine or counter electrodes results in a chemical redox reaction of portions of the graphene crystallite.

8. The memory device as recited in claim 1, wherein the graphene crystallite is reversibly oxidized io graphene oxide when a voltage is applied to the electrodes.

9. The memory device as recited in any of claims 5, 6, 7, or 8, wherein the voltage is approximately in a range of 0,5-4,5 volts.

10. The memory device as recited in any of chums 5, 6, 7, or 8, wherein the voltage is approximately in a range of 1-4 volts.

1 i . The memor device as recited in any of claims 5, 6. 7, or 8, wherein the voltage is less than or equal to 3.3 volts.

12. The memory device as recited in claim .1 , wherein the graphene crystallite is configured to have a change in sheet resistance between lis oxidized and reduced states of an approximate ratio of 50,000.

13. The memory device as recited in claim 2_.» wherein the bitline electrode contacts the graphene crystallite approximately at. its center between where the graphene crystallite contacts the wordlme and counter electrodes.

14. A electronic memory comprising;

a plurality of biilin.es;

a plurality of wordlines;

a plurality of counter electrode Lines

a source of oxygen; and

a plurality of memory cells each comprising a graphene crystallite bridging one of the plurality of bitlines with one of the plurality o wordline and with one of the plurality of counter electrode lines, wherein a. surface of the graphene* crystallite i exposed to oxygen from the source of oxygen.

15. The electronic memory as recited in claim 14, wherein the source of oxygen provides the oxygen ic the surface of the graphene crystallite in a gaseous form,

16. The electronic memory as recited in. claim 14, wherein the source of oxygen is oxygen dissolved in a liquid.

1 ?, The electronic memory as recited in claim 14, wherein at least one of the plurality of memory cells contains a storage of an information bi t when at least a portion of the graphene crystallite is graphene oxide.

IS. The electronic memory as recited in claim 1. ?, wherein the graphene oxide bridges a bitline and a wordline both connected to the at least one of the plurality of memory cells.

19. The electronic memory as recited in claim 17, wherein the graphene oxide bridges one of the plurality of bitlines to one of the plurality of counter electrode lines that are both connected to the at least one of the plurality of memory cells.

20. The electronic memory as recited in claim 14, wherein the plurality of hitlines contact the graphene crystallites in the plurality of memory cells approximaiely at a center location between, where the graphene crystallites contact the wo.rdlin.es and counter electrode Sines.