JP2006303343A - Semiconductor memory and its operation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of a nonvolatile operation by utilizing an ion conduction. <P>SOLUTION: This structure is formed by laminating a first ion conductor layer 27 and a second ion conductor layer 28 between a first electrode 25 and a second electrode 26. This structure functions as a nonvolatile memory which can prevent a back flow of ions by an ion transfer barrier layer of an interface. Writing is carried out by generating a residual potential by ions moving by a voltage applied to the first ion conductor layer 27 and the second ion conductor layer 28. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a non-volatile memory device using ionic conduction and a structure and operation method of a semiconductor memory using the non-volatile memory device.

  With the increase in the density and miniaturization of semiconductor elements accompanying the widespread use of portable devices and electronic devices, problems of power consumption and operating voltage of electronic devices, particularly semiconductor devices, have become prominent. Along with the power consumption problem, the necessity of both volatile and non-volatile memories that are indispensable for system construction is increasing. Realizing such a low power consumption, low voltage drive switching device or memory device is indispensable for further development of electronic devices in the future.

  DRAMs are often used for data storage in systems built with current semiconductor devices. A DRAM generally has a one-transistor + 1 capacitor structure and can be manufactured at a high density. Therefore, the DRAM is often used as a memory having a low unit price per bit. Information of this DRAM is stored in the form of electric charges in a dielectric capacitor. As a result, even if the device structure is miniaturized, the same amount of charge storage is required regardless of the miniaturization in order to ensure read and soft error resistance. Capacitance is an issue. In addition, since charge accumulation in the capacitor is an information accumulation principle, a refresh operation in which a write operation is performed again within a predetermined time is necessary to compensate for the loss of the capacitor charge. The following invention is disclosed for such a DRAM.

  A cell using a superionic conductor as a storage capacitor of a DRAM memory cell array is disclosed (for example, see Patent Document 1). As shown in FIG. 11, in a DRAM cell to which a storage capacitor 112 is connected via a selection transistor 111, the storage capacitor is formed by forming a superionic conductor 115 between the first capacitor electrode 113 and the second capacitor electrode 114. The capacitor 112 is realized. It is disclosed that a capacitor having a high dielectric constant can be realized by using cerium fluoride as an ion conductor.

  Further, Patent Documents 2 to 6 are listed as documents showing general technical levels related to the present invention. Patent Document 2 utilizes the interaction between electrons and ions. Patent Document 3 uses a solid electrolyte secondary battery as a charge holding portion. Patent Documents 4 and 5 utilize changes in electrical characteristics due to the formation of metal dendrites. Patent Document 6 uses an oxidation-reduction reaction.

  For example, when a battery is formed by utilizing ionic conduction in an electrolyte such as a solid electrolyte, an electromotive force generated by the battery is used, but as in the example disclosed in Patent Document 1. Since the charge due to ions disappears, it can be said that it is a DRAM type and a volatile type that requires a refresh operation as in Patent Document 1.

Moreover, in the example (patent document 4 and patent document 5) which implement | achieves switch operation | movement (low resistance reduction) by causing metal precipitation in solid electrolyte by reduction reaction after moving ion, in order to produce metal precipitation, Although it operates in a non-volatile manner, it uses the principle of reduction deposition and is characterized in that the metal is deposited in the solid electrolyte. Patent Document 6 uses the same principle.
Japanese translation of PCT publication No. 2004-529502 (FIG. 11) JP 9-36355 A Japanese Patent Laid-Open No. 2003-60083 Special Table 2000-512058 JP-T-2001-525606 JP 2003-157672 A

  Patent Document 1 aims to increase the storage capacitor capacity of the DRAM, and there is a problem that the nonvolatile operation of the present invention cannot be realized.

  On the other hand, in the structure in which metal deposition is caused in the solid electrolyte by utilizing the oxidation-reduction reaction, the non-volatile operation is achieved, but the change in volume occurs due to the change from the ion to the metal in the solid electrolyte. Since the structure is destroyed, there is a problem as operation reliability as a switch and a memory device.

  The DRAM is used for storing data during information processing, and it is necessary to retain charges when the system is in operation. In Patent Document 1, after the movable ions in the ion conductor are moved by applying a voltage to the capacitive electrode, the movable ions return to their original positions when the voltage is removed. This is because reverse diffusion occurs due to the gradient of the ion concentration in the ion conductor. Therefore, Patent Document 1 has a disadvantage that a refresh operation is required as in the case of an existing DRAM, and a nonvolatile operation cannot be realized. As described above, when an ion conductor is integrated as a capacitor in a DRAM cell, it is only possible to achieve an increase in capacity, and the application is limited.

  Therefore, if the movement of ions is controlled in addition to simply replacing the capacitor, a nonvolatile semiconductor memory can be realized. As a result, the refresh operation is unnecessary or can be significantly reduced, and in addition to the feature of the DRAM having a high-density random access memory, the disadvantage of the refresh operation of the DRAM can be improved. However, from the conventional example, even if the non-volatile operation is not achieved or the non-volatility is achieved, the operation is accompanied by structural destruction such as dendri and precipitation in the solid electrolyte, and the reliability as a switch or a memory device is improved. There was a problem. In other words, if a method for solving these two problems can be disclosed, an epoch-making memory and switch device can be realized, and the present invention has been invented with these two as the main points.

  Hereinafter, problems of a general DRAM additionally solved by the present invention will be described.

  First, in a DRAM, a write operation is charging of a capacitor, and a read operation is detecting the amount of charge due to discharge of the capacitor. Therefore, it is destructive reading in which writing is necessary once read is performed, and further, writing and reading cannot be performed at the same time.

  Furthermore, the capacitor in the DRAM is not suitable for an analog memory because the presence / absence of a charge accumulation amount is data.

  The present invention has been devised from the above viewpoint, and provides a semiconductor memory that greatly improves the disadvantages of existing DRAM and DRAM memory cells using ion conductors.

  According to the semiconductor memory using the first memory device of the present invention, the first electrode and the second electrode, and the ion conductor layer composed of two layers between the first electrode and the second electrode. It is comprised from the memory device which has this. By making the ion conductor layer have a laminated structure, an interface barrier is formed at the interface of the ion conductor layer. As a result, only ions that have moved beyond the interface barrier move to one of the ion conductor layers, and a residual potential is generated by the moved ions.

  Therefore, it becomes possible to control the ion movement by the voltage applied between the first electrode and the second electrode, and to prevent the reverse flow of ions due to the reverse electric field due to the ion density, and it is non-volatile. In addition, since it is possible to operate without causing metal deposition during operation, the structural failure of the solid electrolyte of the solid electrolyte does not occur and the problem of reliability can be solved.

  According to the semiconductor memory using the second memory device of the present invention, in the memory device of the first invention of the present invention, an ion is interposed between the first ion conductor layer and the second ion conductor layer. A conductive barrier layer is provided. By providing an ion conduction barrier layer, even in the case of a material combination with a low interface ion conduction barrier such as the same material structure of the first ion conductor layer and the second ion conductor layer Ability will be improved.

  According to the semiconductor memory using the third memory device of the present invention, the memory device using the first ion conduction of the present invention further includes at least one third electrode for detecting the electrical characteristics of the ion conductor. It is characterized by that.

  Since an electrode is provided separately from the voltage application electrode and the electrical characteristics of the ion conductor can be detected, it is possible to simultaneously perform a writing operation and a reading operation.

  According to the semiconductor memory using the fourth memory device of the present invention, between the first ion conductor layer or the second ion conductor layer and the first electrode or the second electrode and the detection electrode. A semiconductor layer is provided. By providing the semiconductor layer, it is possible to change the conductance of the semiconductor layer by ion movement. Therefore, it is possible to read information of the memory device by reading the conductivity of the semiconductor layer.

  According to a semiconductor memory using the fifth memory device of the present invention, in the memory device according to any one of claims 1 to 4, the first electrode or the second electrode and the first ion conductor layer or the second The capacitor is connected to at least one of any of the ion conductor layers. Since the capacitor is formed between the ion conductor and the electrode, it is possible to prevent the electrode and the ion conductor from being in direct contact and to induce charge in the capacitor.

  According to the sixth memory device using ion conduction of the present invention, a capacitor is provided on at least one of the first electrode and the second electrode of the memory device using ion conduction according to the first to fifth inventions. It is characterized by a connected configuration. Since a capacitor is connected in series to a memory device using ionic conduction, mobile electrons associated with the conduction carrier movement of the memory device using ionic conduction are stored in the capacitor, so by reading the potential stored in the capacitor Information can be read out, and ion movement of the memory device using ion conduction can be converted into a charge amount.

  According to the seventh memory device using ionic conduction of the present invention, the ionic conduction in which a resistor is connected to the first electrode or the second electrode in the memory device using ionic conduction according to claims 1 to 4. The memory device cell structure using Since the resistor is connected, the amount of charge accompanying ion movement can be converted to voltage by resistance, and the amount of ion movement when voltage is applied to the first electrode or the second electrode is converted to voltage. .

  According to the memory device using the eighth ion conduction of the present invention, it relates to the operation method of the memory device using the first to fourth ion conduction of the present invention, and the voltage is applied to the first electrode and the second electrode. Is a method of operating a memory device using ionic conduction, characterized in that writing is performed by applying an electric field and information is read out by applying an electric field in a predetermined direction again. Since information is read by the amount of ion movement, information can be read even when the ion transport number of the ion conductor is other than 1.

  According to a ninth aspect of the present invention, there is provided a memory device using ion conduction according to any one of claims 3 to 4, wherein a voltage is applied to the first electrode and the second electrode. And a write operation performed by applying a voltage, and reading out information by detecting a current by applying a voltage between the detection electrode and either the first electrode or the second electrode. Since the detection electrode is provided separately, not only the reading operation can be performed simultaneously with the writing operation, but also the reading operation can be performed without greatly disturbing the ion distribution state.

  According to a tenth aspect of the present invention, there is provided a memory device using the ionic conduction according to claim 9, wherein the voltage is applied between the sensing electrode and the first electrode or the second electrode. When a read operation is performed by applying a positive polarity, a read operation is performed by applying positive and negative bipolar pulses. Since the bipolar pulse is used, the reading operation can be performed without disturbing the ion distribution.

  According to the semiconductor memory using the memory device using ionic conduction according to the present invention, the ion conductor layer is stacked, and the ions are moved by the voltage applied to the electrodes to perform the charge transfer, and the ion transport barrier existing at the interface. Therefore, the reverse flow of ions is prevented, so that a residual potential is generated and a non-volatile operation becomes possible. Further, since metal deposition due to reduction does not occur in the solid electrolyte, structural breakdown of the solid electrolyte can be prevented. In addition, since the read operation can be realized by reading the residual potential, nondestructive read is possible. Furthermore, by controlling the amount of ion movement by the write voltage and time, it can be used as an analog memory. Further, by separately providing an electrode for detecting ionic conductivity, writing and reading can be performed simultaneously and a nondestructive reading operation can be realized.

  A semiconductor memory using ion conduction in an embodiment of the present invention will be described below.

  In the present invention, the ion conductor refers to a substance capable of ion migration, such as a solid electrolyte, electrolyte gel, organic ion conductor, polymer ion conductor, and ionic liquid. If the material has a particularly high ion transport number, the effects of the present invention can be obtained.

(Embodiment 1)
A semiconductor memory including a memory device using ionic conduction according to the present invention will be described with reference to FIG. In particular, when used as a semiconductor memory cell, a large number of memory devices using ion conduction are arranged. FIG. 1 shows a circuit diagram of the cell. The memory device 11 using ion conduction is connected to the selection transistor 12 that selects the memory device 11 using ion conduction, and the word line 13 is connected so as to control on / off of the selection transistor 12. As for information, complementary data is prepared in the first bit line 14 and the second bit line 15. A cell is selected by the word line 13 and writing is performed in the memory device 11 using ion conduction. At this time, the data prepared in the first bit line 14 and the second bit line 15 is physically prepared as a potential, but the ion movement is performed by applying a voltage to the memory device 11 using ion conduction. Since it only has to occur, either digital data or analog data may be used. In the case of digital data, complementary data is prepared, and in the case of analog data, the potential difference is data. As described above, the writing operation is performed on the cell using the memory device using ion conduction according to the present invention.

  On the other hand, the read operation is as follows. When the selection transistor 12 is turned on by the word line 13, a potential difference is generated between the first bit line 14 and the second bit line 15. Therefore, the read operation is performed by sensing this potential difference.

  FIG. 2 is a structural diagram of the semiconductor memory of the present invention. In FIG. 2, 21 is a silicon substrate, 22 is a transistor portion, 23 is a contact, 24 is a memory device portion, 25 is a first electrode, 26 is a second electrode, 27 is a first ion conductor layer, and 28 is It is a 2nd ion conductor layer. The memory device section 24 is connected to the transistor section 22 via the contact 23. The transistor 22 corresponds to a selection transistor.

<Memory device structure and fabrication method>
A memory device used in the semiconductor memory of the present invention will be described in detail with reference to FIG.
In the memory device of the present invention, the first electrode 33 and the second electrode 34 are arranged so that a voltage can be applied to the first ion conductor layer 31 and the second ion conductor layer 32. It is a feature.

  A manufacturing method and operation of the memory device of the present invention configured as described above will be described below.

  The first ion conductor layer 31 was LiO—SiO-based glass, and the second ion conductor layer 32 was Li—Ti—O-based ion conductor.

  In order to clarify the explanation, a method for manufacturing the ion conductor layer, the first electrode, and the second electrode portion will be described. A memory device was formed so as to be connected to the transistor using a substrate in which a transistor was formed on a semiconductor device such as Si or a glass substrate.

On the substrate on which the transistor was formed, Pt was formed as the first electrode 33 to a thickness of 100 nm by Rf magnetron sputtering. The sputtering conditions were Ar with sputtering gas, gas pressure of 0.2 Pa, and Rf power of 100 w. Using a Pt film as a wiring, patterning was performed by an etching apparatus using ICP plasma. Next, a 20 nm first ion conductor layer 31 was formed on Pt of the first electrode 33 by an Rf magnetron sputtering method using a LiO—SiO-based glass target. The gas pressure was 0.2 Pa, and a mixed gas of Ar and O ₂ was used. Furthermore, 20 nm of 2nd ion conductor layers 32 were formed on the 1st ion conductor layer 31 using the LiO-TiO type | system | group glass target. The thickness of the first ion conductor layer 31 and the second ion conductor layer 32 is selected from 1 nm to 100 nm, but if the thickness is about 10 nm or less, electrons may directly tunnel through the formed ion conductor. Because there is, attention is necessary. In addition, as the thickness increases, there are problems that it takes time for ion movement and that the applied voltage is less likely to be applied to the ion conductor. Therefore, in order to reduce the speed and operating voltage as a memory device, an operating speed of 100 ns or less is achieved by selecting from a thickness of about 1 nm to 100 nm.

  Furthermore, Pt was formed as a second electrode 34 on the second ion conductor layer 32 by sputtering under the same conditions as the first electrode 33, and patterned to form a memory device.

  In this embodiment, the Li: Si ratio of the first ion conductor layer 31 is 60:40, and Li: Ti is 30:70 in the ion conductor of the second ion conductor layer 32. .

  Further, the material of the first electrode 33 and the second electrode 34 is not limited to Pt, but the reaction with the mobile ions, the reactivity with the ion conductor, the first electrode 33 and the second electrode 34 are not limited to Pt. Although it is selected based on the oxidation-reduction potential of the electrode 34 or the like, it is basically necessary that the electrode 34 is not reactive with mobile ions and that the electrode does not elute into the ion conductor. By selecting an electrode that does not cause a redox reaction, dendrite formation is suppressed, and the structure of the first ion conductor layer 31 and the second ion conductor layer 32 is not destroyed. Since an ion transport barrier is formed between the ion conductor layer 31 and the second ion conductor layer 32, it moves across the first ion conductor layer 31 and the second ion conductor layer 32. Has the role of preventing the backflow of ions that have moved once, while requiring energy to cross the ion transport barrier existing at the interface. As a result, since the ions that have moved remain, the non-volatility of the operation appears.

  Further, the selected ion conductor is not limited to the above-described composition, and the present invention is not limited to the present invention as long as it is an existing ion conductor that can be thinned such as Cu, Ag, etc. as well as Li. Applicable to. In particular, ion conductor glasses containing Li, Ag, and Cu, ion conductor glasses containing P, S, and halogen, ion conductor glasses containing not only O but N, or ion conductors based on these elements are present. It is most suitable for the invention, and in particular, the ion conductor glass is most suitable for the present invention because it has almost no electron movement other than ion movement. What is important in the realization of a memory device using ionic conduction in the present invention is to fabricate a laminated structure of ionic conductors to form a transport barrier between the layers, and to cross the transport barrier between the ionic conductor layers when voltage is applied It is necessary for ions to move. As long as this requirement is satisfied, the combination of ion conductors is not limited.

<Operation method of memory device>
Next, the operation of the memory device using ionic conduction according to the present invention will be described below.

  In the description, ions that move between the first ion conductor layer 31 and the second ion conductor layer 32 are hereinafter referred to as movable ions.

  In the memory device using ionic conduction according to the present invention, the first ionic conductor layer 31 and the second ionic conductor layer 32 move with each other by the voltage applied to the first electrode 33 and the second electrode 34. The writing operation is realized by moving the ions. The movable ions in the present embodiment are Li ions. Therefore, simply, the material of the first ion conductor layer 31 and the second ion conductor layer 32 needs to be the same kind of ion conductor. However, it is only necessary to have the same kind of ion-conducting species, and the number of movable ion species is not limited, but a conductor having only the same positive and negative ions is preferable. At this time, the first ion conductor layer 31 and the second ion conductor layer 32 are formed of different materials and joined to each other, so that the first ion conductor layer 31 and the second ion conductor are connected. At the interface of the body layer 32, the atomic arrangement becomes disordered and the arrangement continuity is lost, so that an ion conduction transport barrier is formed. In this ion transport barrier, when an electric field strength higher than the barrier height is applied, ions move across the barrier, but when an electric field lower than the barrier height is applied, ion movement across the ion barrier does not occur. It does not occur.

  Next, the movement of Li ions from the first ion conductor layer 31 to the second ion conductor layer 32 will be described.

  First, Li ions as movable ions are present in the first ion conductor layer 31 and the second ion conductor layer 32. By applying a voltage of 1 V between the first electrode 33 and the second electrode 34, a potential gradient is generated inside the first ion conductor layer 31 and the second ion conductor layer 32, and according to the gradient. Li ions move. At that time, only ions exceeding the height of the ion transport barrier at the interface existing between the first ion conductor layer 31 and the second ion conductor layer 32 are ion-transferred across the interface.

  When the voltage applied between the first electrode 33 and the second electrode 34 is removed, an ion concentration gradient is generated in the first ion conductor layer 31 and the second ion conductor layer 32. When the voltage is removed, movement of Li ions occurs using the concentration gradient as a driving force. However, since an ion transport barrier exists between the first ion conductor layer 31 and the second ion conductor layer 32, ions that cannot cross the ion transport barrier remain in that place. Therefore, when an ion distribution state before applying a voltage to the first electrode 33 and the second electrode 34 is considered as an initial state, a voltage is applied to the first electrode 33 and the second electrode 34 to apply an applied voltage. After the removal, the ion distribution state different from the initial state can be obtained.

  By the way, since the first ion conductor layer 31 and the second ion conductor layer 32 used in the present embodiment hardly move electrons, the charge bias generated by the movement of Li ions is maintained for a long time. Will be. Since this effect can be realized by the presence of an ion transport barrier layer, it cannot be realized by a structure using a single ion conductor layer.

  Even after the voltage applied to the first electrode 33 and the second electrode 34 was removed due to this bias of electric charge, a potential of about 200 mV remained between the first electrode 33 and the second electrode 34.

  It was confirmed that this potential did not disappear after several hours. This is an effect that could not be realized with a DRAM structure using an ionic conductor as a capacitor. By applying the memory device using the ionic conduction of the present invention to the DRAM structure, non-volatility could be realized. It will be.

  As described above, the ions in the first ion conductor layer 31 and the second ion conductor layer 32 are converted into the first ion conductor layer by the voltage applied to the first electrode 33 and the second electrode 34. By moving ions across the interface between the first ion conductor layer 32 and the second ion conductor layer 32, an ion distribution state different from the initial state is created to achieve the same effect as a capacitor while further moving to the interface. In order to prevent ion retrograde by the existing ion transport barrier, a non-volatile memory function is developed in the form of generation of a residual potential.

  If the first ion conductor 31 and the second ion conductor 32 are materials having an ion transport number of 1 or close to 1, this residual potential is maintained for a long time. Further, if the residual potential or the applied voltage is a potential lower than the redox potential of the mobile ions, the ions are not reduced, and the potential is not lost by other conductive carriers such as electrons and holes. Since the amount of ion movement changes with the writing voltage and the application time, and the residual potential also changes, it can be used as an analog memory.

  It has been described that the write operation of the memory device portion of the present invention is achieved by applying a voltage to the first electrode 33 and the second electrode 34. However, if the voltage application direction is reversed, the movement of ions is performed. Since it is self-evident to proceed in the reverse direction, the memory device using ionic conduction of the present invention can operate reversibly.

  Next, the read operation of the semiconductor memory of the present invention will be described.

  After applying a voltage between the first electrode 33 and the second electrode 34 and performing a writing operation, a potential difference is generated between the first electrode 33 and the second electrode 34. Even if the first electrode 33 and the second electrode 34 are short-circuited in a circuit, the potential difference between the first ion conductor layer 31 and the second ion conductor layer 32 is that only ions are carriers. If there is only a sign of mobile ions, the potential difference is preserved. Therefore, by measuring this potential difference, the ion distribution state of the memory device portion of the present invention can be determined, and this operation corresponds to a read operation.

  FIG. 4 shows the state of the memory device using ionic conduction according to the present invention when the movable ions of the first ionic conductor layer 31 and the second ionic conductor layer 32 are Li +.

  The initial state is a state before performing both reading and writing operations. In the initial ion distribution state, the amount of Li ions in the first ion conductor layer 31 is N1Li, and the amount of Li ions in the second ion conductor layer 32 is N2Li. At this time, the potential difference between the first electrode 33 and the second electrode 34 is set to zero. Writing is performed by applying a voltage between the first electrode 33 and the second electrode 34. Li ions move from the first ion conductor layer 31 to the second ion conductor layer 32 by applying a voltage so that the first electrode 33 side becomes relatively positive. As a result, the number of Li ions in the first ion conductor layer 31 decreases, and the number of Li ions in the second ion conductor layer 32 increases. Thereafter, when the applied voltage is removed, a residual potential Vr is generated between the first electrode 33 and the second electrode 34 as shown in FIG. This potential is smaller than the write potential Vw.

  By sensing this Vr, the read operation is completed. As described above, since reading can directly sense the voltage, there is an advantage that the sensing circuit can be realized with a simple one. Further, another method as described below is also possible for reading. First, since the ion movement is caused by the voltage Vw applied at the time of writing, the voltage Vr which is equal to or lower than the same writing voltage and is equal to or higher than the lowest voltage Vt exceeding the ion barrier is applied. The direction of the voltage applied for reading is fixed at a fixed value. At this time, when the read voltage Vr is applied in the direction opposite to the written ion distribution state (that is, the application direction of Vw), the ions move. Therefore, reading can also be performed by detecting a current flowing through a memory device using ionic conduction when Vr is applied.

  As described above, the semiconductor memory according to the present invention has a structure in which the first ion conductor layer 31 and the second ion conductor layer 32 are stacked, and is applied to the first electrode 33 and the second electrode 34. It has a memory device portion that performs writing by moving ions across an ion transport barrier existing at the interface between the first ion conductor layer 31 and the second ion conductor layer 32 by voltage. The memory device portion using this ionic conduction can operate in a non-volatile manner and can perform an analog operation. Further, by applying a voltage between the first electrode 33 and the second electrode 34, a writing operation can be performed, and information can be read by the potential remaining between the first electrode 33 and the second electrode 34. Therefore, information can be easily read out without using a special sense circuit or the like.

(First Modification of Embodiment 1)
FIG. 5 shows a memory device in which an ion transport barrier layer 53 serving as an ion transport barrier is provided between the first ion conductor layer 51 and the second ion conductor layer 52. 5 is different from FIG. 3 in that an ion transport barrier layer 53 is formed between the first ion conductor layer 51 and the second ion conductor layer 52. Reference numeral 54 denotes a first electrode, and reference numeral 55 denotes a second electrode. The ion transport barrier 53 is formed of, for example, an oxide dielectric layer of Al, Si, Ta, Ti or the like of about several nm, a nanoporous material, a material having a cage structure, or the like.

  For the ion transport barrier layer 53, a material having a higher barrier to ion transport than the first ion conductor layer 51 and the second ion conductor layer 52 may be selected. With the configuration as described above, an ion transport barrier to the first ion conductor layer 51 and the second ion conductor layer 52 is surely formed, so that the first ion conductor layer 51 and the first ion conductor layer 51 The ion transport barrier layer 53 reliably prevents ion movement due to electromotive force due to the concentration of ions in the second ion conductor layer 52, and the retention characteristics of the memory can be improved. For example, by forming the Ti oxide layer 1 nm as the ion transport barrier layer 53 at the interface between the first ion conductor layer 51 and the second ion conductor layer 52 with the same configuration as the first embodiment, It was confirmed that the data was retained for one week, and the effect of the ion transport barrier layer was confirmed.

(Second Modification of Embodiment 1)
A second modification of the first embodiment is shown in FIG. As shown in FIG. 6, the circuit configuration is such that a capacitor 66 is inserted between the ion conductor 61 and the selection transistor 62 or between the memory device portion 61 and the second bit line 65. As a result, charge can be induced in the capacitor by ion movement in the memory device 61 using ion conduction.

  A structure in which the memory device portion 61 and the capacitor 66 are integrated is shown in FIG. As shown in FIG. 7, the first ion conductor layer 71 and the first electrode are configured by forming a dielectric 75 between the first ion conductor layer 71 and the first electrode 73 of the memory device portion. It is possible to induce charges on the dielectric 76 without directly contacting 73. As a result, even if there is a possibility that the reaction between the mobile ions and the electrode becomes a problem, it is possible to prevent the mutual reaction and to induce the charge effectively in the capacitor.

(Embodiment 2)
A semiconductor memory using ion conduction in the second embodiment of the present invention will be described. A circuit diagram of the semiconductor memory cell is shown in FIG. 8, and a structural diagram of the semiconductor memory device portion is shown in FIG.
8 differs from FIG. 1 in that a read line 86 is provided. In the structure diagram of the memory device portion, the difference from FIG. 3 is that a third electrode 95 is provided.

  The memory device portion of the semiconductor memory according to the second embodiment of the present invention will be described in detail with reference to FIG.

  A first ion conductor layer 91, a second ion conductor layer 92, a first electrode 93, a second electrode 94, and a third electrode 95 are provided.

  The difference from the memory device portion used in the first embodiment is that a third electrode 95 is provided.

  Next, the operation of the memory device using ion conduction in the second embodiment of the present invention will be described.

  The writing operation for moving the movable ions is performed using the first electrode 93 and the second electrode 94 as in the first embodiment.

  The difference from the first embodiment is the reading method.

  In the memory device using ion conduction according to the second embodiment, reading is performed by detecting the ion conductivity of the second ion conductor layer 92.

  When ion movement is caused to occur in the second ion conductor layer 92 by the writing operation, the carrier ion concentration of the second ion conductor layer 92 increases.

  Since the ion conductivity of the ion conductor layer changes depending on the ion concentration, when ions are moved to the second ion conductor layer 92 and the carrier ion concentration of the second ion conductor layer 92 is changed, The ionic conductivity of the second ionic conductor layer 92 changes compared to before writing.

  Therefore, the ionic conductivity of the second ionic conductor layer 92 can be sensed by applying a voltage between the second electrode 94 and the third electrode 95 and detecting the flowing ionic current.

  Therefore, since the writing operation is performed by applying a voltage to the first electrode 93 and the second electrode 94 and the reading operation is performed between the second electrode 94 and the third electrode 95, writing and reading can be performed simultaneously. It can function as a two-port memory.

  At this time, the voltage applied to the second electrode 94 and the third electrode 95 may be a voltage necessary to detect the flowing ion current, so that the voltage can be lowered and the write operation is almost affected. There is no.

  Here, since the first ion conductor layer 91 and the second ion conductor layer 92 are joined, the ions that have moved from the first ion conductor layer 91 to the second ion conductor layer 92 are Since it is held in the second ion conductor layer 92, the ion current can be kept constant for a long time.

  Further, when reading is performed by applying a voltage to the second electrode 94 and the third electrode 95, the polarity of the applied voltage is read by applying both positive and negative pulses (that is, the read line 86 in FIG. 8). Voltage applied to the ion conductor layer), and the ion distribution in the ion conductor layer can be read without being largely changed by the read pulse. By adopting the above readout method, it is possible to prevent the segregation of ions due to the readout pulse in the ion conductor.

  In the memory device using ion conduction in the first embodiment of the present invention, a material having an ion transport number of 1 or close to 1 is used as the ion conductor, so that a potential difference remains between the electrodes, and the ion potential is Although the reading operation was performed by reading, the memory device using ionic conduction in the second embodiment is provided with a detection electrode for ionic conductivity, so that the ionic conductor may be a mixed conduction material. There are fewer restrictions on body materials.

(Modification of Embodiment 2)
A modification of the second embodiment is shown in FIG. A semiconductor layer 106 was inserted between the second electrode 104, the third electrode 105, and the second ion conductor layer 102. In this case, it is possible to change the conductance of the semiconductor layer 106 by the carrier ions moved to the second ion conductor layer by applying a voltage. Here, since the first ion conductor layer 101 and the second ion conductor layer 102 are joined together, ions that have moved from the first ion conductor layer 101 to the second ion conductor layer 102 are transferred. Since it is held near the semiconductor layer 106, the conductance can be kept constant even after the voltage is removed.

  The semiconductor memory according to the present invention has a feature of being nonvolatile and non-destructively readable while being a DRAM type, and is useful as a semiconductor memory device and a storage device.

Schematic diagram of semiconductor memory of the present invention Structure schematic diagram of semiconductor memory of the present invention Schematic of the memory device portion of the semiconductor memory of the present invention Explanatory diagram of the potential state of the semiconductor memory of the present invention Schematic of the memory device portion of the first semiconductor memory of the present invention Schematic which shows the modification of the 1st semiconductor memory of this invention Schematic of a memory device portion showing a modification of the first semiconductor memory of the present invention Schematic of the second semiconductor memory of the present invention Schematic of the memory device portion of the second semiconductor memory of the present invention Schematic of a memory device portion showing a modification of the second semiconductor memory of the present invention Schematic diagram showing a conventional semiconductor memory

Explanation of symbols

11 memory device section 12 transistor 13 word line 14 first bit line 15 second bit line 21 silicon substrate 22 transistor section 23 contact 24 memory device section 25 first electrode 26 second electrode 27 first ion conductor Layer 28 Second ion conductor layer 31 First ion conductor layer 32 Second ion conductor layer 33 First electrode 34 Second electrode 53 Ion transport barrier layer 61 Memory device part 62 Transistor 63 Word line 64 First bit line 65 Second bit line 66 Capacitor 75 Dielectric 86 Read line 95 Third electrode 106 Semiconductor layer 111 Select transistor 112 Storage capacitor 113 First capacitor electrode 114 Second capacitor electrode 115 Super ion conductor

Claims (10)

A first ionic conductor comprising a transistor and a memory device, wherein the memory device is formed with a first electrode and a second electrode for applying a voltage, and is sandwiched between the first electrode and the second electrode The transistor is electrically connected to the memory device to control voltage application to the memory device, and the first ion conductor layer and the second ion conductor. Semiconductor memory using a memory device, characterized in that writing is performed by ions moving by a voltage applied to the layer 2. The memory device according to claim 1, further comprising an ion transport barrier layer sandwiched between the first ion conductor layer and the second ion conductor layer. 3. The memory device according to claim 1, wherein a third ion source different from the first electrode and the second electrode is provided on either the first ion conductor layer or the second ion conductor layer. Semiconductor memory using memory device, characterized in that at least one electrode is formed 4. The memory device according to claim 3, wherein a semiconductor layer is provided between the first ion conductor layer or the second ion conductor layer and the first electrode or the second electrode and the detection electrode. Semiconductor memory using memory device 5. The memory device according to claim 1, wherein a capacitor is provided at least between one of the first electrode or the second electrode and the first ion conductor layer or the second ion conductor layer. Semiconductor memory cell using connected memory device 5. The memory device according to claim 1, wherein a memory device is used in which a capacitor is connected to at least one of the first electrode and the second electrode. 5. The memory device according to claim 1, wherein the memory device uses a memory device in which a resistor is connected to the first electrode or the second electrode. 5. The operation method of a semiconductor memory using ion conduction according to claim 1, wherein writing is performed by applying a voltage to the first electrode and the second electrode, and the first electrode and the second electrode are written. A method for operating a semiconductor memory using a memory device, wherein an electric field in a certain direction is reapplied to an electrode of the memory and information is read out 5. An operation method of a semiconductor memory using ion conduction according to claim 3, wherein writing is performed by applying a voltage to the first electrode and the second electrode, and one of the detection electrode and the first electrode. Alternatively, a method for operating a semiconductor memory using a memory device, wherein information is read by applying a voltage between the second electrode and detecting a current 10. The method of operating a semiconductor memory using ion conduction according to claim 9, wherein a positive and negative bipolar pulse is applied when a voltage is applied between the sensing electrode and the first electrode or the second electrode. For operating a semiconductor memory using a memory device

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