WO2013114398A2 - Système de réseau prédiffusé programmable par l'utilisateur (fpga) pour la mise en oeuvre d'un pont usb - Google Patents

Système de réseau prédiffusé programmable par l'utilisateur (fpga) pour la mise en oeuvre d'un pont usb Download PDF

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Publication number
WO2013114398A2
WO2013114398A2 PCT/IN2013/000031 IN2013000031W WO2013114398A2 WO 2013114398 A2 WO2013114398 A2 WO 2013114398A2 IN 2013000031 W IN2013000031 W IN 2013000031W WO 2013114398 A2 WO2013114398 A2 WO 2013114398A2
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Prior art keywords
data
host
usb
module
phy
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PCT/IN2013/000031
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English (en)
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WO2013114398A3 (fr
Inventor
Raghukul Dikshit
Akanksha Jain
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The Tata Power Company Ltd.
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Publication of WO2013114398A2 publication Critical patent/WO2013114398A2/fr
Publication of WO2013114398A3 publication Critical patent/WO2013114398A3/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4045—Coupling between buses using bus bridges where the bus bridge performs an extender function
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the field of computing.
  • this disclosure relates to a system for interfacing devices over a computer bus. Still particularly, this disclosure relates to a system for processing data flow through a Universal Serial Bus (USB) using Field-programmable gate array (FPGA).
  • USB Universal Serial Bus
  • FPGA Field-programmable gate array
  • USB Universal Serial Bus
  • PC Personal Computer
  • a USB 2.0 specification defines three data rates pertaining to clocking rates of a system, namely High Speed (480 Mbps), full Speed (12 Mbps) and Low Speed (1.5 Mbps).
  • USB connects a USB Host like a desktop, a laptop, and the like to a USB Device like a mass storage device, a CD-ROM drive, and the like.
  • USB is based on a tiered star topology supporting up to 127 devices attached to a Host at a time using a 7 bit unique address.
  • Each USB packet is identified by its dedicated packet identifier field, henceforth referred to as PID, thereby distinguishing the USB commands from the USB data packets.
  • PID dedicated packet identifier field
  • USB uses a differential transmission pair for data. This is encoded using Non Return to Zero Inverted (NRZI) encoding format and is overfed to ensure adequate transitions in the data stream.
  • NRZI Non Return to Zero Inverted
  • a differential T is transmitted by pulling D+ over 2.8V with a 15K ohm resistor pulled to ground and D- under 0.3V with a 1.5K ohm resistor pulled to 3.6V.
  • a differential ⁇ ' on the other hand is a D- greater than 2.8V and a D+ less than 0.3V with the same appropriate pull down/up resistors.
  • the USB specification supports four types of data transfers depending on the application involved. These are control, bulk, and isochronous and interrupt transfers. This disclosure deals with USB 2.0 High Speed devices and their communication with a Host. For a USB 2.0 device to be recognized, it has to go through a High Speed signaling process with a chirp sequence handshaking between the Host and the Device.
  • Any High Speed Device is initially recognized as a full Speed Device. Post the chirp sequence, it is ready to operate in a High Speed mode. Full and High Speed devices both have a 1.5 ⁇ pull up on the D+ line. When the Device is connected, power is applied to the cable, the Device, and the pull-up on D+ line. This causes the voltage to rise above Vm at the Host, where V IH is the threshold voltage minimum of two volts for full Speed detection. The USB Host then polls the Device and detects full-Speed Device attachment. After the Host detects that a full-Speed Device is connected, it issues reset to the Device.
  • the Device If the Device is High Speed capable, it initiates the chirp sequence with a chirp K .In response to the chirp K detected by the Host from the Device, the Host sends alternate sequence of Ks and Js to the Device. Upon successful detection of at least 3 such KJ pairs, the Device is transitioned to operate in the High Speed mode. Once the Device is ready to communicate with the Host in High Speed mode, the Device enumeration process begins. For any data transfer between the Host and the Device, the communication has to be necessarily initiated by the Host. Control transfers are typically used for command and status operations. Each control transfer comprises three communication stages namely a setup stage, a data stage and a status stage. The setup stage is where the request is sent.
  • the setup token is sent first in the setup phase, which contains an address and an endpoint number.
  • a data packet is sent and always includes a PID type of data and includes a setup packet which details the type of request. If the Device successfully receives the setup data without any CRC (cyclic redundancy check) or PID (packet identifier) error, it responds with an ACK (acknowledge) handshake. If the packet is corrupted, the Device ignores the data and does not send an ACK handshake packet.
  • the setup stage is the optional data stage which involves data transfer between the Host and the Device. For Bulk write transfers i.e.
  • an OUT token is initiated by the Host. After this, the Host sends the data to the Device. On successful reception, the Device issues an acknowledgement to the Host. If the Device cannot accept data due to some reason, it issues a NAK (negative acknowledge) till the Device becomes ready again to receive data from the Host. For functional errors, a Stall packet is sent by the Device. For Bulk read transfers, an IN token is initiated by the Host. In response to this, if the Device is ready, it sends data to the Host. The Host then acknowledges the data with an ACK packet. Finally to indicate successful data transfer is the status stage which is always directed opposite to the data stage. Thus, a successful data transfer is established between the Host and the Device. In order to prevent the USB bus from slipping into inactive mode, a start of frame is sent by the Host at every 125 micro second intervals for High Speed USB transfers.
  • USB mass storage devices responsible for storage of Bulk data, typically USB flash drives, hard drives, pen drives and the like are portable and hence data security in this media is always a concern.
  • Various techniques have been implemented to incorporate encryption at application software or OS (Operating System) level on the USB Host system.
  • OS Operating System
  • Host software based implementations are plagued with disadvantages including:
  • An object of the disclosure is to provide a low cost single chip implementation of a USB 2.0 bridge comprising a USB Host and a Device on a Field Programmable Gate Array (FPGA).
  • FPGA Field Programmable Gate Array
  • Another object of the disclosure is to provide a framework for encrypting data over USB on-the-fly for enhancing security at the hardware level.
  • Yet another object of the disclosure is to implement USB 2.0 Host and Device core and encryption logic in a single FPGA, thereby providing a power efficient and extremely compact solution.
  • Still another object of the disclosure is to capture real time USB data transfer between a USB 2.0 Host and a Device, without any interference in communication and in strict compliance with the USB 2.0 specifications.
  • Another object of the disclosure is to provide a method for capture and storage of data between a USB 2.0 Host and a Device which could be used for recording purposes.
  • Still another object of the disclosure is to provide a method for capture of USB data for analysis or display, thereby enabling the system to be used as an emulator or for debugging purposes.
  • a Field Programmable Gate Array (FPGA) based USB bridge implementation for communication of data between a USB Host and a USB mass storage device, the USB bridge comprising:
  • the FPGA comprising:
  • an initialization module configured to perform initialization of the USB mass storage device and enable handshaking process between the USB Host and the USB mass storage device;
  • a Host ULPI Device wrapper (UDW) module adapted to communicate with the Host PHY;
  • a Device ULPI Device wrapper (UDW) module adapted to communicate with the Device PHY;
  • a Host Interface Engine adapted to transmit and receive data from the Host UDW module
  • a Device Interface adapted to transmit and receive data from the Device UDW module;
  • a Data Identification and Separation module adapted to receive data from the Host Interface Engine and the Device Interface Engine;
  • Custom Encode Logic module adapted to receive data from the Data Identification and Separation module and further adapted to encrypt the data received from the Host PHY to generate modified write data
  • Custom Decode Logic module adapted to receive data from the Identification and Separation module and further adapted to recover original unmodified data received from the Device PHY to generate decrypted read data
  • a Host Data Combiner module adapted to combine commands from the Data Identification and Separation module and the modified write data into a single stream of Host data, the Host Data Combiner module further adapted to process the Host data and transfer the processed Host data to the Device Interface Engine for further transmission to the USB mass storage device;
  • a Device Data Combiner module adapted to combine commands from the Data Identification and Separation module and the decrypted read data into a single stream of Device data, the Device Data Combiner module further adapted to process the Device data and transfer the processed Device data to the Host Interface Engine for further transmission to the USB Host.
  • the Host PHY and the Device PHY is a Hi-Speed USB physical layer transceiver.
  • the ULPI link is adapted to communicate 8 bit data between the FPGA and each of the Host PHY and the Device PHY.
  • the initialization module referred herein above comprises:
  • a Device initialization sub module adapted to perform the initialization and handshaking process for the USB mass storage device, the Device initialization sub module further comprising a Device disconnect sub module adapted to detect ejection of the USB mass storage device;
  • a power on reset sub module adapted to selectively generate a reset signal for all modules of the FPGA ;
  • each of the Host UDW and the Device UDW comprise a receive module and a transmit module, the receive module being adapted to eliminate the CRC (cyclic redundancy check) from the data to generate pure data packets, the transmit module being adapted to receive the pure data packets and further adapted to recalculate the CRC for the pure data packets and transmit the checked data packets to the USB mass storage device via the Device PHY and the USB Host via the Host PHY respectively.
  • CRC cyclic redundancy check
  • the Host Interface Engine comprises:
  • a Host Protocol Handler comprising a first receive engine and a first transmit engine, the first receive engine adapted to receive data from the Host UDW, the first transmit engine adapted to transmit data to the Host UDW for further transmission to the Host PHY;
  • the Device Interface Engine comprises:
  • a Device Protocol Handler comprising a second receive engine and a second transmit engine, the second receive engine adapted to receive data from the Device UDW, the second transmit engine adapted to transmit data to the Device UDW for further transmission to the Device PHY;
  • the Data Identification and Separation module is adapted to receive data from either a Host receive FIFO or a Device receive FIFO constituting the Host Interface Engine and the Device Interface Engine respectively, the Data Identification module being further adapted to separate the data into non Bulk data for transmission to either of the Host Data Combiner module or the Device Data Combiner module and Bulk data for transmission to either of the Custom Encode Logic module or the Custom Decode Logic module.
  • a method of implementing a USB bridge between a USB Host and a USB mass storage device using a Field Programmable Gate Array comprising the following steps:
  • the method of implementing a USB bridge as described herein above typically comprises the following additional steps:
  • FIGURE 1 illustrates a general representation of an FPGA system for USB bridge implementation in accordance with the present disclosure
  • FIGURE 2 illustrates an overall schematic layout of the components of the Field Programmable Gate Array (FPGA) system for USB Bridge implementation of FIGURE 1;
  • FPGA Field Programmable Gate Array
  • FIGURE 3 illustrates a schematic flow diagram of an FPGA sub-module, exhibiting the FPGA to PHY connectivity
  • FIGURE 4 illustrates a schematic flow diagram of a Host Interface Engine of the Field Programmable Gate Array (FPGA) of FIGURE 2 exhibiting data reception and transmission on the Host side; and
  • FPGA Field Programmable Gate Array
  • FIGURE 5 illustrates a schematic flow diagram of a Device Interface Engine of the Field Programmable Gate Array (FPGA) of FIGURE 2 exhibiting data reception and transmission on the Device side.
  • FPGA Field Programmable Gate Array
  • the present disclosure envisages a Field Programmable Gate Array (FPGA) based Universal Serial Bus (USB) bridge implementation for communication of data between a USB Host and a USB mass storage device.
  • FPGA Field Programmable Gate Array
  • USB Universal Serial Bus
  • the single FPGA based implementation emulates both, a USB 2.0 High Speed Host and a USB 2.0 High Speed Device. Any write or read operation on the Device, initiated by the Host, happens through the USB bridge as envisaged.
  • the disclosure further focuses on data encryption feature at the hardware level for USB mass storage device class in particular.
  • the Field Programmable Gate Array (FPGA) based USB bridge implementation for communication of data between a USB Host, and a USB mass storage device in accordance with the present disclosure will now be explained with reference to FIGURE 1 through FIGURE 5 with the key components being generally referenced by numerals as illustrated.
  • FPGA Field Programmable Gate Array
  • the present disclosure envisages an FPGA 10 for implementation of the USB bridge 60.
  • the FPGA 10 is configured for receiving and converting USB data from a USB Source (USB Host 40 or USB mass storage device 50) into a format compatible for storage and its subsequent transmission to a recipient side (USB mass storage device 50 or USB Host 40) of a communication bus, maintaining compliance with USB 2.0 specifications.
  • the USB system 100 as illustrated in FIGURE 1 reads input data from the USB Source, typically, USB transceivers, in a parallel form, compatible for storage in the FPGA internal buffers and subsequent communication to the intended recipient side (USB mass storage device 50 or Host 40).
  • USB mass storage device 50 or Host 40 USB mass storage device 50 or Host 40
  • the data from the USB Host 40 is written into the FPGA 10 of the USB Bridge 60 through the Host PHY 30.
  • This data, in parallel form, is then stored internally and subsequently communicated to the USB mass storage device 50 through the Device PHY 20 over a Device ULPI (UTMI + Lowe Pin Interface) Interface.
  • UTMI + Lowe Pin Interface UTMI + Lowe Pin Interface
  • FIGURE 2 illustrates an overall schematic layout of the components of the Field Programmable Gate Array (FPGA) system for USB Bridge implementation of FIGURE 1.
  • FPGA Field Programmable Gate Array
  • USB bridge 60 The main components of the USB bridge 60 as illustrated in FIGURE 2 are referenced generally with numerals as indicated below:
  • Custom Encode Logic module 16
  • Custom Decode Logic module 22
  • the USB bridge in accordance with the present disclosure, is implemented using the FPGA 10.
  • the bridge comprises the FPGA 10 as the heart of the system along with two USB PHY (20, 30), one emulating the Host while the other emulating the Device.
  • the Host PHY 30, operating in a Device mode interacts with the USB Host 40 through a USB Interface.
  • the Device PHY 20, operating in a Host mode interacts with the USB mass storage device 50 through its USB Interface.
  • the PHY (30, 20) interacts with the FPGA 10, commonly referred to as link through its ULPI Interface.
  • the Host ULPI Device wrapper (UDW) 34 and the Device ULPI Device wrapper (UDW) 36 communicate directly with the Host PHY 30 and the Device PHY 20 respectively over their corresponding ULPI Interfaces.
  • the initialization module 8 comprises the Device initialization sub module 18 and the power on reset sub module 28.
  • the Device initialization sub-module 18 performs the initialization and the handshaking process for the USB mass storage device 50. It further embodies the Device disconnect module 38.
  • the Device disconnect module 38 supports the plug and play functionality of the USB mass storage device 50 by detecting the mass storage device ejection from the USB system and consequently signaling the power on reset sub module 28 to reset the entire system.
  • a clock module (not shown) provides the respective clocks to the Host and the Device modules of the USB bridge 60.
  • the USB link is a bidirectional link that transmits and receives data over a single differential pair of wire (D+ and D-).
  • the PHYs used Interface the serial USB link with the parallel input Interface of the FPGA 10.
  • the ULPI Device wrapper (UDW) Modules (34, 36) connect to the PHY (20, 30) over the ULPI Interface. This module separates the bidirectional data into individual receive and transmit streams. For example, if the Host sends some data to the Device then the receive engine of the Host UDW 34 strips off the incoming cyclic redundancy check (CRC) and passes pure data packets through the receive stream to the Host Interface Engine 12.
  • CRC cyclic redundancy check
  • the transmit engine of the Device UDW 36 receives this data from the Host UDW 34 after processing through the further sub-modules.
  • the CRC is re-calculated for the data packets in the Device UDW 36 transmit engine and passed on to the Device PHY 30 from where it is subsequently transmitted to the USB mass storage device 50.
  • the separated data receive and transmit data streams are thus passed on to the respective Interface modules for subsequent processing of data till it reaches the other end of the USB bus.
  • the Host Interface Engine 12 processes the incoming Host data from the Host UDW 34 and passes it to the subsequent Data Identification and Separator 32 module. It also reads the response from the Device side and passes it to the Host UDW 34. For data buffering on both the paths, it comprises individual receive and transmit First In First Out storage buffers (henceforth referred to as FIFOs).
  • the receive stream passes the entire set of commands and the unmodified write data to the Data Identification and Separation module 32.
  • the transmit stream receives the Device response from the Device Data Combiner module 26 and passes it to the Host PHY 30 from where it is subsequently passed on to the USB Host 40.
  • the Device Interface Engine 14 processes the incoming Device data from the Device UDW 36 and passes it to the subsequent Data Identification and Separator 32 module. It also reads the data (commands as well as modified write data) from the Host Data Combiner module 24 and passes it to the Device UDW 36. For data storage on both the paths, it comprises individual receive and transmit FIFOs. The receive stream passes the entire set of commands and the modified read data to the data modification module. The transmit stream receives the Host data from the Host Data Combiner module 24 and passes it to the Device PHY 20 from where it is subsequently passed on to the USB mass storage device 50.
  • the USB mass storage device 50 is used to store Bulk data during USB 2.0 Bulk transfers. Henceforth, any data being written by the USB Host 40 to the USB mass storage device 50 is referred to as Bulk write data while any data being read from the USB mass storage device 50 is referred to as Bulk read data.
  • the Data Identifier and Separation module 32 further contains a Data Identification sub module and a Separator sub module.
  • This module receives the data from the receive FIFO of the Host Interface or the Device Interface Engines. Any Bulk operation (whether Bulk read or Bulk write) is always initiated by the USB Host 40, by sending the respective commands to the mass storage device 20.
  • the Data Identification sub module identifies these incoming commands from the Host. Based on the identification, it is ascertained whether the data following the command, needs to be encrypted or decrypted (depending on whether it is a data initiated by the Host or the Device respectively). Once the internal logic processes this data, it is bifurcated into two separate paths namely non-Bulk and Bulk path.
  • the non-Bulk path contains the commands which would be passed blindly through the Data Combiner to the recipient.
  • the Bulk path contains the data which needs to be passed through the Custom Logic module for encryption. If the Bulk data is initiated by the Host to be written into the mass storage device, it is passed to the Custom Encode Logic module 16 for data encryption. On the other hand, if the data is being read from the mass storage device, it is passed to the Custom Decode Logic module 22 for recovering the original unmodified data before passing it to the Host side. Before passing it through the Custom Logic module, this Bulk data is packetized into blocks of 512 bytes and stored in an internal Bulk memory buffer.
  • the Host Data Combiner module 24 sub-module combines the commands coming from the Data Identification and Separation module 32 and modified write data from the Custom Encode Logic module 16 into a single stream of Host data. The combined data is then processed typically into byte data format before passing it to the Device Interface Engine 14.
  • the Device Data Combiner module 26 combines the command coming from the Data Identification and Separation module 32 and decrypted read data from the Custom Decode Logic module 22 into a single stream of data. This combined data is then processed typically into byte data format before passing it to the Host Interface Engine 12.
  • This Custom Encode Logic module 16 is typically, any user defined cryptographic implementation used for securing the data content on the USB mass storage device 50.
  • This module modifies the incoming Bulk write data from the Data Identification and Separation module 32. The write data is then encrypted before finally being written into the USB mass storage device 50 through the Host Data Combiner module 24.
  • the Custom Decode Logic module 22 extracts the original Bulk data from the encrypted read data, during a Bulk read operation. This decoded read data is then passed on to the Device Data Combiner module 26 from where it is subsequently passed on to the USB Host 40.
  • the Decode Logic performs an exactly reverse operation, of the Encode Logic, on the incoming modified data in order to extract the original data from it.
  • FIGURE 3 illustrates a schematic flow diagram exhibiting the FPGA 10 to PHY connectivity.
  • a USB Host 40 or Device communicates with a corresponding ULPI Device wrapper via a respective PHY.
  • the ULPI Interface comprises 12 signals to communicate with the FPGA 10, commonly referred to as the link.
  • Each ULPI Device wrapper (UDW) consists of two engines referred to as a receive module and a transmit module.
  • the received information from the USB Host 40 or Device is processed by the receive module and subsequently signaled to the corresponding Interface Engine.
  • the transmit module receives information from a Transmit FIFO and eventually passes it to the intended recipient.
  • an 8 bit ULPI data bus can either transmit data to the link or receive data from the link.
  • the PHY sends data to the FPGA 10 on assertion of the DIR signal. Only when the DIR signal is de-asserted, the link can initiate data transmission to the PHY. Each data byte is acknowledged by the PHY with the assertion of the NXT signal.
  • the USB PHY is a Hi-Speed USB Physical Layer Transceiver (PHY).
  • PHY Hi-Speed USB Physical Layer Transceiver
  • ULPI Interface allows the USB PHY to operate as a Device, Host, or an On-The-Go (OTG) Device.
  • OTG On-The-Go
  • This PHY is designed from the start with a ULPI Interface. This provides the PHY with a low latency transmit and receive time.
  • the simple and efficient ULPI Interface supported by the USB PHY makes it aptly suitable for FPGA 10 interfacing purpose.
  • the receive module of the ULPI Device wrapper module receives the information from the USB (Host/Device) through the PHY over the ULPI Interface and bifurcates the electrical level signaling data from the USB packets. The processed information is then passed to the corresponding Interface Engine module wherein it is subsequently written into the corresponding receive FIFO. This stored data is then processed before it is being finally read at the recipient side.
  • UW ULPI Device wrapper module
  • the transmit module of the ULPI Device wrapper (UDW) module receives the information from the link and transmits it to the PHY over the ULPI Interface. This module retrieves the data from a transmit FIFO and makes it compatible to be transmitted to the USB PHY. The information is transmitted to the PHY on the de-assertion of the direction (DIR) signal. The transmission is commissioned with assertion of the stop (STP) signal indicating the last data bit being sent, in full compliance with the ULPI specifications.
  • DIR de-assertion of the direction
  • STP stop
  • FIGURE 4 illustrates a schematic flow diagram of a Host Interface Engine of the Field Programmable Gate Array (FPGA) of FIGURE 2 exhibiting data reception and transmission on the Host side.
  • the Host Interface Engine 12 comprises the Host Protocol Handler, the Host receive FIFO and the Host transmit FIFO.
  • the Host Protocol Handler in turn comprises a receive engine, and a transmit engine.
  • the receive engine receives the data from the Host UDW 34 and finally writes it into the Host receive FIFO.
  • the Tx engine reads off the data from the Host transmit FIFO and finally gives it to the UDW.
  • the UDW in turn transmits it to the Host-PHY.
  • the Host receive FIFO consists of either the command or the unmodified Bulk write data which needs to be encrypted before finally sending to the Device.
  • the Host transmit FIFO either contains the handshakes from the Device or the decrypted Bulk read data.
  • the Host Protocol Handler is responsible for handling the USB data traffic on the Host side. It receives the data to be passed on to the USB mass storage device 50 and stores it in the Host receive FIFO. Internal logic within this module ensures full compliance with the ULPI timing specifications. The internal logic within this module keeps the Host engaged in the response activity till the Device response reaches the Host. This prevents the USB bus from slipping into suspend state.
  • the Host receive FIFO contains the data from the Host to be eventually sent to the Device. It has independent clock domains for write and read operation.
  • the information stored is either the commands or the Bulk write data preceding the encryption stage.
  • the data is written on the Host clock while read off on the Device clock.
  • the Host transmit FIFO contains the data from the Device to be eventually sent to the Host. It has independent clock domains for write and read operations.
  • the information stored is either the commands or the Bulk read data following the decryption stage.
  • the data is written on the Device clock while read off on the Host clock.
  • FIGURE 5 illustrates a schematic flow diagram of a Device Interface Engine of the Field Programmable Gate Array (FPGA) of FIGURE 2 exhibiting data reception and transmission on the Device side.
  • the Device Interface module comprises the Device Protocol Handler, the Device receive FIFO and the Device transmit FIFO.
  • the Device Protocol Handler in turn comprises a Receive Engine, and a Transmit Engine.
  • the receive engine receives the data from the Device UDW 36 and writes it into the Device receive FIFO.
  • the Tx engine reads the data from the Device transmit FIFO and finally gives it to the Device UDW 36. This UDW in turn transmits it to the Device PHY.
  • the Device receive FIFO consists of either the command or the encrypted read data which needs to be decrypted before finally sending to the Host 40.
  • the Device transmit FIFO either contains the commands or the encrypted Bulk write data (after passing to the Custom Encode Logic 16 module) to be written to the mass storage device.
  • the Device Protocol Handler is responsible for handling the USB data traffic on the Device side. It receives the data to be passed on to the USB Host 40 and stores it in the Device receive FIFO. Internal logic within this module ensures full compliance with the ULPI timing specifications.
  • the Device Interface Engine 14 too comprises separate receive and transmit buffers.
  • the Device receive FIFO is used to buffer the incoming unprocessed data from the USB mass storage device 50 before passing it to the Data Identifier and Separator module for subsequent processing.
  • the Device transmit FIFO receives the input from the Host Data Combiner module 24 and subsequently passes it to the USB mass storage device 50 through the Device UDW 36.
  • the present disclosure thus provides a USB bridge implementation using an FPGA to overcome the drawbacks of the prior art.
  • the technical advancements offered by the Field Programmable Gate Array (FPGA) based USB bridge of the present disclosure includes the realization of: • a low cost single chip implementation of a USB 2.0 bridge comprising a USB Host and a Device on a Field Programmable Gate Array (FPGA);

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Abstract

La mise en œuvre d'un pont USB fondé sur un réseau prédiffusé programmable par l'utilisateur (FPGA) pour la communication de données entre un hôte USB et un dispositif de stockage en masse USB permet de surmonter les inconvénients que présente l'état de la technique, parmi lesquels figure le manque de sécurité causé par la mise en œuvre d'un chiffrement sur une base logicielle et la dépendance entre pilote et OS. Le pont USB comprend un PHY d'hôte fonctionnant en mode dispositif et un PHY de dispositif fonctionnant en mode hôte, en liaison avec l'hôte USB et le dispositif de stockage de masse USB, respectivement par l'intermédiaire d'un lien USB bidirectionnel. Le FPGA est relié au PHY d'hôte et au PHY de dispositif, respectivement par l'intermédiaire d'un lien ULPI bidirectionnel. Les données provenant de l'hôte USB sont écrites dans le FPGA du pont USB par l'intermédiaire du PHY d'hôte. Ces données en parallèle sont ensuite stockées en interne puis communiquées au dispositif de stockage de masse USB par le PHY de dispositif par l'intermédiaire de l'interface ULPI de dispositif.
PCT/IN2013/000031 2012-01-30 2013-01-17 Système de réseau prédiffusé programmable par l'utilisateur (fpga) pour la mise en oeuvre d'un pont usb WO2013114398A2 (fr)

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CN103559159A (zh) * 2013-10-25 2014-02-05 华为技术有限公司 一种信息处理方法以及电子设备
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US10165130B2 (en) 2014-02-13 2018-12-25 Emerge Print Management, Llc System and method for the passive monitoring and reporting of printer-related data on USB cables
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