WO2013109234A3 - Method to accelerate message signaled interrupt processing - Google Patents

Method to accelerate message signaled interrupt processing Download PDF

Info

Publication number
WO2013109234A3
WO2013109234A3 PCT/US2011/059182 US2011059182W WO2013109234A3 WO 2013109234 A3 WO2013109234 A3 WO 2013109234A3 US 2011059182 W US2011059182 W US 2011059182W WO 2013109234 A3 WO2013109234 A3 WO 2013109234A3
Authority
WO
WIPO (PCT)
Prior art keywords
interrupt
msi
interrupt processing
message signaled
signaled interrupt
Prior art date
Application number
PCT/US2011/059182
Other languages
French (fr)
Other versions
WO2013109234A2 (en
Inventor
Yen Hsiang Chew
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2011/059182 priority Critical patent/WO2013109234A2/en
Priority to US13/976,213 priority patent/US9378163B2/en
Priority to TW101140537A priority patent/TWI502361B/en
Publication of WO2013109234A2 publication Critical patent/WO2013109234A2/en
Publication of WO2013109234A3 publication Critical patent/WO2013109234A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/24—Interrupt
    • G06F2213/2418—Signal interruptions by means of a message

Abstract

Methods to accelerate a message signaled interrupt (MSI) are described herein. An embodiment of the invention includes an interrupt controller to receive a messaged signaled interrupt (MSI) request from a device over a bus, and an execution unit coupled to the interrupt controller to execute an interrupt service routine (ISR) associated with the device, the execution unit to retrieve interrupt data from a predetermined memory location specifically allocated to the device and to service the MSI using the interrupt data, without having to obtain the device interrupt data via an input output (IO) transaction.
PCT/US2011/059182 2011-11-03 2011-11-03 Method to accelerate message signaled interrupt processing WO2013109234A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/US2011/059182 WO2013109234A2 (en) 2011-11-03 2011-11-03 Method to accelerate message signaled interrupt processing
US13/976,213 US9378163B2 (en) 2011-11-03 2011-11-03 Method to accelerate message signaled interrupt processing
TW101140537A TWI502361B (en) 2011-11-03 2012-11-01 Processor, method, and system to accelerate message signaled interrupt processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2011/059182 WO2013109234A2 (en) 2011-11-03 2011-11-03 Method to accelerate message signaled interrupt processing

Publications (2)

Publication Number Publication Date
WO2013109234A2 WO2013109234A2 (en) 2013-07-25
WO2013109234A3 true WO2013109234A3 (en) 2013-10-10

Family

ID=48799785

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/059182 WO2013109234A2 (en) 2011-11-03 2011-11-03 Method to accelerate message signaled interrupt processing

Country Status (3)

Country Link
US (1) US9378163B2 (en)
TW (1) TWI502361B (en)
WO (1) WO2013109234A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8996774B2 (en) * 2012-06-27 2015-03-31 Intel Corporation Performing emulated message signaled interrupt handling
US10078603B2 (en) * 2012-11-30 2018-09-18 Red Hat Israel, Ltd. MSI events using dynamic memory monitoring
US9830286B2 (en) 2013-02-14 2017-11-28 Red Hat Israel, Ltd. Event signaling in virtualized systems
CN109684152B (en) * 2018-12-25 2023-03-24 广东浪潮大数据研究有限公司 RISC-V processor instruction downloading method and device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030182484A1 (en) * 2002-03-19 2003-09-25 Intel Corporation Interrupt processing apparatus, system, and method
US20040221066A1 (en) * 2003-05-01 2004-11-04 International Business Machines Corporation Method and apparatus for implementing packet command instructions for network processing
US20060047877A1 (en) * 2004-08-31 2006-03-02 Advanced Micro Devices, Inc. Message based interrupt table
US20060259658A1 (en) * 2005-05-13 2006-11-16 Connor Patrick L DMA reordering for DCA
US20070005858A1 (en) * 2005-06-30 2007-01-04 Intel Corporation Extended message signal interrupt

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW501017B (en) * 2000-04-05 2002-09-01 Via Tech Inc Processing method, chip set and controller for supporting message signaled interrupt
US8762595B1 (en) * 2005-04-05 2014-06-24 Oracle America, Inc. Method for sharing interfaces among multiple domain environments with enhanced hooks for exclusiveness
US7949813B2 (en) * 2007-02-06 2011-05-24 Broadcom Corporation Method and system for processing status blocks in a CPU based on index values and interrupt mapping
US9384154B2 (en) * 2011-11-03 2016-07-05 Intel Corporation Method to emulate message signaled interrupts with multiple interrupt vectors

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030182484A1 (en) * 2002-03-19 2003-09-25 Intel Corporation Interrupt processing apparatus, system, and method
US20040221066A1 (en) * 2003-05-01 2004-11-04 International Business Machines Corporation Method and apparatus for implementing packet command instructions for network processing
US20060047877A1 (en) * 2004-08-31 2006-03-02 Advanced Micro Devices, Inc. Message based interrupt table
US20060259658A1 (en) * 2005-05-13 2006-11-16 Connor Patrick L DMA reordering for DCA
US20070005858A1 (en) * 2005-06-30 2007-01-04 Intel Corporation Extended message signal interrupt

Also Published As

Publication number Publication date
TWI502361B (en) 2015-10-01
TW201344448A (en) 2013-11-01
US20140189182A1 (en) 2014-07-03
US9378163B2 (en) 2016-06-28
WO2013109234A2 (en) 2013-07-25

Similar Documents

Publication Publication Date Title
MX2013008072A (en) System, method, and article to prompt behavior change.
WO2012106806A8 (en) System and method of interfacing co-processors and input/output devices via a main memory system
IN2014DN08833A (en)
EP2857952A4 (en) Method for processing input/output request, host, server, and virtual machine
IL231184A0 (en) System for diagnosing bloodflow characteristics, method thereof, and computer software program
EP2500817A3 (en) Information processing apparatus, information processing system and device linkage method
WO2013078416A3 (en) Apparatus, system, and method to promote behavior change based on mindfulness methodologies
GB201219578D0 (en) System and control method
WO2013016385A3 (en) Multi-core shared page miss handler
WO2012023152A3 (en) Multi-processor electronic systems
EP2680140A3 (en) A method, an apparatus and a computer program product for extending an application in a client device
BR112013027005A2 (en) method and system for sharing and using location information on a handheld terminal
EP2881860A4 (en) Method for implementing an interrupt between virtual processors, related device, and system
GB2565940A (en) Method and apparatus for scheduling in a non-uniform compute device
GB2512785A (en) Distributed function execution for hybrid systems
WO2013109234A3 (en) Method to accelerate message signaled interrupt processing
MX2012015137A (en) Method and system for routing communications.
BR112013027073A2 (en) computing device, method for providing a virtual bios for a virtual machine and computer readable media
EP2672483A3 (en) Data processing system with retained sector reprocessing
EP2650773A3 (en) Data processing system with out of order transfer
GB201302920D0 (en) Managing a storage device using a hybrid controller
MX341218B (en) Application monitoring.
WO2012144757A3 (en) Method and apparatus for connecting devices
EP2892221A3 (en) Information processing system, information processing method, and device
WO2012177877A3 (en) System and method for performing isochronous data buffering

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13976213

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11879178

Country of ref document: EP

Kind code of ref document: A2

122 Ep: pct application non-entry in european phase

Ref document number: 11879178

Country of ref document: EP

Kind code of ref document: A2