WO2013090932A1 - Détection d'introduction de fiche - Google Patents

Détection d'introduction de fiche Download PDF

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Publication number
WO2013090932A1
WO2013090932A1 PCT/US2012/070191 US2012070191W WO2013090932A1 WO 2013090932 A1 WO2013090932 A1 WO 2013090932A1 US 2012070191 W US2012070191 W US 2012070191W WO 2013090932 A1 WO2013090932 A1 WO 2013090932A1
Authority
WO
WIPO (PCT)
Prior art keywords
plug
output
jack
coupled
detection circuitry
Prior art date
Application number
PCT/US2012/070191
Other languages
English (en)
Inventor
Peter J. Shah
Arash MEHRABI
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/433,799 external-priority patent/US9031253B2/en
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of WO2013090932A1 publication Critical patent/WO2013090932A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R5/00—Stereophonic arrangements
    • H04R5/04—Circuit arrangements, e.g. for selective connection of amplifier inputs/outputs to loudspeakers, for loudspeaker detection, or for adaptation of settings to personal preferences or hearing impairments
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
    • G01R31/68—Testing of releasable connections, e.g. of terminals mounted on a printed circuit board
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R2201/00—Details of transducers, loudspeakers or microphones covered by H04R1/00 but not provided for in any of its subgroups
    • H04R2201/10—Details of earpieces, attachments therefor, earphones or monophonic headphones covered by H04R1/10 but not provided for in any of its subgroups
    • H04R2201/107—Monophonic and stereophonic headphones with microphone for two-way hands free communication
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R2420/00—Details of connection covered by H04R, not provided for in its groups
    • H04R2420/05—Detection of connection of loudspeakers or headphones to amplifiers

Definitions

  • the disclosure relates to audio and other media devices, and, in particular, to techniques for automatically detecting insertion of a media plug into a corresponding jack.
  • the disclosure relates to audio and other media devices, and, in particular, to techniques for automatically detecting insertion of a media plug into a corresponding jack.
  • Audio and other media devices often include a jack for receiving a media plug coupled to a peripheral device.
  • a mobile phone may include a jack for receiving a plug coupled to an audio headset with microphone, which allows a user to carry on a voice conversation over the mobile phone using the headset.
  • Other example media devices include MP3 players, handheld gaming devices, tablets, personal computers, notebook computers, personal digital assistants, etc., while other peripheral devices include headphones, hearing-aid devices, personal computer speakers, home entertainment stereo speakers, etc.
  • a media device may be configured to take different actions depending on whether the peripheral device is plugged into the jack or not.
  • an MP3 player may route an audio signal to an audio headset when the headset is plugged in, and otherwise route the audio signal to built-in speakers.
  • one or two additional mechanical pins may be provided in the jack to detect whether a plug is inserted or not. Such additional pins generally need to be routed to an appropriate chip for processing, and further increase the cost of the device in terms of material, board area, chip area, chip pin count, jack size, etc.
  • the form factor of the device may be adversely affected as well.
  • FIG 1 illustrates an exemplary scenario wherein the techniques of the present disclosure may be applied.
  • FIG 2 illustrates an exemplary embodiment of a plug insertion detection system according to the present disclosure.
  • FIG 3 illustrates an exemplary embodiment of a method according to the present disclosure.
  • FIG 4 illustrates an exemplary embodiment of the present disclosure wherein techniques for plug type detection are combined with the techniques for plug insertion detection described herein.
  • FTG 1 illustrates an exemplary scenario 100 wherein the techniques of the present disclosure may be applied.
  • FIG 1 is shown for illustrative purposes only, and is not meant to limit the scope of the present disclosure to the particular system shown.
  • the techniques disclosed herein may also be readily applied to audio devices other than that shown in FIG 1.
  • the techniques may also be readily adapted to other types of multi-media devices, as well as to non-audio media devices, e.g., to accommodate detection of video plug insertion into a video jack.
  • Such alternative exemplary embodiments are contemplated to be within the scope of the present disclosure.
  • a headset 110 includes a left (L) headphone 115, a right (R) headphone
  • the headset 110 is electrically coupled to terminals of a plug 150, which is insertable into a jack 160 of an audio device 140.
  • a plug 150 which is insertable into a jack 160 of an audio device 140.
  • the jack 160 need not extrude from the surface of the device 140 as suggested by FIG 1, and furthermore, the sizes of the elements shown in FIG 1 are generally not drawn to scale.
  • the device 140 may be, for example, a mobile phone, MP3 player, home stereo system, etc. Audio and/or other signals may be exchanged between the device 140 and the headset 110 through the plug 150 and jack 160.
  • the plug 150 receives the audio signals from the jack 160, and routes the signals to the L and R headphones of the headset 110.
  • the plug 150 may further couple an electrical signal with audio content generated by the microphone 130 to the jack 160, and the microphone signal may be further processed by the device 140.
  • the plug 150 may include further terminals not shown, e.g., for communicating other types of signals such as control signals, etc.
  • the headset 110 is detachable from the device 140 by the user.
  • different actions may be taken by the device 140 depending on whether the headset 110 is attached to or detached from the device 140.
  • the device 140 may route an audio signal to the headset 110 when the plug 150 is plugged in, and otherwise may route the audio signal to a built-in speaker (not shown) when the plug 150 is not plugged in. Consequently, it may be desirable to provide techniques for enabling the device 140 to automatically detect when a plug 150 of a peripheral device such as the headset 110 is properly inserted into the jack 160.
  • FIG 2 illustrates an exemplary embodiment 200 of a plug insertion detection system according to the present disclosure.
  • the plug insertion detection system 200 may be provided in the device 140 of FIG 1, e.g., on the same integrated circuit (not shown) on which the audio processing circuitry is provided.
  • an exemplary instance 150.1 of an audio plug 150 is shown fully inserted into a jack 160.1.
  • the audio plug 150.1 has a particular configuration of terminals known as a North-American type configuration, wherein four terminals are provided in series from the base 150a to the tip 150b of the plug 150.1.
  • the four terminals on the plug 150.1 are the microphone terminal (labeled "M” in FIG 2), ground terminal ("G”), right audio channel (“R”), and left audio channel (“L”).
  • terminals are coupled to the corresponding components of the headset 110 as illustrated in FIG 1, with the G terminal being coupled to a common ground connection in the headset 110 not shown in FIG 1.
  • the microphone 130 effectively presents a load resistance RM between the M and G terminals of the plug 150.
  • the right headphone presents a load resistance RR between the R and G terminals of plug 150, and the left headphone presents a load resistance RL between the L and G terminals.
  • jack 160.1 includes terminals #1, #2, #3, and #4, that are electrically engaged with the L, R, G, and M terminals, respectively, of the fully inserted plug 150.1 in FIG 2.
  • the terminals of the jack 160.1 electrically couple the terminals of the plug 150.1 to various nodes of the device 140, which processes signals to and from the headset 110.
  • terminal #1 of the jack 160.1 is coupled to the output of a power amplifier
  • PA PA 222 for driving the L headphone with a voltage VL.
  • the output of the PA 222 may be selectively configured to be a high impedance node if the PA 222 is not called upon to drive the L headphone, for example, when the plug 150.1 is not inserted in the jack 160.1.
  • insertion detection circuitry 220 Further coupled to the output of the PA 222 is insertion detection circuitry 220, whose functionality is further described hereinbelow.
  • the insertion detection circuitry 220 includes a current source 224 and a voltage comparison block 226.
  • the output of the PA 222 is configured to have a high impedance.
  • the plug 150.1 is not fully inserted into the jack 160.1 (i.e., the contrary scenario to what is shown in FIG 2)
  • the node corresponding to VL will remain at high impedance, since there is no other low-resistance path from VL to ground.
  • the current source 224 will cause the voltage VL to be pulled to either of the voltage supply rails, depending on the directionality of the current source. For example, if current source 224 sources positive current from a high voltage supply, then VL will be pulled high.
  • current source 224 sinks positive current to a low voltage supply, then VL will be pulled low.
  • the current source 224 may be configured to source or sink a very low current, e.g., on the order of micro Amps, to reduce standby power consumption.
  • the voltage comparison block 226 compares the level of VL to a predetermined voltage level.
  • the output of block 226 may be directly used as a plug insertion detection indicator.
  • the output of block 226 may indicate no plug insertion when VL is close to the high or low voltage rail, to within a predetermined margin.
  • dynamic techniques may be employed to further process the output voltage of the comparison block 226.
  • additional logic e.g., state machine logic, may be provided to detect whether the output voltage of comparison block 226 undergoes a transition from a high voltage to a low voltage, or vice versa, to further improve robustness of the plug insertion detection mechanism.
  • a digital processing module may be further provided to process any indications of plug insertion to, e.g., alter the operation of the device 140 in response to plug insertion detection.
  • a digital processing module may be further provided to process any indications of plug insertion to, e.g., alter the operation of the device 140 in response to plug insertion detection.
  • the current source 224 may be a transistor current source, i.e., having the drain of a MOS transistor coupled to the output of the current source 224.
  • the current source 224 may include a large resistance coupled to a DC voltage.
  • Such alternative exemplary embodiments are contemplated to be within the scope of the present disclosure.
  • a voltage comparison block 226 may be implemented as a comparator, e.g., a Schmitt trigger.
  • the voltage comparison block 226 may be replaced by an inverter (not shown) having a single input coupled to the voltage VL.
  • current source 224 sources positive current from a high voltage supply
  • VL will be high when there is no load, and consequently the inverter output would be low.
  • the inverter output would be high when there is a load coupled to VL. In this manner, the inverter output would indicate the presence of a load at VL.
  • Such alternative exemplary embodiments are contemplated to be within the scope of the present disclosure.
  • the aforementioned techniques advantageously allow the device insertion detection block 220 to detect full plug insertion, as opposed to only partial insertion.
  • providing the insertion detection circuitry 220 at terminal #1 of the jack 160.1 requires that the tip of the plug 150.1 be fully inserted into the jack 160.1 for the corresponding load to be detected by the circuitry 220.
  • the plug 150.1 were only partially inserted into the jack 160.1, e.g., such that the L terminal of the plug 150.1 instead became electrically engaged with terminal #2 of the jack 160.1 (i.e., three-quarters insertion), then the circuitry 220 coupled to the innermost terminal #1 of the jack 160.1 would not detect insertion.
  • the load detected by the insertion detection circuitry 220 corresponds to the left headphone, or RL, at the tip of the plug 150.1. While a North-American type configuration for the audio plug is illustratively shown in FIG 2, it will be appreciated that the techniques of the present disclosure may be readily applied to alternative plug configurations. The techniques described herein may readily be modified by one of ordinary skill in the art to detect insertion of a plug with alternative terminals and/or an alternative sequence of terminals from that shown in FIG 2.
  • a European type plug having an alternative sequence of terminals (i.e., ordered as G, M, R, L from the base of the plug to the tip), or an auxiliary connector (having, e.g., only G, R, and L terminals), or a video plug, etc., may be readily accommodated using the techniques of the present disclosure.
  • the insertion detection circuitry may always be provided at the innermost terminal of a jack 160, i.e., terminal #1 of jack 160.1 as shown in FIG 2, regardless of whether insertion detection circuitry is also provided at other terminals of the jack 160.1, e.g., terminals #2, #3, #4, etc.
  • similar techniques may be optionally applied to detect whether either (or both) of the other terminals (R or M) of the jack 160.1 is also inserted into the jack.
  • optional insertion detection circuitry 230 and 240 are shown for detecting the presence of a load at the corresponding terminals, e.g., the impedance RR of the right headphone or RM of the microphone.
  • insertion detection circuitry 230 may be provided to detect electrical coupling of the R terminal of the plug 150.1 to terminal #2 of the jack 160.1, in a similar manner as described for the insertion detection circuitry 220 above.
  • insertion detection circuitry 240 may be provided at the output of the microphone bias set block 242, i.e., directly coupled to the output voltage VMbias of the microphone bias set block 242, to detect electrical coupling of the M terminal of the plug 150.1 to terminal #4 of the jack 160.1.
  • an indication of full plug insertion may correspond to, e.g., circuitry 220, 230, and 240 all indicating that the corresponding loads have been detected.
  • voltage comparison blocks 226, 236, and 246 may detect that the corresponding voltages at VL, VR, and VMbias, respectively, are close to ground, prior to signaling that full plug insertion is detected.
  • the power amplifiers 222 and 232 may drive the left and right headphones (or speakers) with an audio signal, e.g., voice, music, etc.
  • the inputs to the power amplifiers 222, 232 may be driven by an appropriate audio signal generator (not shown in FIG 2).
  • terminal #4 of the jack 160.1 may be coupled to a microphone bias set block 242, which may generate a DC bias voltage for biasing the microphone coupled to the plug 150.1 via the bias resistor Rb.
  • Terminal #4 may further be coupled to a microphone signal processing block (not shown) for further processing by the device 140.
  • an exemplary embodiment incorporating the insertion detection circuitry 240 may also be configured to detect when the plug 150.1 is removed from the jack. For example, during playback (e.g., when PA's 222 and 232 are actively driving the L and R terminals, respectively), the insertion detection circuitry 220, 230 may be disabled, as the outputs of PA's 222 and 232 are not configured to have high impedance. In this case, the insertion detection circuitry 240 associated with the microphone bias set 242 output can be used to detect removal, by detecting changes in VMbias as described hereinabove. It will be appreciated that during this time, the output of microphone bias set 242 may be configured to have a high impedance.
  • the insertion detection circuitry 240 may be correspondingly disabled. In this case, either the insertion detection circuitry 220 or 230 may instead be used to detect removal.
  • VMic may be AC- coupled to the microphone signal processing using a coupling capacitor (not shown in FIG 2).
  • the DC voltage content would be lost to any circuitry associated with the microphone signal processing, but would be preserved by circuitry such as insertion detection circuitry 240 coupled to the microphone bias set 242.
  • FIG 3 illustrates an exemplary embodiment of a method 300 according to the present disclosure.
  • a first power amplifier is coupled to a first output.
  • distinct voltages are generated based on whether a load is detected to be coupled to the first output.
  • the innermost terminal of the jack makes contact with the left headphone channel of the plug when the plug is fully inserted.
  • FIG 4 illustrates an exemplary embodiment of the present disclosure wherein techniques for plug type detection are combined with the techniques for plug insertion detection described herein. Note FIG 4 is shown for illustrative purposes only, and is not meant to limit the scope of the present disclosure. In FIG 4, elements labeled with the same numerals as in FIG 2 will be understood to have similar functionality, unless otherwise stated.
  • a switch SI selectively couples the output of the PA 232 to a reference voltage VREF, e.g., ground.
  • VREF reference voltage
  • the plug type of the inserted plug 150.1 may be determined as either North American or European.
  • VMic is determined to be a high voltage when S 1 couples VR to ground
  • the plug 150.1 may be determined to have a North American plug type.
  • VMic is determined to be a low voltage (i.e., close to ground) when SI couples VR to ground
  • the plug 150.1 may be determined to have a European plug type. Further details of the plug type detection scheme may be found in U.S. Provisional Pat.
  • DSP Digital Signal Processor
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • a general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
  • a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
  • a software module may reside in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
  • the storage medium may be integral to the processor.
  • the processor and the storage medium may reside in an ASIC.
  • the ASIC may reside in a user terminal.
  • the processor and the storage medium may reside as discrete components in a user terminal.
  • the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
  • Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
  • a storage media may be any available media that can be accessed by a computer.
  • such computer- readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.
  • any connection is properly termed a computer-readable medium.
  • the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave
  • the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.
  • Disk and disc includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-Ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Acoustics & Sound (AREA)
  • Signal Processing (AREA)
  • Circuit For Audible Band Transducer (AREA)

Abstract

L'invention concerne des techniques pour détecter une introduction complète d'une fiche multimédia dans une prise correspondante. Selon un mode de réalisation donné à titre d'exemple, un premier circuit de détection d'introduction pour détecter la présence d'une charge est accouplé à la borne la plus à l'intérieur de la prise. Pour les fiches audio de type nord américain, le premier circuit de détection d'introduction détecte la présence d'un canal d'écouteur gauche accouplé à la borne la plus à l'intérieur de la fiche. L'accouplement du circuit de détection d'introduction à la borne la plus à l'intérieur de la fiche permet avantageusement la détection uniquement lorsque la fiche est entièrement introduite dans la prise. Un circuit de détection supplémentaire peut être prévu et accouplé aux autres bornes de la prise. Les techniques décrites peuvent être facilement appliquées à d'autres types de fiches multimédia, par exemple des fiches audio européennes, des fiches vidéo, etc.
PCT/US2012/070191 2011-12-16 2012-12-17 Détection d'introduction de fiche WO2013090932A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201161576868P 2011-12-16 2011-12-16
US61/576,868 2011-12-16
US13/433,799 US9031253B2 (en) 2011-12-16 2012-03-29 Plug insertion detection
US13/433,799 2012-03-29

Publications (1)

Publication Number Publication Date
WO2013090932A1 true WO2013090932A1 (fr) 2013-06-20

Family

ID=48613286

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2012/070191 WO2013090932A1 (fr) 2011-12-16 2012-12-17 Détection d'introduction de fiche

Country Status (1)

Country Link
WO (1) WO2013090932A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3142195A4 (fr) * 2014-05-30 2017-04-19 Huawei Technologies Co., Ltd. Support d'écouteur
CN113169489A (zh) * 2018-11-29 2021-07-23 索尼互动娱乐股份有限公司 分割式接地连接器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080164994A1 (en) * 2007-01-05 2008-07-10 Timothy Johnson Audio I/O headset plug and plug detection circuitry
US20100215183A1 (en) * 2009-02-26 2010-08-26 Research In Motion Limited Audio jack for a portable electronic device
US20110099298A1 (en) * 2009-10-27 2011-04-28 Fairchild Semiconductor Corporation Method of detecting accessories on an audio jack

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080164994A1 (en) * 2007-01-05 2008-07-10 Timothy Johnson Audio I/O headset plug and plug detection circuitry
US20100215183A1 (en) * 2009-02-26 2010-08-26 Research In Motion Limited Audio jack for a portable electronic device
US20110099298A1 (en) * 2009-10-27 2011-04-28 Fairchild Semiconductor Corporation Method of detecting accessories on an audio jack

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3142195A4 (fr) * 2014-05-30 2017-04-19 Huawei Technologies Co., Ltd. Support d'écouteur
US9854373B2 (en) 2014-05-30 2017-12-26 Huawei Technologies Co., Ltd. Headphone socket
CN113169489A (zh) * 2018-11-29 2021-07-23 索尼互动娱乐股份有限公司 分割式接地连接器

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