WO2013068633A2

WO2013068633A2 - Methods and systems for cmos-based radio-frequency filters of mems having organized sets of elements

Info

Publication number: WO2013068633A2
Application number: PCT/ES2012/070788
Authority: WO
Inventors: Josep MONTANYÀ SILVESTRE; Marc Antonio LLAMAS MOROTE
Original assignee: Baolab Microsystems Sl
Priority date: 2011-11-11
Filing date: 2012-11-12
Publication date: 2013-05-16
Also published as: WO2013068633A3

Abstract

The invention provides systems and methods for producing a chip comprising a radio-frequency filter which is based on MEMS and is arranged inside an integrated circuit. In one aspect, the systems and methods provide a chip which includes electronic elements formed on a substrate made of semiconductor material. The chip additionally includes an interconnection layer stack which includes layers of conductive material which are separated by layers of dielectric material. A radio-frequency filter is formed inside the interconnection layer stack by applying gaseous HF to the interconnection layers. The radio-frequency filter includes a plurality of resonator elements which are mechanically decoupled.

Description

METHODS AND SYSTEMS FOR RADIOFREQUENCY FILTERS BASED ON CMOS OF MEMS THAT HAVE ORDERED SETS

OF ELEMENTS

Cross reference to related requests

This application claims the priority of US Provisional Patent Application N /558.689 ^{September 61,} filed on 1 November 1, 201 1, and U.S. Patent Application N ^s 13 / 364,149, filed on February 1 , 2012, all which is incorporated herein by reference in its entirety.

Background

An integrated circuit is a semiconductor device that has a substrate of a semiconductor material on which a series of layers have been deposited using photolithographic techniques. The layers are adulterated or doped, polarized and attacked, in such a way that electrical elements (for example, resistors, capacitors or impedances) or electronic elements (for example, diodes or transistors) are produced. Subsequently, other layers that form the interconnection layer structure necessary for electrical connections are deposited.

A chip can include a microelectromechanical system device (MEMS) and an integrated circuit, such that the integrated circuit can control the MEMS. There are several techniques for manufacturing a chip that includes both a MEMS and an integrated circuit. Another technique includes manufacturing MEMS devices inside the interconnection layers of the integrated circuit, using most or all of the interconnection layers. However, this technique leaves little space in the interconnection layers for routing to and from the electronic elements that are also in the integrated circuit. As a result, it is not possible to typically use any silicon area of the chip assigned to the MEMS device for routing, and therefore it is added to the silicon area required to manufacture the integrated circuit.

Accordingly, there is a need for a technique to manufacture MEMS devices within the interconnection layers of an integrated circuit, which allows more reasonable use of the silicon area of the chip.

In addition, there is a need for low-cost radiofrequency (RF) filters integrated in CMOS [complementary metal-oxide-semiconductor ", with very high quality factors and very low insertion losses. Commercially available solutions, such as Surface Acoustic Wave (SAW - "Surface Acoustic Wave") and Volumetric Acoustic Wave (BAW - "Bulk Acoustic Wave") filters, are not integrated into CMOS. Consequently, they cannot be integrated with transceivers, or transceivers, or with amplifiers, which increases the manufacturing cost.

Summary

The systems and methods described herein address the shortcomings of the prior art by allowing the manufacture of MEMS devices within the interconnection layers of an integrated circuit, without using most or all of the interconnection layers. . In particular, the systems and methods described herein make it possible to manufacture a MEMS device within the interconnection layers of an integrated circuit, using at most two layers of conductive material.

Additionally, RF filters using MEMS-based devices are described, which have a low manufacturing cost and are integrated into CMOS. In some embodiments, the RF filter includes an ordered set of mechanically decoupled resonator elements. In some embodiments, the RF filters are tunable and result in reduced computation, size and manufacturing cost.

In one aspect, the systems and methods described herein make possible a method of manufacturing a chip that includes a radio frequency filter based on MEMS and arranged in an integrated circuit. The method includes forming electronic elements on a substrate of semiconductor material. The method further includes forming a stack or stack of layers above the semiconductor material substrate. of interconnection layers including layers of conductive material separated by layers of dielectric material. The method further includes forming a radiofrequency filter within the stack of interconnection layers by applying HF [hydrogen fluoride] gas to the interconnection layers. The formed radio frequency filter includes a plurality of mechanically decoupled resonator elements.

In some embodiments, the chip is manufactured using a CMOS procedure of 180 nm or less. In some embodiments, the chip is manufactured using a 22 nm CMOS procedure, a 32 nm CMOS procedure, a 45 nm CMOS procedure or a 65 nm CMOS procedure. In some embodiments, a portion of the radiofrequency filter is made of tungsten.

In some embodiments, the radiofrequency filter includes an orderly sensor assembly of mechanically decoupled resonator elements. The ordered sensor assembly is configured to function collectively as a radio frequency filter. In some embodiments, the sensor array includes between about 60 and about 200 resonator elements.

In some embodiments, the sensor array is densely formed in a small area of the interconnection layers in order to reduce the frequency mismatch between the resonator elements of the sensor array. In some embodiments, the sensor array has a Q factor of 100 or higher. In some embodiments, the sensor array has a Q factor that ranges from about 5 to about 20.

In some embodiments, the plurality of resonator elements are calibrated using an external clock. In some embodiments, the plurality of resonator elements are of different sizes, and each resonator element has been configured to be activated, or connected, and deactivated, or disconnected. In some embodiments, the radio frequency filter has been configured for the UMTS frequency range, for the GSM frequency range, for the LTE frequency range, the cell frequency range, the WiFi frequency range or any other proper frequency range.

In some embodiments, the resonator elements are electrically connected in series. In some embodiments, the resonator elements are electrically connected in parallel. In some embodiments, the resonator elements are physically placed in a configuration corresponding to one of a line, a square and a grid or grid. In some embodiments, the chip includes a controller to adjust a voltage or electrical voltage applied to one or more resonator elements in order to adjust a resonance frequency of the radiofrequency filter.

In some embodiments, the formation of a resonator element includes forming a movable bridge and at least one capacitance electrode separated from the movable bridge by a first distance, so as to form an initial gap or gap within the resonator element. In some embodiments, the method further includes forming at least one mechanical stop within the resonator element, such that the mechanical stop extends beyond the at least one capacitance electrode in a second distance. In some embodiments, the method further includes applying a drive voltage to at least one drive electrode to move the movable bridge into contact with the at least one mechanical stop, so as to form an approximately equal operating separation space. at the second distance between the movable bridge and the at least one capacitance electrode. In some embodiments, the operating separation space is less than or equal to approximately one of 1 nm, 5 nm, 10 nm, 20 nm, 50 nm and 100 nm. In some embodiments, the method further includes applying the drive voltage after the installation of the chip within an electronic consumer device.

In another aspect, the systems and methods described herein provide a chip that includes a radio frequency filter based on MEMS and arranged in an integrated circuit, in accordance with the above description. It should be appreciated, on the other hand, that the systems and methods described above may be applied to, or used in accordance with, other systems and methods set forth elsewhere in this description.

In some embodiments, a chip includes a MEMS device formed within a stack or stack of interconnecting layers of an integrated circuit. The stack includes, for example, six layers of conductive material, separated by six layers of dielectric material, and in it the layer upper is a layer of conductive material (sometimes referred to as the cover or cover). The MEMS device is formed inside the stack of interconnecting layers by applying HF [hydrofluoric acid] gas to at least one layer of dielectric material located higher up in the stack. As a result, the MEMS device is released into the two layers of conductive material located higher in the stack. However, the remaining layers of dielectric material are not chemically attacked on their surface, and one or more of the remaining layers of conductive material can be used for routing the connections. Accordingly, a MEMS device can be manufactured within a stack of interconnecting layers of an integrated circuit, while still allowing the routing of connections within the lower layers of the stack, whereby the silicon area needed for the chip.

The described solution may also be beneficial for the manufacture of a MEMS device within a stack of interconnecting layers of an integrated circuit, when a complementary metal-oxide-semiconductor (CMOS) manufacturing process is used. ") which includes dielectric materials of low number k, for example, CMOS processes of 130 nm or less. Low number k dielectric materials have a smaller dielectric constant than silicon oxide and are typically difficult to chemically attack on their surface, compared to silicon dioxide, when, for example, gaseous HF is used. A layer of silicon dioxide dielectric material may be included as the highest layer of dielectric material in the cell, while the remaining layers may include low number k dielectric material. The MEMS device can be formed within the stack of interconnecting layers by applying gaseous HF to the silicon oxide dielectric material layer, without the need for superficial chemical attack of any of the low-number dielectric material layers k. Additionally, surface chemical attack using gaseous HF can provide relatively uniform results and provide a higher production capacity when manufacturing such MEMS devices. The superficial chemical attack of a smaller number of layers during manufacturing can also reduce the By-products of surface chemical attack as well as reducing the risk of corrosion of the MEMS device, thereby improving long-term reliability.

The described solution also offers some other advantages. For example, any support anchors for the MEMS device may require a smaller area within the interconnection layers, because the MEMS device is partially supported by the battery layers not chemically attacked on its surface. This can also reduce the parasitic capabilities that are typically observed when a MEMS device has been manufactured within most of the interconnection layers of an integrated circuit, or all of them.

In certain cases, a MEMS device manufactured within the interconnection layers of an integrated circuit using the described solution may not have the sensitivity required for the application for which it is intended. This is because the MEMS element released or released from the layers of conductive material may not be of sufficient length or mass. For example, a MEMS accelerometer may require a certain test or critical mass for use in the environment to which it is intended. In order to achieve a critical mass or length so that the MEMS device has the desired sensitivity, an array or array of MEMS devices can be manufactured within the interconnection layers. For example, an ordered set of MEMS accelerometers having an appropriate combined test mass may be used, as an accelerometer having the required test mass.

On the other hand, due to the saving in silicon area that is obtained with the described solution, multiple ordered sets of MEMS devices can be manufactured within the interconnection layers and arranged above an application-specific integrated circuit (ASIC - " application specific integrated circuit "), which can selectively control the ordered sets. In some embodiments, multiple ordered sets are manufactured, each of which has a different type of MEMS device, and then the ASIC can switch between each ordered set, as required. For example, a reconfigurable motion detection cell can be formed that includes an ordered set of accelerometers, an ordered set of gyroscopes and an ordered set of magnetometers, manufactured within the interconnection layers of the ASIC. The ASIC of the motion detection cell can then select whether the motion detection cell is to offer the functional capability of an accelerometer, gyroscope or magnetometer.

In some embodiments, a single type of MEMS device is manufactured above the ASIC. Certain devices may be initially deprecated and reserved as redundancy in case of failure of another device in use. In the event of a device failure due to problems during manufacturing, the redundant device can help improve the production capacity. In case of failure of a device during operation, the redundant device can help improve long-term reliability. In some embodiments, a hybrid motion sensor is constructed that has redundant elements as well as multiple types of ordered sets of devices, thereby offering the combined benefits of reconfiguration, redundancy and reliability.

In one aspect, the systems and methods described herein provide a method for manufacturing a chip that includes MEMS devices arranged within an integrated circuit. The method includes forming electronic elements in a substrate of semiconductor material. The method additionally includes forming, above the semiconductor material substrate, a stack or stack of interconnecting layers that includes layers of conductive material separated by layers of dielectric material. The method further includes forming MEMS devices within the stack of interconnecting layers by applying gaseous HF to a first layer of dielectric material located in the highest position of the interconnecting layer stack, while at least one of the layers of dielectric material is allowed to remain unchecked chemically on its surface, and at least one of the layers of conductive material is enabled for routing the connections to and from the electronic elements.

In some embodiments, the layer not subjected to surface chemical attack of the dielectric material is the lowest layer of the dielectric material in the cell. In some embodiments, the chip is manufactured using a CMOS method of 180 nm or less. In some embodiments, the chip is manufactured using one of a 22 nm CMOS method, a 32 nm CMOS procedure, a 45 nm CMOS procedure and a 65 nm CMOS procedure.

In some embodiments, the highest layer of conductive material in the stack includes aluminum. In some embodiments, the first layer of dielectric material includes silicon dioxide. In some embodiments, the method further includes forming at least one anchor within the layers of conductive material in order to support a MEMS device or an upper layer of the plurality of layers of conductive material.

In some embodiments, the MEMS devices are of the same type. In some embodiments, MEMS devices comprise a first device and a second device, and the second device is reserved as redundancy in the event of failure of the first device. In some embodiments, MEMS devices are of different types and include a magnetometer, gyroscope or accelerometer.

In some embodiments, MEMS devices include an ordered detection or sensor assembly of MEMS devices that is configured to function, as a whole, as a resonator. In some embodiments, the ordered array of detection includes a first set of MEMS devices configured to function, as a whole, as a first type of device, and a second set of MEMS devices configured to function, as a whole, as a Second type of device. The ordered detection set is capable of being reconfigured starting from an operation as the first type of device, up to an operation as the second type of device. In some embodiments, the ordered detection set is densely formed in a small area of the interconnection layers in order to reduce the frequency mismatch between the MEMS devices of the ordered detection set. In some embodiments, the ordered detection set has a Q factor [quality factor] of 100 or greater. In some embodiments, the ordered detection set has a Q factor that ranges from about 5 to about 20.

In another aspect, the systems and methods described herein make possible a chip that includes electronic elements formed on a substrate of semiconductor material. The chip additionally includes, above the substrate of semiconductor material, a stacking or stack of interconnecting layers that includes layers of conductive material separated by layers of dielectric material. MEMS devices are formed within the stack of interconnection layers by applying gaseous HF to a first layer of dielectric material located higher in the stack of interconnecting layers, while allowing at least one layer of Dielectric material not subjected to surface chemical attack remains unchecked chemically on its surface, and at least one layer of conductive material is enabled for routing connections to and from the electronic elements.

In some embodiments, the layer of dielectric material not subjected to surface chemical attack is the lowest layer of dielectric material in the cell. In some embodiments, the chip is manufactured using a CMOS method of 180 nm or less. In some embodiments, the chip is manufactured using one of a 22 nm CMOS procedure, a 32 nm CMOS procedure, a 45 nm CMOS procedure and a 65 nm CMOS procedure.

In some embodiments, the highest layer of conductive material in the stack includes aluminum. In some embodiments, the first layer of dielectric material includes silicon dioxide. In some embodiments, the chip additionally includes at least one anchor within the layers of conductive material to support a MEMS device or an upper layer of the plurality of layers of conductive material.

In some embodiments, MEMS devices include an ordered detection set consisting of MEMS devices, which is configured to function, as a whole, as a resonator. In some embodiments, the ordered detection set includes a first set of MEMS devices configured to function, as a whole, as a first type of device, and a second set of MEMS devices configured to function, as a whole, as a second type from device. The ordered detection set is capable of being reconfigured from an operation as the first type of device to an operation as the second type of device. In some embodiments, the ordered detection set is densely formed in a small area of interconnection layers in order to reduce the frequency mismatch between the MEMS devices of the ordered detection set. In some embodiments, the ordered detection set has a Q factor of 100 or greater. In some embodiments, the ordered detection set has a Q factor that ranges from about 5 to about 20.

In yet another aspect, the systems and methods described herein make possible a method of manufacturing a chip that includes MEMS devices arranged within an integrated circuit. The method includes forming electronic elements on a substrate of semiconductor material. The method further includes forming, above the semiconductor material substrate, a stack of interconnecting layers that includes layers of conductive material separated by layers of dielectric material. The method further includes forming MEMS devices within the stack of interconnecting layers by applying gaseous HF to a first layer of dielectric material located higher in the stack of interconnecting layers, while allowing at least A layer of dielectric material remains without undergoing surface chemical attack. The chip is manufactured in a CMOS process that includes a low number k dielectric material and has a lower dielectric constant than silicon dioxide. The first layer of dielectric material includes silicon dioxide, and the at least one layer of dielectric material not subjected to surface chemical attack includes low number k dielectric material. In some embodiments, the CMOS procedure is a CMOS procedure of 130 nm or less.

In yet another aspect, the systems and methods described herein make possible a chip that includes MEMS devices arranged within an integrated circuit. The chip includes electronic elements formed on a substrate of semiconductor material. The chip further includes, produced above the substrate of semiconductor material, a stack of interconnecting layers that includes layers of conductive material, separated by layers of dielectric material. The chip additionally includes MEMS devices formed within the stack of interconnecting layers by applying gaseous HF to a first layer of dielectric material located higher in the stack of interconnecting layers, while it allows at least one of the layers of dielectric material to remain unchecked chemically on its surface. The chip is manufactured in a CMOS process that includes a low-k dielectric material having a dielectric constant less than that of silicon dioxide. The first layer of dielectric material includes silicon dioxide and the at least one layer of dielectric material that has not been subjected to surface chemical attack includes a material of low number k. In some embodiments, the CMOS procedure is a CMOS procedure of 130 nm or less.

In yet another aspect, the systems and methods described herein make possible a MEMS resonator device that includes a resonator element, a support member fixed to the resonator element, and a calibration element arranged close to the resonator element. The resonator element is calibrated based on a magnetic field generated by the passage of current through the calibration element.

In some embodiments, the resonator element is formed within a first layer of conductive material, and the calibration element is formed within a second adjacent layer of conductive material. The resonator element is further calibrated based on a capacity generated between the first layer of conductive material and the second layer of conductive material. The capacity helps determine a distance between the calibration element and the resonator element.

In some embodiments, the MEMS resonator device additionally includes a first capacitive element disposed within the adjacent second layer of conductive material. The resonator element is further calibrated based on a first capacity of the first capacitive element. The first capacity helps determine a thickness of the first layer of conductive material. The resonator element is further calibrated based on a second capacity of the second capacitive element. The second capacity helps determine a thickness of the second layer of conductive material.

In some embodiments, the calibration element includes a metal wire arranged close to the resonator element, in a parallel arrangement. In some embodiments, the calibration element includes an inductor arranged close to the resonator element. In some embodiments, a portion of the calibration element is disposed in a layer of dielectric material not subjected to surface chemical attack. In some embodiments, the resonator element includes a magnetometer, and the calibration of the resonator element includes calibrating a gain of the magnetometer.

In accordance with yet another aspect, the systems and methods described herein make possible a calibration method of a MEMS resonator device. The MEMS resonator device includes a resonator element, formed inside a first layer of conductive material, a support member, fixed to the resonator element, and a calibration element, formed within a second, adjacent layer of conductive material. . The calibration element is arranged close to the resonator element. The method includes applying a current to the calibration element in order to generate a magnetic field, and measuring a capacity generated between the first layer of conductive material and the second layer of conductive material. The capacity helps determine a distance between the calibration element and the resonator element. The method further includes calibrating the resonator element based on the magnetic field and the measured capacity.

In some embodiments, the MEMS resonator device includes a first capacitive element disposed within the first layer of conductive material, and a second capacitive element disposed within the second, adjacent layer of conductive material. The method further includes calibrating the resonator element based on a first capacity of the first capacitive element. The first capacity helps determine a thickness of the first layer of conductive material. The method further includes calibrating the resonator element based on a second capacity of the second capacitive element. The second capacity helps determine a thickness of the second layer of conductive material.

In yet another aspect, the systems and methods described in The present specification makes possible a method for manufacturing a chip that includes anchors arranged within an integrated circuit. The method includes forming electronic elements in a substrate of semiconductor material. The method further includes forming a stack of interconnecting layers above the semiconductor material substrate. The stack of interconnecting layers includes layers of conductive material separated by layers of dielectric material. The method further includes forming the anchors within the interconnecting layer stack by applying gaseous HF to a first layer of dielectric material of the interconnecting layer stack, while allowing a layer of dielectric material to remain without undergoing superficial chemical attack, and a layer of conductive material is enabled for routing the connections to and from the electronic elements. Each anchor includes certain portions from the layers of conductive material, separated by tracks. Each anchor supports a top layer of conductive material or a MEMS device formed within the stack of interconnecting layers.

In some embodiments, a portion of an anchor includes dielectric material that replaces the conductive or track material. In some embodiments, an anchor is formed according to a violation of the CMOS procedure design rules. Violation of design rules may include portions of conductive layer and tracks that are substantially similar in width and that do not overlap. Violation of the design rules may include tracks that are wider than a width according to the CMOS procedure.

In yet another aspect, the systems and methods described herein provide a chip that includes anchors arranged within an integrated circuit. The chip includes electronic elements formed on a substrate of semiconductor material. The chip additionally includes a stack of interconnection layers formed above the substrate of semiconductor material. The stack of interconnecting layers includes layers of conductive material separated by layers of dielectric material. The chip additionally includes the anchors formed within the stack of interconnecting layers by applying gaseous HF to a first layer of dielectric material of the interconnecting layer stack, while allowing a layer of material dielectric remains unattached chemically on its surface, and a layer of conductive material is enabled for routing the connections to and from the electronic elements. Each anchor includes portions of the conductive layer from the layers of conductive material, separated by tracks. Each anchor supports a top layer of conductive material or a MEMS device formed within the stack of interconnecting layers.

In some embodiments, a portion of an anchor includes dielectric material that replaces the conductive or track material. In some embodiments, an anchor is formed in accordance with a violation of the CMOS procedure design rules. Violation of design rules may include portions of conductive layer and tracks that are substantially similar in width and that do not overlap. Violation of the design rules may include tracks that are wider than a width according to the CMOS procedure.

Brief description of the drawings

Other advantages and characteristics of the systems and methods described herein will be appreciated by the following description, which provides a non-limiting description of illustrative embodiments, with reference to the accompanying drawings, in which:

Figure 1 represents a cross-section of a flow stage or process sequence, in the course of manufacturing a MEMS device of an ordered assembly, in accordance with an illustrative embodiment of the invention;

Figure 2A illustrates a cross-section of a stage of the process sequence, in the course of manufacturing a MEMS device of an ordered assembly, according to another illustrative embodiment of the invention;

Figure 2B illustrates a cross-section of a stage of the process sequence, during the manufacture of a MEMS device of an ordered assembly, in accordance with yet another illustrative embodiment of the invention;

Figure 3 represents a flow chart for manufacturing a chip that has a geometrically arranged set of MEMS devices arranged in integrated circuit, in accordance with an illustrative embodiment of the invention;

Figure 4A represents a cross-section after a first set of steps of the process sequence for manufacturing a MEMS device of an ordered assembly, in accordance with an illustrative embodiment of the invention;

Figure 4B depicts a cross-section after a second set of steps of the process sequence for manufacturing a MEMS device of an ordered assembly, in accordance with an illustrative embodiment of the invention;

Figure 4C illustrates a cross-section after a third set of steps of the process sequence for manufacturing a MEMS device of an ordered assembly, in accordance with an illustrative embodiment of the invention;

Figure 5A depicts a perspective view of a partially manufactured MEMS device, belonging to an ordered assembly, in accordance with an illustrative embodiment of the invention;

Figure 5B represents a perspective view of a manufactured MEMS device, belonging to a geometrically arranged assembly, in accordance with an illustrative embodiment of the invention;

Figure 5C shows a column anchor for supporting a cover or cover and / or a MEMS device, in accordance with an illustrative embodiment of the invention;

Figure 5D shows a column anchor to support a cover and / or a MEMS device, according to another illustrative embodiment of the invention;

Figure 5E shows a column anchor to support a cover and / or a MEMS device, in accordance with yet another illustrative embodiment of the invention;

Figure 5F shows a column anchor to support a cover and / or a MEMS device, in accordance with yet another illustrative embodiment of the invention;

Figure 5G shows a column anchor to support a cover and / or a MEMS device, in accordance with yet another illustrative embodiment of the invention;

Figure 6A represents a schematic view of an assembly MEMS device sorting, in accordance with an illustrative embodiment of the invention;

Figure 6B illustrates a schematic view of an ordered and reconfigurable set of MEMS devices, in accordance with an illustrative embodiment of the invention;

Figure 6C depicts a perspective view of an ordered set of MEMS devices, in accordance with an illustrative embodiment of the invention;

Figure 7A illustrates schematic view of a chip having an ordered set of MEMS devices disposed within an integrated circuit, in accordance with an illustrative embodiment of the invention;

Figure 7B represents a schematic view of a chip having an ordered set of MEMS devices arranged within an integrated circuit, in accordance with another illustrative embodiment of the invention;

Figure 8A illustrates a schematic view of a resonator element, in accordance with an illustrative embodiment of the invention;

Figure 8B depicts schematic views of several resonator elements, in accordance with an illustrative embodiment of the invention; Y

Figure 8C depicts a perspective view of a MEMS resonator device that includes a resonator element and a calibration element arranged close to the resonator element, in accordance with an illustrative embodiment of the invention.

Figures 9A and 9B represent schematic views, according to the prior art, of a SAW filter and a BAW filter, respectively;

Figures 10A and 10B represent schematic views of ordered sets of resonators for an absorption filter, in accordance with an illustrative embodiment of the invention;

Figure 1 1 represents a schematic view of a resonator element with a narrow lateral separation space, in accordance with an illustrative embodiment of the invention; Y

Figure 12 depicts a schematic view of a resonator element for an RF filter, in accordance with an illustrative embodiment of the invention. Detailed description of achievements

In order to provide a comprehensive understanding of the systems and methods described herein, certain illustrative embodiments will be described below. It will be understood, however, by a person with ordinary knowledge of the art, that the systems and methods described herein can be adapted and modified as appropriate for the application being treated, and that the systems and methods described herein may be used in other suitable applications, and that said other additions and modifications will not depart from the scope thereof.

Figure 1 represents a typical cross section of a MEMS device manufactured inside the interconnection layers of an integrated circuit. The MEMS 100 device is manufactured within all six metal (or conductive material) layers of the stacking or stack of interconnecting layers, including the upper metal layer 106 and the lower metal layer 108. The MEMS device 100 It includes an element 102 supported by anchors 104. However, this technique leaves no space within the interconnection layers, for example, the metal layer 108, for routing to and from electronic elements that are also present on the integrated circuit. . As a result, typically, no silicon area of the chip assigned to the MEMS 100 device can be used for routing, and therefore it is added to the silicon area needed to manufacture the integrated circuit.

The configuration of Figure 1 may also be disadvantageous in terms of long-term reliability. In the embodiment shown, long metal planes and continuous tracks are used to limit the horizontal surface chemical attack and the vertical surface chemical attack, respectively, of the interconnecting layers by HF [hydrofluoric acid] gas. However, such a complex structure can force the gaseous HF to travel through long distances, thus avoiding an unwanted surface chemical attack of the interconnection layers. On the other hand, this solution may allow the water molecules produced as a by-product or by-product of the surface chemical attack reaction to become trapped and cause corrosion and long-term reliability problems. Figure 2A depicts an illustrative cross-section of a MEMS device 200 manufactured within two metal layers of the stack of interconnecting layers. The stack includes six layers of metal separated by six layers of dielectric material, such that the top layer 206 is a layer of conductive material (sometimes referred to as the cover or envelope). The MEMS device 200 is formed inside the stack of interconnecting layers by applying gaseous HF to the two layers of dielectric material 216 and 218 located higher in the stack. As a result, the MEMS device 200 is released or released into the two layers of conductive material 202 and 206 located higher in the stack. However, the remaining layers of dielectric material remain unchecked chemically on their surface, and one or more of the remaining layers of conductive material 208, 210, 212 or 214 can be used for routing the connections. Although layers 208 and 210 include anchors 204 to support the MEMS device 200, these can still be used for routing the connections due to the small space required for anchors 204. In some embodiments, anchors 204 are implemented inside. of two layers of conductive material in order to take into account the variation (around 10%) of the height of the layers in CMOS procedures. Accordingly, a MEMS device can be manufactured within a stack of interconnecting layers of an integrated circuit, while still allowing the routing of the connections within the lower layers of the stack, thereby reducing the silicon area needed for the chip. In one example, this configuration can be used to make a resonator element for an accelerometer or gyroscope.

Figure 2B depicts another illustrative cross-section of a MEMS device 250 manufactured inside two metal layers of the stack of interconnecting layers. The stack includes six layers of metal separated by six layers of dielectric material, such that the top layer 256 is a layer of conductive material (sometimes referred to as a cover or cover). The MEMS 250 device has been formed inside a stack of interconnecting layers by the application of gaseous HF. The gaseous HF chemically attacks the surface of one of the layers of dielectric material 268, located higher in the stack. As a result, the MEMS 250 device is released within the two layers of material conductor 252 and 256 located higher in the stack. However, the remaining layers of dielectric material, including layer 266, are left unchecked chemically on their surface. One or more of the remaining layers of conductive material 258, 260, 262 or 264 may be used for routing the connections. Although the layer 258 includes anchors 254 to support the MEMS device 250, it can still be used for routing the connections due to the small space required for the anchors 254. This configuration may be advantageous over the configuration of Figure 2A because the layer of dielectric material 268 not subjected to surface chemical attack provides support to the MEMS device 250. Accordingly, only small single level anchors 254 are needed to additionally support the MEMS device 250. In some embodiments, the layer of dielectric material 268 not chemically attacked on its surface supports only the MEMS 250 device, thereby eliminating the need for anchors. In one example, this configuration can be used to manufacture a sensor element for a pressure sensor.

The configurations described with respect to Figures 2A and 2B may also be beneficial for manufacturing a MEMS device within a stack of interconnecting layers of an integrated circuit when complementary metal-oxide-semiconductor manufacturing processes (CMOS - "are used. complementary metal oxide semiconductor ") including dielectric materials of low number k, for example, CMOS processes of 130 nm or less. Such procedures can provide advantages such as a smaller die area, lower cost and lower power consumption, compared to CMOS procedures of more than 130 nm. Low number k dielectric materials have dielectric constants lower than that of silicon dioxide and are typically difficult to chemically attack on their surface, compared to silicon dioxide, when, for example, gaseous HF is used. A layer of silicon dioxide dielectric material may be included as the highest layer of dielectric material in the stack, while the remaining layers may include a low number material k. The MEMS device can be formed within the stack of interconnecting layers by applying gaseous HF to the layer of silicon dioxide dielectric material, without the need for superficial chemical attack of any of the layers of dielectric material of low number k.

Additionally, surface chemical attack using gaseous HF can provide relatively uniform results and provide a higher production capacity when manufacturing such MEMS devices. The surface chemical attack of a smaller number of layers during manufacturing can also reduce the by-products or by-products of the surface chemical attack and reduce the risk of corrosion of the MEMS device, thereby improving long-term reliability. In some embodiments, a time-based stop can be used to limit the surface chemical attack of the interconnection layers by the gaseous HF. Without adding complex structures as described with respect to Figure 1, surface chemical attack by gaseous HF can be limited by stopping the attack after a very short period of time. This solution can achieve a minimum risk of corrosion as a result of trapped water molecules that are produced as a byproduct of the surface chemical attack reaction. Both Figure 2A and 2B are illustrative embodiments of this solution to form a MEMS device.

The configurations described with respect to Figures 2A and 2B also offer some other advantages. For example, any support anchors for the MEMS device may require a smaller area within the interconnection layers, because the MEMS device is partially supported by the battery layers that have not been chemically attacked on its surface. This can also reduce the parasitic capabilities that are typically observed when the MEMS device is manufactured within most or all of the interconnecting layers of an integrated circuit.

Figure 3 depicts an illustrative flow chart 300 for manufacturing a chip having an ordered set of MEMS devices arranged within an integrated circuit. The chip is manufactured using a CMOS procedure of 180 nm or less, for example, a 22 nm CMOS procedure, a 32 nm CMOS procedure, a 45 nm CMOS procedure or a 65 nm CMOS procedure. In step 302, electronic elements are formed on a substrate of semiconductor material. In step 304, it is formed, above the material substrate semiconductor, a stack of interconnecting layers that includes layers of conductive material separated by layers of dielectric material. In step 306, gaseous HF is applied to the interconnection layers. In step 308, a first layer of dielectric material placed higher in the stack of interconnecting layers is subjected to surface chemical attack. In some embodiments, a first layer of dielectric material includes silicon dioxide. A second, adjacent layer of dielectric material can also be chemically attacked on its surface. At least one of the layers of dielectric material remains unchecked chemically on its surface. In some embodiments, the unattached layer of the dielectric material is the lowest layer of the dielectric material in the stack. In step 310, MEMS devices are released within the stack of interconnecting layers. In some embodiments, the MEMS devices are of the same type. In some embodiments, MEMS devices comprise a first device and a second device, and the second device is reserved as redundancy in the event of failure of the first device. In some embodiments, MEMS devices are of different types, including a magnetometer, gyroscope or accelerometer. One or more anchors can also be formed to support a MEMS device or an upper layer of the plurality of conductive material layers, within the conductive material layers. In step 312, routing connections to and from the electronic elements are still formed within at least one layer of conductive material.

The steps of the flow or the process sequence for the manufacture of a MEMS device of an ordered set are described below, by means of a CMOS MEMS based procedure. For example, the MEMS device may be manufactured using a CMOS MEMS-based procedure described in Patent Application Publication No. ⁹ 2010/0295138, jointly owned herein and entitled "Methods and systems for the manufacture of MEMS CMOS devices ". However, it is not necessary that the manufacturing procedures for the MEMS device be limited to CMOS MEMS based procedures, but these may include MEMS based procedures, NEMS based procedures [nanoelectromechanical system - "nano-electro-mechanical system "] as well as other suitable procedures. Figure 4A represents an illustrative cross-section after a first set of steps of the process sequence for the manufacture of a MEMS device of an ordered set. The thickness of the layers has been increased. In one embodiment, the MEMS device is manufactured using a standard CMOS method. In one embodiment, the MEMS device is manufactured within a cavity formed inside interconnection layers of a CMOS chip. In an alternative embodiment, the MEMS device is manufactured as a stand-alone MEMS device. Initially, a layer of metal is deposited. The metal layer may be made, for example, of a metal alloy of AlCu. A masking layer is deposited above the metal layer, and then the metal layer is chemically attacked on its surface using, for example, dry HF, to form plates 402. A dielectric layer is deposited between metals (IMD - "Dielectric Inter Metal") above the plates 402, followed by a masking layer, and then the IMD layer is subjected to surface chemical attack and filled with metal to form separators or tracks 404. In one embodiment, the IMD layer includes an unadulterated or doped oxide layer. Another metal layer is deposited, followed by a masking layer deposited above the metal layer, and then the metal layer is subjected to surface chemical attack using, for example, dry HF, to form plates 406 Another IMD layer is deposited above the plates 406, followed by a masking layer, and then the IMD layer is subjected to surface chemical attack and filled with metal to form separators or tracks 408. plates 402 and 404 and spacers 406 and 408 together form anchors for the MEMS device. A metal layer is deposited on the spacers 408 to form a bridge 410 of the MEMS device. Another layer of IMD is deposited on the bridge 410, followed by an upper metal layer 412. A masking layer is deposited on the upper metal layer 412. The upper metal layer 412 is then subjected to surface chemical attack to form some through holes 414. Through holes may allow the passage of surface chemical attack agent, for example, gaseous HF, for the attack of the material located below the upper metal layer 412.

Figures 4B and 4C represent cross sections after a second and a third set of steps of the process sequence, respectively, to manufacture a MEMS device of an ordered set. A surface chemical attack agent, for example, dry HF, is released through the through holes 414 in the upper metal layer 412. The surface chemical attack agent removes certain portions of the IMD layers by attack to release the anchors and the bridge of the MEMS device, as shown in Figure 4B. Bottom plates 402 are embedded or embedded in the remaining oxide 442 of the IMD layers, in order to provide support to the MEMS device. Finally, a metallization layer 428 is deposited on the upper metal layer 412 in order to seal or seal the MEMS device with respect to the outside environment, as shown in Figure 4C. In one embodiment, the MEMS device is manufactured using integrated chip technology based on MEMS, based on NEMS or based on CMOS of MEMS.

In some embodiments, a MEMS device is disposed within an integrated circuit. The steps of the process sequence of Figures 4A-4C are carried out in the interconnection layers of the integrated circuit. Layers are produced that form electrical and / or electronic elements on a substrate of semiconductor material. Interconnection layers are produced that include a bottom layer of conductive material and an upper layer of conductive material, separated by at least one layer of dielectric material. A portion of the MEMS device is formed within the interconnection layers by applying gaseous HF to at least one layer of dielectric material, in accordance with the steps of the process sequence that have been described in relation to Figures 4A- 4C.

Figure 5 represents an illustrative perspective view of a MEMS device of an ordered, partially manufactured assembly. In particular, Figure 5A illustrates a resonator element 500 manufactured with a mobile bridge 502 and connected with anchors 504. The anchors 504 are embedded in the oxide of the dielectric layer between metals (IMD - "Inter Metal Dielectic") 506 with in order to provide support to the resonator element. The deformation or movement of the bridge 502 is limited by the elastic strength of the metal used to make the bridge 502. In one embodiment, the length of the bridge 502 ranges between about 50 μηι and approximately 100 μm. In some embodiments, the length of bridge 502 reaches approximately 300 μm.

Figure 5B depicts an illustrative perspective view of a resonator element 500 with a cover or cover 552 (element 550). The separation and size of the release holes 554 may be more important for MEMS devices manufactured within at most two conductive layers of a stack of interconnecting layers. Typical manufacturing within most layers, or all layers, of the stack is aimed at excessive surface chemical attack, since there are attack blocking structures designed to prevent an unwanted surface chemical attack. However, for the proposed configuration (similar to that of Figures 2A and 2B), a time control can be used to limit the surface chemical attack. As the proposed configuration requires that the gaseous HF travel vertically, at most, below the second conductive layer, while moving horizontally within the entire MEMS device to release the device, it is necessary to carefully consider the maximum separation and the minimum size of the release holes made in the cover. If the release holes are too large or too close, there may be no material left after the surface chemical attack to implement the MEMS device. In some embodiments, the ordered set of release holes is denser in configurations similar to those of Figures 2A and 2B, compared to a configuration similar to that of Figure 1.

Additionally, the proposed configuration may require anchors 556 to support the cover 552 and ensure that the cover 552 does not bend or damage the MEMS device. In some embodiments, a dense array of anchors 556 is required to support the cover 552. In addition to supporting the cover 552, anchors 558 can be used to support the MEMS device. However, the need for these anchors can be eliminated simply by embedding the MEMS device in a dielectric layer (for example, silicon dioxide), which is illustrated in Figure 2B. Since nothing of the dielectric material has been removed by surface chemical attack, the MEMS device will be supported instead by the surrounding dielectric material.

Figures 5C-5G show illustrative column anchors intended to support cover 552 and / or the MEMS device. The terms "column" and "anchor" can be used interchangeably for structures that support deck 552 or a MEMS device. Figure 5C shows an embodiment of column 560 implemented within a stack of metal layers, which extends from an upper metal layer 568 to a metal layer 562. In particular, column 560 includes portions of metal layer 562- 568 separated by tracks 570, inside a stack. The tracks may have a projected area, or "footprint", square and a fixed size in accordance with the design rules of the CMOS procedures. Additionally, the metal layer portions may have minimal overlap from the track. Figure 5D shows another embodiment of column 560 in which tracks 570 have been extended or extended to have a larger projection area. This can help make the column more robust and provide better support for the 552 cover and / or the MEMS device.

Figure 5E shows a column 580 implemented within a stack of metal layers, which extends from an upper metal layer 588 to a metal layer 582. Column 580 has an extended or extended width of portions of metal layer 582 -588 and 590 tracks, compared to column 560, which can help make the column more robust. The metal layer portions and the tracks may have similar widths (Figure 5E), or the metal layer portions may have minimal overlap from the tracks in accordance with the design rules of the CMOS procedures (Figure 5F) . Figure 5G shows another embodiment of column 580 in which a portion of the cell has been replaced by dielectric material. The oxide portion may have a square shape or any other suitable shape, such that the oxide is not removed by surface chemical attack. For example, the upper metal layer 588 may not have release holes in order to retain the oxide below. The combination of metal and oxide can provide greater robustness, compared to other implementations.

Figure 6A depicts an illustrative schematic view of an ordered array 600 of MEMS devices 602. In certain cases, a MEMS device manufactured within interconnecting layers of an integrated circuit using the described solution may not have the sensitivity required for application to which it is intended. This is because the MEMS element released from the layers of conductive material may not be of sufficient length or mass. For example, a MEMS accelerometer may require some test or critical mass to be used in the environment to which it is intended. In order to achieve a critical mass or length so that the MEMS device has the desired sensitivity, an ordered set of MEMS devices can be manufactured within the interconnection layers. For example, an ordered set of MEMS accelerometers having an appropriate combined test mass, such as an accelerometer having the required test mass, can be used.

On the other hand, due to the silicon area savings obtained from the described solution, multiple ordered sets of MEMS can be manufactured within the interconnection layers, and arranged above an application-specific integrated circuit (ASIC - "application specific integrated circuit ") which is capable of selectively controlling the ordered sets. In some embodiments, a single type of MEMS device is manufactured above the ASIC. Certain devices may not be used initially and be reserved as redundancy in the event of failure of another device being used. In case of failure of a device as a result of problems during manufacturing, the redundant device can help improve production capacity. In case of failure of a device during operation, the redundant device can help improve long-term reliability.

In some embodiments, a metal layer is subjected to superficial chemical attack using a time-based arrest, in order to form a MEMS device having a movable plate and springs or springs attached to it. Since the MEMS device is formed from a single metal layer, a typical movable plate can bend or sink with a surrounding electrode or oxide. In such a case, the movable plate can be divided into multiple smaller movable layers. Consequently, an ordered set of MEMS devices can be constructed, each of which has a movable plate and springs attached to it. Such an ordered set will have a higher stiffness as a result of the combined stiffness of the springs. However, soft springs can be used to counteract stiffness (which are further described in relation to Figure 6C, below). Other The advantage offered by such an ordered set of MEMS devices made from a single metal layer is that it can be stacked on top of an application-specific integrated circuit (ASIC), due to its small thickness. In some embodiments, the geometrically arranged set of MEMS devices includes redundant elements to improve production capacity and / or long-term reliability. For example, the ordered set of MEMS devices may include a certain number of accelerometers. In some embodiments, the ordered set of MEMS devices includes sensors of different types. For example, the ordered set of MEMS devices may include a magnetometer, a gyroscope and an accelerometer. In another example, the ordered set of MEMS devices may include a three-dimensional magnetometer, or 3-D, a 3-D gyroscope and a 3-D accelerometer. In some embodiments, the ordered set of MEMS devices is constructed on top of an ASIC.

In some embodiments, MEMS devices include an ordered detection or sensor assembly of MEMS devices that is configured to function, as a whole, as a resonator. In some embodiments, the sensor array includes between about 60 and about 200 MEMS devices. In some embodiments, the ordered sensor assembly is densely formed in a small area of the interconnection layers in order to reduce the frequency mismatch between the MEMS devices of the ordered detection assembly. In some embodiments, the sensor array has a Q factor of 100 or higher. In some embodiments, the ordered detection set has a Q factor that ranges from about 5 to about 20.

In some embodiments, the ordered set of MEMS is used to build a gyroscope. Such a gyroscope may require the implementation of a large test or critical mass through the use of MEMS technology. In embodiments in which the structural layers produced by MEMS technology are thin, an ordered set of small elements or devices can be produced to achieve an effect similar to that of a large test mass. Such a gyroscope may additionally require self-calibration to compensate, for example, mechanical properties that may change with temperature, aging and production. In some embodiments, they can be measured and stored values of the mass and the test or critical capabilities of the gyroscope, while other parameters, such as vertical and lateral stiffness, can be self-calibrated. In some embodiments, a self-calibration algorithm that does not require the measurement or calibration of the mass and the test capabilities can be used.

In some embodiments, the ordered set of MEMS is used to construct a magnetometer. The magnetometer can be made with an ordered set of small devices (or elements). The orderly set of small devices can minimize the bending or bending of the structural layers. The ordered set of small devices can simplify the superficial chemical attack by allowing, for example, the attack to be shorter and more controllable. Such an ordered set of small devices can provide a large mass and / or aggregate area. The ordered array can allow the detection of physical quantities with the appropriate sensitivity and can provide a higher reliability than that of one or more large devices. In some embodiments, the small devices of the array can be nanometric magnetometers or nanomagnetometers.

Figure 6B represents an illustrative schematic view of an ordered and reconfigurable set of MEMS devices. In some embodiments, multiple ordered assemblies are manufactured, each of which has a different type of MEMS device, and then the ASIC can switch between each ordered array as required. For example, a reconfigurable motion detection cell 640 may be formed that includes an ordered accelerometer assembly 644 (which includes elements 642), an ordered gyro set 648 (which includes elements 646), an ordered set 652 of compass ( which includes elements 650), and an ordered 656 magnetometer assembly (which includes elements 654), manufactured within the interconnection layers of the ASIC. The ASIC 658 controller of the motion detection cell can then select whether the motion detection cell should offer the functional capability of an accelerometer, gyroscope, compass or magnetometer. In some embodiments, a hybrid motion sensor is constructed that has redundant elements as well as multiple types of ordered sets of devices, so it offers the benefits combined of susceptibility of reconfiguration, redundancy and reliability.

Figure 6C depicts an illustrative perspective view of an ordered set 680 of MEMS devices 682. Devices 682 include anchors 684. In order to manufacture devices such as magnetometers or inertia sensors, a critical amount of length or length is required. mass, respectively, to achieve a given sensitivity that is desired. To achieve this critical mass or length, the array 680 may include elements 682 intended to function as a single device having the intended length or mass.

Since each MEMS 682 device is made from a single layer of metal, a typical movable plate can bend or sink with an electrode or surrounding oxide. In such a case, the movable plate can be divided into multiple smaller movable plates. Consequently, an ordered set of MEMS devices can each be constructed, each of which has a movable plate and springs or springs attached to it. Said ordered assembly will have a higher rigidity as a result of the combined stiffness of the springs. However, soft springs can be used to counteract stiffness. Such soft springs are manufactured as thin single layer springs, which are fixed to the movable plate and folded together with the movable plate. Thus, since there is no rigid portion that adds stiffness, even the combined stiffness of the soft springs may be suitable to allow the multiple movable plates to work together as a single device.

For devices that require a large quality factor, Q ("quality"), for example, a magnetometer or gyroscope, if the elements of the ordered set are mechanically decoupled, the Q factor of the ordered set will be low due to frequency mismatch of the individual elements. The frequency mismatch may be due to the tolerances of the procedure and the different usage history of each individual element. A low Q of the ordered array, despite having a high Q for the individual elements, can be advantageous in the design of accelerometers, in which there is typically a compromise between the high Q required to reduce Brownian noise and the high Q required to reduce a transient oscillation response to a step function and amplification of high frequency vibrations. With these sets ordered of mechanically decoupled elements, it is possible to have a high Q for the individual elements, which is the important thing when it comes to reducing Brownian noise, and a low Q for the ordered set, which is what counts to avoid amplifying the High frequency vibrations and transient oscillation of the response to a step. The present Applicants have experimentally observed that the Q values of the ordered set are sufficient to achieve the sensitivity expectations for motion sensors satisfactory to the consumer market.

The construction of an ordered set of mechanically coupled elements can be a challenge in the case of a magnetometer. Since each element is formed from a single layer of metal, any mechanical coupling can electrically short-circuit the elements, and current may not flow in the desired direction. In some embodiments, the elements are joined by means of a high density silicon oxide sublayer, which will remain unchecked chemically on its surface while a low oxide density sublayer is removed in the same area, while the sublayer High density remains unchecked chemically on its surface. In order to facilitate the surface chemical attack of a low density sublayer below a lower conductive layer, a column can be placed just below a release hole of the upper conductive layer. The present Applicants have observed that said column can advance the gaseous HF faster vertically below the lower conductive layer, and helps to chemically attack the surface of the target low density sublayer horizontally.

In some embodiments, the elements are joined by oxide of a metal-insulator-metal (MIM) layer, for example, silicon-enriched silicon nitride, which cannot be easily removed by Superficial chemical attack along with silicon nitride. This may require the addition of MIM capacitors to the ordered assembly between an upper conductive layer and a second adjacent conductive layer. In some embodiments, instead of the MIM layer, a silicon nitride sublayer is used that is within the dielectric layer between metals of certain CMOS processes (e.g., a CMOS procedure of 130 nm or less).

Figure 7A depicts an illustrative schematic view of a chip 700 having an ordered set of MEMS devices 702 disposed within an integrated circuit. The illustrated chip 700 includes MEMS 702 devices that have been manufactured within the interconnection layers of the integrated circuit using most or all of the interconnection layers. As a result, this configuration leaves little space in the interconnection layers for routing to and from the electronic elements that are also found in the integrated device. Instead, it is necessary to allocate an additional silicon area for routing 704. In this configuration, any silicon area of the chip assigned for the MEMS device, and therefore, this, cannot be used for routing. It is added to the silicon area required to manufacture the integrated circuit.

Figure 7B depicts another illustrative schematic view of a chip 750 having a set of MEMS devices 752 arranged within an integrated circuit. Chip 750 illustrated includes MEMS 752 devices that have been manufactured within the interconnection layers of the integrated circuit by using at most two layers of conductive material. As a result, one or more of the remaining layers of conductive material are used to route connections 756, in addition to routing connections 754 existing in the chip. Accordingly, the MEMS device 752 can be manufactured within a stack of interconnecting layers of an integrated circuit, while still allowing the routing of connections 756 within the lower layers of the stack, thereby the area of silicon needed for the chip is reduced.

Figures 8A and 8B represent illustrative schematic views of several resonator elements. In the case of inertia sensors, it is preferable to maximize the mass of a resonator element in order to receive the resonance frequency. One such configuration for a resonator element 800 is illustrated in Figure 8A. The resonator element 800 includes a bridge 804 with additional cantilever side projections 802, in order to maximize the mass of the resonator element 800. This type of resonator element can be used, for example, as a gyroscope. Additional configurations 850 for sensor sensors are illustrated in Figure 8B inertia. In contrast to the maximization of the mass in the case of a gyroscope, it is preferable for a magnetometer an inertia sensor that has a minimized area that does not carry current (in order to maximize the signal-to-noise ratio for Brownian motion). Accordingly, any 852-862 configurations may be useful, depending on the type of device considered, for example, a gyroscope, a compass, an accelerometer, a magnetometer or any other suitable device. Bridges may be preferred if the length needs to be maximized. This is due to the fact that the present Applicant has experimentally verified that the residual tension in the metal layers of the CMOS processes is normally tensile, and therefore, this tends to maintain a high degree of plainness in the bridges. For example, bridges can be used to construct a magnetometer in which current flow in one direction is required at all times. Since the bridges are connected in series, the current will flow only in one direction, so that they are very suitable for the construction of a magnetometer. However, if the condition is to reduce the frequency mismatch to maximize the quality factor, Q, of the ordered array, then a cantilever projection type structure may be a better option.

Figure 8C depicts an illustrative perspective view of a MEMS resonator device 880 that includes a resonator element 882, support members 884, fixed to the resonator element 882, and a calibration element 888, arranged close to the resonator element 882. In In the embodiment shown, the calibration element 888 includes a metal wire arranged close to the resonator element 888, in a parallel arrangement, and a portion of the calibration element 888 is disposed within a layer of dielectric material 886 not subjected to attack surface chemical In some embodiments, the calibration element includes an inductor disposed in a position close to the resonator element. The resonator element is calibrated based on a magnetic field generated by the passage of current through the calibration element.

The resonator element 882 has been formed within a first layer of conductive material. Calibration element 888 has been formed within a second, adjacent and lower layer of conductive material. The resonator element 882 is further calibrated based on a capacity generated between the first layer of conductive material and the second layer of conductive material. The capacity helps determine a distance between the calibration element and the resonator element.

In some embodiments, the MEMS 880 resonator device additionally includes a first capacitive element, disposed within the first layer of conductive material, and a second capacitive element, disposed within the second, adjacent layer of conductive material. The resonator element 882 is further calibrated based on a first capacity of the first capacitive element. The first capacity helps determine a thickness of the first layer of conductive material. The resonator element 882 is further calibrated based on a second capacity of the second capacitive element. The second capacity helps determine a thickness of the second layer of conductive material.

In some embodiments, the resonator element includes a magnetometer, and the calibration of the resonator element includes calibrating a gain of the magnetometer. However, in addition to the gain, it may also be necessary to calibrate a magnetometer runout. This may be desirable to avoid high runout that saturates the detection chain, or that requires an unfeasible end terminal that has a high dynamic range, unrealistic, as well as to avoid a constant or fixed error in the output.

There may be two sources of runout in a magnetometer. The first source may be electronic elements. The runout can be measured by deactivating or cutting the Lorentz current, so that no magnetic force is generated. The second source may be the electrostatic force that adds to the magnetic force. The electrostatic force is proportional to the square of the electrical voltage or voltage. If there is a DC (direct current - "DC (direct curren.)") And an AC voltage component (alternating current - "AC (alternating curren.)") (Vdc and Vac) at a frequency f0, the square will generate electrostatic force components at DC, f0 and 2 * f0. The magnetic force will have only one component at f0 (since the Lorentz current is an AC current at f0, the resonant frequency of the resonant element). Consequently, there is a component of the electrostatic force that will add to the magnetic force by adding a runout, since this will be a term constant regardless of the magnetic force.

This term of the electrostatic force at fO is proportional to Vdc * Vac. Since Vac appears due to the voltage drop of the Lorentz current through the resistances of the resonator element, it cannot be eliminated. Instead, Vdc can be reduced to as close to zero as possible. For example, a Vdc of 10 μν may be sufficient to have a contribution almost below the level or magnitude of noise of a magnetometer having approximately 1 μΤ. A problem may be that the decentralization of the electronic elements is typically in the range between 20 mV and 50 mV, such that it may not be possible to control that DC voltage, at least one open loop.

In some embodiments, a digital-to-analog converter (DAC) can be used to test different voltages until the required voltage is reached. In order to determine the DC voltage required from the DAC so that Vdc is close to zero (for example, between approximately -10 μν and approximately +10 μν), the effect of Vdc is detected. This can be achieved by placing an electrode well below the resonator element (for an out-of-plane vibration, that is, X or Y magnetic field components), or parallel to the resonator element (for an in-plane vibration, that is, the magnetic field component Z). The electrode can be electrostatically excited with an AC signal at a faith frequency, such that the bridge presents some deflection at this faith frequency. This modulates the electrostatic force component but not the magnetic component, which helps distinguish the two components. Subsequently, the voltage of the DAC is adjusted in such a way that this spectral component of the detected current, which will be located at a distance faith from the magnetic force, is minimized. Alternatively, the determination of the required DC voltage can be carried out by adding a DC voltage, applying two different voltages, and solving a system of equations in order to find the required voltage value.

RF filters, for example, in cell phone applications and UMTS communications, are usually required to have losses of less than 3 dB and attenuations of more than 50 dB, with narrow passbands. This may involve a quality factor, Q, of the order of 100 in the frequency range of 0.8 GHz to 3 GHz. Due to these demand specifications, such filters cannot be implemented using passive LC filters, due to the high Q required. In other words, inductors and capacitors, especially if they are integrated in a CMOS chip, result in resistances that degrade the quality factor and / or filter insertion losses, so they are not a viable option. These filters cannot be implemented digitally because, in the transmission, they need to handle power signals, and because, in reception, the power consumption needs would be enormous, since it is not possible to reduce the signal bandwidth until the RF filter is applied.

Typically, such RF filters are implemented using SAW and BAW filters. SAW filters (Surface Acoustic Wave - "Surface Acoustic Wave") are electromechanical devices in which electrical signals are converted into a mechanical wave into a device constructed of a piezoelectric crystal or ceramic. Figure 9A represents a schematic view of such a SAW 900 filter. This wave is delayed as it propagates through the device, before being converted back into an electrical signal by additional electrodes. Delayed outputs are recombined to produce a direct analog implementation of an FIR filter (Finite Impulse Response - "Finite Impulse Response"). Typically, SAW filters are limited to frequencies up to 3 GHz.

An evolution of SAW filters is BAW filters (Volumetric Acoustic Wave - "Bulk Acoustic Wave"). BAW filters can implement ladder or grid filters, or grid or grid filters. BAW filters typically operate at frequencies ranging from 2 GHz to 16 GHz and may be smaller or thinner than equivalent SAW filters. An important variant of BAW filters is the FBAR (Thin Film Bulk Acoustic Resonator "). This is a device consisting of a piezoelectric material sandwiched between two electrodes and acoustically isolated from the surrounding environment. FBAR devices that use piezoelectric films with thicknesses ranging from several micrometers down to tenths of a micrometer, resonate in the frequency range of approximately 100 MHz to 10 GHz. Aluminum nitride and zinc oxide are two materials common piezoelectric devices used in FBARs. Figure 9B represents a schematic view of a BAW 950 filter of this type.

Another solution to build high-performance RF filters is to use micromechanical resonators through MEMS technology. Unfortunately, the frequencies of these resonators can be quite low, typically in the range between 10 kHz and 10 MHz, and active transimpedance amplifiers may be necessary to detect the minimum currents they generate. This may limit its applicability in mobile phone applications, which require passive filters around 1 GHz.

Unlike what is done in conventional filters, in which the signal either circulates through them or is bounced back, depending on their frequency content, Figures 10A and 10B show an absorption filter intended for 'absorb' the power of the RF signal at certain frequencies. In some embodiments, the filter includes an ordered set of resonator elements, with a resonance frequency equal to the frequency of interest in absorbing. In some embodiments, the resonator elements are implemented as a circle in the metal line or conduction that carries the RF signal, suspended by a path in the middle of the circle. This path is connected to a metal layer located below, to which all the paths in which the circular resonators are suspended can be connected. Figure 10A depicts schematic views of an ordered set 1000 of resonators for an absorption filter. For an absorption filter that targets cell bands, around 1-3 GHz, the resonator elements can be manufactured using a CMOS method, so that they have a relatively small size characteristic. In some embodiments, the resonator elements may have a larger size when implemented in the form of a ring resonator suspended by additional paths. Figure 10B depicts schematic views of such an ordered set 1050 of resonators for an absorption filter.

In some embodiments, the filters illustrated in Figures 10A and 10B are implemented in conjunction with a switching mechanism, which may be a useful structure in cell phone applications. Additionally, the switching mechanism can provide a tunable filter in the case of disc / ring resonators of different sizes. and that have resonance frequencies and with independent polarization conduits.

In some embodiments, a DC voltage (direct current - "DC (direct curren.)") Is applied to the resonator elements to activate or deactivate the filter, as required. Due to procedural variations, or otherwise, it may be possible to have resonator elements with different sizes and, therefore, with different resonance frequencies throughout the array. This will make it possible to characterize a filter with any desired shape. And this shape can be adjustable if the design is such that it is possible to apply a different voltage (typically, on or off) to different resonator sizes. However, if desired, the sensor array can be densely formed within a small area of the interconnection layers in order to reduce the frequency mismatch between the resonator elements of the sensor array.

In some embodiments, the systems and methods described herein make possible a filter that has a large array of mechanically decoupled resonators. Such a filter can accommodate high resonance frequencies, while maintaining the size of the device. Since small devices have a small mechanical coupling and great resistance to movement, a large array can be constructed having these resonator elements placed in parallel. This can reduce the total resistance to movement, since this will be inversely proportional to the number of resonator elements in parallel. In some embodiments, the resonator elements are arranged in series, in a square or in any other desired configuration.

These resonator elements may have been made with a single bridge, as shown in Figure 5A (described above). The bridge has been built using M5, which is a metallic layer located under the uppermost layer and which is anchored using M4 and M3 below. M3 can make the design more robust against surface chemical attack and process variations (since the thickness tolerance in the CMOS procedure is important), and M3 can also be used to route and connect the different bridges. Figure 5B (formerly described) shows the same bridge, but with the coverage and anchor columns to support the coverage. The cover has a plurality of holes to perform the superficial chemical attack with vHF [vapor phase hydrofluoric acid]. The coverage columns go from the M6 down to the M4, so that the routing can be done using the M3 level: The bridge made with M5 and the coverage made with M6 defines a capacitance. To build an orderly set, many of these bridges can be placed in series. If they do not fit in a row, or to make the design more square, some rows of bridges can be placed in series and connected through thick return pipes in M3.

Figure 1 1 represents a schematic view of a resonator element with a narrow lateral separation space, in accordance with an illustrative embodiment of the invention. In some embodiments, in order to improve the performance of these filters, a key parameter may be to reduce the separation space as much as possible. One way to reduce this separation space beyond what can be achieved by technology, is by using side bridges. These can be constructed by forming a structure with springs or soft springs, which is then closed by contraction, and if there are stops that are placed very short distance from the fixed electrodes, then a very narrow separation space can be achieved. In theory, the limit for this separation space is the grid resolution, for example, for nodes of 0.15 μηη, the limit is typically approximately 10 nm. In practice, it may be necessary for the separation space to be larger due to the fact that the cross section of a thin cantilever element is not straight and the walls have a certain angle. In certain configurations, the operating separation space may be less than or equal to about 1 nm, 5 nm, 10 nm, 20 nm, 50 nm or 100 nm. In addition, each of the sub-layers of the metal stack has its own shape.

In some embodiments, once the closing tension has been released by contraction, the separation space does not open again due to the strictness. The closing tension by contraction can be simply activated, whether the bridges are already attached or crushed against the stops or not. Figure 1 1 represents a top plan view of M5, which has the bridge and stops. The drive electrodes can drive the movable bridge until it closes by contraction and is crushed against the mechanical stops, leaving a gap with the fixed electrode capacitance. Many variants of this design may be possible, including different positions for capacitance drive electrodes, and other types of movable bridge, such as cantilever elements, and many others. Also, the mechanical stops can be placed in different positions.

In certain implementations, the closing tension by contraction can be applied during the manufacturing process of the chip in order to adjust the operating separation space at the time of manufacture. However, in other implementations, the closing voltage by contraction can be applied by the device, for example, an electronic consumer device in which the chip was installed during initial activation or ignition, initialization and / or periodically. In some implementations, a device can detect the position of a bridge with respect to a capacitor electrode to determine if, and when, a shrinkage closing voltage has to be applied to reduce the distance to the distance of operating separation space between bridge its one or more corresponding capacitor electrodes. In another implementation, the mechanical resonator may include electrodes that allow the formation of one or more microsoldaduras, depending on the magnitude of closing tension by contraction applied. In this way, a sufficient closing tension by contraction can be applied so that the bridge is fixed to one or more mechanical stops. Once fixed in position, with the fixed operating separation space, a closing tension by contraction is no longer required.

An important need of the described filters is the ability to tune them easily. One reason for this is the fact of having a single filter in the front RF terminal of the telephone's headphone equipment, instead of a large bank of filters and the corresponding multiplexers or switches to select them. This is especially necessary in the new multi-band and multi-mode cell phones that are beginning to appear on the market. But there is another reason for this need to use the manufacturing process described above in relation to Figures 1-4C. There may be significant tolerances and deviations from the resonant frequency due, in part, to the aging, temperature and use. This is due to the use of the existing metallization of the BEOL or CMOS process, especially aluminum.

As a consequence of these tolerances and mismatches, the filter can be calibrated using an external clock, and adjusted as often as necessary. The change in voltage modifies the electromechanical coupling coefficient. Consequently, both the inductance of movement and the capacitance of movement change, but its product remains constant. However, in practice, the tension in the bridges can change, and Young's modulus or effective elastic may be different, depending on the polarization voltage applied. In addition, the capacitance or electrical capacity can change markedly, and this can also affect the frequency response. This dependence on tension will be different for each resonator design. As an example, Figure 12 depicts schematic views (labels or unlabeled) of a resonator element 1200 for an RF filter. In some embodiments, the resonator element and other filter structures have been made using tungsten, for example, side elements. Tungsten can make possible more stable devices that do not need to be calibrated or tuned often.

In some embodiments, the described filters may have been designed to meet the specifications required for the implementation of UMTS filters. It is possible to achieve very low insertion losses by increasing the bias voltage and the number of elements of the ordered array. However, the tension may have a practical limit, and increasing the number of elements may reduce the attenuation in the stop band. In some embodiments, the requirements for insertion losses may be satisfied, but not the requirements for attenuation if an ordered set is used. In some embodiments, the attenuation requirements may be satisfied, but not the insertion loss requirements if a single element is used. Additionally, the separation space can be adjusted to the grid resolution limit, but, due to the non-vertical walls of the metal layers, the actual effective separation space may be smaller than expected. In some configurations, the operation of the RF filter at frequency intervals associated with protocols for GSM, UMTS, CDMA, AMPS, 802.1 1, and LTE communication protocols. In some configurations, an RF filter operates at any value between approximately 3 Hz and approximately 3 GHz. As regards wireless communications networks, an RF filter can operate in one or more frequency bands between approximately 400 MHz and approximately 4 GHz

There are at least two ways to overcome this compromise between losses and attenuation: lower pressures and modal filters. The decrease in pressures in such a way that the quality factor of the individual resonator elements goes beyond the maximum measured value, can result in non-uniform admittance and filter transfer functions due to the large number of sharp edges and the Random CMOS treatment for MEMS devices and their applications from one device to another. However, for some frequencies, it is possible to align a sufficiently large number of resonator elements, whereby the desired performance for that frequency is provided. In some embodiments, these filters may include intelligent circuits to adjust the voltage in such a way that the resonant frequency of these filters that have been matched in frequency is adjusted to the desired center frequency for the filter.

The other option is to use variable impedances made with an ordered set of mechanically coupled resonator elements, within a modal filter architecture. The modal filter can provide extremely high attenuation. In some embodiments, the modal filter may work well as long as impedance changes of the order of 20 dB are made. Using this combination, an ordered set of mechanical resonators can be designed with a view to minimizing losses, and using the modal architecture to maximize attenuation. In this way, a very high performance, tunable and low cost UMTS filter can be implemented. On the other hand, when implemented in CMOS, the filter can be integrated with other functions, such as the transceiver and amplifiers.

The present Applicants consider as patentable subject matter all the operative combinations of the embodiments disclosed herein. Those skilled in the art will know or be able to devise, using no more than routine experimentation, many equivalents to the realizations and practices described here. Accordingly, it will be understood that the systems and methods described herein are not limited by the embodiments disclosed herein, but should be understood from the following claims, which should be interpreted as broadly as the Law permits. It should also be appreciated that, although the following claims have been arranged in a specific manner, such that certain claims depend on other claims, either directly or indirectly, any of the following claims may depend on any other of the claims that they follow, either directly, or indirectly, to carry out any of the various embodiments described herein.

Claims

one . A method for manufacturing a chip comprising a radio frequency filter based on MEMS and arranged in an integrated circuit, comprising:

forming electronic elements on a substrate of semiconductor material;

forming, above the semiconductor material substrate, a stack of interconnecting layers that includes a plurality of layers of conductive material, each layer being separated by a layer of dielectric material; and forming a radiofrequency filter within the stack of interconnection layers by applying gaseous HF to the interconnection layers, wherein the radiofrequency filter includes a plurality of mechanically decoupled resonator elements.

2. The method according to claim 1, wherein the chip is manufactured using a CMOS method of 180 nm or less.

3. The method according to claim 2, wherein the chip is manufactured using one of a 22 nm CMOS procedure, a 32 nm CMOS procedure, a 45 nm CMOS procedure and a CMOS procedure 65 nm.

4. The method according to claim 1, wherein the radiofrequency filter includes an ordered sensor assembly of mechanically decoupled resonator elements, wherein the ordered sensor assembly has been configured to function collectively as a radiofrequency filter.

5. The method according to claim 4, wherein the sensor array comprises from about 60 to about 200 resonator elements.

6. The method according to claim 4, wherein the sensor array is densely formed in a small area of the interconnection layers in order to reduce the frequency mismatch between the resonator elements of the sensor array.

7. The method according to claim 1, wherein the sensor array has a Q factor of 100 or greater.

8. The method according to claim 1, wherein the sensor array has a Q factor ranging from about 5 to about 20.

9. The method according to claim 1, wherein the plurality of resonator elements are calibrated using an external clock.

10. The method according to claim 1, wherein the plurality of resonator elements are of different sizes, and each resonator element has been configured to be activated or deactivated.

eleven . The method according to claim 1, wherein the radio frequency filter is configured for one or more of the UMTS frequency range, the GSM frequency range, the LTE frequency range, the cellular frequency range and the WiFi frequency range.

12. The method according to claim 1, wherein the resonator elements are electrically connected in series.

13. The method according to claim 1, wherein the resonator elements are electrically connected in parallel.

14. The method according to claim 1, wherein the resonator elements are physically placed in a configuration corresponding to one of a row, a square and a grid.

15. The method according to claim 1, wherein the chip includes a controller for adjusting a voltage applied to one or more resonator elements in order to adjust a resonance frequency of the radiofrequency filter.

16. The method according to claim 1, wherein forming a resonator element includes forming a movable bridge and at least one capacitance electrode, separated from the movable bridge a first distance in order to form an initial gap or gap within the resonator element.

17. The method according to claim 16, comprising forming at least one mechanical stop within the resonator element, the mechanical stop extending beyond the at least one capacitance electrode in a second distance.

18. The method according to claim 17, which comprises applying a driving voltage to at least one electrode of drive to move the movable bridge to its contact with the at least one mechanical stop, so as to form an operating separation space equal to approximately the second distance between the movable bridge and the at least one capacitance electrode.

19. The method according to claim 18, wherein the operating separation space is less than or equal to any one between 1 nm, 5 nm, 10 nm, 20 nm, 50 nm and 100 nm.

20. The method according to claim 18, which comprises applying the drive voltage after the installation of the chip within an electronic consumer device.

twenty-one . The method according to claim 1, wherein a portion of the radiofrequency filter is made of tungsten.

22. A chip comprising a radio frequency filter based on MEMS and disposed within an integrated circuit, comprising:

electronic elements formed on a substrate of semiconductor material;

a stack or stack of interconnection layers, produced above the substrate of semiconductor material, including a plurality of layers of semiconductor material, each layer being separated by a layer of dielectric material; Y

a radiofrequency filter formed within the stack of interconnection layers by applying gaseous HF to the interconnection layers, in which the radiofrequency filter includes a plurality of mechanically decoupled resonator elements.