WO2013065596A1 - Circuit de pixel, dispositif d'affichage le comprenant et procédé de commande de circuit de pixel - Google Patents

Circuit de pixel, dispositif d'affichage le comprenant et procédé de commande de circuit de pixel Download PDF

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Publication number
WO2013065596A1
WO2013065596A1 PCT/JP2012/077723 JP2012077723W WO2013065596A1 WO 2013065596 A1 WO2013065596 A1 WO 2013065596A1 JP 2012077723 W JP2012077723 W JP 2012077723W WO 2013065596 A1 WO2013065596 A1 WO 2013065596A1
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Prior art keywords
power supply
holding capacitor
voltage
pixel circuit
driving transistor
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PCT/JP2012/077723
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English (en)
Japanese (ja)
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宣孝 岸
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シャープ株式会社
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage

Definitions

  • the present invention relates to a display device, and more particularly to a display device including a self-luminous display element driven by a current such as an organic EL display and a driving method thereof.
  • an organic EL (Electro Luminescence) display is known as a thin, high image quality, low power consumption display device.
  • this organic EL display a plurality of pixel circuits including organic EL elements which are self-luminous display elements driven by current and driving transistors for driving the organic EL elements are arranged in a matrix.
  • a method of controlling the amount of current that flows in a current-driven display element such as an organic EL element is a constant current type that controls the current that should flow through the display element by the data signal current that flows through the data signal line electrode of the display element.
  • a control method (or a current program type driving method) and a constant voltage type control method (or a voltage program type driving method) for controlling a current to be supplied to the display element by a voltage corresponding to the data signal voltage are roughly classified.
  • current reduction decrease in luminance caused by variations in threshold voltages of driving transistors and high resistance due to deterioration over time of organic EL elements. There is a need to compensate.
  • the current value of the data signal is controlled so that a constant current flows through the organic EL element regardless of the threshold voltage and the internal resistance of the organic EL element. No compensation is necessary.
  • the constant current type control method the number of driving transistors and wirings is increased as compared to the constant voltage type control method, and it is known that the aperture ratio is lowered. Therefore, the constant voltage type control method is widely used. It has been adopted.
  • Japanese Unexamined Patent Publication No. 2005-31630 describes a pixel circuit 91 shown in FIG.
  • FIG. 20 is a circuit diagram of the pixel circuit 91.
  • the pixel circuit 91 includes first to sixth TFTs (Thin Film Transistors) 11 to 16, an organic EL element 17, and a capacitor 18.
  • the first to sixth TFTs 11 to 16 are all p-channel transistors.
  • the pixel circuit 91 is connected to two scanning signal lines Gi and G (i ⁇ 1), a control line Ei, a data line Sj, a pair of power supply lines VPj, and an electrode having a common potential Vcom. .
  • the source terminal of the TFT 11 is connected to one conduction terminal of the TFT 13 and one conduction terminal of the TFT 15, and the drain terminal of the TFT 11 is connected to one conduction terminal of the TFT 12 and one conduction terminal of the TFT 14.
  • the other conduction terminal of the TFT 13 is connected to a wiring that supplies the power supply potential VDD in the power supply line VPj.
  • the other conduction terminal of the TFT 15 is connected to the data line Sj.
  • the other conduction terminal of the TFT 14 is connected to the anode terminal of the organic EL element 17.
  • One conduction terminal of the TFT 12 is connected to the gate terminal of the TFT 11, and the other conduction terminal of the TFT 12 is connected to the drain terminal of the TFT 11.
  • One conduction terminal of the TFT 16 is connected to a wiring that supplies the initialization potential Vini of the power supply line VPj, and the other conduction terminal of the TFT 16 is connected to a control terminal of the TFT 11.
  • One end of the data holding capacitor 18 is also connected to the control terminal of the TFT 11, and the other end is connected to a wiring for supplying the power supply potential VDD in the power supply line VPj.
  • a common potential Vcom is applied to the cathode terminal of the organic EL element 17.
  • the gate terminals of the TFTs 12 and 15 are connected to the scanning signal line Gi.
  • the gate terminal of the TFT 16 is connected to the scanning signal line G (i ⁇ 1).
  • the gate terminals of the TFTs 13 and 14 are connected to the control line Ei.
  • FIG. 21 is a circuit diagram of the pixel circuit 92.
  • the pixel circuit 92 includes first to sixth TFTs 21 to 26, an organic EL element 17, and a data holding capacitor 28.
  • the first to sixth TFTs 21 to 26 are all p-channel transistors.
  • the pixel circuit 92 is connected to the scanning signal line Gi, the control line Ei, the initialization control line Ii, the data line Sj, a set of two power supply lines VPj, and an electrode having a common potential Vcom.
  • the source terminal of the TFT 22 is connected to the wiring that supplies the power supply potential VDD in the power supply line VPj, and the drain terminal of the TFT 22 is connected to one conduction terminal of the TFT 23.
  • the other conduction terminal of the TFT 23 is connected to the gate terminal of the TFT 22.
  • One conduction terminal of the TFT 25 is connected to the drain terminal of the TFT 22, and the other conduction terminal of the TFT 25 is connected to the anode terminal of the organic EL element 17.
  • one conduction terminal of the TFT 21 is connected to the data line Sj, and the other conduction terminal is connected to one end of the data holding capacitor 28.
  • One conduction terminal of the TFT 24 and one conduction terminal of the TFT 26 are both connected to a wiring for supplying the initialization potential Vini in the power supply line VPj.
  • One conduction terminal of the TFT 24 is connected to the other end of the data holding capacitor 28, and the other conduction terminal of the TFT 26 is connected to one end of the data holding capacitor 28.
  • the other end of the data holding capacitor 28 is connected to the gate terminal of the TFT 22.
  • a common potential Vcom is applied to the cathode terminal of the organic EL element 17.
  • the gate terminals of the TFTs 21 and 23 are connected to the scanning signal line Gi.
  • the gate terminal of the TFT 24 is connected to the initialization control line Ii.
  • the gate terminals of the TFTs 25 and 26 are connected to the control line Ei.
  • FIG. 22 is a circuit diagram of the pixel circuit 93.
  • the pixel circuit 93 includes first to sixth TFTs 31 to 36, an organic EL element 17, and a data holding capacitor 38.
  • the first to sixth TFTs 31 to 36 are all n-channel transistors.
  • the pixel circuit 93 is connected to the scanning signal line Gi, the control lines Eai to Edi, the data line Sj, the power supply line VPj, and the electrode having the common potential Vcom.
  • the drain terminal of the TFT 31 that is a driving transistor is connected to the power supply line VPj that supplies the power supply potential VDD via the TFT 35 on the current path.
  • the source terminal of the TFT 31 is connected to the anode terminal of the organic EL element 17 via the TFT 32 on the current path.
  • One conduction terminal of the TFT 36 is connected to the drain terminal of the TFT 31, and the other conduction terminal is connected to the gate terminal of the TFT 31.
  • One conduction terminal of the TFT 34 is connected to the data line Sj, and the other conduction terminal is connected to the source terminal of the TFT 31.
  • One end of the data holding capacitor 38 is connected to an electrode having a common potential Vcom through the TFT 33.
  • One end of the data holding capacitor 38 is connected to the source terminal of the TFT 31 via the TFT 32.
  • a common potential Vcom is applied to the cathode terminal of the organic EL element 17.
  • the gate terminal of the TFT 34 is connected to the scanning signal line Gi.
  • the gate terminal of the TFT 33 is connected to the control line Edi.
  • the gate terminal of the TFT 36 is connected to the control line Eai.
  • the gate terminal of the TFT 32 is connected to the control line Eci.
  • the gate terminal of the TFT 35 is connected to the control line Ebi.
  • FIG. 23 is a circuit diagram of the pixel circuit 94.
  • the pixel circuit 94 includes first to third TFTs 41 to 43, an organic EL element 17, two data holding capacitors 48a and 48b, and a threshold holding capacitor 49. Yes.
  • the first to third TFTs 41 to 43 are all p-channel transistors.
  • the pixel circuit 94 is connected to electrodes having the scanning signal line Gi, the control line Ei, the data line Sj, the power supply line VPi, and the common potential Vcom.
  • One conduction terminal of the TFT 41 is connected to the data line Sj, and the other conduction terminal is connected to one end of two data holding capacitors 48a and 48b. Of these two data holding capacitors 48a and 48b, the other end of the data holding capacitor 48a is connected to the gate terminal of the TFT 42, and the other end of the data holding capacitor 48b is connected to the power supply line VPi.
  • the drain terminal of the TFT 42 is connected to the power supply line VPi, and the source terminal is connected to the anode terminal of the organic EL element 17.
  • a common potential Vcom is applied to the cathode terminal of the organic EL element 17.
  • One of the conduction terminals of the TFT 43 is connected to the gate terminal of the TFT 42, and the other of the conduction terminals of the TFT 43 is connected to the source terminal of the TFT 42.
  • the gate terminal of the TFT 41 is connected to the scanning signal line Gi.
  • the gate terminal of the TFT 43 is connected to the control line Ei.
  • Japanese Unexamined Patent Application Publication No. 2007-79580 describes a pixel circuit 95 shown in FIG. 24 that is similar to the pixel circuit 92 shown in FIG.
  • FIG. 24 is a circuit diagram of the pixel circuit 95.
  • the pixel circuit 95 includes six TFTs 11 to 16, which are the same components as the pixel circuit 92, the organic EL element 17, the capacitor 18, and further includes an auxiliary capacitor Caux.
  • the other conduction terminal of the TFT 12 is connected to the source terminal instead of the drain terminal of the TFT 11.
  • one conduction terminal of the TFT 15 is connected to the drain terminal instead of the source terminal of the TFT 11.
  • one end of the auxiliary capacitor Caux is connected to the control terminal of the TFT 11 like the capacitor 18, and the other end is connected to the scanning signal line Gi whose potential changes.
  • Each of the pixel circuits 91 to 95 shown in FIGS. 20 to 24 has a configuration in which a potential that is increased or decreased by a predetermined voltage from the potential Vdata of the video signal line (data line) is applied to the driving transistor. Therefore, when the difference (dynamic range) between the maximum value and the minimum value of the potential Vdata of the video signal line is large, an excessive current exceeding an appropriate current may flow to the organic EL element. In order to prevent this, a configuration in which the output dynamic range of the data driver circuit is reduced and a configuration in which the channel length L is increased in order to reduce the current capability of the driving transistor are required.
  • a data driver circuit having a general configuration cannot be used, resulting in an increase in manufacturing cost.
  • a data driver circuit with a small dynamic range has a relatively large output deviation per gray level, so that an output error increases.
  • the channel length L of the driving transistor is increased in order to reduce the current flowing through the organic EL element without changing the dynamic range of the data driver circuit, the area of the pixel circuit increases. As a result, the aperture ratio of the pixel is lowered and it is difficult to increase the definition of the display device.
  • the present invention can provide a current (fine current) that is not excessive to the organic EL element without reducing the dynamic range of the data driver circuit and without increasing the channel length L of the driving transistor. It is an object to provide a pixel circuit that can be used and a display device including the pixel circuit.
  • a first aspect of the present invention is a pixel circuit provided in an active matrix display device, An electro-optic element driven by a current supplied from a power supply line to which a power supply voltage is supplied; A driving transistor provided on a path of a current flowing through the electro-optic element and determining a current to be passed through the path; A threshold holding capacitor having one end connected to the control terminal of the driving transistor and the other end connected to a conduction terminal of the driving transistor or a connection point to which a predetermined fixed voltage is applied; A data holding capacitor having one end connected to the control terminal of the driving transistor and the other end connected to the power supply line or a connection point to which a predetermined voltage is applied; When turned on, the threshold holding capacitor is given a threshold voltage of the driving transistor or a voltage changed by a predetermined voltage with respect to the threshold voltage, and the data holding capacitor has a predetermined initial value.
  • a voltage corresponding to a video signal representing an image to be displayed is added to or subtracted from the threshold voltage, and a voltage changed by a predetermined voltage is applied.
  • First and second write control transistors connected to be held by the threshold holding capacitor and the data holding capacitor; At least one of a first current path between the conduction terminal of the driving transistor and the power supply line and a second current path between the conduction terminal of the driving transistor and the electro-optic element.
  • a light-emitting transistor connected to be conductive in the first or second current path in a light-emitting period provided on the pixel circuit and performing display in the pixel circuit.
  • the light emission control transistor is: A first light emission control transistor provided on the first current path; A second light emission control transistor provided on the second current path,
  • the first write control transistor is connected to apply the initialization voltage to the one end of the data holding capacitor in a predetermined initialization period.
  • the second writing control transistor is connected to apply a voltage corresponding to the video signal to a control terminal of the driving transistor in a predetermined writing period,
  • the other end of the threshold holding capacitor is connected to a conduction terminal of the driving transistor and a conduction terminal of the second write control transistor.
  • the other end of the data holding capacitor is connected to the power supply line.
  • the other end of the data holding capacitor is connected to an initialization power supply line to which the initialization voltage is supplied.
  • One end of a conduction terminal is connected to the other end of the data holding capacitor, and the other end of the conduction terminal is connected to the power supply line or an initialization power supply line to which the initialization voltage is supplied.
  • a fixed potential supply transistor connected to the other end of the data holding capacitor to supply the power supply voltage or the initial overvoltage;
  • the light emission control transistor is provided on the second current path;
  • the first writing control transistor is connected to conduct the control terminal of the driving transistor and one of the conduction terminals of the driving transistor in a predetermined writing period;
  • the second writing control transistor is connected so as to apply a voltage corresponding to the video signal to a control terminal of the driving transistor in the writing period.
  • a sixth aspect of the present invention is the fifth aspect of the present invention,
  • the other end of the threshold holding capacitor is connected to the other conduction terminal of the driving transistor and the power supply line.
  • the other end of the threshold holding capacitor is connected to the initialization power supply line.
  • One end of a conduction terminal is connected to the other end of the data holding capacitor, and the other end of the conduction terminal is connected to a power supply line for applying a voltage lower than the power supply voltage or a cathode terminal of the electro-optic element, A fixed potential supply transistor connected to be conductive in the writing period;
  • the light emission control transistor is: A first light emission control transistor provided on the first current path; A second light emission control transistor provided on the second current path,
  • the first writing control transistor is connected to conduct the control terminal of the driving transistor and one of the conduction terminals of the driving transistor in a predetermined writing period;
  • the second write control transistor is connected to conduct one of the conduction terminals of the driving transistor and a video signal line to which the video signal is supplied in the writing period,
  • the one end of the threshold holding capacitor is connected to a control terminal of the driving transistor, and the other end is connected to the other conduction terminal of the driving transistor.
  • a ninth aspect of the present invention is an active matrix display device, The pixel circuit according to any one of the first to eighth aspects of the present invention; A plurality of video signal lines for transmitting a signal representing the image to be displayed; A plurality of scanning signal lines and a plurality of control lines intersecting with the plurality of video signal lines; A plurality of power supply lines for supplying the power supply voltage to the plurality of pixel circuits; A scanning signal line driving circuit for selectively or collectively driving the plurality of scanning signal lines and the plurality of control lines; A video signal line driving circuit for driving the plurality of video signal lines by applying a signal representing the image to be displayed; A power supply control circuit for driving the plurality of power supply lines, The pixel circuits are arranged in a matrix corresponding to the intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively. The first and second write control transistors and the light emitting transistor have their respective control terminals connected to the corresponding one of the plurality of control lines or the plurality of power supply lines.
  • an electro-optical element driven by a current supplied from a power supply line to which a power supply voltage is supplied, and a path of a current flowing through the electro-optical element are provided and should be passed through the path
  • a driving transistor for determining a current and a threshold holding capacitor having one end connected to the control terminal of the driving transistor and the other end connected to a conduction terminal of the driving transistor or a connection point to which a predetermined fixed voltage is applied
  • a data holding capacitor connected at one end to the control terminal of the driving transistor and connected at the other end to the power supply line or a connection point to which a predetermined voltage is applied
  • the threshold holding capacitor is given a threshold voltage of the driving transistor or a voltage changed by a predetermined voltage with respect to the threshold voltage, and the data holding capacitor is given a predetermined initialization voltage, Alternatively, a voltage obtained by adding or subtracting a voltage corresponding to a video signal representing an image to be displayed to the threshold voltage is further changed by a predetermined voltage
  • An eleventh aspect of the present invention is the tenth aspect of the present invention
  • the pixel circuit is a circuit in which the other end of the threshold holding capacitor is connected to a conduction terminal of the driving transistor,
  • the writing step includes A first writing step of applying the initialization voltage to the one end of the data holding capacitor in a predetermined initialization period; A second writing step of applying a voltage corresponding to the video signal to a control terminal of the driving transistor in a predetermined writing period;
  • the light emitting step is characterized in that the first and second current paths are made conductive from a non-conductive state during the light emission period.
  • a twelfth aspect of the present invention is the tenth aspect of the present invention.
  • the pixel circuit has one end of a conduction terminal connected to the other end of the data holding capacitor, and the other end of the conduction terminal is connected to the power supply line or an initialization power supply line supplied with the initialization voltage.
  • the writing step includes A first writing step of conducting the control terminal of the driving transistor and one of the conduction terminals of the driving transistor in a predetermined writing period; A second writing step of applying a voltage corresponding to the video signal to a control terminal of the driving transistor in a predetermined writing period; In the light emitting step, a current is caused to flow from the power supply line to the electro-optical element by conducting the second current path from a non-conducting state.
  • a thirteenth aspect of the present invention is the tenth aspect of the present invention,
  • one end of a conduction terminal is connected to the other end of the data holding capacitor, and the other end of the conduction terminal is connected to a power supply line that applies a voltage lower than the power supply voltage or a cathode terminal of the electro-optic element.
  • a fixed potential supply transistor connected to be conductive in a predetermined writing period;
  • the pixel circuit is a circuit in which the one end of the threshold holding capacitor is connected to the control terminal of the driving transistor and the other end is connected to the other conduction terminal of the driving transistor.
  • the writing step includes A first writing step of conducting a control terminal of the driving transistor and one of conduction terminals of the driving transistor in a predetermined writing period; A second writing step of conducting one of the conduction terminals of the driving transistor and a video signal line to which the video signal is applied in a predetermined writing period;
  • the light emitting step is characterized in that the first and second current paths are made conductive from a non-conductive state during the light emission period.
  • the pixel circuit includes the threshold value holding capacitor, whereby the dynamic range of the voltage applied to the control terminal of the driving transistor is set to the capacitance value of the data holding capacitor. Is c1, and the capacitance value of the threshold holding capacitor is c2. As a result, it can be reduced by c1 / (c1 + c2), so that the dynamic range of the data driver circuit itself is not changed, and the electro-optic element An appropriate amount of current that does not become excessive can be applied to the electro-optic element without changing the parameters (for example, channel length).
  • a threshold holding capacitor at an appropriate position, a voltage tracking effect can be obtained with respect to the IR drop caused by the arrangement position of the pixel circuit, so that a luminance difference due to the IR drop can be reduced, and display quality can be reduced. Can be suppressed.
  • the circuit area of the pixel circuit can be prevented from increasing compared to the conventional one, and the error of the data potential can be further reduced by using a (general) data driver circuit having a large dynamic range. Therefore, it is possible to suppress the luminance variation of the pixels caused by the output deviation in the data driver circuit. Furthermore, it is possible to control the electro-optic element with a smaller amount of current without changing the size of the driving transistor, and it is not necessary to change the design conditions and manufacturing process, thereby increasing the degree of design freedom. Can do.
  • the load on the power supply circuit can be reduced, and the light emission control transistor. Since the lighting / non-lighting of the electro-optic element is controlled by this, there is no need to change the power supply potential, and the load on the power supply circuit can be reduced.
  • the gate potential of the driving transistor is set to the power supply line against the potential fluctuation of the power supply line during the light emission period. Changes to some extent with respect to the potential fluctuation. Also in this respect, a voltage tracking effect can be obtained with respect to the IR drop, so that a luminance difference due to the IR drop can be reduced, and a reduction in display quality can be suppressed.
  • the other end of the data holding capacitor is connected to the initialization power supply line, it is possible to prevent the influence of the potential fluctuation of the power supply line during the writing period. .
  • the same effects as those of the first aspect of the present invention can be obtained, and the connection relationship of the threshold holding capacitors can be set appropriately, depending on the arrangement position of the pixel circuit.
  • the difference in luminance due to the IR drop that occurs can be greatly reduced, and the deterioration of display quality can be suppressed.
  • the other end of the threshold holding capacitor that functions as a storage capacitor during the light emission period is connected to the power supply line.
  • the gate potential of the driving transistor changes following the potential fluctuation of the power supply line at a predetermined rate. This ratio becomes larger as c1 is smaller than c2 (it becomes easier to follow the potential fluctuation of the power supply line).
  • the seventh aspect of the present invention since the other end of the threshold holding capacitor that functions as a holding capacitor during the light emission period is connected to the initialization power supply line, the potential fluctuation of the power supply line during writing can be prevented. , Completely unaffected. In this respect, a luminance difference due to IR drop can be reduced, and a reduction in display quality can be suppressed.
  • the same effects as those of the first aspect of the present invention can be obtained, and the initialization operation is not necessary. Can be omitted.
  • the display device including the pixel circuit according to the first aspect of the present invention can achieve the same effects as those of the first aspect of the present invention.
  • the method of controlling the pixel circuit in the first, second, fifth, and eighth aspects of the present invention in a similar manner provides The same effects as those of the first, second, fifth, and eighth aspects can be achieved.
  • FIG. 4 is a timing chart illustrating a driving method of the pixel circuit in the embodiment. It is a circuit diagram of the pixel circuit in the 1st modification of the above-mentioned embodiment. It is a circuit diagram of the pixel circuit in the 2nd modification of the above-mentioned embodiment. It is a block diagram which shows the structure of the display apparatus which concerns on the 3rd Embodiment of this invention. It is a circuit diagram of the pixel circuit in the embodiment. It is a block diagram which shows the structure of the display apparatus which concerns on the 4th Embodiment of this invention. It is a circuit diagram of the pixel circuit in the embodiment. 4 is a timing chart illustrating a driving method of the pixel circuit in the embodiment.
  • FIG. 1 is a block diagram showing a configuration of a display device according to the first embodiment of the present invention.
  • a display device 110 shown in FIG. 1 is an organic EL display including a display control circuit 1, a gate driver circuit 2, a data driver circuit 3, a power supply control circuit 4, and (m ⁇ n) pixel circuits 10.
  • m and n are integers of 2 or more
  • i is an integer of 1 to n
  • j is an integer of 1 to m.
  • the display device 110 is provided with n scanning signal lines Gi parallel to each other and m data lines Sj parallel to each other orthogonal thereto. Although omitted in the drawing, a scanning signal line G0 for initialization control described later is further provided.
  • the (m ⁇ n) pixel circuits 10 are arranged in a matrix corresponding to the intersections of the scanning signal lines Gi and the data lines Sj, and display pixels of each color constituting the display image.
  • n control lines Ei are provided in parallel with the scanning signal lines Gi
  • n sets of power supply lines VPi are provided in parallel with the data lines Sj.
  • a common power supply line 9 which is a current supply trunk line for connecting the power supply control circuit 4 and the power supply line VPi is provided.
  • the common power supply line 9 includes two wirings for applying two potentials to be described later.
  • the scanning signal line Gi and the control line Ei are connected to the gate driver circuit 2, and the data line Sj is connected to the data driver circuit 3.
  • the power supply line VPi includes two wirings for applying two potentials to be described later, and is connected to the power supply control circuit 4 via the corresponding common power supply line 9.
  • a common potential Vcom is supplied to the pixel circuit 10 by a common electrode (not shown).
  • one end of each set of two power supply lines VPi is connected to one set of two common power supply lines 9, but is connected to each end thereof (or three or more connection points). It may be.
  • the display control circuit 1 outputs control signals to the gate driver circuit 2, the data driver circuit 3, and the power supply control circuit 4. More specifically, the display control circuit 1 outputs a timing signal OE, a start pulse YI, and a clock YCK to the gate driver circuit 2, and outputs a start pulse SP, a clock CLK, display data DA, and the data driver circuit 3. A latch pulse LP is output, and a control signal CS is output to the power supply control circuit 4.
  • the gate driver circuit 2 includes a shift register circuit, a logic operation circuit, and a buffer (all not shown).
  • the shift register circuit sequentially transfers the start pulse YI in synchronization with the clock YCK.
  • the logical operation circuit performs a logical operation between the pulse output from each stage of the shift register circuit and the timing signal OE.
  • the output of the logical operation circuit is given to the corresponding scanning signal line Gi and control line Ei via the buffer.
  • the m pixel circuits 10 are connected to the scanning signal line Gi, and the pixel circuits 10 are collectively selected by the m using the scanning signal line Gi.
  • the data driver circuit 3 includes an m-bit shift register 5, a register 6, a latch circuit 7, and m D / A converters 8.
  • the shift register 5 has m registers connected in cascade, transfers the start pulse SP supplied to the first-stage register in synchronization with the clock CLK, and outputs a timing pulse DLP from each stage register.
  • Display data DA is supplied to the register 6 in accordance with the output timing of the timing pulse DLP.
  • the register 6 stores display data DA according to the timing pulse DLP.
  • the display control circuit 1 outputs a latch pulse LP to the latch circuit 7.
  • the latch circuit 7 receives the latch pulse LP, the latch circuit 7 holds the display data stored in the register 6.
  • the D / A converter 8 is provided corresponding to the data line Sj.
  • the D / A converter 8 converts the display data held in the latch circuit 7 into an analog voltage, and applies the obtained analog voltage to the data line Sj.
  • the power supply control circuit 4 applies the power supply potential VDD to one of the two common power supply lines 9 and the initialization potential Vini to the other wiring based on the control signal CS. As shown in FIG. 1, since the power supply line VPi is connected to the common power supply line 9, one of the wirings of the power supply line VPi has a power supply potential and the other has an initialization potential.
  • FIG. 2 is a circuit diagram of the pixel circuit 10. As shown in FIG. 2, the pixel circuit 10 includes first to sixth TFTs 11 to 16, an organic EL element 17, a data holding capacitor 18, and a threshold holding capacitor 19.
  • the first to sixth TFTs 11 to 16 are all p-channel transistors. Note that all of these may be configured by n-channel transistors, or may be configured to be used in some cases.
  • the same operation can be easily realized by inverting the power supply potential, the level of the control line, etc. without changing the connection relationship of each TFT and capacitor. it can.
  • the description thereof will be omitted instead of the following description.
  • the first to sixth TFTs 11 to 16 function as an initialization control transistor, a write control transistor, a driving transistor, and a light emission control transistor, respectively. Note that these functions are for explaining the main functions and may have other functions. The contents of these functions will be described later.
  • the organic EL element 17 functions as an electro-optical element.
  • the electro-optical element is an organic EL element, FED (Field Emission Display), LED, charge driving element, liquid crystal, E ink (Electronic Ink), etc. It shall mean all elements whose characteristics change.
  • an organic EL element is illustrated as an electro-optical element, but the same description can be made as long as the light emitting element has a light emission amount controlled according to a current amount.
  • the pixel circuit 10 has two scanning signal lines Gi and G (i ⁇ 1), a control line Ei, a data line Sj, a pair of power supply lines VPj, and a common potential Vcom. Connected to the electrode.
  • the source terminal of the TFT 11 is connected to one conduction terminal of the TFT 13 and one conduction terminal of the TFT 15, and the drain terminal of the TFT 11 is connected to one conduction terminal of the TFT 12 and one conduction terminal of the TFT 14.
  • the other conduction terminal of the TFT 13 is connected to a wiring that supplies the power supply potential VDD in the power supply line VPj.
  • the other conduction terminal of the TFT 15 is connected to the data line Sj.
  • the other conduction terminal of the TFT 14 is connected to the anode terminal of the organic EL element 17.
  • one conduction terminal of the TFT 12 is connected to the gate terminal (control terminal) of the TFT 11, and the other conduction terminal of the TFT 12 is connected to the drain terminal of the TFT 11.
  • one conduction terminal of the TFT 16 is connected to the gate terminal of the TFT 11 while the other conduction terminal of the TFT 16 is connected.
  • One end of the data holding capacitor 18 is also connected to the gate terminal of the TFT 11, and the other end is connected to a wiring for supplying the power supply potential VDD in the power supply line VPj.
  • the threshold holding capacitor 19 is provided between the source terminal and the gate terminal of the TFT 11. A common potential Vcom is applied to the cathode terminal of the organic EL element 17.
  • the gate terminals (control terminals) of the TFTs 12 and 15 are connected to the scanning signal line Gi. These TFTs 12 and 15 function as write control transistors.
  • a gate terminal (control terminal) of the TFT 16 is connected to the scanning signal line G (i ⁇ 1).
  • the TFT 16 functions as an initialization control transistor.
  • the gate terminals (control terminals) of the TFTs 13 and 14 are connected to the control line Ei. These TFTs 13 and 14 function as light emission control transistors.
  • FIG. 3 is a timing chart showing a driving method of the pixel circuit 10.
  • the potentials of the scanning signal lines G (i ⁇ 1) and Gi are high level, that is, inactive, and the potential of the control line Ei is low level, that is, active.
  • the potential of the control line Ei becomes inactive and light emission is stopped in the previous frame.
  • the scanning signal line G (i-1) becomes active, whereby the gate terminal of the TFT 11 and the power source Of the line VPj, the wiring that applies the initialization potential Vini is turned on, and the initialization potential Vini is written to one end of the data holding capacitor 18 (and the gate terminal of the TFT 11 that functions as a driving transistor).
  • the above operation is called an initialization operation.
  • the scanning signal line G (i-1) becomes inactive and the scanning signal line Gi becomes active, so that the TFTs 12 and 15 are turned on.
  • the potential of the data line Sj is a potential corresponding to the display data.
  • this potential is referred to as “data potential Vdata”.
  • Vdata is a threshold voltage of the TFT 11
  • the current I shown in the above formula (5) varies depending on the data potential Vdata, but does not depend on the threshold voltage Vth of the TFT 11. Therefore, even when the threshold voltage Vth varies or the threshold voltage Vth changes with time, a current corresponding to the data potential Vdata is supplied to the organic EL element 17 to cause the organic EL element 17 to emit light with a desired luminance. it can.
  • the overdrive voltage Vov of the p-channel type TFT 11 is defined as a value obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs of the TFT 11, and therefore can be expressed as the following equation (6).
  • the current I flowing through the TFT 11 during the light emission period is proportional to the square of the overdrive voltage Vov. Therefore, in the following, it will be described for convenience that flowing a current corresponding to the data potential Vdata to the organic EL element 17 is flowing a current corresponding to the overdrive voltage Vov.
  • the pixel circuit 10 in the i-th row is lit with a luminance corresponding to the applied data potential.
  • the pixel circuits 10 in the (i + 1) th and subsequent rows may be in the writing period. That is, while a certain pixel circuit is in the writing period, the pixel circuits in the previous row are lit. Therefore, the power supply potential VDD may cause a voltage drop (so-called IR drop). Since the change in the power supply potential VDD changes the overdrive voltage Vov, there is a possibility that a luminance difference occurs depending on the arrangement position of the pixel circuit. is there.
  • the configuration of the present embodiment has an overdrive voltage Vov due to a change in the power supply potential VDD compared to the conventional case. Can be suppressed to c1 / (c1 + c2). As a result, the luminance difference due to the IR drop caused by the arrangement position of the pixel circuit can be reduced, so that the deterioration of display quality can be suppressed.
  • both of them function as a holding capacitor. From this, the holding capacity can be increased without making the data holding capacitor 18 larger than the conventional case. Further, if the combined capacitance value of the data holding capacitor 18 and the threshold holding capacitor 19 is set so as to be equal to the capacitance value in the conventional data holding capacitor 18, the same holding capacitance in the same area as the conventional pixel circuit is obtained. Therefore, the circuit area of the pixel circuit can be prevented from increasing despite the provision of the threshold value holding capacitor 19 newly.
  • the dynamic range (difference between the maximum value and the minimum value) of the data potential Vdata necessary for defining the light emission luminance (proportional to the amount of current) of the organic EL element 17 is c1 / (compared with the conventional case). It can be reduced by c1 + c2).
  • the ratio of c2 to c1 is 1, when driven by the data driver circuit 3 having a dynamic range of 4V, the dynamic range of the overdrive voltage Vov applied to the pixel circuit is 2V. Therefore, for example, even when the amount of current to be passed through the organic EL element 17 is too large in the 4 V dynamic range, an appropriate amount that does not become excessive with respect to the organic EL element 17 without changing the dynamic range of the data driver circuit 3. Current can be given.
  • the error in the data potential caused by the output deviation in the data driver circuit 3 does not necessarily decrease in proportion to the decrease in the dynamic range.
  • the error per gradation becomes larger as the dynamic range increases.
  • the organic EL element can be controlled with a smaller amount of current without changing the size of the TFT 11.
  • the configuration of the TFT included in the pixel circuit is changed as described above, it is necessary to change design conditions, a manufacturing process, and the like, such as adjustment of mobility.
  • the TFT 11 having the same configuration as that of the conventional embodiment can be used, the degree of design freedom can be further increased.
  • the pixel circuit 10a shown in FIG. 4 has the same constituent elements as the pixel circuit 10; first to sixth TFTs 11 to 16, an organic EL element 17, a data holding capacitor 18, and a threshold holding capacitor 19 Including.
  • one end of the data holding capacitor 18 is connected to the gate terminal of the TFT 11 as in the case shown in FIG. 2, but unlike the case shown in FIG. 2, the other end of the data holding capacitor 18 is connected to the power source.
  • the line VPj is connected to a wiring that provides the initialization potential Vini.
  • the pixel circuit 10a shown in FIG. 4 is driven in the same manner as the pixel circuit 10 in the first embodiment. However, in the writing period, the data holding capacitor 18 is not connected to the power supply potential VDD at the other end. Since it is connected to the initialization potential Vini, the voltage of (Vdata + Vth ⁇ Vini) is held.
  • the potential at the gate terminal of the TFT 11 is not affected by the change in the power supply potential VDD. Therefore, even if the power supply potential VDD drops (IR drop) due to lighting of other pixel circuits, the luminance of the pixel circuits is not affected. Therefore, higher quality display can be performed. If there is a fixed potential applied in addition to the initialization potential Vini, it may be used instead of the initialization potential Vini.
  • the data potential cannot be held unless the other end of the data holding capacitor 18 is connected to the fixed potential point.
  • This also applies to the threshold holding capacitor 19 as will be described later.
  • the auxiliary capacitor Caux of the pixel circuit 95 shown in FIG. Different functions. As shown in FIG. 24, one end of the auxiliary capacitor Caux is connected to the control terminal of the TFT 11 like the capacitor 18, but the other end is connected to the scanning signal line Gi whose potential changes. Therefore, the function is completely different from that of the threshold capacitor 19, and the same effect as that of the threshold capacitor 19 cannot be obtained by the auxiliary capacitor Caux.
  • the threshold holding capacitor 19 is provided in all the pixel circuits 10, but only the pixel circuit emitting red (R) shown in FIG. 1 is provided with the threshold holding capacitor 19.
  • the pixel circuit that emits green (G) and the pixel circuit that emits blue (B) may not be provided with the threshold holding capacitor 19.
  • the pixel circuit that emits red (R) has the effect of the first embodiment, and the effect does not reach the pixel circuit that emits green (G) and blue (B).
  • the above-described effect can be obtained as a whole display device by this configuration because the organic EL element emitting red light in the pixel circuit emitting red (R) generally has high luminous efficiency.
  • the red light emitting material in the organic EL element that is currently used generally has higher luminous efficiency than the green light emitting material and the blue light emitting material, the emission luminance is larger than the light emitting materials of other colors when a large current is passed.
  • the white balance (color balance) of the displayed image becomes abnormal. Therefore, a threshold holding capacitor 19 is provided in the pixel circuit that emits red (R) so that a more appropriate weak current flows, and as a result, the dynamic range of the voltage applied to the gate terminal of the driving transistor is c1. Decrease by / (c1 + c2). Therefore, an appropriate amount of current that does not become excessive can be applied to the organic EL element 17 that emits red without changing the dynamic range of the data driver circuit 3 itself (for each color).
  • the green light emitting material in organic EL elements that are currently used generally has higher luminous efficiency than the blue light emitting material. Accordingly, as described above, the threshold value holding capacitor 19 is provided not only in the pixel circuit that emits red (R) but also in the pixel circuit that emits green (G) so that a weaker current flows. As a result, a configuration in which c1 / (c1 + c2) is reduced is also conceivable. Even in this configuration, an appropriate amount of current that does not become excessive can be applied to the organic EL element 17 that emits red and green without changing the dynamic range of the data driver circuit 3 itself (for each color).
  • a blue light emitting material in an organic EL element currently generally used has the lowest light emission efficiency among the respective colors.
  • the threshold holding capacitor 19 may be provided in the pixel circuit emitting blue (B) as described above.
  • the ratio (c1 / c2) of the threshold value holding capacitor 19 to the data holding capacitor 18 in the pixel circuit of each color is the smallest in the pixel circuit that emits red (R), and in the pixel circuit that emits blue (R). Become the largest.
  • the ratio in the pixel circuit that emits blue (B) is maximized, that is, the threshold holding capacitor 19 is not typically provided in the pixel circuit that emits blue (B).
  • the ratio can be easily set.
  • FIG. 5 is a diagram showing a relationship between a suitable pixel current and gradation in each color pixel circuit.
  • the light emission luminance in each color pixel circuit is suitably adjusted and white balance is achieved.
  • the ratio of the pixel current of each color at this time is expressed as the following equation (7).
  • R: G: B 1: 2: 4 (7)
  • the gradation voltage amplitude value that is the voltage range from the minimum gradation value to the maximum gradation value corresponding to the dynamic range in the pixel circuit emitting blue (B) is 4 V
  • the above equation (5) is referred to.
  • the gradation voltage amplitude value in the pixel circuit emitting blue (B) is about 2.8V
  • the gradation voltage amplitude value in the pixel circuit emitting red (R) is 2V.
  • the capacity of the data holding capacitor 18 in the circuit is 1, the capacity of the data holding capacitor 18 in the pixel circuit that emits red (R) is 1, and the capacity of the data holding capacitor 18 in the pixel circuit that emits green (G). May be set to about 0.41. Then, the gradation voltage amplitude value in all the pixel circuits is fixed to 4V, that is, the pixel current in each color pixel circuit is suitably set without changing the dynamic range of the data driver circuit 3 from 4V. It can be done easily.
  • the combined capacitance value (c1 + c2) of the data holding capacitor 18 and the threshold holding capacitor 19 in the pixel circuit of each color is set as follows while maintaining the ratio or without considering the ratio. Can be considered.
  • the combined capacitance values (c1 + c2) in the pixel circuits of the respective colors are all equal. By doing so, it is possible to freely set the dynamic range while keeping the same layout area occupied by the capacitive element in each pixel circuit.
  • the combined capacitance value (c1 + c2) in the red (R) pixel circuit is set to be smaller than the combined capacitance value (c1 + c2) in the green (R) pixel circuit, and the green (G) pixel circuit is set.
  • a configuration in which the combined capacitance value (c1 + c2) is set smaller than the combined capacitance value (c1 + c2) in the blue (B) pixel circuit is conceivable.
  • blue (B) has the shortest lifetime and red (R) has the longest lifetime of an organic EL element used in each color pixel circuit. Therefore, it is preferable to reduce the current density of the current flowing through the organic EL element in order to keep the element life long.
  • the layout area of the element part that is, the light emitting part is increased (the aperture ratio is increased). Is preferred. Therefore, if the combined capacitance value is set as described above, the layout area occupied by the capacitor element becomes smaller in the pixel circuit including the organic EL element having a shorter lifetime, so that the layout area of the light emitting portion can be increased.
  • the combined capacitance value (c1 + c2) in the red (R) pixel circuit is set larger than the combined capacitance value (c1 + c2) in the green (R) pixel circuit, and green (G
  • the combined capacitance value (c1 + c2) in the pixel circuit of () may be set larger than the combined capacitance value (c1 + c2) in the blue (B) pixel circuit.
  • the blue (B) pixel circuit is the largest.
  • the smaller the retained charge the greater the influence of the leakage current in the TFTs 12 and 16 on the retained charge, which may cause display gradation error and flicker. Therefore, if the combined capacitance value (c1 + c2) in the pixel circuit of each color is set as described above, the red (R) pixel circuit having the smallest electric charge held by these capacitors and the next smallest green (G) pixel. The above effects on the circuit are eliminated or reduced.
  • the primary colors displayed by the above pixel circuits have been described as red (R), green (G), and blue (B), but other primary colors may be used.
  • the ratio or the synthetic capacity has been described on the assumption that the organic EL element that emits red light has the highest efficiency and the organic EL element that emits blue light has the lowest efficiency.
  • the efficiency, characteristics, etc. of the organic EL elements of each color are changed due to development, the primary colors may be appropriately changed according to the contents.
  • the pixel circuit may include one that emits white (W) in addition to red (R), green (G), and blue (B).
  • white (W) in addition to red (R), green (G), and blue (B).
  • all pixel circuits include white light emitting elements, and there are many configurations in which color filters for emitting each RGB color are provided.
  • the white (W) pixel circuit since only the white (W) pixel circuit cannot be provided with the color filter, the white (W) pixel circuit has the highest light emission efficiency. Therefore, it is preferable to make the ratio in the white (W) pixel circuit smaller than the ratio in the other pixel circuits (for example, the red pixel circuit). Then, it is possible to easily set the pixel current in the pixel circuit of each color without changing the dynamic range of the data driver circuit 3.
  • the pixel circuit may include one that emits yellow (Y) in addition to red (R), green (G), and blue (B).
  • the luminous efficiency of the organic EL element for emitting yellow (Y) is similar to that of the organic EL element for emitting green (G) at present. Therefore, the ratio in the organic EL element for emitting yellow (Y) is set larger than the ratio in the pixel circuit emitting red (R) and smaller than the ratio in the pixel circuit emitting blue (R). . Then, it is possible to easily set the pixel current in the pixel circuit of each color without changing the dynamic range of the data driver circuit 3.
  • FIG. 6 is a block diagram showing a configuration of a display device according to the second embodiment of the present invention.
  • the display device 120 shown in FIG. 6 has substantially the same configuration as the display device 110 shown in FIG. 1, but the configuration of the pixel circuit 20 is different from the configuration of the pixel circuit 10 and is parallel to the n control lines Ei. Are different in that n initialization control lines Ii are provided. An initialization signal output from the gate driver circuit 2 is given to these initialization control lines Ii.
  • FIG. 7 is a circuit diagram of the pixel circuit 20.
  • the pixel circuit 20 includes first to sixth TFTs 21 to 26, an organic EL element 17, a data holding capacitor 28, and a threshold holding capacitor 29.
  • the first to sixth TFTs 21 to 26 are all p-channel transistors. Note that all of these may be configured by n-channel transistors, or may be configured to be used in some cases.
  • the pixel circuit 20 is connected to the scanning signal line Gi, the control line Ei, the initialization control line Ii, the data line Sj, the pair of power supply lines VPj, and the electrode having the common potential Vcom.
  • the source terminal of the TFT 22 is connected to the wiring that supplies the power supply potential VDD in the power supply line VPj, and the drain terminal of the TFT 22 is connected to one conduction terminal of the TFT 23.
  • the other conduction terminal of the TFT 23 is connected to the gate terminal of the TFT 22.
  • one conduction terminal of the TFT 25 is connected to the drain terminal of the TFT 22, and the other conduction terminal of the TFT 25 is connected to the anode terminal of the organic EL element 17.
  • one conduction terminal of the TFT 21 is connected to the data line Sj, and the other conduction terminal is connected to one end of the data holding capacitor 28.
  • One conduction terminal of the TFT 24 and one conduction terminal of the TFT 26 are both connected to a wiring for supplying the initialization potential Vini in the power supply line VPj.
  • One conduction terminal of the TFT 24 is connected to the other end of the data holding capacitor 28, and the other conduction terminal of the TFT 26 is connected to one end of the data holding capacitor 28.
  • the other end of the data holding capacitor 28 is connected to the gate terminal of the TFT 22.
  • the threshold holding capacitor 29 is provided between the source terminal and the gate terminal of the TFT 22.
  • a common potential Vcom is applied to the cathode terminal of the organic EL element 17.
  • the gate terminals of the TFTs 21 and 23 are connected to the scanning signal line Gi. These TFTs 21 and 23 function as write control transistors.
  • the gate terminal of the TFT 24 is connected to the initialization control line Ii.
  • the TFT 24 functions as an initialization control transistor.
  • the gate terminals of the TFTs 25 and 26 are connected to the control line Ei. These TFTs 25 and 26 function as light emission control transistors. Further, since the TFT 26 applies a fixed potential such as an initialization potential Vini (or a power supply potential VDD as will be described later) to one end of the data holding capacitor 28 during light emission, it also functions as a fixed potential supply transistor.
  • FIG. 8 is a timing chart showing a driving method of the pixel circuit 20.
  • the waveform shown in FIG. 8 is the same as the potential of the scanning signal line Gi and the control line Ei shown in FIG. 3, but the waveform showing the potential change of the initialization control line Ii is the same as that of the scanning signal line G (i ⁇ 1). It is slightly different from the waveform showing potential change.
  • the initialization control line Ii becomes active, whereby the gate terminal of the TFT 22 and the wiring that supplies the initialization potential Vini in the power supply line VPj are brought into conduction, and the initialization potential is supplied to the data holding capacitor 28.
  • Vini is written (initialization operation)
  • the initialization operation is continued at time t22. Note that the initialization potential Vini is smaller than VDD + Vth and is a voltage sufficient to turn on the TFT 22.
  • the scanning signal line Gi becomes active at the time t22 during the initialization operation, the TFTs 21 and 23 are turned on, whereby the initialization potential Vini is reliably written to the data holding capacitor 28.
  • This operation is the same as the conventional one, but in the present embodiment, an operation different from the conventional one can be performed.
  • the scanning signal line G (i ⁇ 1) is used, and the pixel of this embodiment is exactly the same as in the first embodiment (with the waveform shown in FIG. 3).
  • the circuit can be driven. This is because the pixel circuit shown in FIG. 21 is not provided with the threshold holding capacitor 29, and it is necessary to reliably write the initialization potential Vini into the data holding capacitor 28 by driving as described above. . However, in this embodiment, since the threshold holding capacitor 29 is provided, the initialization potential ini can be charged. Therefore, the initialization potential Vini can be reliably written to the data holding capacitor 28. Also in this embodiment, if driven in this way, the initialization control line Ii can be omitted, so that the configuration of the pixel circuit can be simplified and the aperture ratio can be increased.
  • the initialization control line Ii becomes inactive, so that the potential of the node B is Vdata + Vth (Vth is a threshold value of the TFT 22) when the TFT 22 is diode-connected as in the first embodiment. Voltage) and stabilize at that voltage. At this time, since the TFT 25 is turned off, no current flows through the organic EL element 17.
  • Vx ⁇ c1 / (c1 + c2) ⁇ (Vdata ⁇ Vini) + VDD + Vth (11)
  • the current flowing through the organic EL element is not affected by variations in the threshold voltage Vth, and the change in the power supply potential VDD is further improved. It is not affected by.
  • the gate potential Vx of the TFT 22 changes following the change of the power supply potential VDD, as can be seen from the above equation (11). Therefore, the light emission luminance during the light emission period decreases as the power supply potential VDD decreases, and the amount of change becomes closer as the capacitance value c1 of the data retention capacitor 28 becomes smaller than the capacitance value c2 of the threshold retention capacitor 29 (follow-up). Easier to do). As described above, the luminance difference due to the IR drop caused by the arrangement position of the pixel circuit can be greatly reduced, so that the deterioration in display quality can be sufficiently suppressed.
  • the configuration of this embodiment can further reduce the luminance difference due to the IR drop caused by the arrangement position of the pixel circuit, as compared with the case of the first embodiment. it can.
  • the circuit area of the pixel circuit can be prevented from increasing compared to the conventional case, although the threshold holding capacitor 29 is newly provided. Furthermore, an appropriate amount of current that does not become excessive can be applied to the organic EL element 17 without changing the dynamic range of the data driver circuit 3. Further, by using the (general) data driver circuit 3 having a large dynamic range, the error of the data potential can be further reduced, so that the luminance variation of the pixel caused by the output deviation in the data driver circuit 3 is suppressed. be able to. Furthermore, the organic EL element can be controlled with a smaller amount of current without changing the size of the TFT 22, and it is not necessary to change the design conditions, the manufacturing process, etc., and the degree of freedom in design can be further increased. . Furthermore, since the initialization control line Ii can be omitted by driving similarly to the case of the first embodiment, the configuration of the pixel circuit can be simplified and the aperture ratio can be increased.
  • the pixel circuit 20a shown in FIG. 9 has the same constituent elements as the pixel circuit 20, the first to sixth TFTs 21 to 26, the organic EL element 17, the data holding capacitor 28, and the threshold holding capacitor 29. Including.
  • one end of the threshold holding capacitor 29 is connected to the gate terminal of the TFT 22 as in the case shown in FIG. 7, but unlike the case shown in FIG. 7, the other end of the threshold holding capacitor 29 is connected to the power source.
  • the line VPj is connected to a wiring that provides the initialization potential Vini. If there is a fixed potential applied in addition to the initialization potential Vini, it may be used instead of the initialization potential Vini.
  • the potential cannot be held unless the other end of the threshold holding capacitor 29 is connected to a fixed potential point. Therefore, as described above, the function of the auxiliary capacitor Caux included in the pixel circuit 95 shown in FIG. 24 and connected to the scanning signal line Gi whose potential changes is different. The effect similar to that of the threshold holding capacitor 29 is not obtained by Caux.
  • the potential held in the data holding capacitor 28 during the write operation is the same as that in the second embodiment, but the potential held in the threshold holding capacitor 29 is different from that in the second embodiment.
  • (VDD + Vth ⁇ Vini) the potential held in the threshold holding capacitor 29 is different from that in the second embodiment.
  • the accumulated charge Q1 of the data holding capacitor 28 and the accumulated charge Q2 of the threshold holding capacitor 29 are expressed by the following equations (13) and (14), respectively.
  • Q1 c1 ⁇ (VDD + Vth ⁇ Vdata) (13)
  • Q2 c2 ⁇ (VDD + Vth ⁇ Vini) (14)
  • Vx ⁇ c2 / (c1 + c2) ⁇ Vini ⁇ c1 / (c1 + c2) ⁇ Vdata + Vth
  • the overdrive voltage Vov of the TFT 22 can be expressed by the following equation (16) from the above equation (15).
  • Vov ⁇ c2 / (c1 + c2) ⁇ Vini ⁇ c1 / (c1 + c2) ⁇ Vdata (16)
  • the current flowing through the organic EL element is not affected by the variation in the threshold voltage Vth, and the power supply potential VDD is further applied during writing. It is not affected by any changes. Therefore, the luminance difference due to IR drop at the time of writing can be completely eliminated. As described above, the luminance difference due to the IR drop caused by the arrangement position of the pixel circuit can be greatly reduced, so that the deterioration in display quality can be sufficiently suppressed.
  • the configuration of the second embodiment is preferable.
  • the pixel circuit 20b shown in FIG. 10 has the same constituent elements as the pixel circuit 20, the first to sixth TFTs 21 to 26, the organic EL element 17, the data holding capacitor 28, and the threshold holding capacitor 29. Including.
  • the other conduction terminal of the TFT 26 is connected to one end of the data holding capacitor 28. Unlike the second embodiment, one conduction terminal of the TFT 26 is connected. The terminal is connected to the wiring for supplying the power supply potential VDD in the power supply line VPj.
  • the potential held in the data holding capacitor 28 and the threshold holding capacitor 29 during the write operation is the same as in the case of the above formula (8) and formula (9) (in the second embodiment).
  • the voltage at one end of the data holding capacitor 18 during light emission is different as can be seen with reference to FIG. Since the total accumulated charge (Q1 + Q2) of the data holding capacitor 18 and the threshold holding capacitor 19 is the same at the time of writing and at the time of light emission, the charge is redistributed, as shown in the following equation (17), etc.
  • Vx c1 / (c1 + c2) ⁇ Vdata + (2 ⁇ c1 + c2) / (c1 + c2) ⁇ VDD + Vth (18)
  • the overdrive voltage Vov of the TFT 22 can be expressed by the following equation (19) from the above equation (18).
  • the current flowing through the organic EL element is not affected by variations in the threshold voltage Vth. It is not affected by any changes.
  • the gate potential Vx of the TFT 22 completely follows the change of the power supply potential VDD. Therefore, the light emission luminance during the light emission period is not affected at all by the change in the power supply potential VDD.
  • the luminance difference due to IR drop at the time of writing and light emission can be completely eliminated.
  • the luminance difference due to the IR drop caused by the arrangement position of the pixel circuit can be completely eliminated, so that the problem that the display quality is degraded by the IR drop can be completely eliminated.
  • FIG. 11 is a block diagram showing a configuration of a display device according to the third embodiment of the present invention.
  • the display device 130 shown in FIG. 11 has substantially the same configuration as the display device 110 shown in FIG. 1, but the configuration of the pixel circuit 30 is different from the configuration of the pixel circuit 10, and the n control lines Ei are used instead. The difference is that n sets of four control lines Eai to Edi are provided. Further, unlike the first embodiment, there is one power supply line Vpi and the power supply potential VDD is applied.
  • FIG. 12 is a circuit diagram of the pixel circuit 30.
  • the pixel circuit 30 includes first to sixth TFTs 31 to 36, an organic EL element 17, a data holding capacitor 38, and a threshold holding capacitor 39.
  • the first to sixth TFTs 31 to 36 are all n-channel transistors. Note that all of these may be configured by p-channel transistors, or may be configured to be used in some cases.
  • the pixel circuit 30 is connected to electrodes having a scanning signal line Gi, control lines Eai to Edi, a data line Sj, a power supply line VPj, and a common potential Vcom.
  • the drain terminal of the TFT 31 that is a driving transistor is connected to the power supply line VPj that supplies the power supply potential VDD via the TFT 35 on the current path.
  • the source terminal of the TFT 31 is connected to the anode terminal of the organic EL element 17 via the TFT 32 on the current path.
  • One conductive terminal of the TFT 36 is connected to the drain terminal of the TFT 31, and the other conductive terminal is connected to the gate terminal of the TFT 31. This enables diode connection of the TFT 31.
  • one conduction terminal of the TFT 34 is connected to the data line Sj, and the other conduction terminal is connected to one end of the threshold holding capacitor 39 and the source terminal of the TFT 31.
  • the other end of the threshold holding capacitor 39 is connected to the gate terminal of the TFT 31.
  • one end of the data holding capacitor 38 is connected to an electrode having a common potential Vcom through the TFT 33.
  • the electrode may be connected to a wiring that applies a potential sufficiently lower than the power supply potential VDD.
  • One end of the data holding capacitor 38 is connected to the source terminal of the TFT 31 via the TFT 32.
  • a common potential Vcom is applied to the cathode terminal of the organic EL element 17.
  • the gate terminal of the TFT 34 is connected to the scanning signal line Gi.
  • the gate terminal of the TFT 33 is connected to the control line Edi.
  • the gate terminal of the TFT 36 is connected to the control line Eai.
  • These TFTs 33, 34, and 36 function as write control transistors.
  • the TFT 33 also functions as a fixed potential supply transistor because the common potential Vcom or another fixed potential is applied to one end of the data holding capacitor 38.
  • the gate terminal of the TFT 32 is connected to the control line Eci. Further, the gate terminal of the TFT 35 is connected to the control line Ebi. These TFTs 32 and 35 function as light emission control transistors. Note that the TFT 35 is also turned on when the data potential Vdata is written, and thus functions as a write control transistor.
  • the operation of the pixel circuit 30 will be described.
  • the TFTs 33 to 36 are turned on, so that the data potential Vdata is applied to the other end of the data holding capacitor 38.
  • the organic EL element 17 does not emit light.
  • the threshold voltage Vth of the TFT 31 is acquired.
  • the potential of the gate terminal of the TFT 31 is (Vdata + Vth). Therefore, the potential (Vdata + Vth) is held in the data holding capacitor 38, and the threshold voltage Vth is held in the threshold holding capacitor 39.
  • the TFTs 32 and 35 are turned on and the TFTs 33, 34 and 36 are turned off, so that a current corresponding to the gate potential of the TFT 31 flows from the power supply line Vpi to the organic EL element 17.
  • both ends of the data holding capacitor 38 and the threshold holding capacitor 39 are connected, these two capacitors function as a holding capacity during light emission.
  • the total accumulated charge (Q1 + Q2) held in the data holding capacitor 38 and the threshold holding capacitor 39 during the writing operation is the same during writing and during light emission, as in the first or second embodiment. Therefore, charge is redistributed.
  • the overdrive voltage Vov of the TFT 31 included in the pixel circuit 30 of the present embodiment is compared with the conventional case, the configuration of the present embodiment has a power supply potential higher than that of the conventional case.
  • a change in overdrive voltage Vov due to a change in VDD can be suppressed to c1 / (c1 + c2).
  • the luminance difference due to the IR drop caused by the arrangement position of the pixel circuit can be reduced, so that the deterioration of display quality can be suppressed.
  • the circuit area of the pixel circuit can be prevented from increasing compared to the conventional case, although the threshold holding capacitor 39 is newly provided. Furthermore, an appropriate amount of current that does not become excessive can be applied to the organic EL element 17 without changing the dynamic range of the data driver circuit 3. Further, by using the (general) data driver circuit 3 having a large dynamic range, the error of the data potential can be further reduced, so that the luminance variation of the pixel caused by the output deviation in the data driver circuit 3 is suppressed. be able to. Further, the organic EL element can be controlled with a smaller amount of current without changing the size of the TFT 31, and the design flexibility and the manufacturing process do not need to be changed, so that the degree of design freedom can be further increased. .
  • FIG. 13 is a block diagram showing a configuration of a display device according to the fourth embodiment of the present invention.
  • the display device 140 shown in FIG. 13 has substantially the same configuration as the display device 110 shown in FIG. 1, but the configuration of the pixel circuit 40 is different from the configuration of the pixel circuit 10, and there is one n control line Ei.
  • the power supply control circuit 4 instead of the gate driver circuit 2 through the common control line (control trunk line) 9a.
  • there is one power supply line Vpi which is connected to the power supply control circuit 4 via one common control line (power supply trunk line) 9b, and the power supply potential VDD is Given.
  • the power supply line VPi is disposed in parallel to the scanning signal line Gi.
  • FIG. 14 is a circuit diagram of the pixel circuit 40.
  • the pixel circuit 40 includes first to third TFTs 41 to 43, an organic EL element 17, two data holding capacitors 48a and 48b, and a threshold holding capacitor 49. Yes.
  • the first to third TFTs 41 to 43 are all p-channel transistors. Note that all of these may be configured by n-channel transistors, or may be configured to be used in some cases.
  • the pixel circuit 40 is connected to an electrode having a scanning signal line Gi, a control line Ei, a data line Sj, a power supply line VPi, and a common potential Vcom.
  • One conduction terminal of the TFT 41 is connected to the data line Sj, and the other conduction terminal is connected to one end of two data holding capacitors 48a and 48b.
  • the other end of the data holding capacitor 48a is connected to the gate terminal of the TFT 42, and the other end of the data holding capacitor 48b is connected to the power supply line VPi.
  • One end of the threshold holding capacitor 49 is also connected to the power supply line VPi, and the other end is connected to the gate terminal of the TFT 42.
  • the drain terminal of the TFT 42 is connected to the power supply line VPi, and the source terminal is connected to the anode terminal of the organic EL element 17.
  • a common potential Vcom is applied to the cathode terminal of the organic EL element 17.
  • One of the conduction terminals of the TFT 43 is connected to the gate terminal of the TFT 42, and the other of the conduction terminals of the TFT 43 is connected to the source terminal of the TFT 42. By connecting in this way, the TFT 42 can be diode-connected.
  • the gate terminal of the TFT 41 is connected to the scanning signal line Gi.
  • the TFT 41 functions as a write control transistor, but also functions as an initialization control transistor because it is turned on during the initialization operation.
  • the gate terminal of the TFT 43 is connected to the control line Ei.
  • the TFT 43 functions as a light emission control transistor.
  • FIG. 15 is a timing chart showing a driving method of the pixel circuit 40.
  • the pixel circuit 40 performs initialization, threshold value detection (threshold value detection of the TFT 42), writing, and light emission once in one frame period, and is extinguished outside the light emission period.
  • the frame period is a unit period for displaying one image, may include a black insertion period, and can be set to various lengths.
  • the potentials of the scanning signal line G1 and the control line E1 are at a high level.
  • the potential of the power supply line VP1 is maintained at the first low potential VP_L1, which is substantially the same potential as the common potential Vcom.
  • the potential of the control line E1 and the scanning signal lines G1, G2,... Changes to low level (becomes active), and the potential of the power supply line VP1 is maintained at the first low potential VP_L1.
  • the first reference potential Vref1 is applied to the data line Sj.
  • the anode potential of the organic EL element 17 and the gate potential of the TFT 42 become substantially the same potential as the common potential Vcom and are initialized.
  • the first reference potential Vref1 is applied to one end of each of the two data holding capacitors 48a and 48b via the TFT 41.
  • the TFT 42 is turned on, and the charge held at the anode terminal of the organic EL element 17 is discharged toward the power supply line Vpi.
  • the potential of the anode terminal is The low potential VP_L2 is changed to 2, and the anode terminal is initialized.
  • the initialization operation including two stages is performed between time t11 and time t12.
  • the potential of the power supply line VP1 changes to the first low potential VP_L1, and the potential of the control line E1 changes to low level (becomes active).
  • the potentials of the scanning signal lines G1, G2,... Are maintained at a low level.
  • the TFT 43 is turned on in this way, the TFT 42 is in a diode connection state, a current flows from the power supply line VPi to the gate end of the TFT 42, the potential of the gate terminal rises to (VP_L1 + Vth), and the potential is maintained. .
  • the threshold voltage Vth is written and held in the threshold holding capacitor 49.
  • the TFT 41 since the TFT 41 is turned on, the first reference potential Vref1 is applied to one end of the two data holding capacitors 48a and 48b. Therefore, the gate potential of the TFT 42 fluctuates due to the data holding capacitor 48a. Actually, the parasitic capacitance of the organic EL element is relatively large enough, so that the amount of potential fluctuation is small. Such an operation is a threshold detection operation.
  • the TFT 41 is turned on.
  • a data potential Vdata indicating an image to be displayed is applied to the data line Sj.
  • the gate potential of the TFT 42 in the ON state is c1a / (c1a + c2) ⁇ Vdata, and this potential is held in the two data holding capacitors 48a and 48b.
  • the TFT 41 When the potential of the scanning signal line G1 becomes a high level at time t15, the TFT 41 is turned off, and the gate potential of the TFT 42 is kept substantially constant (VP_L1 + Vth) even if the potential of the data line Sj changes.
  • the same operation is performed in the pixel circuits arranged in the next row, and potentials including the data potential Vdata are written in all the pixel circuits.
  • the total accumulated charge (Q1 + Q2) held in the data holding capacitors 48a and 48b and the threshold holding capacitor 49 during the write operation is the same during the write operation and during the light emission as in the above embodiment.
  • the overdrive voltage Vov of the TFT 42 included in the pixel circuit 40 of the present embodiment is compared with the conventional case, in the configuration of the present embodiment, the change in the power supply potential VDD is compared with the conventional case.
  • the change in overdrive voltage Vov due to can be suppressed to c1a / (c1a + c2).
  • the luminance difference due to the IR drop caused by the arrangement position of the pixel circuit can be reduced, so that the deterioration of display quality can be suppressed.
  • the organic EL element 17 starts to emit light.
  • the high level potential is determined so that the TFT 42 operates in the saturation region in the light emission period.
  • the current I flowing through the organic EL element 17 changes according to the data potential Vdata, but does not depend on the threshold voltage Vth of the TFT 42. Therefore, even when the threshold voltage Vth varies or the threshold voltage Vth changes with time, a current corresponding to the data potential Vdata is supplied to the organic EL element 17 to cause the organic EL element 17 to emit light with a desired luminance. it can.
  • the TFT 42 is turned off after time t17. Therefore, no current flows through the organic EL element 17 and the pixel circuit 40 is turned off.
  • the pixel circuit in the first row performs initialization in a period from time t11 to time t12, performs threshold detection in a period from time t12 to time t13, and writes data in a period from time t14 to time t15.
  • the light is emitted during a period from time t17 to time t18, and is turned off during a period other than the period from time t17 to time t18.
  • the pixel circuit in the second row performs initialization in a period from time t11 to time t12 and performs threshold detection in a period from time t12 to time t13.
  • Writing is delayed by a predetermined time Ta from the circuit, and light is emitted and turned off in the same manner as the pixel circuit in the first row.
  • the pixel circuit in the i-th row performs initialization and threshold detection in the same period as the pixel circuits in the other rows, performs writing after a time Ta from the pixel circuit in the (i-1) -th row, and so on. Light is emitted and extinguished in the same period as the pixel circuits in the row.
  • the initialization period can be set to an appropriate period, typically a period longer than the selection period, the output buffer included in the power supply control circuit 4a is sufficiently driven even when the current capability is small. be able to.
  • the threshold detection period can be set to an appropriate period, typically a period longer than the selection period, threshold detection can be performed reliably, and the accuracy of threshold compensation can be improved.
  • a pixel data writing period can be sufficiently taken. Therefore, the configuration of the present invention can be easily applied to a configuration in which a writing period is short, that is, a configuration in which driving is performed at high speed, for example, a three-dimensional image display device (3D television).
  • FIG. 16 is a diagram showing a connection form of the power supply lines VPi in the display device according to the present embodiment.
  • the display device shown in FIG. 13 is provided with one trunk power supply line (common power supply line) 9b for connecting the power supply control circuit 4a and the power supply line VPi.
  • One end of the common power supply line 9b is connected to one output terminal of the power supply control circuit 4a, and all the power supply lines VPi are connected to the common power supply line 9b.
  • the common power supply line 9b is a current supply trunk, but in the present embodiment, any wiring that can connect all the power supply lines VPi to the power supply control circuit 4a in common can be used. In addition, any known configuration can be applied to the number and the connection position with the power supply line VPi.
  • FIG. 17 is a diagram illustrating the operation of the pixel circuits 40 in each row in the display device according to the present embodiment.
  • the power supply control circuit 4a applies the first low potential VP_L1 and the second low potential VP_L2 to the common power supply line 9b for a predetermined time at the beginning of one frame period. For this reason, the pixel circuits in all rows are initialized at the beginning of one frame period. Next, immediately after the initialization, the pixel circuits in all rows perform threshold detection. Subsequently, the pixel circuit in the first row is selected, and the pixel circuit in the first row performs writing. Next, the pixel circuit in the second row is selected, and the pixel circuit in the second row performs writing.
  • the pixel circuits in the third to nth rows are sequentially selected for each row, and the selected pixel circuit performs writing.
  • the pixel circuits in each row are extinguished during a period from the threshold detection to immediately before writing, and after the light is extinguished for a predetermined period that differs for each row after writing, the pixel circuits in all rows simultaneously emit light (collectively) for a certain time T1.
  • the lights are turned off simultaneously at the end of one frame period (in other words, immediately before the initialization of the next frame).
  • the leak current generated in the TFTs 42 can be made substantially the same in the pixel circuits 40 for all rows. Therefore, the amount of decrease in luminance due to the leakage current is almost the same in the pixel circuits 40 in all rows, and as a result, display unevenness can be suppressed.
  • FIG. 18 is a diagram illustrating another example of the connection form of the power supply lines VPi.
  • two common power supply lines 121 and 122 are provided to connect the power supply control circuit 4b and the power supply line VPi.
  • One ends of the common power supply lines 121 and 122 are respectively connected to two output terminals of the power supply control circuit 4b.
  • the power supply lines VP1 to VPn / 2 are connected to the common power supply line 121,
  • the pixel circuits in each row need to emit light for the same time, but unlike the case shown in FIG. 17 which is always initialized at the beginning of the frame, the light emission of the pixel circuit in the n-th row is one frame period. There is no need to complete by the end. Therefore, in the example shown in FIG. 18, the scanning speed of the pixel circuit is the same as normal, and the length of the light emission period of the pixel circuit is about 1 ⁇ 2 frame period. Therefore, it is possible to ensure a sufficiently long writing time as in the normal case.
  • the length of the light emission period may be shorter than the 1 ⁇ 2 frame period while the scanning speed of the pixel circuit is kept at a normal speed. Alternatively, the scanning speed of the pixel circuit may be made faster than usual, and the length of the light emission period may be made longer than the 1 ⁇ 2 frame period.
  • FIG. 19 is a diagram showing still another example of the connection form of the power supply line VPi.
  • This display device is provided with two common power supply lines 131 and 132 for connecting the power supply control circuit 4c and the power supply line VPi.
  • One ends of the common power supply lines 131 and 132 are respectively connected to two output terminals of the power supply control circuit 4c.
  • the odd-numbered power lines VP1, VP3,... Are connected to the common power line 131, and the even-numbered power lines VP2, VP4,.
  • This configuration can reduce the screen brightness difference. That is, in the configuration shown in FIG. 18, when the amount of current flowing through the common power supply lines 121 and 122 is greatly different, such as when the luminance is greatly different between the upper half and the lower half of the screen, a luminance difference occurs at the center of the screen. There are things to do. However, according to this configuration, the amount of current flowing through the common power supply lines 131 and 132 is almost the same in many cases, so that a luminance difference that may occur at the center of the screen can be prevented in advance.
  • the threshold holding capacitor 49 functions as a holding capacitor from writing to light emission and during the light emission period. Therefore, although the threshold holding capacitor 49 is newly provided, the circuit of the pixel circuit is provided. It is possible to prevent the area from increasing compared to the conventional case.
  • the series capacitance c12 can be freely set.
  • the capacitance value of the data holding capacitor 48b (and the threshold holding capacitor 49) can be set as appropriate. In that sense, the data holding capacitor 48b functions as an adjustment capacitor.
  • an appropriate amount of current that does not become excessive can be applied to the organic EL element 17 without changing the dynamic range of the data driver circuit 3.
  • the error of the data potential can be further reduced, so that the luminance variation of the pixel caused by the output deviation in the data driver circuit 3 is suppressed. be able to.
  • the present invention is an active matrix display device that is applied to a display device including a self-luminous display element driven by current, and is particularly suitable for a display device such as an organic EL display. .

Abstract

L'invention concerne un circuit de pixel (10) dans lequel des transistors à couches minces (TFT) (12-16) sont connectés et pilotés de manière à ce qu'un condensateur de maintien de seuil (19), ayant une valeur de capacité c1, maintienne une tension de seuil Vth d'un TFT (11) qui est un transistor d'attaque, et à ce qu'un condensateur de maintien de données (18), qui a une valeur de capacité c2, maintienne des tensions comprenant des potentiels de données Vdata indiquant une image à afficher, et lesdits TFT sont connectés de manière à ce que, durant une émission de lumière, la charge du condensateur de maintien de données (18) et du condensateur de maintien de seuil (19) soit redistribuée. Par ce moyen, le potentiel obtenu par multiplication du potentiel de données Vdata par c1/(c1+c2) est donné au potentiel de grille du TFT (11).
PCT/JP2012/077723 2011-11-02 2012-10-26 Circuit de pixel, dispositif d'affichage le comprenant et procédé de commande de circuit de pixel WO2013065596A1 (fr)

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