WO2013056249A1 - Dispositifs semi-conducteurs à architecture tridimensionnelle et procédés associés - Google Patents

Dispositifs semi-conducteurs à architecture tridimensionnelle et procédés associés Download PDF

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Publication number
WO2013056249A1
WO2013056249A1 PCT/US2012/060291 US2012060291W WO2013056249A1 WO 2013056249 A1 WO2013056249 A1 WO 2013056249A1 US 2012060291 W US2012060291 W US 2012060291W WO 2013056249 A1 WO2013056249 A1 WO 2013056249A1
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Prior art keywords
layer
substrate
processed surface
bonding
semiconductor layer
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PCT/US2012/060291
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English (en)
Inventor
Homayoon Haddad
Leonard Forbes
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Sionyx, Inc.
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Priority claimed from US13/621,737 external-priority patent/US20130168803A1/en
Application filed by Sionyx, Inc. filed Critical Sionyx, Inc.
Publication of WO2013056249A1 publication Critical patent/WO2013056249A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
    • G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
    • G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
    • G01J5/20—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14649—Infrared imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration

Definitions

  • CMOS APS Active pixel sensors
  • CDS true correlated double sampling
  • CMOS APS imagers have utilized backside illuminated (BSI) technology.
  • BSI imager technology includes a semiconductor wafer bonded to a permanent carrier on the front side and then thinned from the backside. Passivation layers, anti-reflecting layers, color filters and micro-lens can be positioned on the backside, and the resulting device can be backside illuminated.
  • Through-Silicon Vias (TSV) can be used to provide electrical connections from the front side to backside output pads.
  • BSI CMOS APS imagers are becoming useful technology for many types of visible imagers in cell phones and digital cameras.
  • electromagnetic radiation can be present across a broad wavelength range, including visible range wavelengths (approximately 350nm to 800nm) and non-visible wavelengths (longer than about 800nm or shorter than 350 nm).
  • the infrared spectrum is often described as including a near infrared portion of the spectrum including wavelengths of approximately 800 to 1300nm, a short wave infrared portion of the spectrum including wavelengths of approximately 1300nm to 3 micrometers, and a mid to long range wave infrared (or thermal infrared) portion of the spectrum including wavelengths greater than about 3 micrometers up to about 20 micrometers.
  • These are generally and collectively referred to herein as infrared portions of the electromagnetic spectrum unless otherwise noted.
  • such silicon based detectors are mostly transparent to infrared light. While other mostly opaque materials (e.g. InGaAs) can be used to detect infrared electromagnetic radiation having wavelengths greater that about 1000nm, silicon is still commonly used because it is relatively cheap to manufacture and can be used to detect wavelengths in the visible spectrum (i.e. visible light, 350 nm– 800 nm). Traditional silicon materials require substantial path lengths and absorption depths to detect photons having wavelengths longer than
  • a method for making a semiconductor device can include forming a device layer on a front side of a semiconductor layer that is substantially defect free, bonding a carrier substrate to the device layer, processing the
  • the method can also include removing the carrier substrate from the semiconductor layer to expose the device layer.
  • CMOS circuitry imaging devices
  • RF circuitry RF circuitry
  • photovoltaic circuitry and other device layer components including combinations thereof.
  • forming the device layer further includes forming optoelectronic circuitry on the front side of the semiconductor layer.
  • processing the semiconductor layer on the back side can include implant and/or laser anneal conditions to reduce surface defects.
  • processing the semiconductor layer on the back side can include thinning the semiconductor layer from the back side to expose the device layer.
  • texturing can be performed on the device layer, the processed surface, or both the device layer and the processed surface.
  • at least one of forming the device layer and processing the semiconductor layer includes forming a textured region thereon.
  • forming the textured region includes texturing with a short pulse duration laser to create surface features.
  • Non-limiting examples can include semiconductive junctions, vias, photodetectors, bolometers, image sensors, CMOS integrated circuits, trenches, surface textures, and the like, including combinations thereof.
  • Such a device can include a substantially defect-free
  • a carrier substrate is oxide bonded to the device layer of the semiconductor layer;
  • FIG. 1 is a flow diagram of a method for making a 3D architecture device in accordance with an aspect of the present disclosure.
  • FIG. 2a shows a cross sectional view of various steps in the manufacture of a 3D architecture device in accordance with another aspect of the present disclosure.
  • FIG. 2b shows a cross sectional view of various steps in the manufacture of a 3D architecture device in accordance with another aspect of the present disclosure.
  • FIG. 2c shows a cross sectional view of various steps in the manufacture of a 3D architecture device in accordance with another aspect of the present disclosure.
  • FIG. 2d shows a cross sectional view of various steps in the manufacture of a 3D architecture device in accordance with another aspect of the present disclosure.
  • FIG. 2e shows a cross sectional view of various steps in the manufacture of a 3D architecture device in accordance with another aspect of the present disclosure.
  • FIG. 3a shows a cross sectional view of various steps in the manufacture of a 3D architecture device in accordance with another aspect of the present disclosure.
  • FIG. 3b shows a cross sectional view of various steps in the manufacture of a 3D architecture device in accordance with another aspect of the present disclosure.
  • FIG. 3c shows a cross sectional view of various steps in the manufacture of a 3D architecture device in accordance with another aspect of the present disclosure.
  • FIG. 3d shows a cross sectional view of various steps in the manufacture of a 3D architecture device in accordance with another aspect of the present disclosure.
  • FIG. 3e shows a cross sectional view of various steps in the manufacture of a 3D architecture device in accordance with another aspect of the present disclosure.
  • FIG. 4 shows a 3D architecture bonding technique in accordance with another aspect of the present disclosure.
  • FIG. 5a is a cross-sectional schematic view of a CMOS APS with far infrared bolometer detector attached to the backside according to one embodiment of the present disclosure.
  • FIG. 5b is a cross-sectional schematic view of a CMOS APS with far infrared bolometer detector attached to a bonded backside carrier wafer according to one embodiment of the present disclosure.
  • FIG. 6a is a cross-sectional schematic view of an infrared detecting photodiode on a bonded wafer attached to the backside of a CMOS APS imager according to one embodiment of the present disclosure.
  • FIG. 6b is a cross-sectional schematic view of an integrated circuit, processor or digital signal processing circuit on a bonded wafer attached to the backside of a CMOS APS imager according to yet another embodiment of the present disclosure.
  • FIG. 7a is a cross-sectional schematic view of a thin film compound semiconductor layer with photo-detecting devices attached to the backside of a CMOS APS imager according to another embodiment of the present disclosure.
  • FIG. 7b is a cross-sectional schematic view of a compound semiconductor photo-detecting device attached to the backside of a CMOS APS imager wired and connected to through-silicon vias according to one embodiment of the present disclosure.
  • FIG. 8a is a cross-sectional schematic view of an infrared imaging array with bolometer type photodetectors and integrated circuits attached to the backside of a CMOS APS imager and wired and connected by through-silicon vias according to one embodiment of the present disclosure.
  • FIG. 8b is a cross-sectional view of an infrared imaging array with photodiode detectors and integrated circuits attached to the backside of a CMOS APS imager and wired and connected by through-silicon vias according to one embodiment of the present disclosure.
  • the term“defect free” refers to a material having no observable crystal lattice defects. Additionally, the term“substantially defect free” refers to a material that is at least about 95% free of crystal lattice defects.
  • the terms“disordered surface” and“textured surface” can be used interchangeably, and refer to a surface having a topology with nano- to micron- sized surface variations formed by the irradiation of laser pulses or other texturing methods such as chemical etching as described herein. While the characteristics of such a surface can be variable depending on the materials and techniques employed, in one aspect such a surface can be several hundred nanometers thick and made up of nanocrystallites (e.g. from about 10 to about 50 nanometers) and nanopores. In another aspect, such a surface can include micron-sized structures (e.g. about 2 ⁇ m to about 60 ⁇ m).
  • the surface can include nano-sized and/or micron-sized structures from about 5 nm and about 500 ⁇ m.
  • surface modifying and“surface modification” refer to the altering of a surface of a semiconductor material to form a textured surface using a variety of surface modification techniques. Non-limiting examples of such techniques include plasma etching, reactive ion etching, porous silicon etching, lasing, chemical etching (e.g. anisotropic etching, isotropic etching), nanoimprinting, material deposition, selective epitaxial growth, and the like, including combinations thereof.
  • surface modification can include processes using primarily laser radiation or laser radiation in combination with a dopant, whereby the laser radiation facilitates the incorporation of the dopant into a surface of the semiconductor material. Accordingly, in one aspect surface modification includes doping of a substrate such as a semiconductor material.
  • target region refers to an area of a substrate that is intended to be doped or surface modified.
  • the target region of the substrate can vary as the surface modifying process progresses. For example, after a first target region is doped or surface modified, a second target region may be selected on the same substrate.
  • backside illumination refers to a device architecture design whereby electromagnetic radiation is incident on a surface of a semiconductor material that is opposite a surface containing the device circuitry. In other words, electromagnetic radiation is incident upon and passes through a semiconductor material prior to contacting the device circuitry.
  • front side illumination refers to a device architecture design whereby electromagnetic radiation is incident on a surface of a semiconductor material containing the device circuitry.
  • a lens can be used to focus incident light onto an active absorbing region of the device while reducing the amount of light that impinges the device circuitry.
  • the term“substantially” refers to the complete or nearly complete extent or degree of an action, characteristic, property, state, structure, item, or result.
  • an object that is“substantially” enclosed would mean that the object is either completely enclosed or nearly completely enclosed.
  • the term“about” is used to provide flexibility to a numerical range endpoint by providing that a given value may be“a little above” or“a little below” the endpoint.
  • the present disclosure provides methods for forming novel semiconductor devices having 3D architectures with low defect densities. Such methods can be utilized to produce devices, circuits, imagers, sensors, and the like, in defect-free or substantially defect-free thin 3D semiconductor structures. This can be accomplished by first forming devices, circuits, imagers, sensors, and the like (i.e. device layer) on a front side surface of a semiconductor layer, such as, for example, standard wafers used in conventional integrated circuit technology having few if any defects.
  • the device layer of the semiconductor layer can be bonded to a carrier substrate to provide support while the backside of the semiconductor layer opposite the device layer is thinned. In some cases, processing in addition to thinning and polishing can be performed on the backside.
  • a smart substrate can then be bonded to the processed surface of the backside of the semiconductor layer.
  • such an architecture can include multiple components or devices arranged in a vertical or 3D architectural configuration that can have distinct or integrated functionality.
  • the carrier substrate can be removed to expose the device layer.
  • all the backside thinning and processing steps, including bonding can be performed at low temperatures. In this manner, the thin semiconductor (e.g. silicon) layer remains defect free or substantially defect free during all subsequent processing steps, at least with respect to heat-induced defects.
  • defect free or substantially defect free semiconductor substrates, layers, devices, circuits, sensors, and the like can be coupled to smart substrates after the fabrication of these device layers.
  • the resulting structure experiences low temperature processes after this point that will not introduce significant defects therein. Because such devices are formed on defect free semiconductor layers, the final devices are also defect free, unlike devices made from conventional process techniques where the starting substrate has a high number of defects and efforts are made to anneal out and reduce or remove these defects before forming the device layer.
  • a method for making a semiconductor device can include steps, as is shown in FIG. 1, 102 forming a device layer on a front side of a semiconductor layer that is substantially defect free, 104 bonding a carrier substrate to the device layer, 106 processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and 108 bonding a smart substrate to the processed surface.
  • the method can further include removing the carrier substrate from the semiconductor layer to expose the device layer.
  • FIGs. 2a-e show various steps in the manufacture of a 3D semiconductor structure according to one aspect of the present disclosure.
  • device layer 202 is formed on the front side of a semiconductor layer 204.
  • the device layer 202 can include any form of device layer that can be incorporated into a semiconductor device, and any such device is considered to be within the present scope.
  • Non-limiting examples of device layer components can include CMOS circuitry, imaging devices, RF circuitry, photovoltaic circuitry, and the like, including combinations thereof.
  • the device layer can include optoelectronic circuitry. It is also contemplated that non-optoelectronic device layer circuitry, either in addition to or instead of optoelectronic circuitry, is within the present scope. As such, the present methods and devices should not be limited to optoelectronics.
  • the semiconductor layer can be made from a variety of materials, it can be beneficial for the semiconductor to be defect free or substantially defect free. Such a defect free semiconductor layer thus allows the formation of a defect free or substantially defect free device layer thereupon. Provided defects are not introduced into the device layer from additional processing steps, the device layer can be maintained in the original defect free state. As one example, in some aspects the semiconductor device is not heated to a temperature of greater than 450 oC following the formation of the device layer.
  • Non-limiting examples of such semiconductor materials can include group IV materials, compounds and alloys comprised of materials from groups II and VI, compounds and alloys comprised of materials from groups III and V, and combinations thereof. More specifically, exemplary group IV materials can include silicon, carbon (e.g. diamond), germanium, and combinations thereof. Various exemplary combinations of group IV materials can include silicon carbide (SiC) and silicon germanium (SiGe).
  • Exemplary combinations of group II-VI materials can include cadmium selenide (CdSe), cadmium sulfide (CdS), cadmium telluride (CdTe), zinc oxide (ZnO), zinc selenide (ZnSe), zinc sulfide (ZnS), zinc telluride (ZnTe), cadmium zinc telluride (CdZnTe, CZT), mercury cadmium telluride (HgCdTe), mercury zinc telluride (HgZnTe), mercury zinc selenide (HgZnSe), and combinations thereof.
  • CdSe cadmium selenide
  • CdS cadmium sulfide
  • CdTe cadmium telluride
  • ZnO zinc oxide
  • ZnSe zinc selenide
  • ZnS zinc sulfide
  • ZnTe zinc telluride
  • CdZnTe cadmium zinc telluride
  • Exemplary combinations of group III-V materials can include aluminum antimonide (AlSb), aluminum arsenide (AlAs), aluminum nitride (AlN), aluminum phosphide (AlP), boron nitride (BN), boron phosphide (BP), boron arsenide (BAs), gallium antimonide (GaSb), gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium antimonide (InSb), indium arsenide (InAs), indium nitride (InN), indium phosphide (InP), aluminum gallium arsenide (AlGaAs, AlxGa1-xAs), indium gallium arsenide (InGaAs, InxGa1-xAs), indium gallium phosphide (InGaP), aluminum indium arsenide (AlInA
  • AlGaAsN indium gallium arsenide nitride
  • InAlAsN indium aluminum arsenide nitride
  • GaAsSbN gallium arsenide antimonide nitride
  • GaInNAsSb gallium indium nitride arsenide antimonide
  • GaInAsSbP gallium indium arsenide antimonide phosphide
  • the semiconductor layer can include silicon.
  • the semiconductor layer can be a silicon wafer.
  • the silicon wafer/material can be monocrystalline, multicrystalline, microcrystalline, amorphous, and the like.
  • the silicon material can be a monocrystalline silicon wafer.
  • a carrier substrate (or handle) 206 can be bonded to the device layer 202. Note that in FIG. 2b, the device has been flipped or rotated 180° as compared to FIG. 2a.
  • the carrier substrate can include a variety of materials.
  • the carrier substrate 206 is a temporary substrate to be removed at a later processing step, the material can be chosen based on its usefulness as a temporary substrate. It can also be beneficial for the carrier substrate 206 to be capable of adequately holding the device layer 202 during processing of the semiconductor layer 204 and yet be capable of easy removal.
  • Non-limiting examples of potential carrier substrate materials can include glass, ceramics, semiconductors, and the like, including combinations thereof.
  • any such bonding technique useful in making a 3D semiconductor device is considered to be within the present scope.
  • One such process can include a liquid UV curable adhesive process that utilizes solids acrylic adhesives designed for temporary bonding of semiconductor wafers to a glass carrier substrate. This technique provides a rigid, uniform support surface that minimizes stress on the wafer during the subsequent processing steps, resulting in less warpage, cracking, edge chipping and higher yields.
  • Other exemplary methods can include bonding and detaching a temporary carrier used for handling a wafer during the fabrication of semiconductor devices, includes bonding the wafer onto the carrier through an adhesive layer.
  • bonding at low or room temperature can include surface cleaning and activation by cleaning or etching, followed by polishing the surfaces to be bonded to a high degree of smoothness and planarity. Reactive ion etching or wet etching is used to slightly etch the surfaces being bonded. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
  • the bonding technique can be a low temperature technique (e.g. below 450o C).
  • the bonding can occur at room temperature or in other words, the bonding does not require a heat source.
  • the device layer 202 and the carrier substrate 206 can be bonded at room temperature and a thermal treatment can be applied to consolidate the bonding interface, provided the thermal treatment is performed at a temperature that does not exceed 450o C.
  • the parameters of the consolidation annealing can be controlled to provide a bonding energy high enough for the heterostructure to withstand post- bonding conventional process steps (e.g. CMOS processing).
  • the bonding technique can include various oxide-oxide, oxide-silicon, or metal-metal bonding methods.
  • Some bonding processes can achieve a bond strength of at least 1 J/m 2 at room temperature. For even higher bond strengths, a bake cycle at 100° - 300° C can be utilized. Some of these oxide-oxide bonding process have been described in U.S. Patent 7,871,898 and U.S. Patent 5,843,832, which are incorporated by reference in their entireties.
  • One method of direct bonding a silicon wafer onto an insulated wafer in order to obtain a 3D semiconductor device is similar to the bonding of two silicon wafers together, with the exception that before bonding a thin thermal oxide layer (e.g. about 1 micron) is grown on one of the wafers.
  • Release of the carrier substrate from the device layer can vary depending on the attachment process.
  • Acrylic adhesives for example, can be released by exposure to UV light.
  • More permanent bonds, such as silicon-oxide bonds may require the removal of the carrier substrate by mechanical grinding and/or chemical etching to expose the device layer.
  • the semiconductor layer 204 (FIG. 2b) is at least partially removed (e.g. polished and thinned) to expose the backside of the device layer 202 or, in other words, to form a processed surface 208 at the backside of the device layer 202.
  • the resulting structure is comprised of the first substrate 206 coupled to the thin device layer 202 which, due to careful processing conditions, can remain at least substantially defect-free.
  • any necessary or beneficial backside processing can be performed on the processed surface 208 of the device layer 202.
  • beneficial backside processing can include, without limitation, texturing the back surface of device layer 202, shallow or deep trench formation, via formation, annealing, implantation, and the like.
  • the exposed surface of the device layer 202 (i.e. the processed surface 208)can be textured, while in other aspects the buried surface of the device layer 202 opposite the processed surface can be textured at a point in the manufacturing process when that surface is available for processing. It is also contemplated that backside circuitry can be formed at the backside surface of the device layer 202 prior to bonding the second substrate to the processed surface 208.
  • backside processing can also include exposing contact pads associated with the device layer.
  • opening the backside of the device layer i.e. at the processed surface
  • electrical contacts can be exposed for bonding and providing electrical contact to subsequent structures, such as the smart substrate (see below).
  • Opening the backside can occur by any known technique, including the thinning and processing methods described. In one specific aspect, opening the backside can be accomplished via plasma etching.
  • any technique useful for removing the semiconductor layer 204 is considered to be within the present scope. It can be beneficial, as has been described, for the processing temperature to not exceed 450o C. Non-limiting examples can include ion implantation/separation processes, laser ablation, laser splitting, CMP processing, dry etching, wet etching and the like, including combinations thereof.
  • the semiconductor layer is removed by CMP techniques to expose the device layer 202.
  • a smart substrate 210 is bonded to the backside of the device layer 202 (i.e. the processed surface 208), as is shown in FIG. 2d. Note that in FIG. 2d, the device has been flipped or rotated by 180° compared to FIG. 2c. Any bonding technique can be utilized to bond the smart substrate 210 to the device layer 202, as was described for the bonding of the first substrate 206 to the device layer 202 (FIG. 2b), provided the process is compatible with both structures.
  • the smart substrate can include a variety of devices, structures, and/or materials and material configurations, depending on the desired design and subsequent properties of the 3D device.
  • a smart substrate can include a
  • a smart substrate can include at least one semiconductive junction. Additional non-limiting examples of smart substrates can include photodetectors, vias, bolometers, image sensors, CMOS circuitry, trench isolation, surface textures, and the like, including combinations thereof.
  • a smart substrate can include a depression or space that will form a cavity when bonded to the device layer.
  • the material utilized for the smart substrate can be selected to provide desired benefits to, or beneficial interactions with, the device layer. It is thus contemplated that, in one aspect, the smart substrate can be at least functionally integrated with the device layer. In other aspects, the smart substrate can function independently of the device layer.
  • the smart substrate can be electrically coupled to, and thus can function in conjunction with, the device layer. Such electrical coupling can be accomplished by vias formed through the processed surface that connect the device layer to the smart substrate.
  • the carrier substrate 206 FIG. 2d
  • the resulting 3D semiconductor structure shown in FIG. 2e includes a smart substrate 210 bonded to the device layer 202 (or in some cases a remaining portion of the semiconductor layer 204). Because of the at least substantially defect free formation of the device layer 202 on the semiconductor layer 204, and the subsequent low temperature processing of the 3D device, the device layer 202 remains defect free or substantially defect free in the final 3D device. It should be noted that the scope of the present disclosure includes the 3D device shown in FIG. 2e, as well as the intermediate structures produced during the formation of the 3D device.
  • portions of the device layer can be selectively removed to expose a given structure, such as an electrical contact, a light incident surface, or some other structure that can benefit from such exposure. Such removal can be accomplished by any known technique, as has been described.
  • FIGs. 3a-e show various steps in the manufacture of a 3D device using an embedded oxide layer to facilitate thinning.
  • device layer 302 can formed on the front side of a semiconductor layer 304.
  • the device layer 302 can include any form of device layer that can be incorporated into a 3D device, as has been described.
  • a thin oxide layer 303 can be embedded within the semiconductor layer 304, either before or after the formation of the device layer 304.
  • the thin oxide layer can be of any shape and thickness useful for the particular device design. In some aspects, however, the thin oxide layer can be from about 4000 angstroms to about 5000 angstroms thick. It is also noted that commercial SOI substrates can be used that are manufactured having such a thin oxide layer embedded.
  • a carrier substrate 306 can be bonded to the device layer 302. Note that in FIG. 3b, the device has been flipped or rotated 180° as compared to FIG. 3a.
  • the carrier substrate can include a variety of materials. Because in most aspects the carrier substrate 306 is a temporary substrate to be removed at a later processing step, the material can be chosen based on its usefulness as a temporary substrate.
  • the semiconductor layer 304 (FIG. 3b) is at least partially removed to form a processed surface 308 near the backside of the device layer 302.
  • the semiconductor layer 304 can be removed at least to the thin oxide layer 303.
  • at least a portion of the thin oxide layer can remain, while in other aspects the thin oxide layer can be completely removed from the
  • This material can be removed by any known method, such as, for example, laser splitting, polishing, thinning, etching, lapping or grinding, CMP processing, or a combination thereof.
  • the resulting structure is comprised of the carrier substrate 306 coupled to the device layer 302.
  • a portion of the semiconductor layer 304 can remain coupled to the device layer 302 opposite the carrier substrate 306.
  • This portion of the semiconductor layer 304 can thus be a crystallographically high quality material, and in some aspects can be lightly doped, passivated and/or laser annealed at low temperatures (e.g. below about 450° C).
  • any necessary or beneficial backside processing can be performed on the device layer 302.
  • processing the semiconductor layer on the backside can include implant and/or laser anneal conditions to reduce surface defects. It is also contemplated that backside circuitry can be formed at the backside surface of the device layer 302 prior to subsequent bonding.
  • a smart substrate 310 can be bonded to the semiconductor layer 304 at backside of the device layer 302, as is shown in FIG. 3d. Note that in FIG. 3d, the device has been flipped or rotated 180° compared to FIG. 3c. Any bonding technique can be utilized to bond the smart substrate 310 to the semiconductor layer 304, as has been described.
  • the carrier substrate 306 (FIG. 3d) can be removed from the device layer 302 following bonding of the smart substrate 310.
  • the resulting 3D semiconductor structure shown in FIG. 3e includes a smart substrate 310 bonded to the semiconductor layer 304, which is bonded to the device layer 302. Because of the at least substantially defect free formation of the device layer 302 on the semiconductor layer 304, and the subsequent low temperature processing of the device, the device layer 302 remains defect free or substantially defect free in the final 3D substrate or 3D device.
  • the scope of the present disclosure includes the 3D substrate shown in FIG. 3e, as well as the intermediate structures produced during the formation of the 3D substrate.
  • a 3D device can be constructed having multiple photo imagers.
  • such an optoelectronic device is capable of detecting multiple wavelengths in the range of from about 200 nm to about 20 microns due to the presence of multiple photo imagers.
  • such a device can include a first photosensitive imager capable of detecting electromagnetic radiation having a first wavelength or range of wavelengths, and a second photosensitive imager capable of detecting electromagnetic radiation having a second wavelength or range of wavelengths.
  • the first range of wavelengths and the second range of wavelengths are mutually exclusive.
  • the first photosensitive imager capable of detecting electromagnetic radiation having a first wavelength or range of wavelengths
  • the photosensitive device detects visible light, while the second photosensitive device detects infrared light.
  • the first and second imagers can be any combination of front side illuminated and/or backside illuminated, depending on the design of the device.
  • the second photosensitive device can be an infrared imager capable of detecting light having a wavelength in the range of about 600nm to about 20 ⁇ m. It is noted that, while the present discussion relates to a first and second photosensitive imager, any number of imagers can be incorporated into a 3D architecture. As such, the present scope extends to any number of imagers and additional components in the device.
  • the first and the second photosensitive imagers can be 3D bonded to each other according to aspects of the present disclosure.
  • a device architecture can utilize a more simplified optic for directing incident light on the first and second photosensitive imagers.
  • the simplified optic can utilize at least a portion of the same optical path to direct electromagnetic radiation having a first wavelength on to the first photosensitive imager and electromagnetic radiation having a second wavelength on to the second photosensitive imager.
  • the electromagnetic radiation having a second wavelength will have a longer wavelength that electromagnetic radiation having a first wavelength, and will thus pass through the first photosensitive imager.
  • CMOS APS complementary metal-oxide-semiconductor
  • the smart substrate can provide both structural support and functionality that goes beyond mere support to the device. It is noted that the level of accuracy of alignment between the smart support and the device layer can depend on the complexity of the smart support, the device layer, and the degree of integration between the two. Alignment techniques utilizing fiducial markers can be employed to facilitate a proper level of integration between structures.
  • At least a portion of the 3D structured semiconductor device can include a textured region.
  • a textured region can be applied to any of the materials of the device that can be beneficial.
  • at least a portion of the device layer, the processed surface of the backside of the device layer, the smart substrate, and the like can include a textured region.
  • the textured region can be positioned on a light incident surface.
  • the texture region can be positioned on a surface that is opposite a light incident surface.
  • textured regions can be positioned at both light incident surfaces as well as surfaces that are opposite light incident surfaces.
  • textured regions can be positioned along isolation features such as trench isolation in order to direct electromagnetic radiation back into the device.
  • the textured region can function to diffuse electromagnetic radiation, to redirect electromagnetic radiation, and/or to absorb electromagnetic radiation, thus increasing the efficiency of the device.
  • the textured region can include surface features to thus increase the effective absorption length of the semiconductor.
  • Such surface features can be micron-sized and/or nano-sized, and can be any shape or configurations. Non-limiting examples of such shapes and configurations include cones, pillars, pyramids, micolenses, quantum dots, inverted features, gratings, protrusions, and the like, including combinations thereof.
  • factors such as manipulating the feature sizes, dimensions, material type, dopant profiles, texture location, etc. can allow the diffusing region to be tunable for a specific wavelength or wavelength range.
  • tuning the device can allow specific wavelengths or ranges of wavelengths to be absorbed.
  • Textured regions can also allow an optoelectronic device to experience multiple passes of incident electromagnetic radiation within the device, particularly at longer wavelengths (i.e. infrared). Such internal reflection increases the effective absorption length to be greater than the thickness of the semiconductor. This increase in absorption length increases the quantum efficiency of the device, leading to an improved signal to noise ratio.
  • the textured region can be formed by various techniques, including plasma etching, reactive ion etching, porous silicon etching, lasing, chemical etching (e.g. anisotropic etching, isotropic etching), nanoimprinting, material deposition, selective epitaxial growth, and the like.
  • One effective method of producing a textured region is through laser processing.
  • Such laser processing allows discrete locations of the passivation region or other substrate to be textured.
  • a variety of techniques of laser processing to form a textured region are contemplated, and any technique capable of forming such a region should be considered to be within the present scope.
  • Laser treatment or processing can allow, among other things, enhanced absorption properties and thus increased electromagnetic radiation focusing and detection.
  • the laser treated region can be associated with the surface nearest the impinging electromagnetic radiation or, in some cases, the laser treated surface can be associated with a surface opposite in relation to impinging electromagnetic radiation, thereby allowing the radiation to pass through the semiconductor before it hits the laser treated region.
  • a target region of a semiconductor material can be irradiated with laser radiation to form a textured region.
  • Examples of such processing have been described in further detail in U.S. Patents 7,057,256, 7,354,792 and 7,442,629, which are incorporated herein by reference in their entireties. Briefly, a surface of a substrate material is irradiated with laser radiation to form a textured or surface modified region.
  • the type of laser radiation used to surface modify a material can vary depending on the material and the intended modification. Any laser radiation known in the art can be used with the devices and methods of the present disclosure. There are a number of laser characteristics, however, that can affect the surface modification process and/or the resulting product including, but not limited to the wavelength of the laser radiation, pulse width, pulse fluence, pulse frequency, polarization, laser propagation direction relative to the semiconductor material, etc.
  • a laser can be configured to provide pulsatile lasing of a material.
  • a short-pulsed laser is one capable of producing femtosecond, picosecond and/or nanosecond pulse durations.
  • Laser pulses can have a central wavelength in a range of about from about 10 nm to about 8 ⁇ m, and more specifically from about 200 nm to about 1200 nm.
  • the pulse width of the laser radiation can be in a range of from about tens of femtoseconds to about hundreds of nanoseconds.
  • laser pulse widths can be in the range of from about 50 femtoseconds to about 50 picoseconds.
  • laser pulse widths can be in the range of from about 50 picoseconds to 100 nanoseconds.
  • laser pulse widths are in the range of from about 50 to 500 femtoseconds.
  • laser pulse widths are in the range of from about 10 femtoseconds to about 500 picoseconds.
  • the number of laser pulses irradiating a target region can be in a range of from about 1 to about 2000. In one aspect, the number of laser pulses irradiating a target region can be from about 2 to about 1000. Further, the repetition rate or frequency of the pulses can be selected to be in a range of from about 10 Hz to about 10 ⁇ Hz, or in a range of from about 1 kHz to about 1 MHz, or in a range from about 10 Hz to about 1 kHz. Moreover, the fluence of each laser pulse can be in a range of from about 1 kJ/m 2 to about 20 kJ/m 2 , or in a range of from about 3 kJ/m 2 to about 8 kJ/m 2 .
  • a structure having a thin or ultra- thin silicon device and circuit wafer with front side oxide and wiring 404 is provided.
  • the structure is bonded to a smart substrate 408.
  • the front side bonding of the completed integrated circuit wafer 406 can be by an oxide-oxide bond, an oxide- silicon bond, an oxide-adhesive bond, a metal-metal bond, or the like 401, to the carrier substrate 402.
  • an oxide 403 can be utilized for bonding.
  • the backside of the integrated circuit wafer 406 can be thinned and an oxide 405 can be deposited thereupon for use in an oxide-oxide bond or a silicon-oxide bond 407 to the smart substrate 408. During these steps there is minimal damage to the device and circuit wafer that under goes only low temperature heat cycles.
  • At least one isolation feature can be formed at a beneficial location with respect to the 3D structure.
  • an isolation feature can be positioned between adjacent photosensitive imager devices to provide optical and/or electrical isolation therebetween.
  • the isolation feature can be a shallow or deep trench isolation feature. Isolation features can also be positioned/configured to reflect incident electromagnetic radiation back into the device to facilitate absorption. As has also been described, in some examples regions of the isolation feature can include a textured region to further facilitate reflection and absorption, thereby increasing the effective absorption length of the device.
  • the sides of isolation features can be doped. In some aspects, a doped isolation feature can form an electrical surface field, similar to an electrical back surface field. The isolation features can be formed at any point in the manufacturing process when the appropriate material layer is exposed for processing.
  • CMOS active pixel visible 502 and near infrared imagers 503 and a bolometer type thermal or far infrared imager 532 can be integrated into a single silicon integrated circuit wafer or die, 500.
  • FIG. 5a shows a first cavity 550 and second cavity 560 etched within the device 500.
  • the first cavity 550 is etched in to the backside (or a first photosensitive imaging device) to a predetermined depth 530, and the second cavity 560 is etched to have larger dimensions than the first cavity 550.
  • the cavities are used to at least partially enclose a microbolometer 532.
  • the microbolometer 532 is supported by pillars 513 formed within the cavity 550 on the back of the CMOS imager wafer 504.
  • the imager pixels 502 can be isolated from each other by an isolation region 517 and the two wafers (device wafer 504, smart substrate 570) can be joined by silicon-silicon bonding.
  • the imager pixels 502, 503 can be conventional structures capable of detecting electromagnetic radiation having a first wavelength (i.e. visible light) and can include a p-type region 510, an n-type diode region 516, a p-type pinning layer 514, and transfer device and other transistors 511. The details of the transfer device and readout circuit, or four transistor sense circuit are not shown in FIG. 5a.
  • Electromagnetic radiation 509 is incident on a light incident surface 515.
  • a thermal or far infrared microbolometer 532 is positioned on the back of a thinned silicon wafer and connected to the associated readout circuits, in this case a direct injection sensor circuit is coupled by through silicon vias 527.
  • the read out integrated circuit 512 on the front surface is connected to wiring by vias 528.
  • Electromagnetic radiation 509 is incident at the light incident surface 515 of the pixels. Short wavelength visible radiation will be strongly absorbed near the surface of the pinned photodiode including the P+ surface layer, a buried N-type diode, on the p-type silicon substrate.
  • the microbolometer type thermal or far infrared detector 532 has been placed and spaced away from the backside of the silicon substrate 510, allowing for a proper design of the thermal time constant of the microbolometer type detector whose temperature is increased by radiation from the scene in the field of view.
  • FIG. 5b shows 501 CMOS active pixel visible and near infrared imagers with microbolometer type thermal or far infrared detector 532 on a smart substrate 570.
  • the smart substrate 570 is bonded to a silicon CMOS APS wafer 510.
  • a cavity 560 can be formed in the smart wafer 570 to coincide with the position of the microbolometer.
  • the metal wiring on the back of the CMOS APS imager wafer 580 and wiring on the front of the smart wafer 582 form the metal to metal bond joining the wafers. All other number designations in FIG.5b have the same designations and meanings as those in FIG. 5a.
  • FIG. 6a illustrates a system 600 including a photodiode or other infrared detector 626 on a smart substrate 670 that can be bonded to a metal containing material 580 over an insulator layer 631 on the backside of the CMOS APS imager.
  • Metallization 680 can be on the smart substrate 670.
  • Wiring 691 in dielectric interconnection insulation 602 is connected to front side metallization 680 on the smart substrate 670 by vias 690.
  • FIG. 6b illustrates a system 601 including an integrated circuit 627 on a smart substrate 670 that can be bonded to a metal containing material 580 over an insulator layer 631 on the backside of the CMOS APS imager.
  • Metallization 680 can be on the smart substrate 670.
  • Wiring 691 in dielectric interconnection insulation 602 is connected to front side metallization 680 on the smart substrate 670 by vias 690.
  • Components that have the same numbers as used in previous figures have the same description.
  • FIG. 7a shows an additional dielectric layer 631 can be placed on the back of the CMOS APS imager.
  • the combined system 700 consists of a CMOS APS imager with a thin film of III-V semiconductor layers 710 containing photodiodes or other detectors bonded by layer 731 containing of low temperature metal-metal bonds.
  • Semiconductor layers 710 can be epitaxial liftoff layers fabricated by the techniques known to those skilled in the art. Known methods can allow for layers to be formed at higher temperatures but later bonded to silicon wafers at low temperatures. Post pattern processing can then be used to define the individual photodetectors. Components that have the same numbers as used in previous figures have the same description.
  • III-V semiconductor photodetectors bonded on to the back of a CMOS APS imager form an integrated detection system 701.
  • the photodetectors are shown here as p-n junction diodes with doped layers 714 and 715. These layers can be patterned by photolithography and electrically connected to the through silicon vias (TSVs) 527 in the imager by wiring and vias 711 and 712. All of this patterning and wiring can be low temperature processes compatible with the already formed CMOS APS imagers. Components that have the same numbers as used in previous figures have the same description.
  • CMOS APS imager having at least one via per pixel and TSVs to individually connect each pixel on the bonded side of the carrier wafer to front side circuitry on the silicon CMOS APS imager is provided.
  • This aspect allows for the use of fewer TSVs.
  • FIG. 8a-b shows two embodiments where a smart substrate 870 includes photodetectors, integrated circuitry 850 and TSVs at the edges of the arrays on the smart substrate 870. Components that have the same numbers as used in previous figures have the same description.
  • FIG. 8a shows one aspect of an electromagnetic sensing system 800 including a bolometer type imaging array bonded to the back of a CMOS visible imager.
  • the smart substrate 870 has integrated bolometer detectors 632 and circuitry 850.
  • the integrated circuitry 850 allows address decoding and signal processing on the smart substrate of the far infrared image signals, which are transferred to the front side of the CMOS visible imager wafer at the edges of the array by vias 527.
  • an electromagnetic sensing system 801 including a narrow bandgap compound semiconductor infrared detecting photodiode type imaging array bonded to the back of a CMOS visible imager.
  • the smart substrate 870 has integrated photodetectors 626 and circuitry 850.
  • the integrated circuitry 850 allows address decoding and signal processing on the carrier wafer of the infrared image signals, which are transferred to the front side of the CMOS visible imager wafer at the edges of the array by vias 527.
  • the smart substrate 870 might, for example, be an InGaAs near infrared imaging array on an InP substrate.
  • Integrated circuit devices and transistors can be fabricated in the InP substrate and smart substrate 870. Components that have the same numbers as used in previous figures have the same description.

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Abstract

La présente invention concerne des dispositifs semi-conducteurs à architecture tridimensionnelle (3D) et des procédés de fabrication de ces dispositifs. Par exemple, selon un aspect, un procédé de fabrication d'un dispositif semi-conducteur peut comprendre les étapes consistant à former une couche du dispositif sur une surface avant d'une couche semi-conductrice sensiblement sans défaut, coller un substrat de support à la couche du dispositif, traiter la couche semi-conductrice sur une surface arrière en regard de la couche du dispositif de façon à former une surface traitée et coller un substrat évolué à la surface traitée. Selon certains aspects, le procédé peut également comprendre une étape consistant à retirer le substrat de support de la couche semi-conductrice de façon à exposer la couche du dispositif.
PCT/US2012/060291 2011-10-13 2012-10-15 Dispositifs semi-conducteurs à architecture tridimensionnelle et procédés associés WO2013056249A1 (fr)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109801934A (zh) * 2018-12-13 2019-05-24 深圳市灵明光子科技有限公司 一种图像传感单元及其制作方法、图像传感器
US10741399B2 (en) 2004-09-24 2020-08-11 President And Fellows Of Harvard College Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate
CN112992693A (zh) * 2019-12-17 2021-06-18 美光科技公司 在激光释放下使用永久键的重构晶片到晶片键合

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001339057A (ja) * 2000-05-30 2001-12-07 Mitsumasa Koyanagi ３次元画像処理装置の製造方法
KR20060052278A (ko) * 2004-10-28 2006-05-19 소니 가부시끼 가이샤 고체 촬상소자와 그 제조 방법 및 반도체 장치와 그 제조방법
US7235812B2 (en) * 2004-09-13 2007-06-26 International Business Machines Corporation Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques
KR100825808B1 (ko) * 2007-02-26 2008-04-29 삼성전자주식회사 후면 조명 구조의 이미지 센서 및 그 이미지 센서 제조방법
JP2010278472A (ja) * 2010-08-30 2010-12-09 Sony Corp 固体撮像装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001339057A (ja) * 2000-05-30 2001-12-07 Mitsumasa Koyanagi ３次元画像処理装置の製造方法
US7235812B2 (en) * 2004-09-13 2007-06-26 International Business Machines Corporation Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques
KR20060052278A (ko) * 2004-10-28 2006-05-19 소니 가부시끼 가이샤 고체 촬상소자와 그 제조 방법 및 반도체 장치와 그 제조방법
KR100825808B1 (ko) * 2007-02-26 2008-04-29 삼성전자주식회사 후면 조명 구조의 이미지 센서 및 그 이미지 센서 제조방법
JP2010278472A (ja) * 2010-08-30 2010-12-09 Sony Corp 固体撮像装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10741399B2 (en) 2004-09-24 2020-08-11 President And Fellows Of Harvard College Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate
CN109801934A (zh) * 2018-12-13 2019-05-24 深圳市灵明光子科技有限公司 一种图像传感单元及其制作方法、图像传感器
CN112992693A (zh) * 2019-12-17 2021-06-18 美光科技公司 在激光释放下使用永久键的重构晶片到晶片键合

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