WO2013046513A1 - Signal processing circuit for touch sensor and touch sensor - Google Patents

Signal processing circuit for touch sensor and touch sensor Download PDF

Info

Publication number
WO2013046513A1
WO2013046513A1 PCT/JP2012/004610 JP2012004610W WO2013046513A1 WO 2013046513 A1 WO2013046513 A1 WO 2013046513A1 JP 2012004610 W JP2012004610 W JP 2012004610W WO 2013046513 A1 WO2013046513 A1 WO 2013046513A1
Authority
WO
WIPO (PCT)
Prior art keywords
lines
drive
circuit
detection
terminal
Prior art date
Application number
PCT/JP2012/004610
Other languages
French (fr)
Japanese (ja)
Inventor
直人 島高
英明 笹原
Original Assignee
旭化成エレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 旭化成エレクトロニクス株式会社 filed Critical 旭化成エレクトロニクス株式会社
Priority to JP2013535836A priority Critical patent/JP5715703B2/en
Priority to TW101133379A priority patent/TW201316236A/en
Publication of WO2013046513A1 publication Critical patent/WO2013046513A1/en

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0445Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416Control or interface arrangements specially adapted for digitisers
    • G06F3/0418Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Definitions

  • the present invention relates to a signal processing circuit of a touch sensor including a capacitive touch panel.
  • Patent Document 1 Conventionally, inventions described in Patent Document 1 and Patent Document 2 are known as inventions related to touch sensors including this type of touch panel.
  • the invention of Patent Document 1 includes a plurality of first electrodes extending in a first direction, a plurality of second electrodes extending in a second direction different from the first direction, a drive circuit, a detection circuit, And a coordinate position calculation circuit.
  • the drive circuit sequentially selects two first electrodes from the plurality of first electrodes, supplies a voltage having a higher potential than the reference voltage to one of the two selected first electrodes, and supplies the other to the reference Supply voltage.
  • the detection circuit includes a capacitance A between the selected second electrode and the first electrode supplied with the high potential voltage, and the selected second electrode and the first electrode supplied with the reference voltage. A capacitance difference (A ⁇ B) with the capacitance B between the two is detected. Further, the coordinate position calculation circuit calculates the touch position of the observer on the touch panel based on the selected positions of the first electrode and the second electrode and the capacitance difference (AB).
  • Patent Document 2 is a signal processing circuit for a touch sensor that detects a touch position on a touch panel, and includes a drive circuit, a multiplexer, two reference capacitors, and a charge amplifier. .
  • the drive circuit selects two drive lines from a plurality of drive lines extending in one direction on the substrate, and supplies an AC drive voltage to the selected drive lines.
  • the multiplexer selects two sense lines from a plurality of sense lines on the substrate extending so as to intersect with the plurality of drive lines.
  • the charge amplifier uses a differential amplifier, and has capacitance values A1 and A2 between two sense lines selected by the multiplexer and two drive lines selected by the drive circuit, and two reference capacitances. An output voltage corresponding to the difference between the values B1 and B2 is output.
  • the touch position is detected based on the output voltage output from the charge amplifier.
  • Patent Document 1 it is possible to cancel a parasitic capacitance and detect a small inter-electrode capacitance, and to realize a high-resolution touch sensor with a large number of electrodes.
  • noise generated when a finger touches the touch panel cannot be reduced (suppressed).
  • Patent Document 2 since differential amplification is performed by the charge amplifier, noise generated when a finger touches the touch panel can be reduced.
  • an output is not output when an object to be detected such as a finger comes just between the two electrodes, and it cannot be distinguished from a non-touch time.
  • an object of the present invention is to provide a signal processing circuit for a touch sensor that employs new signal processing with respect to the signal processing of the touch sensor. Another object of the present invention relates to signal processing of a touch sensor, which can reduce noise generated when a finger touches the touch panel and can improve S / N. It is to provide a signal processing circuit of a sensor.
  • One embodiment of the present invention is a touch sensor including a touch panel including a plurality of first lines and a plurality of second lines arranged so as to intersect the plurality of first lines via an insulating layer.
  • a signal processing circuit having a first drive terminal and a second drive terminal, a first detection terminal and a second detection terminal, and an output terminal, wherein the first drive terminal and the second drive terminal
  • the difference between the first capacitance connected between one detection terminal and the second capacitance connected between the second drive terminal and the first detection terminal is expressed as a first difference.
  • the capacitance difference is obtained as a third capacitance connected between the first drive terminal and the second detection terminal, and is connected between the second drive terminal and the second detection terminal.
  • the difference from the fourth capacitance is obtained as the second capacitance difference, and the first capacitance difference and the second capacitance difference are obtained.
  • a capacitance measuring circuit that converts a difference from the quantity difference into a predetermined signal and outputs the selected signal, and one or more lines are selected as a first drive line group from the plurality of first lines, or the first In addition to one drive line group, zero or more lines different from the first drive line group are selected as a second drive line group, and the first drive line group is connected to the first drive terminal.
  • Capacitance calculation circuits for calculating the respective capacitances may be provided.
  • One or more lines are selected as the first drive line group from the plurality of first lines, the selected first drive line group is connected to the first drive terminal, and the first drive line group is selected.
  • a first offset adjusting capacitor having a predetermined capacitance value is connected between the second drive terminal and the first detection terminal, and the second drive terminal and the second detection terminal are connected in advance.
  • a second offset adjustment capacitor having a predetermined capacitance value may be connected.
  • the calculation of the capacitance is performed based on the output signal of the capacitance measuring circuit and the conversion matrix, and the capacitance at each intersection of the selected drive line and each selected detection line is calculated.
  • a circuit may be provided.
  • the transformation matrix may be a Hadamard transformation matrix.
  • the total number of lines belonging to the group may be n.
  • a capacity calculation circuit for calculating the capacity may be provided.
  • the transformation matrix may be a Hadamard transformation matrix.
  • the combination of the drive pattern and the detection pattern is (m ⁇ n), and the total number of lines belonging to the selected first and second drive line groups is m according to each drive pattern and detection pattern.
  • the total number of lines belonging to the selected first and second detection lines may be n.
  • the selection circuit changes, for each of the plurality of drive patterns, a line connected to the first drive terminal and a line connected to the second drive terminal, and the first drive terminal and The line connected to the first detection terminal and the line connected to the second detection terminal may be changed according to the change of the line connected to the second drive terminal.
  • the selection circuit changes the connection of the line selected as the line connected to the first drive terminal to the first drive terminal to the connection to the first detection terminal, and The connection of the line selected as the line connected to the second drive terminal to the connection to the second detection terminal is changed to the connection to the second detection terminal, and the line selected as the line connected to the first detection terminal is changed.
  • the connection to the first detection terminal is changed to the connection to the first drive terminal, and the connection to the second detection terminal of the line selected as the line to be connected to the second detection terminal is changed to the second.
  • the connection to the drive terminal may be changed.
  • the transformation matrix uses a first transformation matrix and a second transformation matrix, and any one of the first transformation matrix and the second transformation matrix is the plurality of first transformation matrices.
  • the first transformation matrix is predetermined based on the transformation matrix and the second transformation matrix and the size of the first transformation matrix is equal to or larger than the number of the plurality of first lines
  • the first transformation matrix A third transformation matrix excluding a part of the row vector or column vector is used as the first transformation matrix, and the size of the second transformation matrix is larger than the number of the plurality of second lines.
  • the row vector of the second transformation matrix Alternatively, a fourth transformation matrix excluding a part of a column vector is used as the second transformation matrix, and the capacity calculation unit performs each transposition of the first transformation matrix and the second transformation matrix. Matrixes or their respective generalized inverses may be used.
  • the above configuration may further include a touch position detection circuit that detects a touch position on the touch panel based on each capacitance calculated by the capacitance calculation circuit.
  • the transformation matrix uses a transformation matrix having a size equal to or larger than the number of the plurality of first lines or the plurality of second lines, and the plurality of detection patterns are row vectors of the transformation matrix.
  • the number of rows or the number of columns is predetermined based on a matrix in which the number of the first lines or the plurality of second lines is matched, and the capacitance calculation circuit includes It may use a transpose of the matrix or a generalized inverse matrix.
  • the capacitance calculation circuit may process the output signal of the capacitance measurement circuit as 0 when the detection pattern is a predetermined detection pattern among the plurality of detection patterns. In the above configuration, the capacitance calculation circuit may process the output signal of the capacitance measurement circuit as 0 when a predetermined detection pattern and drive pattern among the plurality of detection patterns and drive patterns.
  • Another aspect of the present invention includes a touch panel including a plurality of first lines and a plurality of second lines arranged so as to intersect the plurality of first lines via an insulating layer.
  • a sensor signal processing circuit having a first drive terminal and a second drive terminal, a detection terminal, and an output terminal, the first drive terminal being connected between the first drive terminal and the detection terminal
  • a capacitance measuring circuit that converts a difference between the first capacitance and the second capacitance connected between the second drive terminal and the detection terminal into a predetermined signal and outputs the predetermined signal;
  • Each time one drive pattern is selected from among a plurality of drive patterns determined according to a certain transformation matrix, one of the plurality of first lines is selected according to the selected drive pattern. Select these lines as the first drive line group.
  • a selection circuit that connects a detection line group to the detection terminal, each predetermined signal detected by the capacitance measurement circuit, and the conversion matrix are used to perform an operation, and the selected drive line and each selected detection
  • a signal processing circuit for a touch sensor comprising: a capacitance calculation circuit that calculates a capacitance at each intersection with the line.
  • the transformation matrix may be a Hadamard transformation matrix.
  • the total number of lines belonging to the group may be n.
  • the above configuration may further include a touch position detection circuit that detects a touch position on the touch panel based on each capacitance calculated by the capacitance calculation circuit.
  • the transformation matrix uses a transformation matrix having a size equal to or larger than the number of the plurality of first lines or the plurality of second lines, and the plurality of detection patterns are row vectors of the transformation matrix.
  • the number of rows or the number of columns is predetermined based on a matrix in which the number of the first lines or the plurality of second lines is matched, and the capacitance calculation circuit includes It may use a transpose of the matrix or a generalized inverse matrix.
  • the capacitance calculation circuit may process the output signal of the capacitance measurement circuit as 0 when the drive pattern is a predetermined drive pattern among the plurality of drive patterns.
  • Another aspect of the present invention is a touch sensor comprising the touch sensor signal processing circuit according to any one of the above aspects.
  • a touch panel including a plurality of first lines and a plurality of second lines arranged so as to intersect the plurality of first lines via an insulating layer, and outputs a driving voltage.
  • a driving circuit having a first output terminal and a second output terminal, a first voltage corresponding to the input voltage of the first input terminal, and a second voltage corresponding to the input voltage of the second input terminal;
  • a voltage detection circuit that detects a differential voltage of the first circuit, a selective connection between the plurality of first lines and a first output terminal or a second output terminal of the drive circuit, and the plurality of second lines.
  • a signal processing method of a touch sensor including a selection circuit that performs selective connection between a line and a first input terminal or a second input terminal of the voltage detection circuit, wherein the computer determines in advance Multiple patterns defined according to a certain transformation matrix One pattern is selected, and one or more lines are selected as a first drive line group from the plurality of first lines according to the selected pattern, or the first drive is selected. In addition to the line group, zero or more lines different from the first drive line group are selected as the second drive line group, and the first drive line group is connected to the first output terminal of the drive circuit.
  • One or more lines are selected as a first detection line group, zero or more lines different from the first detection line group are selected as a second detection line group, and the first detection line group is selected as the first detection line group.
  • the plurality of first lines and the plurality of second lines are divided into the first drive line group and the second drive line group for each of the plurality of patterns.
  • the plurality of first lines and the plurality of second lines are changed to the first detection line group and the second step in response to the change in the first step.
  • the selection as the second detection line group may be changed.
  • the voltage detection is performed by connecting the selected first drive line group to the first output terminal of the drive circuit.
  • the connection is changed to the connection to the first input terminal of the circuit, and the connection of the selected second drive line group to the second output terminal of the drive circuit is connected to the second input terminal of the voltage detection circuit.
  • the connection of the selected first detection line group to the first input terminal of the voltage detection circuit is changed to the connection to the first output terminal of the drive circuit,
  • the connection of the selected second detection line group to the second input terminal of the voltage detection circuit may be changed to the connection to the second output terminal of the drive circuit.
  • the transformation matrix uses a transformation matrix having a size equal to or larger than the number of the plurality of first lines or the plurality of second lines
  • the plurality of patterns include a row vector of the transformation matrix or Excluding a part of the column vector, the number of rows or the number of columns is determined in advance based on a matrix in which the number of the plurality of first lines or the plurality of second lines is matched, and the first step and the second step
  • the plurality of predetermined detection patterns may be used, and in the process of the fourth step, a transposed matrix or a generalized inverse matrix of the matrix may be used.
  • the transformation matrix uses a first transformation matrix and a second transformation matrix, and any one of the first transformation matrix and the second transformation matrix is the plurality of first transformation matrices.
  • the first transformation matrix is predetermined based on the matrix and the second transformation matrix and the size of the first transformation matrix is equal to or larger than the number of the plurality of first lines
  • a third transformation matrix excluding a part of a row vector or column vector is used as the first transformation matrix
  • the size of the second transformation matrix is larger than the number of the plurality of second lines.
  • a row vector of the second transformation matrix or A fourth transformation matrix excluding a part of the column vector is used as the second transformation matrix in advance, and in each process of the first step and the second step, the first transformation matrix and the second transformation matrix A plurality of patterns defined by a transformation matrix are used, and the transposition matrix of each of the first transformation matrix and the second transformation matrix or their respective generalized inverse matrix is used in the processing of the fourth step. It's okay.
  • the transformation matrix may be a Hadamard transformation matrix.
  • Another aspect of the present invention is a touch sensor signal processing program that causes a computer to execute each step in the touch sensor signal processing method described in the above aspect.
  • a signal processing circuit for a touch sensor that employs a new signal processing for the signal processing of the touch sensor. Further, according to the present invention, regarding signal processing of the touch panel, noise generated when a finger touches the touch panel can be reduced, and S / N can be improved.
  • FIG. 5 is a diagram illustrating the timing of operations in states 1 to 4 of the drive circuit and the voltage detection circuit, and the on / off states of the switches at that time.
  • FIG. 6 is a diagram summarizing the relationship between the operation of states 1 to 4 of the drive circuit and the voltage detection circuit and the on / off states of the corresponding switches. It is explanatory drawing explaining operation
  • FIG. 4 is a diagram showing detection patterns 1 to 4 according to the first embodiment and the connection relationship between the corresponding drive circuit and voltage detection circuit and each line.
  • FIG. 6 is a diagram illustrating detection patterns 5 to 8 according to the first embodiment and a connection relationship between the corresponding drive circuit and voltage detection circuit and each line. It is a block diagram which shows the structure of the touch sensor to which 2nd Embodiment of this invention is applied.
  • FIG. 10 is a diagram showing detection patterns 1 to 4 according to the second embodiment and the connection relationship between the corresponding drive circuit and voltage detection circuit and each line.
  • FIG. 10 is a diagram illustrating detection patterns 5 to 8 according to the second embodiment and a connection relationship between the corresponding drive circuit and voltage detection circuit and each line. It is a figure explaining the modification of 2nd Embodiment.
  • It is a block diagram which shows the structure of the touch sensor to which 3rd Embodiment of this invention is applied.
  • It is a circuit diagram which shows the specific structure of the electrostatic capacitance circuit of 3rd Embodiment.
  • FIG. 10 is a diagram showing detection patterns 1 to 4 according to the second embodiment and the connection relationship between the corresponding drive circuit and voltage detection circuit and each line.
  • FIG. 10 is a diagram illustrating detection patterns 5 to 8 according to the second embodiment and a connection relationship between the corresponding drive circuit and voltage detection circuit and each line. It is a figure explaining the modification of 2nd Embodiment.
  • It is a block
  • FIG. 10 is a diagram showing drive patterns 1 to 4 according to the third embodiment and the connection relationship between the corresponding drive circuit and voltage detection circuit and each line.
  • FIG. 10 is a diagram illustrating drive patterns 5 to 8 according to the third embodiment and the connection relationship between the corresponding drive circuit and voltage detection circuit and each line. It is a block diagram which shows the structure of the touch sensor to which 4th Embodiment of this invention is applied. It is a figure which shows the connection relationship of four lines among the eight conversion patterns of the 1st of 4th Embodiment, the drive circuit corresponding to it, and a voltage detection circuit, and each line.
  • FIG. 1 is a block diagram showing a configuration of a touch sensor to which the first embodiment of the present invention is applied.
  • the touch sensor to which the first embodiment is applied includes a touch panel 1, a selection circuit 2, a drive circuit 3, a voltage detection circuit 4, an A / D conversion circuit 5, and a capacitance calculation circuit. 6, a touch position detection circuit 7, a control circuit 8, an address generation circuit 9, a memory 10, and a latch 11.
  • the touch panel 1 is formed of a substrate (not shown) made of glass or the like, and, for example, eight X lines X1 to X8 are arranged on the substrate at predetermined intervals in the X direction.
  • a substrate made of glass or the like
  • eight Y lines Y1 to Y8 are arranged at predetermined intervals in the Y direction so as to intersect the X lines X1 to X8 via an insulating layer. For this reason, the X lines X1 to X8 and the Y lines Y1 to Y8 are insulated from each other via an insulating layer and capacitively coupled.
  • the selection circuit 2 selects, for example, two of the Y lines Y1 to Y8 of the touch panel 1 as drive lines, and connects the selected two drive lines to the drive circuit 3.
  • the selection circuit 2 selects at least two of the X lines X1 to X8 of the touch panel 1 as detection lines, connects a part thereof to one input terminal (detection terminal) of the voltage detection circuit 4, and The rest is connected to the other input terminal (detection terminal) of the voltage detection circuit 4.
  • the drive circuit 3 generates a voltage whose voltage value (amplitude) changes as will be described later, and supplies the generated voltage as a drive voltage to the two lines selected as the drive lines by the selection circuit 2.
  • the voltage detection circuit 4 when the selection circuit 2 selects at least two of the X lines X1 to X8 as detection lines, and the selected detection lines are connected to the two input terminals, the voltage detection circuit 4 corresponds to the connection. The voltage is output as the output voltage.
  • the A / D conversion circuit 5 A / D converts the output voltage of the voltage detection circuit 4 and outputs the A / D converted voltage to the capacitance calculation circuit 6.
  • the capacity calculation circuit 6 performs an operation based on each output voltage of the voltage detection circuit 4 A / D converted by the A / D conversion circuit 5 and a predetermined conversion matrix.
  • the capacitance at each intersection of one drive line selected by the selection circuit 2 and each detection line selected by the selection circuit 2, the other drive line selected by the selection circuit 2, and the selection circuit 2 The capacitances of the differences from the capacitances at the intersections with the respective detection lines selected in (1) are calculated.
  • the touch position detection circuit 7 detects the touch position of the touch panel 1 based on each capacitance calculated by the capacitance calculation circuit 6.
  • the control circuit 8 controls the driving circuit 3, the voltage detection circuit 4, the address generation circuit 9, and the latch 11 as described later.
  • the address generation circuit 9 generates an address for reading setting data for controlling the operation of the selection circuit 2 stored in the memory 10 based on an instruction from the control circuit 8.
  • data for controlling on / off of a switch described later of the selection circuit 2 according to the detection procedure is stored in advance.
  • the latch 11 temporarily stores setting data read from the memory 10 when on / off control of a later-described switch of the selection circuit 2 is performed.
  • the selection circuit 2 includes switch units 21-1 to 21-8, switch units 22-1 to 22-8, decoders 23-1 to 23-8, decoders 24-1 to 24-8, and a connection line 25. To 29. However, in FIG. 2, the switch units 21-5 to 21-8, the switch units 22-5 to 22-8, the decoders 23-5 to 23-8, and the decoders 24-5 to 24-8 are omitted.
  • the switch units 21-1 to 21-8 connect the X lines X1 to X8 to any one of the voltage detection circuit 4, the drive circuit 3, and the ground voltage VSS via the connection lines 25 to 29. It is.
  • the switch units 22-1 to 22-8 connect the Y lines Y1 to Y8 to any one of the voltage detection circuit 4, the drive circuit 3, and the ground voltage VSS via the connection lines 25 to 29. It is.
  • each of the switch units 21-1 to 21-8 and the switch units 22-1 to 22-8 includes five switches SW11 to SW15.
  • the switch SW11 is used to connect the input terminal 44 of the voltage detection circuit 4 to one of the X lines X1 to X8 and the Y lines Y1 to Y8.
  • the switch SW12 is used to connect the input terminal 45 of the voltage detection circuit 4 to one of the X lines X1 to X8 and the Y lines Y1 to Y8.
  • the switch SW13 is used to connect the output terminal 33 of the drive circuit 3 to one of the X lines X1 to X8 and the Y lines Y1 to Y8.
  • the switch SW14 is used to connect the output terminal 34 of the drive circuit 3 to one of the X lines X1 to X8 and the Y lines Y1 to Y8.
  • the switch SW15 is used to connect one of the X lines X1 to X8 and the Y lines Y1 to Y8 to the ground voltage VSS.
  • the decoders 23-1 to 23-8 perform on / off control of the switches SW11 to SW15 included in each of the switch units 21-1 to 21-8 according to the output data from the latch 11.
  • the decoders 24-1 to 24-8 perform on / off control of the switches SW11 to SW15 included in each of the switch units 22-1 to 22-8 according to the output data from the latch 11.
  • the drive circuit 3 includes a first drive circuit 31, a second drive circuit 32, and two output terminals 33 and 34.
  • the first drive circuit 31 connects the switch SW1 and the switch SW2 in series, applies a high-potential power supply voltage VDD (for example, 3.3V) to one end of the switch SW1, and applies a low-potential power supply voltage to one end of the switch SW2.
  • VDD high-potential power supply voltage
  • VSS ground voltage
  • the power supply voltage VDD and the power supply voltage VSS are selectively output from the output terminal 33 by performing on / off control of the switches SW1 and SW2.
  • the second drive circuit 32 connects the switch SW3 and the switch SW4 in series, applies the power supply voltage VDD to one end of the switch SW3, and applies the power supply voltage VSS to one end of the switch SW4. Then, the power supply voltage VDD and the power supply voltage VSS are selectively output from the output terminal 34 by performing on / off control of the switches SW3 and SW4.
  • the voltage detection circuit 4 includes an integration circuit 41 that integrates an input voltage described later, an integration circuit 42 that integrates an input voltage described later, an output voltage of the integration circuit 41, and an output voltage of the integration circuit 42. And a subtracting circuit 43 for calculating the difference between the two and two input terminals 44 and 45.
  • the integration circuit 41 includes an operational amplifier OP1, an integration capacitor Cf, and a switch SW6.
  • the input voltage is input to the inverting input terminal ( ⁇ ) of the operational amplifier OP1, and the voltage VCOM (VDD / 2) is applied to the non-inverting input terminal (+) of the operational amplifier OP1.
  • a parallel circuit of an integrating capacitor Cf and a switch SW6 is connected between the inverting input terminal and the output terminal of the operational amplifier OP1.
  • the integration circuit 42 includes an operational amplifier OP2, an integration capacitor Cf, and a switch SW5.
  • the input voltage is input to the inverting input terminal of the operational amplifier OP2, and the voltage VCOM (VDD / 2) is applied to the non-inverting input terminal of the operational amplifier OP2. Further, a parallel circuit of an integrating capacitor Cf and a switch SW5 is connected between the inverting input terminal and the output terminal of the operational amplifier OP2. As shown in FIG. 4, the subtraction circuit 43 includes an operational amplifier OP3 and four resistors R1 to R4.
  • the output of the integrating circuit 42 is supplied to the inverting input terminal of the operational amplifier OP3 via the resistor R2, and the output of the integrating circuit 41 is supplied to the non-inverting input terminal of the operational amplifier OP3 via the resistor R1.
  • the non-inverting input terminal of the operational amplifier OP3 is connected to the voltage VCOM (VDD / 2) through the resistor R3.
  • a resistor R4 is connected as a feedback resistor between the inverting input terminal and the output terminal of the operational amplifier OP3.
  • the drive circuit 3 and the voltage detection circuit 4 constitute a capacitance measurement circuit. As shown in FIG. 5, the driving circuit 3 and the voltage detection circuit 4 repeat the operation of the “state 1” operation (charging operation) and the “state 2” operation (charge-voltage conversion operation) as one operation. .
  • “state 1” the switches SW1 and SW4 of the drive circuit 3 are turned on, SW2 and SW3 are turned off, and the switches SW5 and SW6 of the voltage detection circuit 4 are turned on.
  • state 2 the switches SW1 and SW4 of the drive circuit 3 are turned off, SW2 and SW3 are turned on, and the switches SW5 and SW6 of the voltage detection circuit 4 are turned off.
  • the drive circuit 3 and the voltage detection circuit 4 may perform the operations of “state 1” to “state 4” as one operation and repeat this operation.
  • the switches SW1 to SW6 are turned on / off in the same manner as the first operation.
  • the switches SW1 and SW4 of the drive circuit 3 are turned off, SW2 and SW3 are turned on, and the switches SW5 and SW6 of the voltage detection circuit 4 are turned on.
  • the switches SW1 and SW4 of the drive circuit 3 are turned on, SW2 and SW3 are turned off, and the switches SW5 and SW6 of the voltage detection circuit 4 are turned off.
  • FIG. 7 shows a summary of the operations of “state 1” to “state 4” and the on / off states of the switches SW1 to SW6 corresponding thereto.
  • the drive circuit 3 can apply voltages having different polarities to the same drive line, and the voltage detection circuit 4 performs two measurements. Can be performed (see FIG. 8). By taking the difference between the two measurements, there is an effect of removing low frequency noise.
  • FIG. 8 shows a case where the Y lines Y1 and Y2 of the touch panel 1 are connected to the drive circuit 3, and the X lines X1 and X2 of the touch panel 1 are connected to the voltage detection circuit 4, and the X lines X1 and X2 and the Y line Y1 are connected.
  • Y2 are capacitances formed at the intersections of Y2 and C2. Then, the drive circuit 3 and the voltage detection circuit 4 perform “state 1” and “state 2” operations as shown in FIG.
  • the switches SW1 and SW4 of the drive circuit 3 are turned on, SW2 and SW3 are turned off, the switches SW5 and SW6 of the voltage detection circuit 4 are turned on, and the on / off states of the switches SW1 to SW6 are shown in FIG. As shown.
  • the drive circuit 3 applies a high-potential power supply voltage VDD (for example, 3.3 V) to the Y line Y2, and applies a low-potential power supply voltage VSS (for example, 0 V) to the Y line Y1.
  • VDD high-potential power supply voltage
  • VSS for example, 0 V
  • the output voltage Vout of the voltage detection circuit 4 is expressed by the following equation (1C).
  • Vout VCOM + ⁇ (C1-C2-C3 + C4) / Cf ⁇ ⁇ VDD ... (1C)
  • the output voltage Vout of the voltage detection circuit 4 is A / D converted at a predetermined timing within the period of “state 2”.
  • the selection circuit 2 selects two predetermined lines as drive lines among the Y lines Y1 to Y8 of the touch panel 1 in accordance with a predetermined drive pattern.
  • Y lines Y 1 and Y 2 are selected as drive lines, and the selected Y lines Y 1 and Y 2 are connected to the drive circuit 3.
  • the selection circuit 2 selects the X lines X1 to X1 of the touch panel 1 according to the selected detection pattern.
  • a part of X8 is connected to one input terminal of the voltage detection circuit 4, and the remainder of the X lines X1 to X8 is connected to the other input terminal of the voltage detection circuit 4.
  • FIGS. 9A to 9D and FIGS. 10E to 10H show eight detection patterns 1 to 8 determined according to the Hadamard transform matrix and X lines X1 to X8 corresponding to these detection patterns.
  • the voltage detection circuit 4 are connected.
  • X lines X1 to X8 are connected to one input terminal of voltage detection circuit 4, and the other input terminal of voltage detection circuit 4 is connected to VCOM.
  • the X lines X1, X3, X5, and X7 are connected to one input terminal of the voltage detection circuit 4, and the X lines X2, X4, X6, and X8 are connected.
  • the other input terminal of the voltage detection circuit 4 is connected.
  • reference numerals C1 to C8 are capacitances formed at the intersections of the Y line Y2 and the X lines X1 to X8.
  • Reference numerals C9 to C16 are Y line Y1 and Capacitance formed at each intersection with the X lines X1 to X8.
  • the output voltage D1 of the voltage detection circuit 4 is as follows.
  • the drive circuit 3 and the voltage detection circuit 4 perform the operations of “state 1” and “state 2” shown in FIG. A corresponding potential difference is detected, and this detected voltage is output as an output voltage.
  • the calculation process in which the voltage detection circuit 4 detects the eight potential differences according to the detection patterns 1 to 8 can be expressed by the following equation (2). Note that VCOM and VDD / Cf in the expression (1D) are not related to capacitance calculation and touch coordinate detection, and are omitted for simplification.
  • D1 to D8 are output voltages (detection voltages) of the voltage detection circuit 4 obtained according to the eight detection patterns 1 to 8.
  • the transformation matrix on the right side is a Hadamard transformation matrix.
  • C1 to C8 are capacitances between the Y line Y2 and the X lines X1 to X8.
  • C9 to C16 are capacitances between the Y line Y1 and the X lines X1 to X8.
  • Each of the eight rows of the Hadamard transform matrix corresponds to the eight detection patterns 1 to 8 described above. Further, 1 and ⁇ 1 in each row correspond to the connection state between the X lines X1 to X8 of each detection pattern and the voltage detection circuit 4.
  • the output voltages D1 to D8 of the voltage detection circuit 4 are each A / D converted by the A / D conversion circuit 5 at a predetermined timing of the operation of “state 2” in FIG.
  • the A / D converted output voltages D1 to D8 are sequentially stored in the capacitance calculation circuit 6.
  • the capacitance calculation circuit 6 performs the capacitance difference (C1-C9), (C2) based on the stored output voltages D1 to D8 and the Hadamard transformation matrix that is the transformation matrix. -C10)... (C8-C16) are calculated.
  • the arithmetic processing performed by the capacity calculation circuit 6 can be expressed by the following equation (3).
  • the touch position detection circuit 7 detects the position of the touch panel 1 based on the capacitance values (C1-C9), (C2-C10)... (C8-C16) calculated by the capacitance calculation circuit 6.
  • the above operation is an example in which the touch position on the touch panel 1 is detected by a one-dimensional operation. However, when the touch position on the touch panel 1 is detected by a two-dimensional operation, the above operation is repeated. become.
  • the selection circuit 2 sequentially changes the connection between the Y lines Y1 to Y8 and the drive circuit 3 according to the drive pattern, and for each change, the voltage detection circuit 4 changes to the detection patterns 1 to 8 described above. In response, a calculation process for detecting eight voltages is performed.
  • data relating to the selection and connection operations of the selection circuit 2 is stored in advance in the memory 10 for each predetermined drive pattern and detection pattern. That is, the memory 10 stores the switch SW11 of each of the switch units 21-1 to 21-8 and the switch units 22-1 to 22-8 of the selection circuit 2 for each predetermined drive pattern and detection pattern 1 to 8. Stores data for ON / OFF control of SW15.
  • the control circuit 8 instructs the address generation circuit 9 to generate an address for reading out the data for each of the predetermined drive patterns and detection patterns 1 to 8, and latches necessary data according to the generated address. Read to.
  • the data read to the latch 11 is transferred to the decoders 23-1 to 23-8 and the decoders 24-1 to 24-8.
  • the decoders 23-1 to 23-8 perform on / off control of the switches SW11 to SW15 of the switch units 21-1 to 21-8.
  • the decoders 24-1 to 24-8 perform on / off control of the switches SW11 to SW15 of the switch units 22-1 to 22-8.
  • the decoder 24-1 is connected to the switch section 22-1.
  • the switch SW13 is turned on, and the decoder 24-2 turns on the switch SW14 of the switch unit 22-2.
  • X lines X1 to X8 of the touch panel 1 are selected as the first detection lines, and X lines X5 to X8 are selected as the second detection lines, respectively.
  • the operation is as follows. That is, each of the decoders 23-1 to 23-4 turns on the switch SW11 of the switch units 21-1 to 21-4.
  • Each of the decoders 23-5 to 23-8 turns on the switch SW12 of the switch units 21-5 to 21-8.
  • the voltage detection circuit 4 performs the calculation process according to the first to eighth detection patterns to obtain the output voltages D1 to D8, respectively, and the output voltages D1 to D8 are obtained. Differential amplification was performed when D8 was obtained. Therefore, noise can be reduced when the output voltages D1 to D8 are obtained, and the S / N can be improved.
  • the voltage detection circuit 4 uses the capacitance formed between the lines of the touch panel 1 as a capacitor for offset adjustment in order to obtain the output voltages D1 to D8. There is no need to provide a capacitor.
  • an Hadamard transformation matrix of 8 rows ⁇ 8 columns is used as shown in the equation (2).
  • a Hadamard transform matrix such as 4 rows ⁇ 4 columns or 16 rows ⁇ 16 columns can also be used.
  • the number of the detection patterns is n, and the voltage detection circuit 4 is used according to each detection pattern.
  • Modification 1 is a case where the number of lines (number of electrodes) of the touch panel is not a multiple of 4, for example, 7 in the X-axis direction.
  • the basic configuration is the same as that in FIG. 1, and only the size of the touch panel 1 is different. The operation is also the same as in the first embodiment. Only the parts different from the first embodiment will be described below.
  • the size of the Hadamard transform matrix is selected by a multiple of 4 that is greater than the number of electrodes.
  • 8 is used as a minimum multiple of 4 that is 7 or more, that is, an Hadamard transformation matrix of 8 rows ⁇ 8 columns is used.
  • the detection pattern uses eight types of detection patterns according to the Hadamard transform matrix of the selected size. That is, the electrode X8 in FIGS. 9 and 10 is omitted.
  • the calculation process in which the voltage detection circuit 4 detects the eight potential differences according to the eight detection patterns described above can be expressed by the following equation (4).
  • the coefficient matrix of equation (4) deletes the eighth column (rightmost column) of the 8-row ⁇ 8-column Hadamard transformation matrix that is the coefficient matrix of equation (2), and sets the number of columns to an electrode in the X-axis direction. It matches the number. Note that the position of the column to be deleted may be anywhere, and the number of columns as a result of deleting the column only needs to match the number of electrodes in the X-axis direction.
  • the eight output voltages output from the voltage detection circuit 4 are each A / D converted by the A / D conversion circuit 5 in a predetermined evening of the operation of “state 2” in FIG.
  • the A / D converted output voltages are sequentially stored in the capacity calculation circuit 6.
  • the capacitance calculation circuit 6 When the storage of the output voltages D1 to D8 is completed, the capacitance calculation circuit 6 performs the capacitance difference (C1-C9), (C2) based on the stored output voltages D1 to D8 and the Hadamard transformation matrix that is the transformation matrix. -C10)... (C7-C15) are calculated.
  • the arithmetic processing performed by the capacity calculation circuit 6 can be expressed by the following equation (5).
  • the coefficient matrix appearing in the equation (5) has a transposed matrix of the coefficient matrix of the equation (4) and a Moore-Penrose generalized inverse matrix (a scalar multiple thereof).
  • the output voltage output from the voltage detection circuit 4 is eight and more than seven electrodes
  • the coefficient matrix of the equation (5) is obtained because it is a generalized inverse matrix of the coefficient matrix of the equation (4).
  • (C1-C9), (C2-C10)... (C7-C15) are least squares solutions that satisfy the equation (4). Therefore, the greater the number of output voltages of the voltage detection circuit 4, the better the S / N.
  • the coefficient matrix appearing in the equation (4) is not the one obtained by deleting some columns of the Hadamard transform, but the coefficient matrix obtained by deleting some columns of the orthogonal matrix and the orthogonal matrix multiplied by the scalar. Applicable. Note that the first modification can be applied to second and third embodiments described later.
  • Y1 is connected to the-terminal 34 of the drive circuit 3
  • Y2 is connected to the + terminal 33 of the drive circuit 3
  • X1 to X8 are The drive circuit 3 and the voltage detection circuit 4 can be exchanged, although they are configured to be connected to the + side terminal 44 or the ⁇ side terminal 45 of the voltage detection circuit 4 according to a predetermined pattern. That is, Y1 is connected to the negative terminal 45 of the voltage detection circuit 4, Y2 is connected to the positive terminal of the voltage detection circuit 4, and X1 to X8 are the positive side terminal 33 or negative side terminal 34 of the drive circuit 3 according to a predetermined pattern. It can also be configured to connect to.
  • the output of the voltage detection circuit is exactly the same as in the first embodiment, and therefore, the same configuration as in FIG. 1 can be used only by changing the drive / detection pattern stored in the memory 10 of FIG. it can.
  • the second modification can be applied to the first modification of the first embodiment.
  • FIG. 11 is a block diagram showing a schematic configuration of a touch sensor to which the second embodiment of the present invention is applied.
  • the touch sensor to which the second embodiment is applied includes a touch panel 1, a selection circuit 2, a drive circuit 3, a voltage detection circuit 4, an A / D conversion circuit 5, and a capacitance calculation circuit.
  • the second embodiment is based on the configuration of the first embodiment shown in FIG. 1, and the capacitance calculation circuit 6, the touch position detection circuit 7, and the control circuit 8 shown in FIG.
  • the capacitance calculation circuit 6A, the touch position detection circuit 7A, and the control circuit 8A are replaced with a capacitance circuit 12.
  • the second embodiment has parts common to the components of the first embodiment.
  • the common components are denoted by the same reference numerals, and the description thereof is omitted as much as possible.
  • the capacitance circuit 12 includes offset adjusting capacitors CR1 and CR2 each having a predetermined capacitance value, and switches SW7 to SW9.
  • One end of the capacitor CR1 is connected to the input terminal 44 of the voltage detection circuit 4, and the other end of the capacitor CR1 is connected to the output terminal 34 of the drive circuit 3 via the switch SW7.
  • One end side of the capacitor CR2 is connected to the input terminal 45 of the voltage detection circuit 4, and the other end side of the capacitor CR2 is connected to the output terminal 34 of the drive circuit 3 via the switch SW8.
  • one end side of the switch SW9 is connected to the input terminal 45 of the voltage detection circuit 4, and the other end side of the switch SW9 is connected to VCOM.
  • the selection circuit 2 selects one predetermined line from among the Y lines Y1 to Y8 of the touch panel 1 as a drive line according to a predetermined drive pattern.
  • the Y line Y1 is selected as the drive line, and the selected Y line Y1 is connected to the output terminal 33 of the drive circuit 3 (see FIGS. 13 and 14).
  • the selection circuit 2 selects the X lines X1 to X1 of the touch panel 1 according to the selected detection pattern.
  • a part of X8 is connected to the input terminal 44 of the voltage detection circuit 4, and the remainder of the X lines X1 to X8 is connected to the input terminal 45 of the voltage detection circuit 4.
  • FIGS. 13A to 13D and FIGS. 14E to 14H show detection patterns 1 to 8 determined according to the Hadamard transformation matrix and X lines X1 to X corresponding to these detection patterns 1 to 8, respectively.
  • the connection state between X8 and the voltage detection circuit 4 is shown.
  • the X lines X 1 to X 8 are connected to the input terminal 44 of the voltage detection circuit 4.
  • the X lines X1, X3, X5, and X7 are connected to the input terminal 44 of the voltage detection circuit 4
  • the X lines X2, X4, X6, and X8 are connected. Is connected to the input terminal 45 of the voltage detection circuit 4.
  • Reference numerals C1 to C8 in FIGS. 13 and 14 are capacitances (capacitors) formed between the Y line Y1 and the X lines X1 to X8, respectively.
  • the drive circuit 3 and the voltage detection circuit 4 perform the operations of “state 1” and “state 2” shown in FIG. A potential difference corresponding to ⁇ 8 is detected.
  • the switches SW7 and SW9 shown in FIG. 12 are turned on.
  • the capacitor CR1 is connected between the output terminal 34 of the drive circuit 3 and the input terminal 44 of the voltage detection circuit 4, and the input terminal 45 of the voltage detection circuit 4 is connected to VCOM.
  • the switches SW7 and SW8 shown in FIG. 12 are turned on. Therefore, the capacitor CR1 is connected between the output terminal 34 of the drive circuit 3 and the input terminal 44 of the voltage detection circuit 4, and the capacitor CR2 is connected between the output terminal 34 of the drive circuit 3 and the input terminal 45 of the voltage detection circuit 4. Connected between.
  • the calculation processing in which the voltage detection circuit 4 detects eight potential differences according to the detection patterns 1 to 8 can be expressed by the following equation (6).
  • D1 to D8 are output voltages (detection voltages) of the voltage detection circuit 4 obtained according to the eight detection patterns 1 to 8.
  • the transformation matrix on the right side is a Hadamard transformation matrix.
  • C1 to C8 are capacitances between the Y line Y1 and the X lines X1 to X8.
  • each of the eight rows of the Hadamard transform matrix corresponds to the eight detection patterns 1 to 8 described above.
  • 1 and ⁇ 1 in each row correspond to the connection state between the X lines X1 to X8 of each detection pattern and the voltage detection circuit 4.
  • the output voltages D1 to D8 output from the voltage detection circuit 4 are each A / D converted by the A / D conversion circuit 5 at a predetermined timing of the operation of “state 2” in FIG.
  • the A / D converted output voltages D1 to D8 are sequentially stored in the capacity calculation circuit 6A.
  • the capacity calculation circuit 6A performs an operation for calculating the capacitances C1 to C8 based on the stored output voltages D1 to D8 and the Hadamard transform matrix as a conversion matrix. Do.
  • the arithmetic processing performed by the capacity calculation circuit 6A can be expressed by the following equation (7).
  • the touch position detection circuit 7A detects the touch position of the touch panel 1 based on the capacitances C1 to C8 calculated by the capacitance calculation circuit 6A.
  • the above operation is an example in which the touch position on the touch panel 1 is detected by a one-dimensional operation. However, when the touch position on the touch panel 1 is detected by a two-dimensional operation, the above operation is repeated. become. In this case, the connection between the Y lines Y1 to Y8 and the drive circuit 3 is sequentially changed according to the drive pattern, and for each change, the voltage detection circuit 4 has eight outputs corresponding to the detection patterns 1 to 8. An arithmetic process for detecting the voltage is performed.
  • the voltage detection circuit 4 when the voltage detection circuit 4 obtains the output voltages D1 to D8 by performing arithmetic processing according to the eight detection patterns, and obtains the output voltages D1 to D8, respectively. Differential amplification was performed. Therefore, noise can be reduced when the output voltages D1 to D8 are obtained, and the S / N can be improved.
  • an Hadamard transformation matrix of 8 rows ⁇ 8 columns is used as shown in Equation (6).
  • a Hadamard transform matrix such as 4 rows ⁇ 4 columns or 16 rows ⁇ 16 columns can also be used.
  • the number of the detection patterns is n, and the voltage detection circuit 4 is used according to each detection pattern.
  • FIGS. 15A and 15B show detection states in the detection pattern 5.
  • A is the case where the finger 100 is in the vicinity of the capacitances C1 to C4, and the output voltage D5 of the voltage detection circuit 4 is D5 ⁇ 0.
  • B is the case where the finger 100 is in the vicinity of the capacitances C5 to C8, and the output voltage D5 of the voltage detection circuit 4 is D5> 0.
  • FIGS. 15C and 15D both show detection states in the detection pattern 7.
  • C is the case where the finger 100 is in the vicinity of the capacitances C3 to C6, and the output voltage D7 of the voltage detection circuit 4 is D7> 0.
  • D is the case where the finger 100 is in the vicinity of the capacitances C1 and C2 or the capacitances C7 and C8, and the output voltage D7 of the voltage detection circuit 4 is D7 ⁇ 0. Therefore, based on the output voltages D5 and D7 of the voltage detection circuit 4, the position of the finger is the capacitance C1, C2, capacitance C3, C4, capacitance C5, C6, or capacitance C7, C8. It can be determined in which neighborhood.
  • the X and Y coordinates of the touch position can be detected by performing the following operation instead of the operation of the second embodiment.
  • multipoint touch here means that two or more different points on the touch panel are touched within a predetermined time.
  • the selection circuit 2 selects all of the Y lines Y1 to Y8 of the touch panel 1 according to a predetermined drive pattern instead of selecting one predetermined line as a drive line. The rest is the same as the description of the operation of the second embodiment. Thereby, the X coordinate of the touch position can be detected.
  • the above operation is performed again by exchanging the X line and the Y line. Thereby, the Y coordinate of the touch position can be detected.
  • FIG. 16 is a block diagram showing a schematic configuration of a touch sensor to which the third embodiment of the present invention is applied.
  • the touch sensor to which the third embodiment is applied includes a touch panel 1, a selection circuit 2, a drive circuit 3, a voltage detection circuit 4A, an A / D conversion circuit 5, and a capacitance calculation circuit. 6A, touch position detection circuit 7A, control circuit 8B, address generation circuit 9, memory 10, latch 11, and capacitance circuit 12A for offset adjustment.
  • the third embodiment is based on the configuration of the second embodiment shown in FIG. 11, and the differential amplification type voltage detection circuit 4, the control circuit 8A, and the capacitance circuit 12 of FIG.
  • a single type voltage detection circuit 4A, a control circuit 8B, and a capacitance circuit 12A are replaced.
  • the third embodiment has a part common to the constituent elements of the second embodiment, and the common constituent elements are denoted by the same reference numerals, and the description thereof is omitted as much as possible.
  • the voltage detection circuit 4A includes an operational amplifier OP4, an integration capacitor Cf, and a switch SW10. An input voltage is input to the inverting input terminal ( ⁇ ) of the operational amplifier OP4, and the non-inverting input terminal (+) of the operational amplifier OP4 is connected to VCOM. Further, a parallel circuit of an integrating capacitor Cf and a switch SW10 is connected between the inverting input terminal and the output terminal of the operational amplifier OP4.
  • the capacitance circuit 12A includes an offset adjustment capacitor CR3 having a predetermined capacitance value and a switch SW20.
  • One end side of the capacitor CR3 is connected to the input terminal of the voltage detection circuit 4A, and the other end side of the capacitor CR3 is connected to the output terminal 34 of the drive circuit 3 via the switch SW20.
  • the control circuit 8B controls the drive circuit 3, the voltage detection circuit 4A, the address generation circuit 9, the latch 11, and the capacitance circuit 12A.
  • the selection circuit 2 selects one predetermined line as a detection line among the Y lines Y1 to Y8 of the touch panel 1 according to a predetermined detection pattern.
  • the Y line Y1 is selected as the detection line, and the selected Y line Y1 is connected to the input terminal of the voltage detection circuit 4 (see FIGS. 18 and 19).
  • the selection circuit 2 selects the X lines X1 to X1 of the touch panel 1 according to the selected drive pattern.
  • a part of X8 is connected to the output terminal 33 of the drive circuit 3, and the remainder of the X lines X1 to X8 is connected to the output terminal 34 of the drive circuit 3.
  • FIGS. 19E to 19H show driving patterns 1 to 8 determined according to the Hadamard transformation matrix and X lines X1 to X corresponding to these driving patterns 1 to 8, respectively.
  • the connection state between X8 and the drive circuit is shown.
  • the X lines X 1 to X 8 are connected to the output terminal 33 of the drive circuit 3.
  • the X lines X1, X3, X5, and X7 are connected to the output terminal 33 of the drive circuit 3
  • the X lines X2, X4, X6, and X8 are connected. Connected to the output terminal 34 of the drive circuit 3.
  • the drive circuit 3 and the voltage detection circuit 4A perform the first operation and the second operation as operations corresponding to “state 1” and “state 2” shown in FIG.
  • the voltage detection circuit 4A detects a voltage corresponding to the drive patterns 1-8.
  • the switches SW1 and SW4 of the drive circuit 3 are turned on, SW2 and SW3 are turned off, and the switch SW10 of the voltage detection circuit 4A is turned on.
  • the switches SW1 and SW4 of the drive circuit 3 are turned off, SW2 and SW3 are turned on, and the switch SW10 of the voltage detection circuit 4A is turned off.
  • Each of the eight rows of the Hadamard transform matrix corresponds to the eight drive patterns 1 to 8 described above. Further, 1 and ⁇ 1 in each row correspond to the connection state between the X lines X1 to X8 of each drive pattern and the drive circuit 3.
  • Output voltages D1 to D8 output from the voltage detection circuit 4A are A / D converted by the A / D conversion circuit 5, respectively.
  • the A / D converted output voltages D1 to D8 are sequentially stored in the capacity calculation circuit 6A.
  • the capacity calculation circuit 6A When the storage of the output voltages D1 to D8 is completed, the capacity calculation circuit 6A performs an operation for calculating the capacitances C1 to C8 based on the stored output voltages D1 to D8 and the Hadamard transform matrix as a conversion matrix. Do.
  • the arithmetic processing performed by the capacity calculation circuit 6A can be expressed by the above equation (7).
  • the touch position detection circuit 7A detects the touch position of the touch panel 1 based on the capacitances C1 to C8 calculated by the capacitance calculation circuit 6A.
  • the above operation is an example in which the touch position on the touch panel 1 is detected by a one-dimensional operation. However, when the touch position on the touch panel 1 is detected by a two-dimensional operation, the above operation is repeated. become. In this case, the connection between the Y lines Y1 to Y8 and the voltage detection circuit 4A is sequentially changed, and for each change, the voltage detection circuit 4A detects eight voltages according to the drive patterns 1 to 8. Perform arithmetic processing.
  • the voltage detection circuit 4A is configured as a single type as shown in FIG. 17, the configuration is simplified.
  • the capacitor CR3 and the switch SW20 shown in FIG. 17 may be omitted.
  • the detection in the case of FIG. 18A is omitted, and a fixed value such as 0 is used as the measurement value.
  • an Hadamard transformation matrix of 8 rows ⁇ 8 columns is used as shown in the equation (6).
  • a Hadamard transform matrix such as 4 rows ⁇ 4 columns or 16 rows ⁇ 16 columns can also be used.
  • the number of the driving patterns is n, and the driving circuit 3 is connected according to each driving pattern.
  • the X and Y coordinates of the touch position can be detected by performing the following operation instead of the operation of the second embodiment.
  • the selection circuit 2 selects all Y lines instead of selecting one predetermined line as a detection line from among the Y lines Y1 to Y8 of the touch panel 1 in accordance with a predetermined detection pattern. .
  • the rest is the same as the description of the operation of the third embodiment.
  • the X coordinate of the touch position can be detected.
  • the above operation is performed again by exchanging the X line and the Y line.
  • the Y coordinate of the touch position can be detected.
  • FIG. 20 is a block diagram showing a schematic configuration of a touch sensor to which the fourth embodiment of the present invention is applied.
  • the touch sensor to which the fourth embodiment is applied includes a touch panel 1, a selection circuit 2, a drive circuit 3, a voltage detection circuit 4, an A / D conversion circuit 5, and a capacitance calculation circuit. 6B, a touch position detection circuit 7B, a control circuit 8C, an address generation circuit 9, a memory 10, a latch 11, and a capacitance circuit 12 for offset adjustment. That is, the fourth embodiment is based on the configuration of the second embodiment shown in FIG. 11. As shown in FIG. 20, the capacitance calculation circuit 6A, the touch position detection circuit 7A, and the control circuit 8A shown in FIG. The calculation circuit 6B, the touch position detection circuit 7B, and the control circuit 8C are replaced.
  • the fourth embodiment has parts common to the components of the second embodiment, and the common components are denoted by the same reference numerals, and description thereof is omitted as much as possible.
  • the control circuit 8C controls the drive circuit 3, the voltage detection circuit 4, the address generation circuit 9, the latch 11, and the capacitance circuit 12 when detecting the touch position of the touch panel 1.
  • the selection circuit 2 selects the selected conversion pattern. Accordingly, a part of the Y lines Y1 to Y8 of the touch panel 1 is connected to the output terminal 33 of the drive circuit 3, and the rest of the Y lines Y1 to Y8 is connected to the output terminal 34 of the drive circuit 3.
  • the selection circuit 2 selects a part of the X lines X1 to X8 of the touch panel 1 according to the selected conversion pattern as the input terminal 44 of the voltage detection circuit 4. And the remainder of the X lines X 1 to X 8 is connected to the input terminal 45 of the voltage detection circuit 4.
  • 21 to 36 show 64 conversion patterns determined according to the Hadamard transformation matrix, the connection states of the Y lines Y1 to Y8 and the drive circuit 3 according to these 64 conversion patterns, and the X lines X1 to X1. The connection state between X8 and the voltage detection circuit 4 is shown.
  • FIG. 21 and FIG. 22 show eight conversion patterns obtained by combining pattern 1 and eight patterns 1-8.
  • 23 and 24 show eight conversion patterns obtained by combining the pattern 2 and the eight patterns 1 to 8.
  • FIG. 25 and 26 show eight conversion patterns obtained by combining the pattern 3 and the eight patterns 1 to 8.
  • 27 and 28 show eight conversion patterns obtained by combining the pattern 4 and the eight patterns 1 to 8.
  • FIG. 21 and FIG. 22 show eight conversion patterns obtained by combining pattern 1 and eight patterns 1-8.
  • 23 and 24 show eight conversion patterns obtained by combining the pattern 2 and the eight patterns 1 to 8.
  • FIG. 25 and 26 show eight conversion patterns obtained by combining the pattern 3 and the eight patterns 1 to 8.
  • 27 and 28 show eight conversion patterns obtained by combining the pattern 4 and the eight patterns 1 to 8.
  • FIG. 21 and FIG. 22 show eight conversion patterns obtained by combining pattern 1 and eight patterns 1-8.
  • 29 and 30 show eight conversion patterns obtained by combining pattern 5 and eight patterns 1-8.
  • 31 and 32 show eight conversion patterns obtained by combining the pattern 6 and the eight patterns 1 to 8.
  • 33 and 34 show eight conversion patterns obtained by combining the pattern 7 and the eight patterns 1-8.
  • 35 and 36 show eight conversion patterns obtained by combining the pattern 8 and the eight patterns 1 to 8.
  • the Y axis is connected to the drive circuit 3 and the X axis is connected to the voltage detection circuit 4, but the X axis is connected to the drive circuit 3 and the Y axis is connected to the voltage detection circuit 4.
  • the voltage detection circuit 4 has a single-ended configuration. In this case, except for the case of FIG. 21A, voltage detection is performed by switching the + terminal of the drive circuit 3 and the + terminal of the voltage detection circuit 4 and switching the ⁇ terminal of the drive circuit 3 and the ⁇ terminal of the voltage detection circuit 4.
  • the voltage detection circuit 4 having a differential configuration is used in all patterns except the pattern of FIG. 21A, and the S / N is further improved. Can do. Further, even if the + terminal of the drive circuit 3 and the + terminal of the voltage detection circuit 4 and the ⁇ terminal of the drive circuit 3 and the ⁇ terminal of the voltage detection circuit 4 are interchanged, the operation of the capacitance calculation circuit 6B may be the same. Further, by omitting the measurement of FIG. 21A and treating the measured value as 0, a conversion pattern may be configured so as not to use the single-ended voltage detection circuit at all, and the S / N is further improved. Can do. Assuming that the capacitance formed between the axis Xi and the axis Yj is Cij, the relationship with the value appearing at the output Dmn of the voltage detection circuit 4 is expressed by the following equation (7A).
  • s mi and s nj are the (m, i) component and (n, j) component of the Hadamard transform matrix expressed by the following equation (9), respectively.
  • the drive circuit 3 and the voltage detection circuit 4 perform the operations of “state 1” and “state 2” shown in FIG. 5, and the voltage detection circuit 4 A potential difference corresponding to the conversion pattern is detected.
  • the calculation process in which the voltage detection circuit 4 detects the voltage corresponding to the potential difference in accordance with the 64 conversion patterns can be expressed by the following equation (8).
  • the terms VCOM and VDD / Cf in equation (7A) are irrelevant to capacitance calculation and touch position detection, and are therefore omitted for the sake of brevity.
  • D is 64 output voltages (detected voltages) of the voltage detection circuit 4 obtained according to the 64 conversion patterns, and is an 8 ⁇ 8 matrix.
  • H on the right side of equation (8) is the Hadamard transform matrix shown in equation (9).
  • C is 64 capacitances at the intersections of the X lines X1 to X8 and the Y lines Y1 to Y8 of the touch panel 1, and is an 8 ⁇ 8 matrix.
  • the H on the right side of equation (8) and the subscript T attached to the right shoulder is obtained by replacing the rows and columns of the Hadamard transform matrix of equation (9).
  • the 64 output voltages output from the voltage detection circuit 4 are each A / D converted by the A / D conversion circuit 5 at a predetermined timing of the operation of “state 2” in FIG.
  • the A / D converted output voltages are sequentially stored in the capacity calculation circuit 6B.
  • the capacitance calculation circuit 6B based on the stored output voltage and the Hadamard transformation matrix that is a transformation matrix, each of the X lines X1 to X8 and the Y lines Y1 to Y8 of the touch panel 1 is stored.
  • An operation for calculating each of the 64 capacitances at the intersection is performed.
  • the arithmetic processing performed by the capacity calculation circuit 6B can be expressed by the following equation (10).
  • the touch position detection circuit 7B detects the touch position of the touch panel 1 based on the 64 electrostatic capacitances calculated by the capacity calculation circuit 6B.
  • the voltage detection circuit 4 performs arithmetic processing according to the 64 conversion patterns to obtain 64 output voltages, respectively, and the difference is obtained when each output voltage is obtained. Dynamic amplification was performed. For this reason, when obtaining each output voltage, noise can be reduced and S / N can be improved.
  • an Hadamard transformation matrix of 8 rows ⁇ 8 columns is used as shown in equations (8) and (9). However, a Hadamard transformation matrix such as 2 rows ⁇ 2 columns, 4 rows ⁇ 4 columns, 16 rows ⁇ 16 columns, or the like can also be used.
  • the number of the conversion patterns is (m ⁇ n), and according to each conversion pattern, the number of drive lines connected to the drive circuit 3 is m, and the number of detection lines connected to the voltage detection circuit 4 is n.
  • Modification 1 of 4th Embodiment The configuration and operation of Modification 1 of the fourth embodiment are basically the same as those of the fourth embodiment. Hereinafter, a different part from 4th Embodiment is demonstrated.
  • X lines X1 to X8 X1 and X2 are grouped into X line group 1
  • X3 and X4 are grouped into X line group 2
  • X5 and X6 are grouped into X line group 3
  • X7 and X8 are grouped into X line group 4. That is, the X lines X1 to X8 are divided into four groups.
  • Y lines Y1 to Y8 are divided into two groups.
  • the electrodes that are easted by the above grouping are regarded as one electrode, it can be seen that the X line is four and the Y line is two panels.
  • the X line is four and the Y line is two panels.
  • the grouping of the X line and the Y line is indicated by a symbol “ ⁇ ”.
  • the drive / detection patterns shown in FIGS. 37 and 38 are stored in the memory 10, and the selection circuit 2, the drive circuit 3, the voltage detection circuit 4, and the A / D conversion circuit 5 are operated in the same manner as in the fourth embodiment.
  • the A / D converted value is acquired.
  • the capacity calculation circuit 6B the X line is 4 groups, so the 4 rows ⁇ 4 columns Hadamard transform is used, and the Y line is 2 groups, so the 2 rows ⁇ 2 columns Hadamard transform is used.
  • the same processing as in the fourth embodiment is performed.
  • the total capacitance formed at the intersection of X line X5, X6 and Y line Y1, Y2, Y3, Y4, formed at the intersection of X line X5, X6 and Y line Y5, Y6, Y7, Y8 The total capacitance formed, the total capacitance formed at the intersection of X lines X7, X8 and Y lines Y1, Y2, Y3, Y4, X lines X7, X8 and Y lines Y5, Y6, Y7, The total capacitance formed at the intersection of Y8 is determined.
  • Modification 1 of the fourth embodiment has a smaller number of measurement points than the fourth embodiment, and is convenient for operation in a low power consumption mode.
  • the capacity change for each group can be greatly increased as the spatial resolution is reduced, it is particularly convenient for detecting hovering.
  • Modification 2 of 4th Embodiment is a case where the number of touch panel lines (number of electrodes) is not a multiple of 4, for example, 7 in the X-axis direction and 9 in the Y-axis direction.
  • the basic configuration is the same as that in FIG. 20, and only the size of the touch panel 1 is different.
  • the operation is the same as that of the fourth embodiment. Only the parts different from the fourth embodiment will be described below.
  • an Hadamard transformation matrix of 8 that is, 8 rows ⁇ 8 columns, is used as the minimum multiple of 4 in the X-axis direction.
  • the number of electrodes in the Y-axis direction is 9, 12 is used as the minimum multiple of 4 in the Y-axis direction, that is, a 12-row ⁇ 12-column Hadamard transformation matrix is used.
  • mi is the (m, i) component of the aforementioned 8-row ⁇ 8-column Hadamard transform matrix
  • s nj ′ is the (n, j) component of the aforementioned 12-row ⁇ 12-column Hadamard transform matrix.
  • the drive circuit 3 and the voltage detection circuit 4 perform the operations of “state 1” and “state 2” shown in FIG. 5, and the voltage detection circuit 4 performs the 96 conversions.
  • a potential difference corresponding to the pattern is detected.
  • the calculation process in which the voltage detection circuit 4 detects the voltage corresponding to the potential difference in accordance with the 96 conversion patterns can be expressed by the following equation (12). Note that the terms VCOM and VDD / Cf in equation (11) are irrelevant to the capacitance calculation and the touch position detection, and are therefore omitted for simplification.
  • the calculation process performed by the capacity calculation circuit 6B can be expressed by the following equation (14).
  • H x is the 8th row ⁇ 8th column Hadamard transformation matrix as shown in the equation (13A), and the 8th column (the rightmost column) is deleted to make the number of columns the number of electrodes in the X-axis direction.
  • This is a matrix representation of s mi in equation (11). Note that the position of the column to be deleted may be anywhere, and the number of columns as a result of deleting the column only needs to match the number of electrodes in the X-axis direction.
  • the transposed matrices H x T and H x are in a Moore-Penrose generalized inverse matrix (scalar multiple).
  • H y is the number of columns in the Y-axis direction to remove the 10-12 column of the Hadamard transform matrix of 12 rows ⁇ 12 columns as expressed by (13B) (3 rows of rightmost) This corresponds to the number of electrodes, and is a matrix representation of s nj ′ in equation (11). Note that the position of the column to be deleted may be anywhere, and the number of columns as a result of deleting the column only needs to match the number of electrodes in the Y-axis direction. The columns to be deleted need not be adjacent to each other.
  • the transposed matrices H y T and H y are in a Moore-Penrose generalized inverse matrix (scalar multiple).
  • H x T and H y in the equation (14) are generalizations of H x and H y T in the equation (12), respectively. Since it is an inverse matrix, the obtained C ij is a least squares solution that satisfies the equation (11). Therefore, the greater the number of output voltages of the voltage detection circuit 4, the better the S / N.
  • H x and H y are obtained by deleting some of the rows of the Hadamard transformation matrix, but not only the Hadamard transformation matrix but also an orthogonal transformation matrix and a scalar multiple of the orthogonal transformation matrix. Since the transposed matrix of the matrix from which a part of the column is deleted becomes a Moore-Penrose generalized inverse matrix (scalar multiple) of the original matrix, this variation can be applied.
  • the touch position detection circuit 7B detects the touch position of the touch panel 1 based on the 63 electrostatic capacitances calculated by the capacitance calculation circuit 6B. This modification can be applied even when the number of electrode groups by grouping is not 2 or a multiple of 4 in Modification 1 of the fourth embodiment.
  • the capacity calculation circuit 6, the touch position detection circuit 7, the control circuit 8, and the like can be replaced with a computer.
  • functions such as the capacity calculation circuit 6, the touch position detection circuit 7, and the control circuit 8 shown in FIG. 1 are replaced with a computer (not shown), and the computer performs the selection circuit 2 and the drive circuit 3
  • the operation of the voltage detection circuit 4 and the like are controlled, and the calculation processing of the capacitance calculation circuit 6 and the touch position detection circuit 7 is performed.
  • procedures (programs) of various processes such as various predetermined controls and calculations are stored in advance in, for example, the memory 10 of FIG.
  • the computer performed various processing such as control and calculation.
  • each of the plurality of addresses of the memory 10 of FIG. 1 includes a selection circuit 2 for each detection pattern determined according to a predetermined drive pattern and a predetermined conversion matrix (for example, Hadamard conversion matrix). It is assumed that control data for controlling operations of the drive circuit 3 and the voltage detection circuit 4 is stored in advance.
  • step S1 in order to read out control data corresponding to the drive pattern and detection pattern stored in the memory 10, the address of the memory 10 is set to the start address.
  • step S2 control data corresponding to the drive and detection patterns stored at the start address of the set memory 10 is read.
  • step S3 the switches SW11 to SW15 of the switch units 21-1 to 21-8 of the selection circuit 2 are on / off controlled based on the control data, and the switches of the selection circuit 2 are set.
  • a predetermined line among the Y lines Y1 to Y8 of the touch panel 1 is selected as a drive line and connected to the output terminal of the drive circuit 3.
  • a part of the X lines X 1 to X 8 of the touch panel 1 is connected to one input terminal of the voltage detection circuit 4, and the rest is connected to the other input terminal of the voltage detection circuit 4.
  • the operation of the drive circuit 3 and the voltage detection circuit 4 is set to “state 1” based on the control data stored at the start address of the memory 10 (see FIG. 5). This setting is performed by controlling the switches SW1 to SW4 of the drive circuit 3 and the switches SW5 and SW6 of the voltage detection circuit 4.
  • step S5 the process waits for a predetermined time in step S5, and when this standby is completed, the process proceeds to the next step S6.
  • step S6 the operation of the drive circuit 3 and the voltage detection circuit 4 is set to “state 2” based on the control data stored at the start address of the memory 10 (see FIG. 5).
  • step S7 the process waits for a predetermined time, and this standby is completed.
  • the voltage detection circuit 4 detects the voltage difference between the input voltages input to its two input terminals, and outputs the detected voltage to the A / conversion circuit 5.
  • step S8 an A / D conversion value output from the A / D conversion circuit 5 is acquired.
  • step S9 the acquired A / D conversion value is stored.
  • step S10 it is determined whether or not the current address of the memory 10 is an end address. As a result of this determination, if it is not the end address (NO), the address is incremented (step S11), the process returns to step S2, and a series of processes of steps S2 to S10 is performed. On the other hand, in the case of an end address (YES), the process proceeds to step S12.
  • step S12 the capacitance difference is calculated by performing Hadamard inverse transformation based on the A / D conversion value stored in step S9. This calculation corresponds to the function of the capacity calculation circuit 6 of FIG.
  • step S13 the touch position is detected based on the capacitance difference calculated in step S12. This detection corresponds to the function of the touch position detection circuit 7 in FIG.
  • step S14 the coordinates of the touch position detected in step S13 are output.
  • functions such as the capacity calculation circuit 6, the touch position detection circuit 7, and the control circuit 8 shown in FIG. 1 are replaced with a computer.
  • the functions of the capacitance calculation circuit 6A, the touch position detection circuit 7A, the control circuit 8A, and the like may be replaced with a computer.
  • the functions of the capacitance calculation circuit 6A, the touch position detection circuit 7A, the control circuit 8B, and the like may be replaced with a computer.
  • the functions of the capacity calculation circuit 6B, the touch position detection circuit 7B, the control circuit 88C, and the like may be replaced with a computer.
  • each of the second to fourth embodiments includes capacitance circuits 12 and 12A as shown in FIG. 11, FIG. 16, or FIG. For this reason, in the flowchart of FIG. 37, a process for setting the capacitance circuit switch and the capacitance value is added between step S3 and step S4.
  • the signal processing circuit of the touch sensor of the present invention can be applied not only to the touch sensor but also to a display device including the touch sensor.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Position Input By Displaying (AREA)

Abstract

The purpose of the present invention, with regard to signal processing for a touch panel, is to improve the signal-to-noise ratio by enabling the noise generated when a finger is brought into contact with a touch panel to be lessened. A selection circuit (2) selects two from among Y-lines (Y1-Y8) to serve as detection lines, and also selects at least two lines from among X-lines (X1-X8) to serve as detection lines, in accordance with the selection of one from among a plurality of detection patterns determined in accordance with a transformation matrix. A drive circuit (3) supplies a voltage to selected drive lines. A voltage detection circuit (4) detects the difference between one electrical potential and another electrical potential generated on the selected detection lines. A capacity calculation circuit (6) carries out a computation on the basis of the respective detected electrical potential differences and the transformation matrix, and respectively calculates the electrostatic capacitance of the difference between the electrostatic capacitance of each intersecting part between one selected drive line and a selected detection line, and between the electrostatic capacitance of each intersecting part between another selected drive line and each selected detection line.

Description

タッチセンサの信号処理回路、およびタッチセンサTouch sensor signal processing circuit and touch sensor
 本発明は、静電容量型のタッチパネルを含むタッチセンサの信号処理回路などに関するものである。 The present invention relates to a signal processing circuit of a touch sensor including a capacitive touch panel.
 従来、この種のタッチパネルを含むタッチセンサに関する発明としては、特許文献1、特許文献2に記載される発明が知られている。
 まず、特許文献1の発明は、第1の方向に延びる複数の第1電極と、第1の方向とは異なる第2の方向に延びる複数の第2電極と、駆動回路と、検出回路と、座標位置演算回路とを有している。
Conventionally, inventions described in Patent Document 1 and Patent Document 2 are known as inventions related to touch sensors including this type of touch panel.
First, the invention of Patent Document 1 includes a plurality of first electrodes extending in a first direction, a plurality of second electrodes extending in a second direction different from the first direction, a drive circuit, a detection circuit, And a coordinate position calculation circuit.
 駆動回路は、複数の第1電極の中から2つの第1電極を順次選択し、当該選択された2つの第1電極の一方に基準電圧よりも高電位の電圧を供給し、他方には基準電圧を供給する。また、検出回路は、選択した第2電極と高電位の電圧が供給された第1電極との間の静電容量Aと、選択した第2電極と基準電圧が供給された第1電極との間の静電容量Bとの間の容量差(A-B)を検出する。さらに、座標位置演算回路は、選択された第1電極および第2電極の位置と、容量差(A-B)とに基づき観察者のタッチパネルへのタッチ位置を演算する。 The drive circuit sequentially selects two first electrodes from the plurality of first electrodes, supplies a voltage having a higher potential than the reference voltage to one of the two selected first electrodes, and supplies the other to the reference Supply voltage. The detection circuit includes a capacitance A between the selected second electrode and the first electrode supplied with the high potential voltage, and the selected second electrode and the first electrode supplied with the reference voltage. A capacitance difference (A−B) with the capacitance B between the two is detected. Further, the coordinate position calculation circuit calculates the touch position of the observer on the touch panel based on the selected positions of the first electrode and the second electrode and the capacitance difference (AB).
 次に、特許文献2の発明は、タッチパネル上のタッチ位置を検出するタッチセンサ用の信号処理回路であって、駆動回路と、マルチプレクサと、2つの基準容量と、電荷増幅器と、を備えている。
 駆動回路は、基板上の一方向に延びた複数の駆動ラインの中から2本の駆動ラインを選択し、選択された駆動ラインに交流駆動電圧を供給する。また、マルチプレクサは、複数の駆動ラインと交差するように延びた基板上の複数のセンスラインの中から、2本のセンスラインを選択する。
Next, the invention of Patent Document 2 is a signal processing circuit for a touch sensor that detects a touch position on a touch panel, and includes a drive circuit, a multiplexer, two reference capacitors, and a charge amplifier. .
The drive circuit selects two drive lines from a plurality of drive lines extending in one direction on the substrate, and supplies an AC drive voltage to the selected drive lines. Further, the multiplexer selects two sense lines from a plurality of sense lines on the substrate extending so as to intersect with the plurality of drive lines.
 さらに、電荷増幅器は、差動増幅器が使用され、マルチプレクサによって選択された2つのセンスラインと駆動回路により選択された2つの駆動ラインとの間の容量値A1、A2と、2つの基準容量の容量値B1、B2との差に応じた出力電圧を出力する。
 そして、特許文献2の発明の信号処理回路では、電荷増幅器から出力された出力電圧に基づいてタッチ位置を検出する。
Further, the charge amplifier uses a differential amplifier, and has capacitance values A1 and A2 between two sense lines selected by the multiplexer and two drive lines selected by the drive circuit, and two reference capacitances. An output voltage corresponding to the difference between the values B1 and B2 is output.
In the signal processing circuit according to the invention of Patent Document 2, the touch position is detected based on the output voltage output from the charge amplifier.
特開2009-15489号公報Japanese Unexamined Patent Publication No. 2009-15489 特開2010-282539号公報JP 2010-282539 A
 特許文献1に記載の発明によれば、寄生容量をキャンセルして、小さな電極間容量を検出することが可能となり、電極数が多い高分解能のタッチセンサを実現することが可能となる。しかし、タッチパネルに指を触れるときに発生するノイズを軽減(抑圧)することができない。
 これに対して、特許文献2に記載の発明によれば、電荷増幅器で差動増幅を行うので、タッチパネルに指を触れるときに発生するノイズを軽減することができる。しかし、指などの被検出物体が2つの電極のちょうど中間に来た場合に出力が出ず、非タッチ時と区別できないという問題点がある。
According to the invention described in Patent Document 1, it is possible to cancel a parasitic capacitance and detect a small inter-electrode capacitance, and to realize a high-resolution touch sensor with a large number of electrodes. However, noise generated when a finger touches the touch panel cannot be reduced (suppressed).
On the other hand, according to the invention described in Patent Document 2, since differential amplification is performed by the charge amplifier, noise generated when a finger touches the touch panel can be reduced. However, there is a problem that an output is not output when an object to be detected such as a finger comes just between the two electrodes, and it cannot be distinguished from a non-touch time.
 このような背景の下において、タッチセンサの信号処理に関し、新たな信号処理を採用するようにしたタッチセンサの信号処理回路の新たな出現が望まれる。
 さらに、タッチセンサの信号処理回路の新たな出現に際しては、タッチパネルに指を触れるときに発生するノイズを軽減することができる上に、S/Nの向上を図ることが望まれる。
Under such circumstances, a new appearance of the signal processing circuit of the touch sensor that adopts the new signal processing is desired for the signal processing of the touch sensor.
Furthermore, when a signal processing circuit of a touch sensor newly appears, it is desired to reduce noise generated when a finger touches the touch panel and to improve S / N.
 そこで、本発明の目的は、タッチセンサの信号処理に関し、新たな信号処理を採用するようにしたタッチセンサの信号処理回路を提供することにある。
 また、本発明の他の目的は、タッチセンサの信号処理に関し、タッチパネルに指を触れるときに発生するノイズを軽減することができる上に、S/Nの向上を図ることができるようにしたタッチセンサの信号処理回路などを提供することにある。
Therefore, an object of the present invention is to provide a signal processing circuit for a touch sensor that employs new signal processing with respect to the signal processing of the touch sensor.
Another object of the present invention relates to signal processing of a touch sensor, which can reduce noise generated when a finger touches the touch panel and can improve S / N. It is to provide a signal processing circuit of a sensor.
 本発明の一態様は、複数の第1のラインと、前記複数の第1のラインと絶縁層を介して交差するように配置される複数の第2のラインと、を備えるタッチパネルを含むタッチセンサの信号処理回路であって、第1の駆動端子および第2の駆動端子と、第1の検出端子および第2の検出端子と、出力端子とを有し、前記第1の駆動端子および前記第1の検出端子の間に接続された第1の静電容量と、前記第2の駆動端子および前記第1の検出端子の間に接続された第2の静電容量との差を第1の容量差として求め、前記第1の駆動端子および前記第2の検出端子の間に接続された第3の静電容量と、前記第2の駆動端子および前記第2の検出端子の間に接続された第4の静電容量との差を第2の容量差として求め、前記第1の容量差と第2の容量差との差を所定の信号に変換して出力する容量測定回路と、前記複数の第1のラインの中から、1つ以上のラインを第1の駆動ライン群として選択し、または前記第1の駆動ライン群に加えて前記第1の駆動ライン群とは異なる0本以上のラインを第2の駆動ライン群として選択し、前記第1の駆動ライン群を前記第1の駆動端子に接続し、前記第2の駆動ライン群を前記第2の駆動端子に接続し、かつ、前記複数の第2のラインの中から、0本以上のラインを第1の検出ライン群として選択し、前記第1の検出ライン群とは異なる1つ以上のラインを第2の検出ライン群として選択し、前記第1の検出ライン群を前記第1の検出端子に接続し、前記第2の検出ライン群を前記第2の検出端子に接続する選択回路と、を備えることを特徴とするタッチセンサの信号処理回路である。 One embodiment of the present invention is a touch sensor including a touch panel including a plurality of first lines and a plurality of second lines arranged so as to intersect the plurality of first lines via an insulating layer. A signal processing circuit having a first drive terminal and a second drive terminal, a first detection terminal and a second detection terminal, and an output terminal, wherein the first drive terminal and the second drive terminal The difference between the first capacitance connected between one detection terminal and the second capacitance connected between the second drive terminal and the first detection terminal is expressed as a first difference. The capacitance difference is obtained as a third capacitance connected between the first drive terminal and the second detection terminal, and is connected between the second drive terminal and the second detection terminal. The difference from the fourth capacitance is obtained as the second capacitance difference, and the first capacitance difference and the second capacitance difference are obtained. A capacitance measuring circuit that converts a difference from the quantity difference into a predetermined signal and outputs the selected signal, and one or more lines are selected as a first drive line group from the plurality of first lines, or the first In addition to one drive line group, zero or more lines different from the first drive line group are selected as a second drive line group, and the first drive line group is connected to the first drive terminal. And connecting the second drive line group to the second drive terminal and selecting zero or more lines as the first detection line group from the plurality of second lines, One or more lines different from the first detection line group are selected as a second detection line group, the first detection line group is connected to the first detection terminal, and the second detection line group is selected. And a selection circuit for connecting the second detection terminal to the second detection terminal. A signal processing circuit of a touch sensor.
 上記の構成において、前記選択回路は、予め決めてある変換行列に応じて定められた複数の検出パターンのうちの1つの検出パターンが選択されるたびに、当該選択される検出パターンに応じて、前記複数の第2のラインの中から、少なくとも1つのラインを前記第1の駆動ライン群として選択し、前記第1の駆動ライン群とは異なる少なくとも1つのラインを前記第2の駆動ライン群として選択するものであってよい。 In the above configuration, each time the detection circuit is selected from among a plurality of detection patterns determined according to a predetermined conversion matrix, the selection circuit is selected according to the selected detection pattern. At least one line is selected as the first drive line group from the plurality of second lines, and at least one line different from the first drive line group is used as the second drive line group. It may be a choice.
 さらに、前記容量測定回路の出力信号と前記変換行列とを基に演算を行い、前記選択された第1の駆動ライン群と前記選択された第1と第2の各検出ライン群との各交差部における静電容量と、これに対応する、前記選択された第2の駆動ライン群と前記選択された第1と第2の各検出ライン群との各交差部における静電容量との差の静電容量をそれぞれ算出する容量算出回路を、備えていてよい。 Further, an operation is performed based on the output signal of the capacitance measuring circuit and the conversion matrix, and each intersection of the selected first drive line group and the selected first and second detection line groups. And a corresponding difference in capacitance between the selected second drive line group and the selected first and second detection line groups corresponding to each other. Capacitance calculation circuits for calculating the respective capacitances may be provided.
 上記の構成において、前記選択回路は、予め決めてある変換行列に応じて定められた複数の検出パターンのうちの1つの検出パターンが選択されるたびに、当該選択される検出パターンに応じて、前記複数の第1のラインの中から、1つ以上のラインを前記第1の駆動ライン群として選択し、この選択した第1の駆動ライン群を前記第1の駆動端子に接続し、前記第2の駆動端子と前記第1の検出端子の間に予め定めた静電容量値を有する第1のオフセット調整コンデンサを接続し、前記第2の駆動端子と前記第2の検出端子の間に予め定めた静電容量値を有する第2のオフセット調整コンデンサを接続するものであってよい。 In the above configuration, each time the detection circuit is selected from among a plurality of detection patterns determined according to a predetermined conversion matrix, the selection circuit is selected according to the selected detection pattern. One or more lines are selected as the first drive line group from the plurality of first lines, the selected first drive line group is connected to the first drive terminal, and the first drive line group is selected. A first offset adjusting capacitor having a predetermined capacitance value is connected between the second drive terminal and the first detection terminal, and the second drive terminal and the second detection terminal are connected in advance. A second offset adjustment capacitor having a predetermined capacitance value may be connected.
 さらに、前記容量測定回路の出力信号と前記変換行列とを基に演算を行い、前記選択された駆動ラインと前記選択された各検出ラインとの各交差部における静電容量をそれぞれ算出する容量算出回路を、備えていてよい。
 上記の構成において、前記変換行列は、アダマール変換行列であってよい。
 さらに、前記アダマール変換行列はn行×n列からなり(n=2、4の倍数)、前記複数の検出パターンはn個の検出パターンであり、前記選択される第1と第2の検出ライン群に属する全ライン数はn個であってよい。
Further, the calculation of the capacitance is performed based on the output signal of the capacitance measuring circuit and the conversion matrix, and the capacitance at each intersection of the selected drive line and each selected detection line is calculated. A circuit may be provided.
In the above configuration, the transformation matrix may be a Hadamard transformation matrix.
Further, the Hadamard transform matrix has n rows × n columns (n = 2, multiple of 4), the plurality of detection patterns are n detection patterns, and the first and second detection lines to be selected are selected. The total number of lines belonging to the group may be n.
 上記の構成において、前記選択回路は、予め決めてある変換行列に応じて定められた複数の駆動パターンのうちの1つの駆動パターンが選択されるたびに、当該選択される駆動パターンに応じて、前記複数の第1のラインの中から、1つ以上のラインを第1の駆動ライン群として選択し、前記複数の第1のラインの中で前記第1の駆動ライン群とは異なる0本以上のラインを第2の駆動ライン群として選択し、予め決めてある前記変換行列に応じて定められた複数の検出パターンのうちの1つの検出パターンが選択されるたびに、当該選択される検出パターンに応じて、前記複数の第2のラインの中から、1つ以上のラインを第1の検出ライン群として選択し、前記複数の第2のラインの中で前記第1の検出ライン群とは異なる0本以上のラインを第2の検出ライン群として選択するものであってよい。 In the above-described configuration, each time a driving pattern is selected from among a plurality of driving patterns determined according to a predetermined conversion matrix, the selection circuit according to the selected driving pattern, One or more lines are selected as a first drive line group from among the plurality of first lines, and zero or more different from the first drive line group among the plurality of first lines. Is selected as the second drive line group, and each time one detection pattern is selected from among a plurality of detection patterns determined according to the predetermined conversion matrix, the selected detection pattern Accordingly, one or more lines are selected as a first detection line group from the plurality of second lines, and the first detection line group is the first detection line group among the plurality of second lines. 0 or more different It may be one that selects the in as second detection line group.
 さらに、前記容量測定回路の出力信号と前記変換行列とを基に演算を行い、前記複数の第1のラインと前記複数の第2ラインとの交差部に形成される容量マトリクスのそれぞれの静電容量を算出する容量算出回路を、備えていてよい。
 上記の構成において、前記変換行列は、アダマール変換行列であってよい。
Further, an operation is performed based on the output signal of the capacitance measuring circuit and the conversion matrix, and each capacitance of the capacitance matrix formed at the intersection of the plurality of first lines and the plurality of second lines is calculated. A capacity calculation circuit for calculating the capacity may be provided.
In the above configuration, the transformation matrix may be a Hadamard transformation matrix.
 さらに、前記アダマール変換行列が、第1の方向にm行×m列(m=2、4の倍数)、第2の方向にn行×n列(n=2、4の倍数)の場合には、前記駆動パターンおよび前記検出パターンの組み合わせは(m×n)個となり、各駆動パターンおよび検出パターンに応じて、前記選択される第1と第2の駆動ライン群に属する全ライン数はm個、前記選択される第1と第2の検出ラインに属する全ライン数はn個であってよい。 Further, when the Hadamard transform matrix is m rows × m columns (m = 2, a multiple of 4) in the first direction and n rows × n columns (n = 2, a multiple of 4) in the second direction. The combination of the drive pattern and the detection pattern is (m × n), and the total number of lines belonging to the selected first and second drive line groups is m according to each drive pattern and detection pattern. The total number of lines belonging to the selected first and second detection lines may be n.
 上記の構成において、前記選択回路は、前記複数の駆動パターンごとに、前記第1の駆動端子に接続するラインおよび前記第2の駆動端子に接続するラインを変更し、前記第1の駆動端子および第2の駆動端子に接続するラインの変更に応じて、前記第1の検出端子に接続するラインおよび前記第2の検出端子に接続するラインを変更するものであってよい。 In the above configuration, the selection circuit changes, for each of the plurality of drive patterns, a line connected to the first drive terminal and a line connected to the second drive terminal, and the first drive terminal and The line connected to the first detection terminal and the line connected to the second detection terminal may be changed according to the change of the line connected to the second drive terminal.
 上記の構成において、前記選択回路は、前記第1の駆動端子に接続するラインとして選択したラインの前記第1の駆動端子への接続を前記第1の検出端子への接続に変更し、前記第2の駆動端子に接続するラインとして選択したラインの前記第2の駆動端子への接続を前記第2の検出端子への接続に変更し前記第1の検出端子に接続するラインとして選択したラインの前記第1の検出端子への接続を前記第1の駆動端子への接続に変更し、前記第2の検出端子に接続するラインとして選択したラインの前記第2の検出端子への接続を第2の駆動端子への接続に変更するものであってよい。 In the above configuration, the selection circuit changes the connection of the line selected as the line connected to the first drive terminal to the first drive terminal to the connection to the first detection terminal, and The connection of the line selected as the line connected to the second drive terminal to the connection to the second detection terminal is changed to the connection to the second detection terminal, and the line selected as the line connected to the first detection terminal is changed. The connection to the first detection terminal is changed to the connection to the first drive terminal, and the connection to the second detection terminal of the line selected as the line to be connected to the second detection terminal is changed to the second. The connection to the drive terminal may be changed.
 上記の構成において、前記変換行列は、第1の変換行列と第2の変換行列とを使用し且つ、前記第1の変換行列および第2の変換行列のいずれか一方は、前記複数の第1のラインの個数以上のサイズの第1の変換行列であるかまたは前記複数の第2のラインの個数以上のサイズの第2の変換行列であって、前記複数の検出パターンは、前記第1の変換行列と前記第2の変換行列とを基に予め定め、且つ前記第1の変換行列のサイズが前記複数の第1のラインの個数以上のサイズである場合には、前記第1の変換行列の行ベクトルまたは列ベクトルの一部を除いた第3の変換行列を前記第1の変換行列として用い、前記第2の変換行列のサイズが前記複数の第2のラインの個数以上のサイズである場合には、前記第2の変換行列の行ベクトルまたは列ベクトルの一部を除いた第4の変換行列を前記第2の変換行列として用いて予め定め、前記容量算出部は、前記第1の変換行列および前記第2の変換行列の各転置行列またはそれらの各一般化逆行列を使用するものであってよい。 In the above configuration, the transformation matrix uses a first transformation matrix and a second transformation matrix, and any one of the first transformation matrix and the second transformation matrix is the plurality of first transformation matrices. A first transformation matrix having a size greater than or equal to the number of lines, or a second transformation matrix having a size greater than or equal to the number of the plurality of second lines, wherein the plurality of detection patterns are the first transformation matrix. In the case where the first transformation matrix is predetermined based on the transformation matrix and the second transformation matrix and the size of the first transformation matrix is equal to or larger than the number of the plurality of first lines, the first transformation matrix A third transformation matrix excluding a part of the row vector or column vector is used as the first transformation matrix, and the size of the second transformation matrix is larger than the number of the plurality of second lines. If the row vector of the second transformation matrix Alternatively, a fourth transformation matrix excluding a part of a column vector is used as the second transformation matrix, and the capacity calculation unit performs each transposition of the first transformation matrix and the second transformation matrix. Matrixes or their respective generalized inverses may be used.
 上記の構成において、前記容量算出回路で算出した各静電容量に基づいて前記タッチパネル上のタッチ位置を検出するタッチ位置検出回路を、さらに備えていてよい。
 上記の構成において、前記変換行列は、前記複数の第1のラインまたは前記複数の第2のラインの個数以上のサイズの変換行列を使用し、前記複数の検出パターンは、前記変換行列の行ベクトルまたは列ベクトルの一部を除いて行数または列数を前記複数の第1のラインまたは前記複数の第2のラインの個数に一致させた行列を基に予め定め、前記容量算出回路は、前記行列の転置行列または一般化逆行列を使用するものであってよい。
The above configuration may further include a touch position detection circuit that detects a touch position on the touch panel based on each capacitance calculated by the capacitance calculation circuit.
In the above configuration, the transformation matrix uses a transformation matrix having a size equal to or larger than the number of the plurality of first lines or the plurality of second lines, and the plurality of detection patterns are row vectors of the transformation matrix. Alternatively, excluding a part of the column vector, the number of rows or the number of columns is predetermined based on a matrix in which the number of the first lines or the plurality of second lines is matched, and the capacitance calculation circuit includes It may use a transpose of the matrix or a generalized inverse matrix.
 上記の構成において、前記容量算出回路は、前記複数の検出パターンのうち所定の検出パターンのときには、前記容量測定回路の出力信号を0として処理するものであってよい。
 上記の構成において、前記容量算出回路は、前記複数の検出パターンおよび駆動パターンのうち所定の検出パターンおよび駆動パターンのときには、前記容量測定回路の出力信号を0として処理するものであってよい。
In the above configuration, the capacitance calculation circuit may process the output signal of the capacitance measurement circuit as 0 when the detection pattern is a predetermined detection pattern among the plurality of detection patterns.
In the above configuration, the capacitance calculation circuit may process the output signal of the capacitance measurement circuit as 0 when a predetermined detection pattern and drive pattern among the plurality of detection patterns and drive patterns.
 本発明の他の態様は、複数の第1のラインと、前記複数の第1のラインと絶縁層を介して交差するように配置される複数の第2のラインと、を備えるタッチパネルを含むタッチセンサの信号処理回路であって、第1の駆動端子および第2の駆動端子と、検出端子と、出力端子とを有し、前記第1の駆動端子および前記検出端子の間に接続された第1の静電容量と、前記第2の駆動端子および前記検出端子の間に接続された第2の静電容量との差を所定の信号に変換して出力する容量測定回路と、予め決めてある変換行列に応じて定められた複数の駆動パターンのうちの1つの駆動パターンが選択されるたびに、当該選択される駆動パターンに応じて、前記複数の第1のラインの中から、1つ以上のラインを第1の駆動ライン群として選択し、または前記第1の駆動ライン群に加えて前記第1の駆動ライン群とは異なる0本以上のラインを第2の駆動ライン群として選択し、前記第1の駆動ライン群を前記第1の駆動端子に接続し、前記第2の駆動ライン群を前記第2の駆動端子に接続し、かつ、前記複数の第2のラインの中から、1つ以上のラインを検出ライン群として選択し、前記検出ライン群を前記検出端子に接続する選択回路と、前記容量測定回路が検出した各所定の信号と前記変換行列とを基に演算を行い、前記選択された駆動ラインと前記選択された各検出ラインとの各交差部における静電容量をそれぞれ算出する容量算出回路と、を備えることを特徴とするタッチセンサの信号処理回路である。 Another aspect of the present invention includes a touch panel including a plurality of first lines and a plurality of second lines arranged so as to intersect the plurality of first lines via an insulating layer. A sensor signal processing circuit having a first drive terminal and a second drive terminal, a detection terminal, and an output terminal, the first drive terminal being connected between the first drive terminal and the detection terminal A capacitance measuring circuit that converts a difference between the first capacitance and the second capacitance connected between the second drive terminal and the detection terminal into a predetermined signal and outputs the predetermined signal; Each time one drive pattern is selected from among a plurality of drive patterns determined according to a certain transformation matrix, one of the plurality of first lines is selected according to the selected drive pattern. Select these lines as the first drive line group. Alternatively, in addition to the first drive line group, zero or more lines different from the first drive line group are selected as the second drive line group, and the first drive line group is selected as the first drive line group. Connecting to the terminal, connecting the second drive line group to the second drive terminal, and selecting one or more lines as a detection line group from the plurality of second lines, A selection circuit that connects a detection line group to the detection terminal, each predetermined signal detected by the capacitance measurement circuit, and the conversion matrix are used to perform an operation, and the selected drive line and each selected detection A signal processing circuit for a touch sensor, comprising: a capacitance calculation circuit that calculates a capacitance at each intersection with the line.
 上記の構成において、前記変換行列は、アダマール変換行列であってよい。
 さらに、前記アダマール変換行列はn行×n列からなり(n=2、4の倍数)、前記複数の検出パターンはn個の駆動パターンであり、前記選択される第1と第2の駆動ライン群に属する全ライン数はn個であってよい。
 上記の構成において、前記容量算出回路で算出した各静電容量に基づいて前記タッチパネル上のタッチ位置を検出するタッチ位置検出回路を、さらに備えていてよい。
In the above configuration, the transformation matrix may be a Hadamard transformation matrix.
Further, the Hadamard transform matrix is composed of n rows × n columns (n = 2, a multiple of 4), the plurality of detection patterns are n drive patterns, and the selected first and second drive lines are selected. The total number of lines belonging to the group may be n.
The above configuration may further include a touch position detection circuit that detects a touch position on the touch panel based on each capacitance calculated by the capacitance calculation circuit.
 上記の構成において、前記変換行列は、前記複数の第1のラインまたは前記複数の第2のラインの個数以上のサイズの変換行列を使用し、前記複数の検出パターンは、前記変換行列の行ベクトルまたは列ベクトルの一部を除いて行数または列数を前記複数の第1のラインまたは前記複数の第2のラインの個数に一致させた行列を基に予め定め、前記容量算出回路は、前記行列の転置行列または一般化逆行列を使用するものであってよい。 In the above configuration, the transformation matrix uses a transformation matrix having a size equal to or larger than the number of the plurality of first lines or the plurality of second lines, and the plurality of detection patterns are row vectors of the transformation matrix. Alternatively, excluding a part of the column vector, the number of rows or the number of columns is predetermined based on a matrix in which the number of the first lines or the plurality of second lines is matched, and the capacitance calculation circuit includes It may use a transpose of the matrix or a generalized inverse matrix.
 上記の構成において、前記容量算出回路は、前記複数の駆動パターンのうち所定の駆動パターンのときには、前記容量測定回路の出力信号を0として処理するものであってよい。
 本発明の他の態様は、上記態様のいずれかに記載のタッチセンサの信号処理回路を備えることを特徴とするタッチセンサである。
In the above configuration, the capacitance calculation circuit may process the output signal of the capacitance measurement circuit as 0 when the drive pattern is a predetermined drive pattern among the plurality of drive patterns.
Another aspect of the present invention is a touch sensor comprising the touch sensor signal processing circuit according to any one of the above aspects.
 本発明の他の態様は、複数の第1のライン及び前記複数の第1のラインと絶縁層を介して交差するように配置される複数の第2のラインを備えるタッチパネルと、駆動電圧を出力する第1の出力端子及び第2の出力端子を有する駆動回路と、第1の入力端子の入力電圧に応じた第1の電圧と第2の入力端子の入力電圧に応じた第2の電圧との差分電圧を検出する電圧検出回路と、前記複数の第1のラインと前記駆動回路の第1の出力端子または第2の出力端子との間の選択的な接続と、前記複数の第2のラインと前記電圧検出回路の第1の入力端子または第2の入力端子との間の選択的な接続を行う選択回路と、を含むタッチセンサの信号処理方法であって、コンピュータが、予め決めてある変換行列に応じて定められた複数のパターンのうちの1つのパターンを選択し、当該選択されたパターンに応じて、前記複数の第1のラインの中から、1つ以上のラインを第1の駆動ライン群として選択し、または前記第1の駆動ライン群に加えて前記第1の駆動ライン群とは異なる0本以上のラインを第2の駆動ライン群として選択し、前記第1の駆動ライン群を前記駆動回路の第1の出力端子に接続し、前記第2の駆動ライン群を前記駆動回路の第2の出力端子に接続するように、前記選択回路の動作を制御する第1ステップと、前記複数の第2のラインの中から、1つ以上のラインを第1の検出ライン群として選択し、前記第1の検出ライン群とは異なる0本以上のラインを第2の検出ライン群として選択し、前記第1の検出ライン群を前記電圧検出回路の第1の入力端子に接続し、前記第2の検出ライン群を前記電圧検出回路の第2の入力端子に接続するように、前記選択回路の動作を制御する第2ステップと、前記駆動回路が所定の駆動電圧を出力するように前記駆動回路の動作を制御し、前記電圧検出回路が前記差分電圧を検出するように前記電圧検出回路の動作を制御する第3ステップと、前記電圧検出回路の出力信号と前記変換行列とを基に演算を行い、前記選択された駆動ラインと前記選択された各検出ラインとの各交差部における静電容量をそれぞれ算出する第4ステップと、を実行することを特徴とするタッチセンサの信号処理方法である。 According to another aspect of the present invention, there is provided a touch panel including a plurality of first lines and a plurality of second lines arranged so as to intersect the plurality of first lines via an insulating layer, and outputs a driving voltage. A driving circuit having a first output terminal and a second output terminal, a first voltage corresponding to the input voltage of the first input terminal, and a second voltage corresponding to the input voltage of the second input terminal; A voltage detection circuit that detects a differential voltage of the first circuit, a selective connection between the plurality of first lines and a first output terminal or a second output terminal of the drive circuit, and the plurality of second lines. A signal processing method of a touch sensor, including a selection circuit that performs selective connection between a line and a first input terminal or a second input terminal of the voltage detection circuit, wherein the computer determines in advance Multiple patterns defined according to a certain transformation matrix One pattern is selected, and one or more lines are selected as a first drive line group from the plurality of first lines according to the selected pattern, or the first drive is selected. In addition to the line group, zero or more lines different from the first drive line group are selected as the second drive line group, and the first drive line group is connected to the first output terminal of the drive circuit. The first step of controlling the operation of the selection circuit so as to connect the second drive line group to the second output terminal of the drive circuit, and among the plurality of second lines, 1 One or more lines are selected as a first detection line group, zero or more lines different from the first detection line group are selected as a second detection line group, and the first detection line group is selected as the first detection line group. Connect to the first input terminal of the voltage detection circuit A second step of controlling the operation of the selection circuit so as to connect the second detection line group to a second input terminal of the voltage detection circuit; and the drive circuit outputting a predetermined drive voltage. Based on the third step of controlling the operation of the drive circuit and controlling the operation of the voltage detection circuit so that the voltage detection circuit detects the differential voltage, the output signal of the voltage detection circuit, and the conversion matrix. And a fourth step of calculating a capacitance at each intersection of the selected drive line and each selected detection line, respectively, and performing signal processing of the touch sensor Is the method.
 上記の構成において、前記第1ステップでは、前記複数のパターンごとに、前記複数の第1のラインと前記複数の第2のラインとを前記第1の駆動ライン群および前記第2の駆動ライン群として選択するのを変更し、前記第2ステップでは、前記第1ステップでの変更に応じて、前記複数の第1のラインと前記複数の第2のラインとを前記第1の検出ライン群および前記第2の検出ライン群として選択するのを変更するものであってよい。 In the above-described configuration, in the first step, the plurality of first lines and the plurality of second lines are divided into the first drive line group and the second drive line group for each of the plurality of patterns. In the second step, the plurality of first lines and the plurality of second lines are changed to the first detection line group and the second step in response to the change in the first step. The selection as the second detection line group may be changed.
 上記の構成において、前記複数のパターンのうちの所定のパターンのときには、前記第1ステップでは、前記選択した第1の駆動ライン群の前記駆動回路の第1の出力端子への接続を前記電圧検出回路の第1の入力端子への接続に変更し、前記選択した第2の駆動ライン群の前記駆動回路の第2の出力端子への接続を前記電圧検出回路の第2の入力端子への接続に変更し、前記第2ステップでは、前記選択した第1の検出ライン群の前記電圧検出回路の第1の入力端子への接続を前記駆動回路の第1の出力端子への接続に変更し、前記選択した第2の検出ライン群の前記電圧検出回路の第2の入力端子への接続を前記駆動回路の第2の出力端子への接続に変更するものであってよい。 In the above configuration, when the predetermined pattern is the plurality of patterns, in the first step, the voltage detection is performed by connecting the selected first drive line group to the first output terminal of the drive circuit. The connection is changed to the connection to the first input terminal of the circuit, and the connection of the selected second drive line group to the second output terminal of the drive circuit is connected to the second input terminal of the voltage detection circuit. In the second step, the connection of the selected first detection line group to the first input terminal of the voltage detection circuit is changed to the connection to the first output terminal of the drive circuit, The connection of the selected second detection line group to the second input terminal of the voltage detection circuit may be changed to the connection to the second output terminal of the drive circuit.
 さらに、前記複数のパターンのうち所定のパターンのときには、前記第1ステップから前記第3ステップまでの各処理を省略し、前記第4ステップにおいて前記電圧検出回路の出力信号を0として処理するものであってよい。
 上記の構成において、前記変換行列は、前記複数の第1のラインまたは前記複数の第2のラインの個数以上のサイズの変換行列を使用し、前記複数のパターンは、前記変換行列の行ベクトルまたは列ベクトルの一部を除いて行数または列数を前記複数の第1のラインまたは前記複数の第2のラインの個数に一致させた行列を基に予め定め、前記第1ステップと前記第2ステップの各処理では、前記定められている複数の検出パターンを使用し、前記第4ステップの処理では、前記行列の転置行列または一般化逆行列を使用してよい。
Further, when the pattern is a predetermined pattern among the plurality of patterns, the processes from the first step to the third step are omitted, and the output signal of the voltage detection circuit is processed as 0 in the fourth step. It may be.
In the above configuration, the transformation matrix uses a transformation matrix having a size equal to or larger than the number of the plurality of first lines or the plurality of second lines, and the plurality of patterns include a row vector of the transformation matrix or Excluding a part of the column vector, the number of rows or the number of columns is determined in advance based on a matrix in which the number of the plurality of first lines or the plurality of second lines is matched, and the first step and the second step In each process of the step, the plurality of predetermined detection patterns may be used, and in the process of the fourth step, a transposed matrix or a generalized inverse matrix of the matrix may be used.
 上記の構成において、前記変換行列は、第1の変換行列と第2の変換行列とを使用し且つ、前記第1の変換行列および第2の変換行列のいずれか一方は、前記複数の第1のラインの個数以上のサイズの第1の変換行列であるかまたは前記複数の第2のラインの個数以上のサイズの第2の変換行列であって、前記複数のパターンは、前記第1の変換行列と前記第2の変換行列とを基に予め定め、且つ前記第1の変換行列のサイズが前記複数の第1のラインの個数以上のサイズである場合には、前記第1の変換行列の行ベクトルまたは列ベクトルの一部を除いた第3の変換行列を前記第1の変換行列として用い、前記第2の変換行列のサイズが前記複数の第2のラインの個数以上のサイズである場合には、前記第2の変換行列の行ベクトルまたは列ベクトルの一部を除いた第4の変換行列を前記第2の変換行列として用いて予め定め、前記第1ステップと前記第2ステップの各処理では、前記第1の変換行列および第2の変換行列によって定められている複数のパターンを使用し、前記第4ステップの処理では、前記第1の変換行列および前記第2の変換行列の各転置行列またはそれらの各一般化逆行列を使用してよい。 In the above configuration, the transformation matrix uses a first transformation matrix and a second transformation matrix, and any one of the first transformation matrix and the second transformation matrix is the plurality of first transformation matrices. A first transformation matrix having a size greater than or equal to the number of lines, or a second transformation matrix having a size greater than or equal to the number of the plurality of second lines, wherein the plurality of patterns are the first transformation matrix. In the case where the first transformation matrix is predetermined based on the matrix and the second transformation matrix and the size of the first transformation matrix is equal to or larger than the number of the plurality of first lines, When a third transformation matrix excluding a part of a row vector or column vector is used as the first transformation matrix, and the size of the second transformation matrix is larger than the number of the plurality of second lines. Includes a row vector of the second transformation matrix or A fourth transformation matrix excluding a part of the column vector is used as the second transformation matrix in advance, and in each process of the first step and the second step, the first transformation matrix and the second transformation matrix A plurality of patterns defined by a transformation matrix are used, and the transposition matrix of each of the first transformation matrix and the second transformation matrix or their respective generalized inverse matrix is used in the processing of the fourth step. It's okay.
 上記の構成において、前記変換行列は、アダマール変換行列であってよい。
 本発明の他の態様は、上記態様に記載のタッチセンサの信号処理方法における各ステップを、コンピュータに実行させることを特徴とするタッチセンサの信号処理プログラムである。
In the above configuration, the transformation matrix may be a Hadamard transformation matrix.
Another aspect of the present invention is a touch sensor signal processing program that causes a computer to execute each step in the touch sensor signal processing method described in the above aspect.
 本発明によれば、タッチセンサの信号処理に関し、新たな信号処理を採用するようにしたタッチセンサの信号処理回路を提供することにある。
 また、本発明によれば、タッチパネルの信号処理に関し、タッチパネルに指を触れるときに発生するノイズを軽減することができる上に、S/Nの向上を図ることができる。
According to the present invention, there is provided a signal processing circuit for a touch sensor that employs a new signal processing for the signal processing of the touch sensor.
Further, according to the present invention, regarding signal processing of the touch panel, noise generated when a finger touches the touch panel can be reduced, and S / N can be improved.
本発明の第1実施形態が適用されるタッチセンサの構成を示すブロック図である。It is a block diagram which shows the structure of the touch sensor to which 1st Embodiment of this invention is applied. 第1実施形態の選択回路の具体的な構成を示す回路図である。It is a circuit diagram which shows the specific structure of the selection circuit of 1st Embodiment. 第1実施形態の駆動部の具体的な構成を示す回路図である。It is a circuit diagram which shows the specific structure of the drive part of 1st Embodiment. 第1実施形態の電圧検出回路の具体的な構成を示す回路図である。It is a circuit diagram which shows the specific structure of the voltage detection circuit of 1st Embodiment. 駆動回路および電圧検出回路の状態1、2の動作のタイミングと、そのときのスイッチのオンオフ状態を示す図である。It is a figure which shows the timing of the operation | movement of the states 1 and 2 of a drive circuit and a voltage detection circuit, and the ON / OFF state of the switch at that time. 駆動回路および電圧検出回路の状態1~4の動作のタイミングと、そのときのスイッチのオンオフ状態を示す図である。FIG. 5 is a diagram illustrating the timing of operations in states 1 to 4 of the drive circuit and the voltage detection circuit, and the on / off states of the switches at that time. 駆動回路および電圧検出回路の状態1~4の動作と、これに対応するスイッチのオンオフ状態との関係をまとめた図である。FIG. 6 is a diagram summarizing the relationship between the operation of states 1 to 4 of the drive circuit and the voltage detection circuit and the on / off states of the corresponding switches. 第1実施形態の駆動回路と電圧検出回路の動作を説明する説明図である。It is explanatory drawing explaining operation | movement of the drive circuit and voltage detection circuit of 1st Embodiment. 第1実施形態の検出パターン1~4と、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。FIG. 4 is a diagram showing detection patterns 1 to 4 according to the first embodiment and the connection relationship between the corresponding drive circuit and voltage detection circuit and each line. 第1実施形態の検出パターン5~8と、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。FIG. 6 is a diagram illustrating detection patterns 5 to 8 according to the first embodiment and a connection relationship between the corresponding drive circuit and voltage detection circuit and each line. 本発明の第2実施形態が適用されるタッチセンサの構成を示すブロック図である。It is a block diagram which shows the structure of the touch sensor to which 2nd Embodiment of this invention is applied. 第2実施形態の静電容量回路の具体的な構成を示す回路図である。It is a circuit diagram which shows the specific structure of the electrostatic capacitance circuit of 2nd Embodiment. 第2実施形態の検出パターン1~4と、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。FIG. 10 is a diagram showing detection patterns 1 to 4 according to the second embodiment and the connection relationship between the corresponding drive circuit and voltage detection circuit and each line. 第2実施形態の検出パターン5~8と、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。FIG. 10 is a diagram illustrating detection patterns 5 to 8 according to the second embodiment and a connection relationship between the corresponding drive circuit and voltage detection circuit and each line. 第2実施形態の変形例を説明する図である。It is a figure explaining the modification of 2nd Embodiment. 本発明の第3実施形態が適用されるタッチセンサの構成を示すブロック図である。It is a block diagram which shows the structure of the touch sensor to which 3rd Embodiment of this invention is applied. 第3実施形態の静電容量回路の具体的な構成を示す回路図である。It is a circuit diagram which shows the specific structure of the electrostatic capacitance circuit of 3rd Embodiment. 第3実施形態の駆動パターン1~4と、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。FIG. 10 is a diagram showing drive patterns 1 to 4 according to the third embodiment and the connection relationship between the corresponding drive circuit and voltage detection circuit and each line. 第3実施形態の駆動パターン5~8と、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。FIG. 10 is a diagram illustrating drive patterns 5 to 8 according to the third embodiment and the connection relationship between the corresponding drive circuit and voltage detection circuit and each line. 本発明の第4実施形態が適用されるタッチセンサの構成を示すブロック図である。It is a block diagram which shows the structure of the touch sensor to which 4th Embodiment of this invention is applied. 第4実施形態の1つ目の8つの変換パターンのうちの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows the connection relationship of four lines among the eight conversion patterns of the 1st of 4th Embodiment, the drive circuit corresponding to it, and a voltage detection circuit, and each line. 第4実施形態の1つ目の8つの変換パターンのうちの残りの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows the remaining 4 of the 1st 8 conversion patterns of 4th Embodiment, the drive circuit corresponding to it, a voltage detection circuit, and the connection relation of each line. 第4実施形態の2つ目の8つの変換パターンのうちの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows the connection relationship of four lines among the eight conversion patterns of the 2nd of 4th Embodiment, the drive circuit corresponding to it, and a voltage detection circuit, and each line. 第4実施形態の2つ目の8つの変換パターンのうちの残りの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows remaining 4 of the 2nd 8 conversion patterns of 4th Embodiment, and the connection relationship of the drive circuit and voltage detection circuit corresponding to it, and each line. 第4実施形態の3つ目の8つの変換パターンのうちの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows the connection relationship of four lines among the eight 8th conversion patterns of 4th Embodiment, the drive circuit corresponding to it, a voltage detection circuit, and each line. 第4実施形態の3つ目の8つの変換パターンのうちの残りの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows the remaining 4 of the 3rd 8 conversion patterns of 4th Embodiment, the drive circuit corresponding to it, and the connection relationship of a voltage detection circuit and each line. 第4実施形態の4つ目の8つの変換パターンのうちの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows the connection relationship of four lines among the four 8th conversion patterns of 4th Embodiment, the drive circuit corresponding to it, a voltage detection circuit, and each line. 第4実施形態の4つ目の8つの変換パターンのうちの残りの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows the remaining 4 of the 4th 8 conversion patterns of 4th Embodiment, the drive circuit corresponding to it, a voltage detection circuit, and the connection relationship of each line. 第4実施形態の5つ目の8つの変換パターンのうちの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows the connection relationship of four lines among the eight 8th conversion patterns of 4th Embodiment, the drive circuit corresponding to it, a voltage detection circuit, and each line. 第4実施形態の5つ目の8つの変換パターンのうちの残りの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows the remaining 4 of the 5th 8 conversion patterns of 4th Embodiment, the drive circuit corresponding to it, and the connection relationship of a voltage detection circuit and each line. 第4実施形態の6つ目の8つの変換パターンのうちの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows the connection relationship of four lines among the eight 8th conversion patterns of 4th Embodiment, the drive circuit corresponding to it, and a voltage detection circuit, and each line. 第4実施形態の6つ目の8つの変換パターンのうちの残りの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows the remaining 4 of the 6th 8 conversion patterns of 4th Embodiment, the drive circuit corresponding to it, a voltage detection circuit, and the connection relation of each line. 第4実施形態の7つ目の8つの変換パターンのうちの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows the connection relation of four lines among the eight 8th conversion patterns of 4th Embodiment, the drive circuit corresponding to it, and a voltage detection circuit, and each line. 第4実施形態の7つ目の8つの変換パターンのうちの残りの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows remaining 4 of the 8th conversion patterns of the 7th of 4th Embodiment, and the connection relationship of a drive circuit and voltage detection circuit corresponding to it, and each line. 第4実施形態の8つ目の8つの変換パターンのうちの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows the connection relation of four lines among the eight 8th conversion patterns of 4th Embodiment, the drive circuit corresponding to it, and a voltage detection circuit, and each line. 第4実施形態の8つ目の8つの変換パターンのうちの残りの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows the remaining 4 of the 8 8th conversion patterns of 4th Embodiment, and the connection relationship of the drive circuit and voltage detection circuit corresponding to it, and each line. 第4実施形態の変形例1の8つの変換パターンのうちの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows the connection relationship of four among the eight conversion patterns of the modification 1 of 4th Embodiment, and the drive circuit and voltage detection circuit corresponding to it. 第4実施形態の変形例1の8つの変換パターンのうちの残りの4つと、それに対応する駆動回路および電圧検出回路と各ラインの接続関係を示す図である。It is a figure which shows the remaining 4 of the 8 conversion patterns of the modification 1 of 4th Embodiment, and the connection relationship of a drive circuit and voltage detection circuit corresponding to it, and each line. 本発明の第5実施形態のコンピュータによる制御、演算の処理手順の一例を示すフローチャートである。It is a flowchart which shows an example of the process sequence of the control by the computer of 5th Embodiment of this invention, and a calculation.
 以下、本発明の実施形態について図面を参照して説明する。
(第1実施形態の構成)
 図1は、本発明の第1実施形態が適用されるタッチセンサの構成を示すブロック図である。
 第1実施形態が適用されるタッチセンサは、図1に示すように、タッチパネル1と、選択回路2と、駆動回路3と、電圧検出回路4と、A/D変換回路5と、容量算出回路6と、タッチ位置検出回路7と、制御回路8と、アドレス生成回路9と、メモリ10と、ラッチ11と、を備えている。
Embodiments of the present invention will be described below with reference to the drawings.
(Configuration of the first embodiment)
FIG. 1 is a block diagram showing a configuration of a touch sensor to which the first embodiment of the present invention is applied.
As shown in FIG. 1, the touch sensor to which the first embodiment is applied includes a touch panel 1, a selection circuit 2, a drive circuit 3, a voltage detection circuit 4, an A / D conversion circuit 5, and a capacitance calculation circuit. 6, a touch position detection circuit 7, a control circuit 8, an address generation circuit 9, a memory 10, and a latch 11.
 タッチパネル1は、ガラスなどからなる基板(図示せず)で形成され、その基板上に、例えば8本のXラインX1~X8がX方向に所定の間隔で配置される。また、その基板上に、XラインX1~X8と絶縁層を介して交差するように、例えば8本のYラインY1~Y8がY方向に所定の間隔で配置される。このため、XラインX1~X8とYラインY1~Y8とは絶縁層を介して互いに絶縁され、かつ容量結合している。 The touch panel 1 is formed of a substrate (not shown) made of glass or the like, and, for example, eight X lines X1 to X8 are arranged on the substrate at predetermined intervals in the X direction. On the substrate, for example, eight Y lines Y1 to Y8 are arranged at predetermined intervals in the Y direction so as to intersect the X lines X1 to X8 via an insulating layer. For this reason, the X lines X1 to X8 and the Y lines Y1 to Y8 are insulated from each other via an insulating layer and capacitively coupled.
 選択回路2は、例えば、タッチパネル1のYラインY1~Y8のうちの2つを駆動ラインとして選択し、この選択した2つの駆動ラインを駆動回路3と接続する。また、選択回路2は、タッチパネル1のXラインX1~X8のうちの少なくとも2つを検出ラインとして選択し、その一部を電圧検出回路4の一方の入力端子(検出端子)と接続し、その残りを電圧検出回路4の他方の入力端子(検出端子)と接続する。 The selection circuit 2 selects, for example, two of the Y lines Y1 to Y8 of the touch panel 1 as drive lines, and connects the selected two drive lines to the drive circuit 3. The selection circuit 2 selects at least two of the X lines X1 to X8 of the touch panel 1 as detection lines, connects a part thereof to one input terminal (detection terminal) of the voltage detection circuit 4, and The rest is connected to the other input terminal (detection terminal) of the voltage detection circuit 4.
 駆動回路3は、後述のように電圧値(振幅)が変化する電圧を生成し、この生成した電圧を、選択回路2で駆動ラインとして選択された2つのラインに、駆動電圧として供給する。
 電圧検出回路4は、選択回路2がXラインX1~X8のうちの少なくとも2つを検出ラインとして選択し、この選択した検出ラインが2つの入力端子に接続されたときに、その接続に応じた電圧を出力電圧として出力する。
The drive circuit 3 generates a voltage whose voltage value (amplitude) changes as will be described later, and supplies the generated voltage as a drive voltage to the two lines selected as the drive lines by the selection circuit 2.
In the voltage detection circuit 4, when the selection circuit 2 selects at least two of the X lines X1 to X8 as detection lines, and the selected detection lines are connected to the two input terminals, the voltage detection circuit 4 corresponds to the connection. The voltage is output as the output voltage.
 A/D変換回路5は、電圧検出回路4の出力電圧をA/D変換し、このA/D変換した電圧を容量算出回路6に出力する。
 容量算出回路6は、後述のように、A/D変換回路5でA/D変換された電圧検出回路4の各出力電圧と、所定の変換行列とを基に演算を行う。そして、選択回路2で選択された一方の駆動ラインと選択回路2で選択された各検出ラインとの各交差部における静電容量と、選択回路2で選択された他方の駆動ラインと選択回路2で選択された各検出ラインとの各交差部における静電容量との差の静電容量をそれぞれ算出する。
The A / D conversion circuit 5 A / D converts the output voltage of the voltage detection circuit 4 and outputs the A / D converted voltage to the capacitance calculation circuit 6.
As will be described later, the capacity calculation circuit 6 performs an operation based on each output voltage of the voltage detection circuit 4 A / D converted by the A / D conversion circuit 5 and a predetermined conversion matrix. The capacitance at each intersection of one drive line selected by the selection circuit 2 and each detection line selected by the selection circuit 2, the other drive line selected by the selection circuit 2, and the selection circuit 2 The capacitances of the differences from the capacitances at the intersections with the respective detection lines selected in (1) are calculated.
 タッチ位置検出回路7は、容量算出回路6が算出した各静電容量に基づいて、タッチパネル1のタッチ位置を検出する。
 制御回路8は、タッチパネル1のタッチ位置を検出するときに、駆動回路3、電圧検出回路4、アドレス生成回路9、およびラッチ11を後述のようにそれぞれ制御する。
 アドレス生成回路9は、制御回路8からの指示に基づき、メモリ10に格納される選択回路2の動作を制御するための設定データを読み出すためのアドレスを生成する。
 メモリ10には、タッチパネル1のタッチ位置を検出するときに、その検出手順に応じて選択回路2の後述のスイッチをオンオフ制御するデータが、予め格納されている。
 ラッチ11は、選択回路2の後述のスイッチをオンオフ制御する場合に、メモリ10から読み出される設定データを一時的に格納する。
The touch position detection circuit 7 detects the touch position of the touch panel 1 based on each capacitance calculated by the capacitance calculation circuit 6.
When detecting the touch position of the touch panel 1, the control circuit 8 controls the driving circuit 3, the voltage detection circuit 4, the address generation circuit 9, and the latch 11 as described later.
The address generation circuit 9 generates an address for reading setting data for controlling the operation of the selection circuit 2 stored in the memory 10 based on an instruction from the control circuit 8.
In the memory 10, when detecting the touch position of the touch panel 1, data for controlling on / off of a switch described later of the selection circuit 2 according to the detection procedure is stored in advance.
The latch 11 temporarily stores setting data read from the memory 10 when on / off control of a later-described switch of the selection circuit 2 is performed.
 次に、図1の選択回路2の具体的な構成について、図2を参照して説明する。
 選択回路2は、スイッチ部21-1~21-8と、スイッチ部22-1~22-8と、デコーダ23-1~23-8と、デコーダ24-1~24-8と、接続ライン25~29と、を備えている。ただし、図2では、スイッチ部21-5~21-8、スイッチ部22-5~22-8、デコーダ23-5~23-8、およびデコーダ24-5~24-8は省略されている。
Next, a specific configuration of the selection circuit 2 in FIG. 1 will be described with reference to FIG.
The selection circuit 2 includes switch units 21-1 to 21-8, switch units 22-1 to 22-8, decoders 23-1 to 23-8, decoders 24-1 to 24-8, and a connection line 25. To 29. However, in FIG. 2, the switch units 21-5 to 21-8, the switch units 22-5 to 22-8, the decoders 23-5 to 23-8, and the decoders 24-5 to 24-8 are omitted.
 スイッチ部21-1~21-8は、XラインX1~X8と、電圧検出回路4、駆動回路3、およびグランド電圧VSSのうちのいずれかとの接続を、接続ライン25~29を介して行うものである。スイッチ部22-1~22-8は、YラインY1~Y8と、電圧検出回路4、駆動回路3、およびグランド電圧VSSのうちのいずれかとの接続を、接続ライン25~29を介して行うものである。 The switch units 21-1 to 21-8 connect the X lines X1 to X8 to any one of the voltage detection circuit 4, the drive circuit 3, and the ground voltage VSS via the connection lines 25 to 29. It is. The switch units 22-1 to 22-8 connect the Y lines Y1 to Y8 to any one of the voltage detection circuit 4, the drive circuit 3, and the ground voltage VSS via the connection lines 25 to 29. It is.
 このため、スイッチ部21-1~21-8およびスイッチ部22-1~22-8のそれぞれは、5つのスイッチSW11~SW15を備えている。ただし、図2では、スイッチ部22-4のスイッチSW11~SW15のみ符号が付され、他のスイッチ部についてはそれらの符号は省略されている。
 スイッチSW11は、電圧検出回路4の入力端子44とXラインX1~X8およびYラインY1~Y8のうちの1つのラインとの接続のために使用する。スイッチSW12は、電圧検出回路4の入力端子45とXラインX1~X8およびYラインY1~Y8のうちの1つのラインとの接続のために使用する。
Therefore, each of the switch units 21-1 to 21-8 and the switch units 22-1 to 22-8 includes five switches SW11 to SW15. However, in FIG. 2, only the switches SW11 to SW15 of the switch unit 22-4 are denoted by reference numerals, and those numerals are omitted for the other switch sections.
The switch SW11 is used to connect the input terminal 44 of the voltage detection circuit 4 to one of the X lines X1 to X8 and the Y lines Y1 to Y8. The switch SW12 is used to connect the input terminal 45 of the voltage detection circuit 4 to one of the X lines X1 to X8 and the Y lines Y1 to Y8.
 スイッチSW13は、駆動回路3の出力端子33とXラインX1~X8およびYラインY1~Y8のうちの1つのラインとの接続のために使用する。スイッチSW14は、駆動回路3の出力端子34とXラインX1~X8およびYラインY1~Y8のうちの1つのラインとの接続のために使用する。スイッチSW15は、XラインX1~X8およびYラインY1~Y8のうちの1つのラインをグランド電圧VSSに接続するために使用する。 The switch SW13 is used to connect the output terminal 33 of the drive circuit 3 to one of the X lines X1 to X8 and the Y lines Y1 to Y8. The switch SW14 is used to connect the output terminal 34 of the drive circuit 3 to one of the X lines X1 to X8 and the Y lines Y1 to Y8. The switch SW15 is used to connect one of the X lines X1 to X8 and the Y lines Y1 to Y8 to the ground voltage VSS.
 デコーダ23-1~23-8は、ラッチ11からの出力データに応じて、スイッチ部21-1~21-8のそれぞれが備えるスイッチSW11~SW15のオンオフ制御を行う。デコーダ24-1~24-8は、ラッチ11から出力データに応じて、スイッチ部22-1~22-8のそれぞれが備えるスイッチSW11~SW15のオンオフ制御を行う。 The decoders 23-1 to 23-8 perform on / off control of the switches SW11 to SW15 included in each of the switch units 21-1 to 21-8 according to the output data from the latch 11. The decoders 24-1 to 24-8 perform on / off control of the switches SW11 to SW15 included in each of the switch units 22-1 to 22-8 according to the output data from the latch 11.
 次に、図1の駆動回路3の具体的な構成について、図3を参照して説明する。
 駆動回路3は、図3に示すように、第1駆動回路31と、第2駆動回路32と、2つの出力端子33、34とを備えている。
 第1駆動回路31は、スイッチSW1とスイッチSW2を直列に接続し、スイッチSW1の一端に高電位の電源電圧VDD(例えば3.3V)を印加し、スイッチSW2の一端に低電位の電源電圧であるグランド電圧VSS(例えば0V)を印加している。そして、スイッチSW1、SW2をオンオフ制御することにより、電源電圧VDDと電源電圧VSSとを出力端子33から選択的に出力する。
Next, a specific configuration of the drive circuit 3 in FIG. 1 will be described with reference to FIG.
As illustrated in FIG. 3, the drive circuit 3 includes a first drive circuit 31, a second drive circuit 32, and two output terminals 33 and 34.
The first drive circuit 31 connects the switch SW1 and the switch SW2 in series, applies a high-potential power supply voltage VDD (for example, 3.3V) to one end of the switch SW1, and applies a low-potential power supply voltage to one end of the switch SW2. A certain ground voltage VSS (for example, 0 V) is applied. Then, the power supply voltage VDD and the power supply voltage VSS are selectively output from the output terminal 33 by performing on / off control of the switches SW1 and SW2.
 第2駆動回路32は、スイッチSW3とスイッチSW4を直列に接続し、スイッチSW3の一端に電源電圧VDDを印加し、スイッチSW4の一端に電源電圧VSSを印加している。そして、スイッチSW3、SW4をオンオフ制御することにより、電源電圧VDDと電源電圧VSSとを出力端子34から選択的に出力する。 The second drive circuit 32 connects the switch SW3 and the switch SW4 in series, applies the power supply voltage VDD to one end of the switch SW3, and applies the power supply voltage VSS to one end of the switch SW4. Then, the power supply voltage VDD and the power supply voltage VSS are selectively output from the output terminal 34 by performing on / off control of the switches SW3 and SW4.
 次に、図1の電圧検出回路4の具体的な構成について、図4を参照して説明する。
 電圧検出回路4は、図4に示すように、後述の入力電圧を積分する積分回路41と、後述の入力電圧を積分する積分回路42と、積分回路41の出力電圧と積分回路42の出力電圧との差分を求める演算をする減算回路43と、2つの入力端子44、45と、を備えている。
 積分回路41は、図4に示すように、オペアンプOP1と、積分コンデンサCfと、スイッチSW6と、を備えている。
Next, a specific configuration of the voltage detection circuit 4 of FIG. 1 will be described with reference to FIG.
As shown in FIG. 4, the voltage detection circuit 4 includes an integration circuit 41 that integrates an input voltage described later, an integration circuit 42 that integrates an input voltage described later, an output voltage of the integration circuit 41, and an output voltage of the integration circuit 42. And a subtracting circuit 43 for calculating the difference between the two and two input terminals 44 and 45.
As shown in FIG. 4, the integration circuit 41 includes an operational amplifier OP1, an integration capacitor Cf, and a switch SW6.
 オペアンプOP1の反転入力端子(-)には入力電圧が入力され、オペアンプOP1の非反転入力端子(+)には電圧VCOM(VDD/2)が印加される。また、オペアンプOP1の反転入力端子と出力端子との間には、積分コンデンサCfとスイッチSW6との並列回路が接続されている。
 積分回路42は、図4に示すように、オペアンプOP2と、積分コンデンサCfと、スイッチSW5と、を備えている。
The input voltage is input to the inverting input terminal (−) of the operational amplifier OP1, and the voltage VCOM (VDD / 2) is applied to the non-inverting input terminal (+) of the operational amplifier OP1. Further, a parallel circuit of an integrating capacitor Cf and a switch SW6 is connected between the inverting input terminal and the output terminal of the operational amplifier OP1.
As shown in FIG. 4, the integration circuit 42 includes an operational amplifier OP2, an integration capacitor Cf, and a switch SW5.
 オペアンプOP2の反転入力端子には入力電圧が入力され、オペアンプOP2の非反転入力端子には電圧VCOM(VDD/2)が印加される。また、オペアンプOP2の反転入力端子と出力端子との間には、積分コンデンサCfとスイッチSW5との並列回路が接続されている。
 減算回路43は、図4に示すように、オペアンプOP3と、4つの抵抗R1~R4と、を備えている。
The input voltage is input to the inverting input terminal of the operational amplifier OP2, and the voltage VCOM (VDD / 2) is applied to the non-inverting input terminal of the operational amplifier OP2. Further, a parallel circuit of an integrating capacitor Cf and a switch SW5 is connected between the inverting input terminal and the output terminal of the operational amplifier OP2.
As shown in FIG. 4, the subtraction circuit 43 includes an operational amplifier OP3 and four resistors R1 to R4.
 オペアンプOP3の反転入力端子には、積分回路42の出力が抵抗R2を介して供給され、オペアンプOP3の非反転入力端子には、積分回路41の出力が抵抗R1を介して供給される。また、オペアンプOP3の非反転入力端子は、抵抗R3を介して電圧VCOM(VDD/2)に接続されている。そして、オペアンプOP3の反転入力端子と出力端子との間には、帰還抵抗として抵抗R4が接続されている。 The output of the integrating circuit 42 is supplied to the inverting input terminal of the operational amplifier OP3 via the resistor R2, and the output of the integrating circuit 41 is supplied to the non-inverting input terminal of the operational amplifier OP3 via the resistor R1. The non-inverting input terminal of the operational amplifier OP3 is connected to the voltage VCOM (VDD / 2) through the resistor R3. A resistor R4 is connected as a feedback resistor between the inverting input terminal and the output terminal of the operational amplifier OP3.
 次に、駆動回路3および電圧検出回路4の動作について、図5および図6を参照して説明する。駆動回路3および電圧検出回路4で容量測定回路を構成する。
 駆動回路3および電圧検出回路4は、図5に示すように、「状態1」の動作(充電動作)と「状態2」の動作(電荷-電圧変換動作)を一つの動作とし、これを繰り返す。
 「状態1」では、駆動回路3のスイッチSW1、SW4がオン、SW2、SW3がオフとなり、電圧検出回路4のスイッチSW5、SW6がオンになる。「状態2」では、駆動回路3のスイッチSW1、SW4がオフ、SW2、SW3がオンとなり、電圧検出回路4のスイッチSW5、SW6がオフとなる。
Next, operations of the drive circuit 3 and the voltage detection circuit 4 will be described with reference to FIGS. The drive circuit 3 and the voltage detection circuit 4 constitute a capacitance measurement circuit.
As shown in FIG. 5, the driving circuit 3 and the voltage detection circuit 4 repeat the operation of the “state 1” operation (charging operation) and the “state 2” operation (charge-voltage conversion operation) as one operation. .
In “state 1”, the switches SW1 and SW4 of the drive circuit 3 are turned on, SW2 and SW3 are turned off, and the switches SW5 and SW6 of the voltage detection circuit 4 are turned on. In “state 2”, the switches SW1 and SW4 of the drive circuit 3 are turned off, SW2 and SW3 are turned on, and the switches SW5 and SW6 of the voltage detection circuit 4 are turned off.
 また、駆動回路3および電圧検出回路4は、図6に示すように、「状態1」~「状態4」の動作を一つの動作とし、これを繰り返すようにしても良い。
 図6の場合は、「状態1」および「状態2」では、スイッチSW1~SW6は第1の動作と同様にオンオフ動作する。そして、「状態3」では、駆動回路3のスイッチSW1、SW4がオフ、SW2、SW3がオンとなり、電圧検出回路4のスイッチSW5、SW6がオンになる。「状態4」では、駆動回路3のスイッチSW1、SW4がオン、SW2、SW3がオフとなり、電圧検出回路4のスイッチSW5、SW6がオフになる。
Further, as shown in FIG. 6, the drive circuit 3 and the voltage detection circuit 4 may perform the operations of “state 1” to “state 4” as one operation and repeat this operation.
In the case of FIG. 6, in “State 1” and “State 2”, the switches SW1 to SW6 are turned on / off in the same manner as the first operation. In “state 3”, the switches SW1 and SW4 of the drive circuit 3 are turned off, SW2 and SW3 are turned on, and the switches SW5 and SW6 of the voltage detection circuit 4 are turned on. In “state 4”, the switches SW1 and SW4 of the drive circuit 3 are turned on, SW2 and SW3 are turned off, and the switches SW5 and SW6 of the voltage detection circuit 4 are turned off.
 このような「状態1」~「状態4」の動作と、これに対応するスイッチSW1~SW6のオンオフ状態をまとめると、図7のようになる。
 図6に示す動作の場合には、状態1、2と状態3、4では、駆動回路3が同一の駆動ラインに極性の異なる電圧を印加することができ、電圧検出回路4は2回の測定を行うことができる(図8参照)。前記2回の測定の差をとることにより、低周波ノイズを除去する効果がある。
FIG. 7 shows a summary of the operations of “state 1” to “state 4” and the on / off states of the switches SW1 to SW6 corresponding thereto.
In the case of the operation shown in FIG. 6, in the states 1, 2, and 3, 4, the drive circuit 3 can apply voltages having different polarities to the same drive line, and the voltage detection circuit 4 performs two measurements. Can be performed (see FIG. 8). By taking the difference between the two measurements, there is an effect of removing low frequency noise.
(第1実施形態の動作)
 次に、第1実施形態の動作について、図面を参照して説明する。
 まず、駆動回路3および電圧検出回路4の動作について、図8を参照して説明する。
 図8は、タッチパネル1のYラインY1、Y2が駆動回路3に接続され、タッチパネル1のXラインX1、X2が電圧検出回路4に接続された場合であり、XラインX1、X2とYラインY1、Y2の各交差部に形成される静電容量をC1~C4とする。
 そして、駆動回路3および電圧検出回路4は、図5に示すような「状態1」と「状態2」の動作を行う。
(Operation of the first embodiment)
Next, the operation of the first embodiment will be described with reference to the drawings.
First, operations of the drive circuit 3 and the voltage detection circuit 4 will be described with reference to FIG.
FIG. 8 shows a case where the Y lines Y1 and Y2 of the touch panel 1 are connected to the drive circuit 3, and the X lines X1 and X2 of the touch panel 1 are connected to the voltage detection circuit 4, and the X lines X1 and X2 and the Y line Y1 are connected. , Y2 are capacitances formed at the intersections of Y2 and C2.
Then, the drive circuit 3 and the voltage detection circuit 4 perform “state 1” and “state 2” operations as shown in FIG.
 「状態1」の動作では、駆動回路3のスイッチSW1、SW4がオン、SW2、SW3がオフとなり、電圧検出回路4のスイッチSW5、SW6がオンになり、スイッチSW1~SW6のオンオフ状態は図8に示すようになる。
 このため、駆動回路3により、YラインY2には高電位の電源電圧VDD(例えば3.3V)が印加され、YラインY1には低電位の電源電圧VSS(例えば0V)が印加される。またスイッチSW5、SW6がオンになることにより、オペアンプOP1、OP2はボルテージフォロワとなり、XラインX1、X2は電圧VCOMに駆動される。これにより、静電容量C1、C2が充電されるとともに静電容量C3、C4が充電される。
In the operation of “state 1”, the switches SW1 and SW4 of the drive circuit 3 are turned on, SW2 and SW3 are turned off, the switches SW5 and SW6 of the voltage detection circuit 4 are turned on, and the on / off states of the switches SW1 to SW6 are shown in FIG. As shown.
For this reason, the drive circuit 3 applies a high-potential power supply voltage VDD (for example, 3.3 V) to the Y line Y2, and applies a low-potential power supply voltage VSS (for example, 0 V) to the Y line Y1. When the switches SW5 and SW6 are turned on, the operational amplifiers OP1 and OP2 become voltage followers, and the X lines X1 and X2 are driven to the voltage VCOM. Thereby, the electrostatic capacitances C1 and C2 are charged and the electrostatic capacitances C3 and C4 are charged.
 その後、「状態2」の動作では、駆動回路3のスイッチSW1、SW4がオフ、SW2、SW3がオンとなり、電圧検出回路4のスイッチSW5、SW6がオフとなる。このため、静電容量C1、C2、C3、C4に充電された電荷の一部が積分回路41、42の積分コンデンサCfに移動し、オペアンプOP1の出力端子には、以下の(1A)式のような出力電圧Vout1が現れ、オペアンプOP2の出力端子には、以下の(1B)式のような出力電圧Vout2が現れる。
 Vout1=VCOM+{(C1-C2)/Cf}×VDD
                           ・・・(1A)
 Vout2=VCOM+{(C3-C4)/Cf}×VDD
                           ・・・(1B)
Thereafter, in the operation of “state 2”, the switches SW1 and SW4 of the drive circuit 3 are turned off, SW2 and SW3 are turned on, and the switches SW5 and SW6 of the voltage detection circuit 4 are turned off. Therefore, some of the charges charged in the capacitances C1, C2, C3, and C4 move to the integration capacitor Cf of the integration circuits 41 and 42, and the output terminal of the operational amplifier OP1 has the following equation (1A). An output voltage Vout1 like this appears, and an output voltage Vout2 like the following expression (1B) appears at the output terminal of the operational amplifier OP2.
Vout1 = VCOM + {(C1-C2) / Cf} × VDD
... (1A)
Vout2 = VCOM + {(C3-C4) / Cf} × VDD
... (1B)
 オペアンプOP3では、オペアンプOP1の出力電圧とオペアンプOP2の出力電圧の差を求める演算が行われる。この結果、電圧検出回路4の出力電圧Voutは、以下の(1C)式のようになる。
 Vout=VCOM+{(C1-C2-C3+C4)/Cf}×VDD
                           ・・・(1C)
 電圧検出回路4の出力電圧Voutは、図5に示すように、「状態2」の期間内の所定のタイミングでA/D変換される。
In the operational amplifier OP3, an operation for obtaining a difference between the output voltage of the operational amplifier OP1 and the output voltage of the operational amplifier OP2 is performed. As a result, the output voltage Vout of the voltage detection circuit 4 is expressed by the following equation (1C).
Vout = VCOM + {(C1-C2-C3 + C4) / Cf} × VDD
... (1C)
As shown in FIG. 5, the output voltage Vout of the voltage detection circuit 4 is A / D converted at a predetermined timing within the period of “state 2”.
 次に、第1実施形態において、タッチパネル1のタッチ位置を検出する場合の動作について、図1、図2などを参照して説明する。
 まず、選択回路2は、予め定めてある駆動パターンに応じて、タッチパネル1のYラインY1~Y8のうち、予め定めてある2つのラインを駆動ラインとして選択する。この例では、駆動ラインとしてYラインY1、Y2を選択し、この選択したYラインY1、Y2を駆動回路3と接続する。
Next, in the first embodiment, an operation when detecting the touch position of the touch panel 1 will be described with reference to FIGS.
First, the selection circuit 2 selects two predetermined lines as drive lines among the Y lines Y1 to Y8 of the touch panel 1 in accordance with a predetermined drive pattern. In this example, Y lines Y 1 and Y 2 are selected as drive lines, and the selected Y lines Y 1 and Y 2 are connected to the drive circuit 3.
 また、選択回路2は、所定の変換行列に応じて予め定めてある8つの検出パターンのうちの1つが選択されたときに、その選択された検出パターンに応じて、タッチパネル1のXラインX1~X8のうちの一部を電圧検出回路4の一方の入力端子と接続し、XラインX1~X8のうちの残りを電圧検出回路4の他方の入力端子と接続する。 In addition, when one of eight predetermined detection patterns is selected according to a predetermined conversion matrix, the selection circuit 2 selects the X lines X1 to X1 of the touch panel 1 according to the selected detection pattern. A part of X8 is connected to one input terminal of the voltage detection circuit 4, and the remainder of the X lines X1 to X8 is connected to the other input terminal of the voltage detection circuit 4.
 図9(A)~(D)および図10(E)~(H)は、アダマール変換行列に応じて定めた8つの検出パターン1~8と、これらの検出パターンに応じたXラインX1~X8と電圧検出回路4との接続状態を示している。
 例えば、図9(A)に示す検出パターン1の場合には、XラインX1~X8が電圧検出回路4の一方の入力端子に接続され、電圧検出回路4の他方の入力端子はVCOMに接続される。また、図9(B)に示す検出パターン2の場合には、XラインX1、X3、X5、X7が電圧検出回路4の一方の入力端子に接続され、XラインX2、X4、X6、X8が電圧検出回路4の他方の入力端子に接続される。
FIGS. 9A to 9D and FIGS. 10E to 10H show eight detection patterns 1 to 8 determined according to the Hadamard transform matrix and X lines X1 to X8 corresponding to these detection patterns. And the voltage detection circuit 4 are connected.
For example, in the case of detection pattern 1 shown in FIG. 9A, X lines X1 to X8 are connected to one input terminal of voltage detection circuit 4, and the other input terminal of voltage detection circuit 4 is connected to VCOM. The In the case of the detection pattern 2 shown in FIG. 9B, the X lines X1, X3, X5, and X7 are connected to one input terminal of the voltage detection circuit 4, and the X lines X2, X4, X6, and X8 are connected. The other input terminal of the voltage detection circuit 4 is connected.
 なお、図9および図10における符号C1~C8は、YラインY2と、XラインX1~X8との各交差部に形成される静電容量であり、符号C9~C16は、YラインY1と、XラインX1~X8との各交差部に形成される静電容量である。
 図9(A)に示す検出パターン1の場合には、電圧検出回路4の出力電圧D1は次のようになる。
 D1=VCOM+{(C1+C2+C3+C4+C5+C6+C7+C8-C9
  -C10-C11-C12-C13-C14-C15-C16)/Cf}×VDD
 図9、図10で示した検出パターンによる出力電圧Dnは、次の(1D)式で表すことができる。
9 and 10, reference numerals C1 to C8 are capacitances formed at the intersections of the Y line Y2 and the X lines X1 to X8. Reference numerals C9 to C16 are Y line Y1 and Capacitance formed at each intersection with the X lines X1 to X8.
In the case of the detection pattern 1 shown in FIG. 9A, the output voltage D1 of the voltage detection circuit 4 is as follows.
D1 = VCOM + {(C1 + C2 + C3 + C4 + C5 + C6 + C7 + C8-C9
-C10-C11-C12-C13-C14-C15-C16) / Cf} × VDD
The output voltage Dn based on the detection patterns shown in FIGS. 9 and 10 can be expressed by the following equation (1D).
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
 また、図9および図10における符号「+」と「-」は、「+」がsk=+1であることを意味し、「-」がsk=-1であることを意味する。
 次に、上記の検出パターン1~8ごとに、駆動回路3および電圧検出回路4は、図5に示す「状態1」と「状態2」の動作を行い、電圧検出回路4はその検出パターンに応じた電位差を検出し、この検出電圧を出力電圧として出力する。
 電圧検出回路4が、上記の検出パターン1~8に応じて8つの電位差をそれぞれ検出する演算処理は、次の(2)式で表すことができる。なお、(1D)式のVCOMとVDD/Cfは静電容量算出およびタッチ座標検出に関係しないため、簡略化のため省略する。
Also, the signs “+” and “−” in FIGS. 9 and 10 mean that “+” is sk = + 1 and “−” is sk = −1.
Next, for each of the detection patterns 1 to 8, the drive circuit 3 and the voltage detection circuit 4 perform the operations of “state 1” and “state 2” shown in FIG. A corresponding potential difference is detected, and this detected voltage is output as an output voltage.
The calculation process in which the voltage detection circuit 4 detects the eight potential differences according to the detection patterns 1 to 8 can be expressed by the following equation (2). Note that VCOM and VDD / Cf in the expression (1D) are not related to capacitance calculation and touch coordinate detection, and are omitted for simplification.
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000002
 (2)式において、D1~D8は、8つの検出パターン1~8に応じて得られる電圧検出回路4の出力電圧(検出電圧)である。右辺の変換行列は、アダマール変換行列である。C1~C8は、YラインY2とXラインX1~X8との間の容量である。C9~C16は、YラインY1とXラインX1~X8との間の静電容量である。
 アダマール変換行列の8つの各行は、上記の8つの検出パターン1~8に相当する。また、各行の1、-1とは、各検出パターンのXラインX1~X8と電圧検出回路4の接続状態に対応する。
In the equation (2), D1 to D8 are output voltages (detection voltages) of the voltage detection circuit 4 obtained according to the eight detection patterns 1 to 8. The transformation matrix on the right side is a Hadamard transformation matrix. C1 to C8 are capacitances between the Y line Y2 and the X lines X1 to X8. C9 to C16 are capacitances between the Y line Y1 and the X lines X1 to X8.
Each of the eight rows of the Hadamard transform matrix corresponds to the eight detection patterns 1 to 8 described above. Further, 1 and −1 in each row correspond to the connection state between the X lines X1 to X8 of each detection pattern and the voltage detection circuit 4.
 電圧検出回路4の出力電圧D1~D8は、図5の「状態2」の動作の所定のタイミングにおいて、A/D変換回路5でそれぞれA/D変換される。このA/D変換された各出力電圧D1~D8は、容量算出回路6に順次記憶される。そして、出力電圧D1~D8の記憶が完了すると、容量算出回路6は、記憶した出力電圧D1~D8と変換行列であるアダマール変換行列とに基づき、静電容量差(C1-C9)、(C2-C10)・・・(C8-C16)をそれぞれ算出する演算を行う。
 この容量算出回路6が行う演算処理は、次の(3)式で表すことができる。
The output voltages D1 to D8 of the voltage detection circuit 4 are each A / D converted by the A / D conversion circuit 5 at a predetermined timing of the operation of “state 2” in FIG. The A / D converted output voltages D1 to D8 are sequentially stored in the capacitance calculation circuit 6. When the storage of the output voltages D1 to D8 is completed, the capacitance calculation circuit 6 performs the capacitance difference (C1-C9), (C2) based on the stored output voltages D1 to D8 and the Hadamard transformation matrix that is the transformation matrix. -C10)... (C8-C16) are calculated.
The arithmetic processing performed by the capacity calculation circuit 6 can be expressed by the following equation (3).
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000003
 タッチ位置検出回路7は、容量算出回路6が算出した静電容量値(C1-C9)、(C2-C10)・・・(C8-C16)に基づいて、タッチパネル1の位置を検出する。
 以上の動作は、タッチパネル1上のタッチ位置を1次元的な動作により検出する例であるが、タッチパネル1上のタッチ位置を2次元的な動作により検出する場合には、上記の動作を繰り返すことになる。
 この場合には、駆動パターンに応じて選択回路2がYラインY1~Y8と駆動回路3との接続を順次変更し、この変更ごとに、電圧検出回路4が、上記の検出パターン1~8に応じて8つの電圧を検出する演算処理を行う。
The touch position detection circuit 7 detects the position of the touch panel 1 based on the capacitance values (C1-C9), (C2-C10)... (C8-C16) calculated by the capacitance calculation circuit 6.
The above operation is an example in which the touch position on the touch panel 1 is detected by a one-dimensional operation. However, when the touch position on the touch panel 1 is detected by a two-dimensional operation, the above operation is repeated. become.
In this case, the selection circuit 2 sequentially changes the connection between the Y lines Y1 to Y8 and the drive circuit 3 according to the drive pattern, and for each change, the voltage detection circuit 4 changes to the detection patterns 1 to 8 described above. In response, a calculation process for detecting eight voltages is performed.
 次に、選択回路2の選択、接続の動作の具体例について、図1および図2を参照して説明する。
 この第1実施形態では、選択回路2の選択、接続の動作に係るデータは、予め定めてある駆動パターンおよび検出パターンごとに、メモリ10に予め格納されている。すなわち、メモリ10には、予め定めてある駆動パターンおよび検出パターン1~8ごとに、選択回路2のスイッチ部21-1~21-8およびスイッチ部22-1~22-8のそれぞれのスイッチSW11~SW15をオンオフ制御するためのデータが格納されている。
Next, specific examples of selection and connection operations of the selection circuit 2 will be described with reference to FIGS.
In the first embodiment, data relating to the selection and connection operations of the selection circuit 2 is stored in advance in the memory 10 for each predetermined drive pattern and detection pattern. That is, the memory 10 stores the switch SW11 of each of the switch units 21-1 to 21-8 and the switch units 22-1 to 22-8 of the selection circuit 2 for each predetermined drive pattern and detection pattern 1 to 8. Stores data for ON / OFF control of SW15.
 そして、制御回路8は、予め定めてある駆動パターンおよび検出パターン1~8ごとに、そのデータを読み出すためのアドレスの生成をアドレス生成回路9に指示し、その生成アドレスにより必要なデータをラッチ11に読み出す。
 ラッチ11に読み出されたデータは、デコーダ23-1~23-8およびデコーダ24-1~24-8に転送される。これにより、デコーダ23-1~23-8は、スイッチ部21-1~21-8のスイッチSW11~SW15をオンオフ制御する。また、デコーダ24-1~24-8は、スイッチ部22-1~22-8のスイッチSW11~SW15をオンオフ制御する。
Then, the control circuit 8 instructs the address generation circuit 9 to generate an address for reading out the data for each of the predetermined drive patterns and detection patterns 1 to 8, and latches necessary data according to the generated address. Read to.
The data read to the latch 11 is transferred to the decoders 23-1 to 23-8 and the decoders 24-1 to 24-8. Thus, the decoders 23-1 to 23-8 perform on / off control of the switches SW11 to SW15 of the switch units 21-1 to 21-8. Further, the decoders 24-1 to 24-8 perform on / off control of the switches SW11 to SW15 of the switch units 22-1 to 22-8.
 例えば、駆動パターンに応じて、YラインY1、Y2を駆動ラインとして選択し、この選択したYラインY1、Y2を駆動回路3と接続する場合には、デコーダ24-1がスイッチ部22-1のスイッチSW13をオンとし、デコーダ24-2がスイッチ部22-2のスイッチSW14をオンとする。 For example, when the Y lines Y1 and Y2 are selected as drive lines according to the drive pattern, and the selected Y lines Y1 and Y2 are connected to the drive circuit 3, the decoder 24-1 is connected to the switch section 22-1. The switch SW13 is turned on, and the decoder 24-2 turns on the switch SW14 of the switch unit 22-2.
 また、検出パターンに応じて、タッチパネル1のXラインX1~X8のうち、XラインX1~X4を第1の検出ラインとし、XラインX5~X8を第2の検出ラインとしてそれぞれ選択し、その選択したXラインX1~X4とXラインX5~X8とを電圧検出回路4にそれぞれ接続する場合には、以下のようになる。
 すなわち、デコーダ23-1~23-4のそれぞれが、スイッチ部21-1~21-4のスイッチSW11をオンとする。また、デコーダ23-5~23-8のそれぞれが、スイッチ部21-5~21-8のスイッチSW12をオンとする。
Further, according to the detection pattern, among the X lines X1 to X8 of the touch panel 1, X lines X1 to X4 are selected as the first detection lines, and X lines X5 to X8 are selected as the second detection lines, respectively. When the X lines X1 to X4 and the X lines X5 to X8 are connected to the voltage detection circuit 4, respectively, the operation is as follows.
That is, each of the decoders 23-1 to 23-4 turns on the switch SW11 of the switch units 21-1 to 21-4. Each of the decoders 23-5 to 23-8 turns on the switch SW12 of the switch units 21-5 to 21-8.
 以上のように、第1実施形態では、電圧検出回路4が、第1~第8の検出パターンに応じた演算処理を行なって出力電圧D1~D8をそれぞれ得るようにし、その各出力電圧D1~D8を得るときに差動増幅を行うようにした。このため、その出力電圧D1~D8を得るときにノイズを軽減できる上に、S/Nの向上を図ることができる。 As described above, in the first embodiment, the voltage detection circuit 4 performs the calculation process according to the first to eighth detection patterns to obtain the output voltages D1 to D8, respectively, and the output voltages D1 to D8 are obtained. Differential amplification was performed when D8 was obtained. Therefore, noise can be reduced when the output voltages D1 to D8 are obtained, and the S / N can be improved.
 また、第1実施形態では、電圧検出回路4が出力電圧D1~D8を得るために、タッチパネル1のライン間に形成される静電容量をオフセット調整用のコンデンサとして使用するようにしたので、かかるコンデンサを特に設ける必要がない。
 なお、第1実施形態では、(2)式に示すように、8行×8列のアダマール変換行列を使用するようにした。しかし、4行×4列、16行×16列などのアダマール変換行列を使用することもできる。
In the first embodiment, since the voltage detection circuit 4 uses the capacitance formed between the lines of the touch panel 1 as a capacitor for offset adjustment in order to obtain the output voltages D1 to D8. There is no need to provide a capacitor.
In the first embodiment, an Hadamard transformation matrix of 8 rows × 8 columns is used as shown in the equation (2). However, a Hadamard transform matrix such as 4 rows × 4 columns or 16 rows × 16 columns can also be used.
 このため、n行×n列(n=2、4の倍数)のアダマール変換行列を使用する場合には、上記の検出パターンはn個となり、この各検出パターンに応じて電圧検出回路4に使用される検出用ラインはn個となる。上記の例では、検出パターンは図9および図10に示すように8つとなり、この8つの検出パターンに応じて電圧検出回路4に使用される検出用ラインは8つとなる。 Therefore, when the Hadamard transformation matrix of n rows × n columns (n = 2, a multiple of 4) is used, the number of the detection patterns is n, and the voltage detection circuit 4 is used according to each detection pattern. There are n detection lines. In the above example, there are eight detection patterns as shown in FIGS. 9 and 10, and eight detection lines are used in the voltage detection circuit 4 in accordance with the eight detection patterns.
(第1実施形態の変形例1)
 この変形例1は、タッチパネルのライン数(電極数)が4の倍数でない場合であり、例えばX軸方向で7個の場合である。
 この変形例1は、基本構成は図1と同一であり、タッチパネル1のサイズだけが異なっている。また、その動作も第1実施形態と同様である。以下、第1実施形態と異なる部分だけを説明する。
(Modification 1 of the first embodiment)
Modification 1 is a case where the number of lines (number of electrodes) of the touch panel is not a multiple of 4, for example, 7 in the X-axis direction.
In the first modification, the basic configuration is the same as that in FIG. 1, and only the size of the touch panel 1 is different. The operation is also the same as in the first embodiment. Only the parts different from the first embodiment will be described below.
 アダマール変換行列の大きさを電極数以上の4の倍数で選ぶ。ここではX軸方向の電極数は7であるので7以上の最小の4の倍数として8、すなわち8行×8列のアダマール変換行列を使用する。
 検出パターンは選択したサイズのアダマール変換行列に従い、8種類の検出パターンを使用する。すなわち、図9、図10の電極X8を省略した形になっている。
 電圧検出回路4が、前述の8種類の検出パターンに応じて8種類の電位差をそれぞれ検出する演算処理は次の(4)式で表すことができる。
The size of the Hadamard transform matrix is selected by a multiple of 4 that is greater than the number of electrodes. Here, since the number of electrodes in the X-axis direction is 7, 8 is used as a minimum multiple of 4 that is 7 or more, that is, an Hadamard transformation matrix of 8 rows × 8 columns is used.
The detection pattern uses eight types of detection patterns according to the Hadamard transform matrix of the selected size. That is, the electrode X8 in FIGS. 9 and 10 is omitted.
The calculation process in which the voltage detection circuit 4 detects the eight potential differences according to the eight detection patterns described above can be expressed by the following equation (4).
Figure JPOXMLDOC01-appb-M000004
Figure JPOXMLDOC01-appb-M000004
 (4)式の係数行列は(2)式の係数行列である8行×8列のアダマール変換行列の第8列目(一番右の列)を削除して列数をX軸方向の電極数に一致させたものである。なお、削除する列の位置はどこでもよく、列を削除した結果列数がX軸方向の電極数に一致していれば良い。
 電圧検出回路4から出力される8個の出力電圧は、図5の「状態2」の動作の所定の夕イミングにおいて、A/D変換回路5でそれぞれA/D変換される。このA/D変換された各出力電圧は容量算出回路6に順次記憶される。そして、出力電圧D1~D8の記憶が完了すると、容量算出回路6は、記憶した出力電圧D1~D8と変換行列であるアダマール変換行列とに基づき、静電容量差(C1-C9)、(C2-C10)・・・(C7-C15)をそれぞれ算出する演算を行う。
 この容量算出回路6が行う演算処理は、次の(5)式で表すことができる。
The coefficient matrix of equation (4) deletes the eighth column (rightmost column) of the 8-row × 8-column Hadamard transformation matrix that is the coefficient matrix of equation (2), and sets the number of columns to an electrode in the X-axis direction. It matches the number. Note that the position of the column to be deleted may be anywhere, and the number of columns as a result of deleting the column only needs to match the number of electrodes in the X-axis direction.
The eight output voltages output from the voltage detection circuit 4 are each A / D converted by the A / D conversion circuit 5 in a predetermined evening of the operation of “state 2” in FIG. The A / D converted output voltages are sequentially stored in the capacity calculation circuit 6. When the storage of the output voltages D1 to D8 is completed, the capacitance calculation circuit 6 performs the capacitance difference (C1-C9), (C2) based on the stored output voltages D1 to D8 and the Hadamard transformation matrix that is the transformation matrix. -C10)... (C7-C15) are calculated.
The arithmetic processing performed by the capacity calculation circuit 6 can be expressed by the following equation (5).
Figure JPOXMLDOC01-appb-M000005
Figure JPOXMLDOC01-appb-M000005
 但し、(5)式に現れる係数行列は(4)式の係数行列の転置行列かつムーア・ペンローズの一般化逆行列(のスカラー倍)の関係になっている。
 電圧検出回路4から出力される出力電圧は8個と電極数7個よりも多いが、(5)式の係数行列は(4)式の係数行列の一般化逆行列であるため、得られた(C1-C9)、(C2-C10)・・・(C7-C15)は(4)式を満たす最小二乗解になっている。そのため電圧検出回路4の出力電圧の個数が多ければ多いほどS/Nも改善される。
 この変形例1は(4)式に現れる係数行列がアダマール変換の一部の列を削除したもの以外にも係数行列が直交行列および直交行列をスカラー倍したものの一部の列を削除したものでも適用可能である。
 なお、この変形例1については、後述の第2、第3の各実施形態に適用することができる。
However, the coefficient matrix appearing in the equation (5) has a transposed matrix of the coefficient matrix of the equation (4) and a Moore-Penrose generalized inverse matrix (a scalar multiple thereof).
Although the output voltage output from the voltage detection circuit 4 is eight and more than seven electrodes, the coefficient matrix of the equation (5) is obtained because it is a generalized inverse matrix of the coefficient matrix of the equation (4). (C1-C9), (C2-C10)... (C7-C15) are least squares solutions that satisfy the equation (4). Therefore, the greater the number of output voltages of the voltage detection circuit 4, the better the S / N.
In the first modified example, the coefficient matrix appearing in the equation (4) is not the one obtained by deleting some columns of the Hadamard transform, but the coefficient matrix obtained by deleting some columns of the orthogonal matrix and the orthogonal matrix multiplied by the scalar. Applicable.
Note that the first modification can be applied to second and third embodiments described later.
(第1実施形態の変形例2)
 第1実施形態は図9、図10の(A)~(H)に示すように、Y1を駆動回路3の-端子34、Y2を駆動回路3の+端子33に接続し、X1~X8は予め定められたパターンに従って電圧検出回路4の+側端子44、あるいは-側端子45に接続するよう構成されているが、駆動回路3と電圧検出回路4は交換することができる。すなわち、Y1を電圧検出回路4の-端子45、Y2を電圧検出回路4の+端子に接続し、X1~X8は予め定められたパターンに従って駆動回路3の+側端子33、あるいは-側端子34に接続するよう構成することもできる。この構成でも電圧検出回路の出力は第1実施形態と全く同じであり、従って図1のメモリ10に格納される駆動・検出パターンを変更するだけで図1と全く同一の構成を使用することができる。また、この場合は図9の(A)のパターンを含め、全パターンが差動の構成で電圧検出されるため、コモンモードノイズヘの耐性が改善する。
 なお、この変形例2は第1実施例の変形例1に適用することができる。
(Modification 2 of the first embodiment)
In the first embodiment, as shown in FIGS. 9 and 10A to 10H, Y1 is connected to the-terminal 34 of the drive circuit 3, Y2 is connected to the + terminal 33 of the drive circuit 3, and X1 to X8 are The drive circuit 3 and the voltage detection circuit 4 can be exchanged, although they are configured to be connected to the + side terminal 44 or the − side terminal 45 of the voltage detection circuit 4 according to a predetermined pattern. That is, Y1 is connected to the negative terminal 45 of the voltage detection circuit 4, Y2 is connected to the positive terminal of the voltage detection circuit 4, and X1 to X8 are the positive side terminal 33 or negative side terminal 34 of the drive circuit 3 according to a predetermined pattern. It can also be configured to connect to. Even in this configuration, the output of the voltage detection circuit is exactly the same as in the first embodiment, and therefore, the same configuration as in FIG. 1 can be used only by changing the drive / detection pattern stored in the memory 10 of FIG. it can. In this case, since all patterns including the pattern of FIG. 9A are detected with a differential configuration, resistance to common mode noise is improved.
The second modification can be applied to the first modification of the first embodiment.
(第2実施形態の構成)
 図11は、本発明の第2実施形態が適用されるタッチセンサの概略構成を示すブロック図である。
 第2実施形態が適用されるタッチセンサは、図11に示すように、タッチパネル1と、選択回路2と、駆動回路3と、電圧検出回路4と、A/D変換回路5と、容量算出回路6Aと、タッチ位置検出回路7Aと、制御回路8Aと、アドレス生成回路9と、メモリ10と、ラッチ11と、オフセット調整用の静電容量回路12と、を備えている。
(Configuration of Second Embodiment)
FIG. 11 is a block diagram showing a schematic configuration of a touch sensor to which the second embodiment of the present invention is applied.
As shown in FIG. 11, the touch sensor to which the second embodiment is applied includes a touch panel 1, a selection circuit 2, a drive circuit 3, a voltage detection circuit 4, an A / D conversion circuit 5, and a capacitance calculation circuit. 6A, a touch position detection circuit 7A, a control circuit 8A, an address generation circuit 9, a memory 10, a latch 11, and a capacitance circuit 12 for offset adjustment.
 このように、第2実施形態は、図1に示す第1実施形態の構成を基本とし、図1の容量算出回路6、タッチ位置検出回路7、および制御回路8を、図11に示すように、容量算出回路6A、タッチ位置検出回路7A、および制御回路8Aに置き換え、かつ静電容量回路12を追加したものである。 As described above, the second embodiment is based on the configuration of the first embodiment shown in FIG. 1, and the capacitance calculation circuit 6, the touch position detection circuit 7, and the control circuit 8 shown in FIG. The capacitance calculation circuit 6A, the touch position detection circuit 7A, and the control circuit 8A are replaced with a capacitance circuit 12.
 ここで、第2実施形態は、第1実施形態の構成要素と共通する部分があり、この共通の構成要素には同一符号を付してその説明はできるだけ省略する。
 静電容量回路12は、図12に示すように、それぞれが予め定めた静電容量値を有するオフセット調整用のコンデンサCR1、CR2と、スイッチSW7~SW9とを備えている。
Here, the second embodiment has parts common to the components of the first embodiment. The common components are denoted by the same reference numerals, and the description thereof is omitted as much as possible.
As shown in FIG. 12, the capacitance circuit 12 includes offset adjusting capacitors CR1 and CR2 each having a predetermined capacitance value, and switches SW7 to SW9.
 コンデンサCR1の一端側は電圧検出回路4の入力端子44に接続され、コンデンサCR1の他端側はスイッチSW7を介して駆動回路3の出力端子34に接続されている。また、コンデンサCR2の一端側は電圧検出回路4の入力端子45に接続され、コンデンサCR2の他端側はスイッチSW8を介して駆動回路3の出力端子34に接続されている。さらに、スイッチSW9の一端側は電圧検出回路4の入力端子45に接続され、スイッチSW9の他端側はVCOMに接続されている。
 制御回路8Aは、タッチパネル1のタッチ位置を検出するときに、駆動回路3、電圧検出回路4、アドレス生成回路9、ラッチ11、静電容量回路12を後述のようにそれぞれ制御する。
One end of the capacitor CR1 is connected to the input terminal 44 of the voltage detection circuit 4, and the other end of the capacitor CR1 is connected to the output terminal 34 of the drive circuit 3 via the switch SW7. One end side of the capacitor CR2 is connected to the input terminal 45 of the voltage detection circuit 4, and the other end side of the capacitor CR2 is connected to the output terminal 34 of the drive circuit 3 via the switch SW8. Furthermore, one end side of the switch SW9 is connected to the input terminal 45 of the voltage detection circuit 4, and the other end side of the switch SW9 is connected to VCOM.
When detecting the touch position of the touch panel 1, the control circuit 8A controls the drive circuit 3, the voltage detection circuit 4, the address generation circuit 9, the latch 11, and the capacitance circuit 12 as described later.
(第2実施形態の動作)
 次に、第2実施形態において、タッチパネル1のタッチ位置を検出する場合について、図11~図14を参照して説明する。
 まず、選択回路2は、予め定めてある駆動パターンに応じて、タッチパネル1のYラインY1~Y8のうち、予め定めてある1つのラインを駆動ラインとして選択する。この例では、駆動ラインとしてYラインY1を選択し、この選択したYラインY1を駆動回路3の出力端子33と接続する(図13および図14参照)。
(Operation of Second Embodiment)
Next, a case where the touch position of the touch panel 1 is detected in the second embodiment will be described with reference to FIGS.
First, the selection circuit 2 selects one predetermined line from among the Y lines Y1 to Y8 of the touch panel 1 as a drive line according to a predetermined drive pattern. In this example, the Y line Y1 is selected as the drive line, and the selected Y line Y1 is connected to the output terminal 33 of the drive circuit 3 (see FIGS. 13 and 14).
 また、選択回路2は、所定の変換行列に応じて予め定めてある8つの検出パターンのうちの1つが選択されたときに、その選択された検出パターンに応じて、タッチパネル1のXラインX1~X8のうちの一部を電圧検出回路4の入力端子44と接続し、XラインX1~X8のうちの残りを電圧検出回路4の入力端子45と接続する。 In addition, when one of eight predetermined detection patterns is selected according to a predetermined conversion matrix, the selection circuit 2 selects the X lines X1 to X1 of the touch panel 1 according to the selected detection pattern. A part of X8 is connected to the input terminal 44 of the voltage detection circuit 4, and the remainder of the X lines X1 to X8 is connected to the input terminal 45 of the voltage detection circuit 4.
 図13(A)~(D)および図14(E)~(H)は、アダマール変換行列に応じて定めた検出パターン1~8と、これらの検出パターン1~8に応じたXラインX1~X8と電圧検出回路4との接続状態を示している。
 例えば、図13(A)に示す検出パターン1の場合には、XラインX1~X8が電圧検出回路4の入力端子44に接続される。また、図13(B)に示す第2の検出パターンの場合には、XラインX1、X3、X5、X7が電圧検出回路4の入力端子44に接続され、XラインX2、X4、X6、X8が電圧検出回路4の入力端子45に接続される。
FIGS. 13A to 13D and FIGS. 14E to 14H show detection patterns 1 to 8 determined according to the Hadamard transformation matrix and X lines X1 to X corresponding to these detection patterns 1 to 8, respectively. The connection state between X8 and the voltage detection circuit 4 is shown.
For example, in the case of the detection pattern 1 shown in FIG. 13A, the X lines X 1 to X 8 are connected to the input terminal 44 of the voltage detection circuit 4. In the case of the second detection pattern shown in FIG. 13B, the X lines X1, X3, X5, and X7 are connected to the input terminal 44 of the voltage detection circuit 4, and the X lines X2, X4, X6, and X8 are connected. Is connected to the input terminal 45 of the voltage detection circuit 4.
 なお、図13および図14における符号C1~C8は、YラインY1と、XラインX1~X8との間で形成されるそれぞれ静電容量(キャパシタ)である。
 次に、上記の検出パターン1~8ごとに、駆動回路3および電圧検出回路4は、図5に示す「状態1」と「状態2」の動作を行い、電圧検出回路4はその検出パターン1~8に応じた電位差を検出する。
Reference numerals C1 to C8 in FIGS. 13 and 14 are capacitances (capacitors) formed between the Y line Y1 and the X lines X1 to X8, respectively.
Next, for each of the detection patterns 1 to 8, the drive circuit 3 and the voltage detection circuit 4 perform the operations of “state 1” and “state 2” shown in FIG. A potential difference corresponding to ˜8 is detected.
 なお、図13および図14に示すように、検出パターン1の場合には、図12に示すスイッチSW7、SW9がオンとなる。このため、コンデンサCR1が駆動回路3の出力端子34と電圧検出回路4の入力端子44との間に接続され、電圧検出回路4の入力端子45はVCOMに接続される。
 また、検出パターン2~8の場合には、図12に示すスイッチSW7、SW8がオンとなる。このため、コンデンサCR1が駆動回路3の出力端子34と電圧検出回路4の入力端子44との間に接続され、コンデンサCR2が駆動回路3の出力端子34と電圧検出回路4の入力端子45との間に接続される。
 ここで、電圧検出回路4が、上記の検出パターン1~8に応じて8つの電位差を検出する演算処理は、次の(6)式で表すことができる。
As shown in FIGS. 13 and 14, in the case of the detection pattern 1, the switches SW7 and SW9 shown in FIG. 12 are turned on. For this reason, the capacitor CR1 is connected between the output terminal 34 of the drive circuit 3 and the input terminal 44 of the voltage detection circuit 4, and the input terminal 45 of the voltage detection circuit 4 is connected to VCOM.
In the case of detection patterns 2 to 8, the switches SW7 and SW8 shown in FIG. 12 are turned on. Therefore, the capacitor CR1 is connected between the output terminal 34 of the drive circuit 3 and the input terminal 44 of the voltage detection circuit 4, and the capacitor CR2 is connected between the output terminal 34 of the drive circuit 3 and the input terminal 45 of the voltage detection circuit 4. Connected between.
Here, the calculation processing in which the voltage detection circuit 4 detects eight potential differences according to the detection patterns 1 to 8 can be expressed by the following equation (6).
 (6)式において、D1~D8は、8つの検出パターン1~8に応じて得られる電圧検出回路4の出力電圧(検出電圧)である。右辺の変換行列は、アダマール変換行列である。C1~C8は、YラインY1とXラインX1~X8との間の静電容量である。
 ここで、アダマール変換行列の8つの各行は、上記の8つの検出パターン1~8に相当する。また、各行の1、-1とは、各検出パターンのXラインX1~X8と電圧検出回路4の接続状態に対応する。
In the equation (6), D1 to D8 are output voltages (detection voltages) of the voltage detection circuit 4 obtained according to the eight detection patterns 1 to 8. The transformation matrix on the right side is a Hadamard transformation matrix. C1 to C8 are capacitances between the Y line Y1 and the X lines X1 to X8.
Here, each of the eight rows of the Hadamard transform matrix corresponds to the eight detection patterns 1 to 8 described above. Further, 1 and −1 in each row correspond to the connection state between the X lines X1 to X8 of each detection pattern and the voltage detection circuit 4.
 電圧検出回路4から出力される出力電圧D1~D8は、図5の「状態2」の動作の所定のタイミングにおいて、A/D変換回路5でそれぞれA/D変換される。このA/D変換された各出力電圧D1~D8は、容量算出回路6Aに順次記憶される。そして、出力電圧D1~D8の記憶が完了すると、容量算出回路6Aは、記憶した出力電圧D1~D8と変換行列であるアダマール変換行列とに基づき、静電容量C1~C8をそれぞれ算出する演算を行う。
 この容量算出回路6Aが行う演算処理は、次の(7)式で表すことができる。
The output voltages D1 to D8 output from the voltage detection circuit 4 are each A / D converted by the A / D conversion circuit 5 at a predetermined timing of the operation of “state 2” in FIG. The A / D converted output voltages D1 to D8 are sequentially stored in the capacity calculation circuit 6A. When the storage of the output voltages D1 to D8 is completed, the capacity calculation circuit 6A performs an operation for calculating the capacitances C1 to C8 based on the stored output voltages D1 to D8 and the Hadamard transform matrix as a conversion matrix. Do.
The arithmetic processing performed by the capacity calculation circuit 6A can be expressed by the following equation (7).
Figure JPOXMLDOC01-appb-M000007
Figure JPOXMLDOC01-appb-M000007
 タッチ位置検出回路7Aは、容量算出回路6Aが算出した静電容量C1~C8に基づいて、タッチパネル1のタッチ位置を検出する。
 以上の動作は、タッチパネル1上のタッチ位置を1次元的な動作により検出する例であるが、タッチパネル1上のタッチ位置を2次元的な動作により検出する場合には、上記の動作を繰り返すことになる。
 この場合には、駆動パターンに応じてYラインY1~Y8と駆動回路3との接続を順次変更し、この変更ごとに、電圧検出回路4が、上記の検出パターン1~8に応じて8つの電圧を検出する演算処理を行う。
The touch position detection circuit 7A detects the touch position of the touch panel 1 based on the capacitances C1 to C8 calculated by the capacitance calculation circuit 6A.
The above operation is an example in which the touch position on the touch panel 1 is detected by a one-dimensional operation. However, when the touch position on the touch panel 1 is detected by a two-dimensional operation, the above operation is repeated. become.
In this case, the connection between the Y lines Y1 to Y8 and the drive circuit 3 is sequentially changed according to the drive pattern, and for each change, the voltage detection circuit 4 has eight outputs corresponding to the detection patterns 1 to 8. An arithmetic process for detecting the voltage is performed.
 以上のように、第2実施形態では、電圧検出回路4が、8つの検出パターンに応じた演算処理を行なって出力電圧D1~D8をそれぞれ得るようにし、その各出力電圧D1~D8を得るときに差動増幅を行うようにした。このため、その出力電圧D1~D8を得るときにノイズを軽減できる上に、S/Nの向上を図ることができる。
 なお、第2実施形態では、(6)式に示すように、8行×8列のアダマール変換行列を使用するようにした。しかし、4行×4列、16行×16列などのアダマール変換行列を使用することもできる。
As described above, in the second embodiment, when the voltage detection circuit 4 obtains the output voltages D1 to D8 by performing arithmetic processing according to the eight detection patterns, and obtains the output voltages D1 to D8, respectively. Differential amplification was performed. Therefore, noise can be reduced when the output voltages D1 to D8 are obtained, and the S / N can be improved.
In the second embodiment, an Hadamard transformation matrix of 8 rows × 8 columns is used as shown in Equation (6). However, a Hadamard transform matrix such as 4 rows × 4 columns or 16 rows × 16 columns can also be used.
 このため、n行×n列(n=2、4の倍数)のアダマール変換行列を使用する場合には、上記の検出パターンはn個となり、この各検出パターンに応じて電圧検出回路4に使用される検出用ラインはn個となる。上記の例では、検出パターンは図13および図14に示すように8つとなり、この8つの検出パターンに応じて電圧検出回路4に使用される検出用ラインは8つとなる。 Therefore, when the Hadamard transformation matrix of n rows × n columns (n = 2, a multiple of 4) is used, the number of the detection patterns is n, and the voltage detection circuit 4 is used according to each detection pattern. There are n detection lines. In the above example, there are eight detection patterns as shown in FIGS. 13 and 14, and eight detection lines are used in the voltage detection circuit 4 in accordance with these eight detection patterns.
(第2実施形態の変形例1)
 次に、第2実施形態において、タッチパネル1に指が接触していないが、タッチパネル1上に接近した場合にその位置を特定する、ホバリングの検出例について、図15を参照して説明する。
 この例は、図14(E)の検出パターン5と図14(G)の検出パターン7とを組み合わせることにより、ホバリング検出を行うものである。
 図15(A)(B)は、いずれも検出パターン5での検出状態を示す。(A)は指100が静電容量C1~C4の近傍にある場合であり、電圧検出回路4の出力電圧D5は、D5<0となる。(B)は指100が静電容量C5~C8の近傍にある場合であり、電圧検出回路4の出力電圧D5は、D5>0となる。
(Modification 1 of 2nd Embodiment)
Next, in the second embodiment, a detection example of hovering that specifies the position when the finger is not in contact with the touch panel 1 but approaches the touch panel 1 will be described with reference to FIG.
In this example, hovering detection is performed by combining the detection pattern 5 in FIG. 14E and the detection pattern 7 in FIG.
FIGS. 15A and 15B show detection states in the detection pattern 5. (A) is the case where the finger 100 is in the vicinity of the capacitances C1 to C4, and the output voltage D5 of the voltage detection circuit 4 is D5 <0. (B) is the case where the finger 100 is in the vicinity of the capacitances C5 to C8, and the output voltage D5 of the voltage detection circuit 4 is D5> 0.
 また、図15(C)(D)は、いずれも検出パターン7での検出状態を示す。(C)は指100が静電容量C3~C6の近傍にある場合であり、電圧検出回路4の出力電圧D7は、D7>0となる。(D)は指100が静電容量C1、C2あるいは静電容量C7、C8の近傍にある場合であり、電圧検出回路4の出力電圧D7は、D7<0となる。
 このため、電圧検出回路4の出力電圧D5、D7を基に、指の位置が静電容量C1、C2、静電容量C3、C4、静電容量C5、C6、あるいは静電容量C7、C8のいずれの近傍にあるかを判定できる。
FIGS. 15C and 15D both show detection states in the detection pattern 7. (C) is the case where the finger 100 is in the vicinity of the capacitances C3 to C6, and the output voltage D7 of the voltage detection circuit 4 is D7> 0. (D) is the case where the finger 100 is in the vicinity of the capacitances C1 and C2 or the capacitances C7 and C8, and the output voltage D7 of the voltage detection circuit 4 is D7 <0.
Therefore, based on the output voltages D5 and D7 of the voltage detection circuit 4, the position of the finger is the capacitance C1, C2, capacitance C3, C4, capacitance C5, C6, or capacitance C7, C8. It can be determined in which neighborhood.
(第2実施形態の変形例2)
 多点タッチ検出が不要な場合、第2実施例の動作の代わりに次のような動作を行うことによりタッチ位置のX,Y座標を検出することができる。なお、ここでいう多点タッチとは、タッチパネル上の異なる2以上のポイントが所定時間内にタッチされることをいう。
 まず、選択回路2は、予め定めてある駆動パターンに応じて、タッチパネル1のYラインY1~Y8のうち、予め定めてある1つのラインを駆動ラインとして選択する代わりに全ラインを選択する。それ以外は全て第2実施形態の動作の説明と同様である。これによりタッチ位置のX座標が検出できる。次に前述の動作をXラインとYラインを交換して再度行う。これによりタッチ位置のY座標が検出できる。
(Modification 2 of the second embodiment)
When multipoint touch detection is not required, the X and Y coordinates of the touch position can be detected by performing the following operation instead of the operation of the second embodiment. In addition, multipoint touch here means that two or more different points on the touch panel are touched within a predetermined time.
First, the selection circuit 2 selects all of the Y lines Y1 to Y8 of the touch panel 1 according to a predetermined drive pattern instead of selecting one predetermined line as a drive line. The rest is the same as the description of the operation of the second embodiment. Thereby, the X coordinate of the touch position can be detected. Next, the above operation is performed again by exchanging the X line and the Y line. Thereby, the Y coordinate of the touch position can be detected.
(第3実施形態の構成)
 図16は、本発明の第3実施形態が適用されるタッチセンサの概略構成を示すブロック図である。
 第3実施形態が適用されるタッチセンサは、図16に示すように、タッチパネル1と、選択回路2と、駆動回路3と、電圧検出回路4Aと、A/D変換回路5と、容量算出回路6Aと、タッチ位置検出回路7Aと、制御回路8Bと、アドレス生成回路9と、メモリ10と、ラッチ11と、オフセット調整用の静電容量回路12Aと、を備えている。
 このように、第3実施形態は、図11に示す第2実施形態の構成を基本とし、図11の差動増幅型の電圧検出回路4、制御回路8A、および静電容量回路12を、図16に示すように、シングル型の電圧検出回路4A、制御回路8B、および静電容量回路12Aに置き換えたものである。
(Configuration of Third Embodiment)
FIG. 16 is a block diagram showing a schematic configuration of a touch sensor to which the third embodiment of the present invention is applied.
As shown in FIG. 16, the touch sensor to which the third embodiment is applied includes a touch panel 1, a selection circuit 2, a drive circuit 3, a voltage detection circuit 4A, an A / D conversion circuit 5, and a capacitance calculation circuit. 6A, touch position detection circuit 7A, control circuit 8B, address generation circuit 9, memory 10, latch 11, and capacitance circuit 12A for offset adjustment.
In this way, the third embodiment is based on the configuration of the second embodiment shown in FIG. 11, and the differential amplification type voltage detection circuit 4, the control circuit 8A, and the capacitance circuit 12 of FIG. As shown in FIG. 16, a single type voltage detection circuit 4A, a control circuit 8B, and a capacitance circuit 12A are replaced.
 ここで、第3実施形態は、第2実施形態の構成要素と共通する部分があり、この共通の構成要素には同一符号を付してその説明はできるだけ省略する。
 電圧検出回路4Aは、図17に示すように、オペアンプOP4と、積分コンデンサCfと、スイッチSW10と、を備えている。
 オペアンプOP4の反転入力端子(-)には入力電圧が入力され、オペアンプOP4の非反転入力端子(+)はVCOMに接続されている。また、オペアンプOP4の反転入力端子と出力端子との間には、積分コンデンサCfとスイッチSW10との並列回路が接続されている。
Here, the third embodiment has a part common to the constituent elements of the second embodiment, and the common constituent elements are denoted by the same reference numerals, and the description thereof is omitted as much as possible.
As shown in FIG. 17, the voltage detection circuit 4A includes an operational amplifier OP4, an integration capacitor Cf, and a switch SW10.
An input voltage is input to the inverting input terminal (−) of the operational amplifier OP4, and the non-inverting input terminal (+) of the operational amplifier OP4 is connected to VCOM. Further, a parallel circuit of an integrating capacitor Cf and a switch SW10 is connected between the inverting input terminal and the output terminal of the operational amplifier OP4.
 静電容量回路12Aは、図17に示すように、予め定めた静電容量値を有するオフセット調整用のコンデンサCR3と、スイッチSW20とを備えている。コンデンサCR3の一端側は電圧検出回路4Aの入力端子に接続され、コンデンサCR3の他端側はスイッチSW20を介して駆動回路3の出力端子34に接続されている。
 制御回路8Bは、タッチパネル1のタッチ位置を検出するときに、駆動回路3、電圧検出回路4A、アドレス生成回路9、ラッチ11、および静電容量回路12Aをそれぞれ制御する。
As shown in FIG. 17, the capacitance circuit 12A includes an offset adjustment capacitor CR3 having a predetermined capacitance value and a switch SW20. One end side of the capacitor CR3 is connected to the input terminal of the voltage detection circuit 4A, and the other end side of the capacitor CR3 is connected to the output terminal 34 of the drive circuit 3 via the switch SW20.
When detecting the touch position of the touch panel 1, the control circuit 8B controls the drive circuit 3, the voltage detection circuit 4A, the address generation circuit 9, the latch 11, and the capacitance circuit 12A.
(第3実施形態の動作)
 次に、第3実施形態において、タッチパネル1のタッチ位置を検出する場合について、図16~図19を参照して説明する。
 まず、選択回路2は、予め定めてある検出パターンに応じて、タッチパネル1のYラインY1~Y8のうち、予め定めてある1つのラインを検出ラインとして選択する。この例では、検出ラインとしてYラインY1を選択し、この選択したYラインY1を電圧検出回路4の入力端子と接続する(図18および図19参照)。
(Operation of Third Embodiment)
Next, in the third embodiment, a case where the touch position of the touch panel 1 is detected will be described with reference to FIGS. 16 to 19.
First, the selection circuit 2 selects one predetermined line as a detection line among the Y lines Y1 to Y8 of the touch panel 1 according to a predetermined detection pattern. In this example, the Y line Y1 is selected as the detection line, and the selected Y line Y1 is connected to the input terminal of the voltage detection circuit 4 (see FIGS. 18 and 19).
 また、選択回路2は、所定の変換行列に応じて予め定めてある8つの駆動パターンのうちの1つが選択されたときに、その選択された駆動パターンに応じて、タッチパネル1のXラインX1~X8のうちの一部を駆動回路3の出力端子33と接続し、XラインX1~X8のうちの残りを駆動回路3の出力端子34と接続する。 In addition, when one of eight predetermined drive patterns is selected according to a predetermined conversion matrix, the selection circuit 2 selects the X lines X1 to X1 of the touch panel 1 according to the selected drive pattern. A part of X8 is connected to the output terminal 33 of the drive circuit 3, and the remainder of the X lines X1 to X8 is connected to the output terminal 34 of the drive circuit 3.
 図18(A)~(D)および図19(E)~(H)は、アダマール変換行列に応じて定めた駆動パターン1~8と、これらの駆動パターン1~8に応じたXラインX1~X8と駆動回路との接続状態を示している。
 例えば、図18(A)に示す駆動パターン1の場合には、XラインX1~X8が駆動回路3の出力端子33に接続される。また、図18(B)に示す第2の駆動パターンの場合には、XラインX1、X3、X5、X7が駆動回路3の出力端子33に接続され、XラインX2、X4、X6、X8が駆動回路3の出力端子34に接続される。
18A to 18D and FIGS. 19E to 19H show driving patterns 1 to 8 determined according to the Hadamard transformation matrix and X lines X1 to X corresponding to these driving patterns 1 to 8, respectively. The connection state between X8 and the drive circuit is shown.
For example, in the case of the drive pattern 1 shown in FIG. 18A, the X lines X 1 to X 8 are connected to the output terminal 33 of the drive circuit 3. In the case of the second drive pattern shown in FIG. 18B, the X lines X1, X3, X5, and X7 are connected to the output terminal 33 of the drive circuit 3, and the X lines X2, X4, X6, and X8 are connected. Connected to the output terminal 34 of the drive circuit 3.
 次に、上記の駆動パターン1~8ごとに、駆動回路3および電圧検出回路4Aは、図5に示す「状態1」と「状態2」に相当する動作として第1動作と第2動作と行い、電圧検出回路4Aはその駆動パターン1~8に応じた電圧を検出する。
 第1動作では、駆動回路3のスイッチSW1、SW4がオン、SW2、SW3がオフとなり、電圧検出回路4AのスイッチSW10がオンになる。第2動作では、駆動回路3のスイッチSW1、SW4がオフ、SW2、SW3がオンとなり、電圧検出回路4AのスイッチSW10がオフとなる。
Next, for each of the drive patterns 1 to 8, the drive circuit 3 and the voltage detection circuit 4A perform the first operation and the second operation as operations corresponding to “state 1” and “state 2” shown in FIG. The voltage detection circuit 4A detects a voltage corresponding to the drive patterns 1-8.
In the first operation, the switches SW1 and SW4 of the drive circuit 3 are turned on, SW2 and SW3 are turned off, and the switch SW10 of the voltage detection circuit 4A is turned on. In the second operation, the switches SW1 and SW4 of the drive circuit 3 are turned off, SW2 and SW3 are turned on, and the switch SW10 of the voltage detection circuit 4A is turned off.
 なお、図18および図19に示すように、駆動パターン1の場合には、図17に示すスイッチSW20がオンとなる。このため、コンデンサCR3が駆動回路3の出力端子34と電圧検出回路4Aの入力端子44との間に接続される。
 ここで、電圧検出回路4Aが、上記の駆動パターン1~8に応じて8つの電圧を検出する演算処理は、上記の(6)式で表すことができる。
As shown in FIGS. 18 and 19, in the case of the drive pattern 1, the switch SW20 shown in FIG. 17 is turned on. For this reason, the capacitor CR3 is connected between the output terminal 34 of the drive circuit 3 and the input terminal 44 of the voltage detection circuit 4A.
Here, the calculation process in which the voltage detection circuit 4A detects eight voltages according to the drive patterns 1 to 8 can be expressed by the above equation (6).
 アダマール変換行列の8つの各行は、上記の8つの駆動パターン1~8に相当する。また、各行の1、-1とは、各駆動パターンのXラインX1~X8と駆動回路3の接続状態に対応する。
 電圧検出回路4Aから出力される出力電圧D1~D8は、A/D変換回路5でそれぞれA/D変換される。このA/D変換された各出力電圧D1~D8は、容量算出回路6Aに順次記憶される。
Each of the eight rows of the Hadamard transform matrix corresponds to the eight drive patterns 1 to 8 described above. Further, 1 and −1 in each row correspond to the connection state between the X lines X1 to X8 of each drive pattern and the drive circuit 3.
Output voltages D1 to D8 output from the voltage detection circuit 4A are A / D converted by the A / D conversion circuit 5, respectively. The A / D converted output voltages D1 to D8 are sequentially stored in the capacity calculation circuit 6A.
 そして、出力電圧D1~D8の記憶が完了すると、容量算出回路6Aは、記憶した出力電圧D1~D8と変換行列であるアダマール変換行列とに基づき、静電容量C1~C8をそれぞれ算出する演算を行う。この容量算出回路6Aが行う演算処理は、上記の(7)式で表すことができる。
 タッチ位置検出回路7Aは、容量算出回路6Aが算出した静電容量C1~C8に基づいて、タッチパネル1のタッチ位置を検出する。
When the storage of the output voltages D1 to D8 is completed, the capacity calculation circuit 6A performs an operation for calculating the capacitances C1 to C8 based on the stored output voltages D1 to D8 and the Hadamard transform matrix as a conversion matrix. Do. The arithmetic processing performed by the capacity calculation circuit 6A can be expressed by the above equation (7).
The touch position detection circuit 7A detects the touch position of the touch panel 1 based on the capacitances C1 to C8 calculated by the capacitance calculation circuit 6A.
 以上の動作は、タッチパネル1上のタッチ位置を1次元的な動作により検出する例であるが、タッチパネル1上のタッチ位置を2次元的な動作により検出する場合には、上記の動作を繰り返すことになる。
 この場合には、YラインY1~Y8と電圧検出回路4Aとの接続を順次変更し、この変更ごとに、電圧検出回路4Aが、上記の駆動パターン1~8に応じて8つの電圧を検出する演算処理を行う。
The above operation is an example in which the touch position on the touch panel 1 is detected by a one-dimensional operation. However, when the touch position on the touch panel 1 is detected by a two-dimensional operation, the above operation is repeated. become.
In this case, the connection between the Y lines Y1 to Y8 and the voltage detection circuit 4A is sequentially changed, and for each change, the voltage detection circuit 4A detects eight voltages according to the drive patterns 1 to 8. Perform arithmetic processing.
 以上のように、第3実施形態では、電圧検出回路4Aを図17に示すようにシングル型で構成するようにしたので、その構成が簡易となる。
 また、第3実施形態では、図17に示すコンデンサCR3およびスイッチSW20を省略するようにしても良い。この場合には、図18(A)の場合の検出を省略して測定値として例えば0などの固定値を使用する。
As described above, in the third embodiment, since the voltage detection circuit 4A is configured as a single type as shown in FIG. 17, the configuration is simplified.
In the third embodiment, the capacitor CR3 and the switch SW20 shown in FIG. 17 may be omitted. In this case, the detection in the case of FIG. 18A is omitted, and a fixed value such as 0 is used as the measurement value.
 なお、第3実施形態では、(6)式に示すように、8行×8列のアダマール変換行列を使用するようにした。しかし、4行×4列、16行×16列などのアダマール変換行列を使用することもできる。
 このため、n行×n列(n=2、4の倍数)のアダマール変換行列を使用する場合には、上記の駆動パターンはn個となり、この各駆動パターンに応じて駆動回路3に接続される駆動ラインはn個となる。上記の例では、駆動パターンは図18および図19に示すように8つとなり、この8つの駆動パターンに応じて駆動回路3に接続される駆動ラインは8つとなる。
In the third embodiment, an Hadamard transformation matrix of 8 rows × 8 columns is used as shown in the equation (6). However, a Hadamard transform matrix such as 4 rows × 4 columns or 16 rows × 16 columns can also be used.
For this reason, when the Hadamard transformation matrix of n rows × n columns (n = 2, multiple of 4) is used, the number of the driving patterns is n, and the driving circuit 3 is connected according to each driving pattern. There are n drive lines. In the above example, there are eight drive patterns as shown in FIGS. 18 and 19, and there are eight drive lines connected to the drive circuit 3 in accordance with these eight drive patterns.
(第3実施形態の動作の変形例)
 多点タッチ検出が不要な場合、第2実施形態の動作の代わりに次のような動作を行うことによりタッチ位置のX,Y座標を検出することができる。
 まず、選択回路2は、予め定めてある検出パターンに応じて、タッチパネル1のYラインY1~Y8のうち、予め定めてある1つのラインを検出ラインとして選択する代わりに全てのYラインを選択する。それ以外は全て第3実施形態の動作の説明と同様である。これによりタッチ位置のX座標が検出できる。次に前述の動作をXラインとYラインを交換して再度行う。これによりタッチ位置のY座標が検出できる。
(Modification of the operation of the third embodiment)
When multi-point touch detection is not required, the X and Y coordinates of the touch position can be detected by performing the following operation instead of the operation of the second embodiment.
First, the selection circuit 2 selects all Y lines instead of selecting one predetermined line as a detection line from among the Y lines Y1 to Y8 of the touch panel 1 in accordance with a predetermined detection pattern. . The rest is the same as the description of the operation of the third embodiment. Thereby, the X coordinate of the touch position can be detected. Next, the above operation is performed again by exchanging the X line and the Y line. Thereby, the Y coordinate of the touch position can be detected.
(第4実施形態の構成)
 図20は、本発明の第4実施形態が適用されるタッチセンサの概略構成を示すブロック図である。
 第4実施形態が適用されるタッチセンサは、図20に示すように、タッチパネル1と、選択回路2と、駆動回路3と、電圧検出回路4と、A/D変換回路5と、容量算出回路6Bと、タッチ位置検出回路7Bと、制御回路8Cと、アドレス生成回路9と、メモリ10と、ラッチ11と、オフセット調整用の静電容量回路12と、を備えている。
 すなわち、第4実施形態は、図11に示す第2実施形態の構成を基本とし、図20に示すように、図11の容量算出回路6A、タッチ位置検出回路7A、および制御回路8Aを、容量算出回路6B、タッチ位置検出回路7B、および制御回路8Cに置き換えたものである。
(Configuration of Fourth Embodiment)
FIG. 20 is a block diagram showing a schematic configuration of a touch sensor to which the fourth embodiment of the present invention is applied.
As shown in FIG. 20, the touch sensor to which the fourth embodiment is applied includes a touch panel 1, a selection circuit 2, a drive circuit 3, a voltage detection circuit 4, an A / D conversion circuit 5, and a capacitance calculation circuit. 6B, a touch position detection circuit 7B, a control circuit 8C, an address generation circuit 9, a memory 10, a latch 11, and a capacitance circuit 12 for offset adjustment.
That is, the fourth embodiment is based on the configuration of the second embodiment shown in FIG. 11. As shown in FIG. 20, the capacitance calculation circuit 6A, the touch position detection circuit 7A, and the control circuit 8A shown in FIG. The calculation circuit 6B, the touch position detection circuit 7B, and the control circuit 8C are replaced.
 ここで、第4実施形態は、第2実施形態の構成要素と共通する部分があり、この共通の構成要素には同一符号を付してその説明はできるだけ省略する。
 制御回路8Cは、タッチパネル1のタッチ位置を検出するときに、駆動回路3、電圧検出回路4、アドレス生成回路9、ラッチ11、および静電容量回路12をそれぞれ制御する。
Here, the fourth embodiment has parts common to the components of the second embodiment, and the common components are denoted by the same reference numerals, and description thereof is omitted as much as possible.
The control circuit 8C controls the drive circuit 3, the voltage detection circuit 4, the address generation circuit 9, the latch 11, and the capacitance circuit 12 when detecting the touch position of the touch panel 1.
(第4実施形態の動作)
 次に、第4実施形態において、タッチパネル1のタッチ位置を検出する場合について、図20~図36を参照して説明する。
 まず、選択回路2は、所定の変換行列に応じて予め定めてある64個の変換パターン(駆動パターンと検出パターンの組み合わせ)のうちの1つが選択されたときに、その選択された変換パターンに応じて、タッチパネル1のYラインY1~Y8のうちの一部を駆動回路3の出力端子33と接続し、YラインY1~Y8のうちの残りを駆動回路3の出力端子34と接続する。
(Operation of Fourth Embodiment)
Next, a case where the touch position of the touch panel 1 is detected in the fourth embodiment will be described with reference to FIGS.
First, when one of 64 conversion patterns (combination of drive pattern and detection pattern) that is predetermined according to a predetermined conversion matrix is selected, the selection circuit 2 selects the selected conversion pattern. Accordingly, a part of the Y lines Y1 to Y8 of the touch panel 1 is connected to the output terminal 33 of the drive circuit 3, and the rest of the Y lines Y1 to Y8 is connected to the output terminal 34 of the drive circuit 3.
 また、選択回路2は、上記の変換パターンが選択されたときに、その選択された変換パターンに応じて、タッチパネル1のXラインX1~X8のうちの一部を電圧検出回路4の入力端子44と接続し、XラインX1~X8のうちの残りを電圧検出回路4の入力端子45と接続する。
 図21~図36は、アダマール変換行列に応じて定めた64個の変換パターンと、これら64個の変換パターンに応じた、YラインY1~Y8と駆動回路3の接続状態、およびXラインX1~X8と電圧検出回路4との接続状態を示している。
Further, when the above conversion pattern is selected, the selection circuit 2 selects a part of the X lines X1 to X8 of the touch panel 1 according to the selected conversion pattern as the input terminal 44 of the voltage detection circuit 4. And the remainder of the X lines X 1 to X 8 is connected to the input terminal 45 of the voltage detection circuit 4.
21 to 36 show 64 conversion patterns determined according to the Hadamard transformation matrix, the connection states of the Y lines Y1 to Y8 and the drive circuit 3 according to these 64 conversion patterns, and the X lines X1 to X1. The connection state between X8 and the voltage detection circuit 4 is shown.
 ここで、図21および図22は、パターン1と8つのパターン1~8とを組み合わせた8つの変換パターンを示す。図23および図24は、パターン2と8つのパターン1~8とを組み合わせた8つの変換パターンを示す。図25および図26は、パターン3と8つのパターン1~8とを組み合わせた8つの変換パターンを示す。図27および図28は、パターン4と8つのパターン1~8とを組み合わせた8つの変換パターンを示す。 Here, FIG. 21 and FIG. 22 show eight conversion patterns obtained by combining pattern 1 and eight patterns 1-8. 23 and 24 show eight conversion patterns obtained by combining the pattern 2 and the eight patterns 1 to 8. FIG. 25 and 26 show eight conversion patterns obtained by combining the pattern 3 and the eight patterns 1 to 8. 27 and 28 show eight conversion patterns obtained by combining the pattern 4 and the eight patterns 1 to 8. FIG.
 また、図29および図30は、パターン5と8つのパターン1~8とを組み合わせた8つの変換パターンを示す。図31および図32は、パターン6と8つのパターン1~8とを組み合わせた8つの変換パターンを示す。図33および図34は、パターン7と8つのパターン1~8とを組み合わせた8つの変換パターンを示す。図35および図36は、パターン8と8つのパターン1~8とを組み合わせた8つの変換パターンを示す。 29 and 30 show eight conversion patterns obtained by combining pattern 5 and eight patterns 1-8. 31 and 32 show eight conversion patterns obtained by combining the pattern 6 and the eight patterns 1 to 8. 33 and 34 show eight conversion patterns obtained by combining the pattern 7 and the eight patterns 1-8. 35 and 36 show eight conversion patterns obtained by combining the pattern 8 and the eight patterns 1 to 8. FIG.
 図21~図36の例ではY軸を駆動回路3、X軸を電圧検出回路4に接続する構成をとっているが、逆にX軸を駆動回路3、Y軸を電圧検出回路4に接続する構成にしてもよい。また、パターンごとに駆動回路3、電圧検出回路4をX軸に接続するかY軸に接続するか変えても良い。図21、図22の例では電圧検出回路4がシングルエンドの構成になっている。この場合、図21(A)の場合を除き、駆動回路3の+端子と電圧検出回路4の+端子を入れ替え、駆動回路3の-端子と電圧検出回路4の-端子を入れ替えることによって電圧検出回路4を差動の構成に変形することにより、図21(A)のパターンを除く全てのパターンで差動の構成の電圧検出回路4を利用することになり、S/Nをさらに向上させることができる。また、駆動回路3の+端子と電圧検出回路4の+端子、および駆動回路3の-端子と電圧検出回路4の-端子を入れ替えても容量算出回路6Bの動作は同一で良い。さらに図21(A)の測定を省略して測定値を0と扱うことにより、シングルエンド構成の電圧検出回路を全く用いないよう変換パターンを構成しても良く、さらにS/Nを向上させることができる。
 軸Xiと軸Yjの間に形成される静電容量をCijとすると、電圧検出回路4の出力Dmnに現れる値との関係は次の(7A)式のようになる。
21 to 36, the Y axis is connected to the drive circuit 3 and the X axis is connected to the voltage detection circuit 4, but the X axis is connected to the drive circuit 3 and the Y axis is connected to the voltage detection circuit 4. You may make it the structure to carry out. Moreover, you may change whether the drive circuit 3 and the voltage detection circuit 4 are connected to an X-axis or a Y-axis for every pattern. In the examples of FIGS. 21 and 22, the voltage detection circuit 4 has a single-ended configuration. In this case, except for the case of FIG. 21A, voltage detection is performed by switching the + terminal of the drive circuit 3 and the + terminal of the voltage detection circuit 4 and switching the − terminal of the drive circuit 3 and the − terminal of the voltage detection circuit 4. By modifying the circuit 4 to a differential configuration, the voltage detection circuit 4 having a differential configuration is used in all patterns except the pattern of FIG. 21A, and the S / N is further improved. Can do. Further, even if the + terminal of the drive circuit 3 and the + terminal of the voltage detection circuit 4 and the − terminal of the drive circuit 3 and the − terminal of the voltage detection circuit 4 are interchanged, the operation of the capacitance calculation circuit 6B may be the same. Further, by omitting the measurement of FIG. 21A and treating the measured value as 0, a conversion pattern may be configured so as not to use the single-ended voltage detection circuit at all, and the S / N is further improved. Can do.
Assuming that the capacitance formed between the axis Xi and the axis Yj is Cij, the relationship with the value appearing at the output Dmn of the voltage detection circuit 4 is expressed by the following equation (7A).
Figure JPOXMLDOC01-appb-M000008
Figure JPOXMLDOC01-appb-M000008
 なお、図21~図36において、図中の符号「+」はsminj=+1であり、符号「-」はsminj=-1である。smi,snjはそれぞれ後述の(9)式で表されるアダマール変換行列の(m,i)成分、(n,j)成分である。
 次に、上記の64個の変換パターンごとに、駆動回路3および電圧検出回路4は、図5に示す「状態1」と「状態2」の動作を行い、電圧検出回路4はその64個の変換パターンに応じた電位差を検出する。
 ここで、電圧検出回路4が、上記の64個の変換パターンに応じてそれぞれ電位差に応じた電圧を検出する演算処理は、次の(8)式で表すことができる。なお、(7A)式のVCOMとVDD/Cfの項は静電容量算出およびタッチ位置検出に無関係なため、簡略化のため省略した。
21 to 36, the sign “+” in the figure is s mi s nj = + 1, and the sign “−” is s mi s nj = −1. s mi and s nj are the (m, i) component and (n, j) component of the Hadamard transform matrix expressed by the following equation (9), respectively.
Next, for each of the 64 conversion patterns, the drive circuit 3 and the voltage detection circuit 4 perform the operations of “state 1” and “state 2” shown in FIG. 5, and the voltage detection circuit 4 A potential difference corresponding to the conversion pattern is detected.
Here, the calculation process in which the voltage detection circuit 4 detects the voltage corresponding to the potential difference in accordance with the 64 conversion patterns can be expressed by the following equation (8). Note that the terms VCOM and VDD / Cf in equation (7A) are irrelevant to capacitance calculation and touch position detection, and are therefore omitted for the sake of brevity.
Figure JPOXMLDOC01-appb-M000009
Figure JPOXMLDOC01-appb-M000009
 (8)式において、Dは上記の64個の変換パターンに応じて得られる電圧検出回路4の64個の出力電圧(検出電圧)であり、8×8の行列である。(8)式の右辺のHは、(9)式に示すアダマール変換行列である。
 また、(8)式において、Cは、タッチパネル1のXラインX1~X8とYラインY1~Y8との各交差部における64個の静電容量であり、8×8の行列である。さらに、(8)式の右辺のHであって右肩に添字Tが付いたものは、(9)式のアダマール変換行列の行と列を入れ換えたものである。
In the equation (8), D is 64 output voltages (detected voltages) of the voltage detection circuit 4 obtained according to the 64 conversion patterns, and is an 8 × 8 matrix. H on the right side of equation (8) is the Hadamard transform matrix shown in equation (9).
In the equation (8), C is 64 capacitances at the intersections of the X lines X1 to X8 and the Y lines Y1 to Y8 of the touch panel 1, and is an 8 × 8 matrix. Further, the H on the right side of equation (8) and the subscript T attached to the right shoulder is obtained by replacing the rows and columns of the Hadamard transform matrix of equation (9).
Figure JPOXMLDOC01-appb-M000010
Figure JPOXMLDOC01-appb-M000010
 電圧検出回路4から出力される64個の出力電圧は、図5の「状態2」の動作の所定のタイミングにおいて、A/D変換回路5でそれぞれA/D変換される。このA/D変換された各出力電圧は、容量算出回路6Bに順次記憶される。そして、その出力電圧の記憶が完了すると、容量算出回路6Bは、記憶した出力電圧と変換行列であるアダマール変換行列とに基づき、タッチパネル1のXラインX1~X8とYラインY1~Y8との各交差部における64個の静電容量をそれぞれ算出する演算を行う。
 この容量算出回路6Bが行う演算処理は、次の(10)式で表すことができる。
The 64 output voltages output from the voltage detection circuit 4 are each A / D converted by the A / D conversion circuit 5 at a predetermined timing of the operation of “state 2” in FIG. The A / D converted output voltages are sequentially stored in the capacity calculation circuit 6B. When the storage of the output voltage is completed, the capacitance calculation circuit 6B, based on the stored output voltage and the Hadamard transformation matrix that is a transformation matrix, each of the X lines X1 to X8 and the Y lines Y1 to Y8 of the touch panel 1 is stored. An operation for calculating each of the 64 capacitances at the intersection is performed.
The arithmetic processing performed by the capacity calculation circuit 6B can be expressed by the following equation (10).
Figure JPOXMLDOC01-appb-M000011
Figure JPOXMLDOC01-appb-M000011
 タッチ位置検出回路7Bは、容量算出回路6Bが算出した64個の静電容量に基づいて、タッチパネル1のタッチ位置を検出する。
 以上のように、第4実施形態では、電圧検出回路4が、64個の変換パターンに応じた演算処理を行なって64個の出力電圧をそれぞれ得るようにし、その各出力電圧を得るときに差動増幅を行うようにした。このため、その各出力電圧を得るときにノイズを軽減できる上に、S/Nの向上を図ることができる。
 なお、第4実施形態では、(8)(9)式に示すように、8行×8列のアダマール変換行列を使用するようにした。しかし、2行×2列、4行×4列、16行×16列などのアダマール変換行列を使用することもできる。
The touch position detection circuit 7B detects the touch position of the touch panel 1 based on the 64 electrostatic capacitances calculated by the capacity calculation circuit 6B.
As described above, in the fourth embodiment, the voltage detection circuit 4 performs arithmetic processing according to the 64 conversion patterns to obtain 64 output voltages, respectively, and the difference is obtained when each output voltage is obtained. Dynamic amplification was performed. For this reason, when obtaining each output voltage, noise can be reduced and S / N can be improved.
In the fourth embodiment, an Hadamard transformation matrix of 8 rows × 8 columns is used as shown in equations (8) and (9). However, a Hadamard transformation matrix such as 2 rows × 2 columns, 4 rows × 4 columns, 16 rows × 16 columns, or the like can also be used.
 さらに、X軸方向にm行×m列(m=2、4の倍数)、Y軸方向にn行×n列(n=2、4の倍数)のアダマール変換行列を使用する場合には、上記の変換パターンは(m×n)個となり、各変換パターンに応じて、駆動回路3に接続される駆動ラインはm個となるとともに、電圧検出回路4に接続される検出ラインはn個となる。
 上記の例では、変換パターンは図21~図36に示すように64個となり、駆動回路3に接続される駆動ラインは8個、電圧検出回路4に接続される検出ラインは8個となる。
Further, when using a Hadamard transform matrix of m rows × m columns (m = 2, multiple of 4) in the X axis direction and n rows × n columns (n = 2, multiples of 4) in the Y axis direction, The number of the conversion patterns is (m × n), and according to each conversion pattern, the number of drive lines connected to the drive circuit 3 is m, and the number of detection lines connected to the voltage detection circuit 4 is n. Become.
In the above example, there are 64 conversion patterns as shown in FIGS. 21 to 36, 8 drive lines connected to the drive circuit 3, and 8 detection lines connected to the voltage detection circuit 4.
(第4実施形態の変形例1)
 第4実施形態の変形例1の構成、動作は、第4実施形態と基本的に同一である。以下、第4実施形態と異なる部分について説明する。
 XラインX1~X8のうち、X1、X2をXライングループ1、X3,X4をXライングループ2、X5,X6をXライングループ3、X7,X8をXライングループ4にグループ分けする。すなわち、XラインX1~X8は4つのグループに分けられる。
 一方、YラインY1~Y8のうち、Y1,Y2,Y3,Y4をYライングループ1、Y5,Y6,Y7,Y8をYライングループ2にグループ分けする。すなわち、YラインY1~Y8は2つのグループに分けられる。
(Modification 1 of 4th Embodiment)
The configuration and operation of Modification 1 of the fourth embodiment are basically the same as those of the fourth embodiment. Hereinafter, a different part from 4th Embodiment is demonstrated.
Among X lines X1 to X8, X1 and X2 are grouped into X line group 1, X3 and X4 are grouped into X line group 2, X5 and X6 are grouped into X line group 3, and X7 and X8 are grouped into X line group 4. That is, the X lines X1 to X8 are divided into four groups.
On the other hand, among Y lines Y1 to Y8, Y1, Y2, Y3, Y4 are grouped into Y line group 1, and Y5, Y6, Y7, Y8 are grouped into Y line group 2. That is, the Y lines Y1 to Y8 are divided into two groups.
 前述のグループ分けにより東ねられた電極を1本の電極とみなすと、Xラインは4本、Yラインは2本のパネルと見ることができる。後は第4実施形態と同様、Xラインは4行×4列のアダマール変換、Yラインは2行×2列のアダマール変換を適用した駆動・検出パターンを作成することができる。パターンの全ての組み合わせを図37、図38に示す。XラインとYラインのグループ分けを符号「{ 」で示す。 Suppose that the electrodes that are easted by the above grouping are regarded as one electrode, it can be seen that the X line is four and the Y line is two panels. After that, similarly to the fourth embodiment, it is possible to create a drive / detection pattern in which the Hadamard transform of 4 rows × 4 columns is applied to the X line and the Hadamard transform of 2 rows × 2 columns is applied to the Y line. All combinations of patterns are shown in FIGS. The grouping of the X line and the Y line is indicated by a symbol “{”.
 図37、図38で示される駆動・検出パタ-ンをメモリ10に格納し、選択回路2、駆動回路3、電圧検出回路4、A/D変換回路5を第4実施形態と同様に動作させてA/D変換した値を取得する。その後は、容量算出回路6BにおいてXラインは4グル-プであるので4行×4列のアダマール変換、Yラインは2グル-プであるので2行×2列のアダマール変換を使用して第4実施形態と同様の処理を行う。 The drive / detection patterns shown in FIGS. 37 and 38 are stored in the memory 10, and the selection circuit 2, the drive circuit 3, the voltage detection circuit 4, and the A / D conversion circuit 5 are operated in the same manner as in the fourth embodiment. The A / D converted value is acquired. After that, in the capacity calculation circuit 6B, the X line is 4 groups, so the 4 rows × 4 columns Hadamard transform is used, and the Y line is 2 groups, so the 2 rows × 2 columns Hadamard transform is used. The same processing as in the fourth embodiment is performed.
 これにより、XラインX1,X2とYラインY1,Y2,Y3,Y4の交差部に形成される静電容量の合計、XラインX1,X2とYラインY5,Y6,Y7,Y8の交差部に形成される静電容量の合計、XラインX3,X4とYラインY1,Y2,Y3,Y4の交差部に形成される静電容量の合計、XラインX3,X4とYラインY5,Y6,Y7,Y8の交差部に形成される静電容量の合計がそれぞれ求められる。さらに、XラインX5,X6とYラインY1,Y2,Y3,Y4の交差部に形成される静電容量の合計、XラインX5,X6とYラインY5,Y6,Y7,Y8の交差部に形成される静電容量の合計、XラインX7,X8とYラインY1,Y2,Y3,Y4の交差部に形成される静電容量の合計、XラインX7,X8とYラインY5,Y6,Y7,Y8の交差部に形成される静電容量の合計がそれぞれ求められる。以上のように、第4実施形態の変形例1は第4実施形態に比べて測定点数が少ないため、低消費電カモ-ドでの動作に都合が良い。また、空間解像度が落ちた分、グル-プごとの容量変化が大きくとれるので特にホバリングの検出に都合が良い。 As a result, the total capacitance formed at the intersection of X line X1, X2 and Y line Y1, Y2, Y3, Y4, and at the intersection of X line X1, X2 and Y line Y5, Y6, Y7, Y8. Total capacitance formed, total capacitance formed at the intersection of X line X3, X4 and Y line Y1, Y2, Y3, Y4, X line X3, X4 and Y line Y5, Y6, Y7 , Y8, the total capacitances formed at the intersections are respectively obtained. Furthermore, the total capacitance formed at the intersection of X line X5, X6 and Y line Y1, Y2, Y3, Y4, formed at the intersection of X line X5, X6 and Y line Y5, Y6, Y7, Y8 The total capacitance formed, the total capacitance formed at the intersection of X lines X7, X8 and Y lines Y1, Y2, Y3, Y4, X lines X7, X8 and Y lines Y5, Y6, Y7, The total capacitance formed at the intersection of Y8 is determined. As described above, Modification 1 of the fourth embodiment has a smaller number of measurement points than the fourth embodiment, and is convenient for operation in a low power consumption mode. In addition, since the capacity change for each group can be greatly increased as the spatial resolution is reduced, it is particularly convenient for detecting hovering.
(第4実施形態の変形例2)
 この変形例2は、タッチパネルのライン数(電極数)が4の倍数でない場合であり、例えばX軸方向で7個、Y軸方向で9個の場合である。
 この変形例2は、基本構成は図20と同一であり、タッチパネル1のサイズだけが異なっている。また、その動作も第4実施形態と同様である。以下、第4実施形態と異なる部分だけを説明する。
(Modification 2 of 4th Embodiment)
Modification 2 is a case where the number of touch panel lines (number of electrodes) is not a multiple of 4, for example, 7 in the X-axis direction and 9 in the Y-axis direction.
In the second modification, the basic configuration is the same as that in FIG. 20, and only the size of the touch panel 1 is different. The operation is the same as that of the fourth embodiment. Only the parts different from the fourth embodiment will be described below.
 X軸、Y軸それぞれの方向でアダマール変換行列の大きさを電極数以上の4の倍数で選ぶ。ここではX軸方向の電極数は7であるのでX軸方向には7以上の最小の4の倍数として8、すなわち8行×8列のアダマール変換行列を使用する。Y軸方向の電極数は9であるのでY軸方向には9以上の最小の4の倍数として12、すなわち12行×12列のアダマール変換行列を使用する。 ¡Select the size of the Hadamard transform matrix in multiples of 4 greater than the number of electrodes in the X-axis and Y-axis directions. Here, since the number of electrodes in the X-axis direction is 7, an Hadamard transformation matrix of 8, that is, 8 rows × 8 columns, is used as the minimum multiple of 4 in the X-axis direction. Since the number of electrodes in the Y-axis direction is 9, 12 is used as the minimum multiple of 4 in the Y-axis direction, that is, a 12-row × 12-column Hadamard transformation matrix is used.
 変換パタ-ンは選択したサイズのアダマール変換行列に従い、X軸方向に8種類、Y軸方向に12種類、これらの全ての組み合わせである8×12=96種類の変換パタ-ンを使用する。
 軸Xと軸Yの間に形成される静電容量をCijとすると、電圧検出回路4の出力Dmnに現れる値との関係は(11)式のようになる。
According to the Hadamard transformation matrix of the selected size, 8 types in the X-axis direction, 12 types in the Y-axis direction, and 8 × 12 = 96 types of conversion patterns, which are all combinations thereof, are used.
Assuming that the capacitance formed between the axis X i and the axis Y j is C ij, the relationship with the value appearing at the output Dmn of the voltage detection circuit 4 is as shown in equation (11).
Figure JPOXMLDOC01-appb-M000012
Figure JPOXMLDOC01-appb-M000012
 但し、m=1,2,…,8、n=1,2,…,12である。
 smiは前述の8行×8列のアダマール変換行列の(m,i)成分であり、snj’は前述の12行×12列のアダマール変換行列の(n,j)成分である。但し、i=1,2,…,7、j=1,2,…,9であるのでアダマール変換行列の一部の成分は使用されない。
However, m = 1, 2,..., 8 and n = 1, 2,.
s mi is the (m, i) component of the aforementioned 8-row × 8-column Hadamard transform matrix, and s nj ′ is the (n, j) component of the aforementioned 12-row × 12-column Hadamard transform matrix. However, since i = 1, 2,..., 7 and j = 1, 2,..., 9, some components of the Hadamard transform matrix are not used.
 次に上記の96個の変換パターンごとに、駆動回路3と電圧検出回路4は、図5に示す「状態1」と「状態2」の動作を行い、電圧検出回路4はその96個の変換パターンに応じた電位差を検出する。
 ここで電圧検出回路4が、上記の96個の変換パターンに応じてそれぞれ電位差に応じた電圧を検出する演算処理は、次の(12)式で表すことができる。なお、(11)式のVCOMとVDD/Cfの項は静電容量算出およびタッチ位置検出には無関係なため、簡略化のため省略した。
Next, for each of the 96 conversion patterns, the drive circuit 3 and the voltage detection circuit 4 perform the operations of “state 1” and “state 2” shown in FIG. 5, and the voltage detection circuit 4 performs the 96 conversions. A potential difference corresponding to the pattern is detected.
Here, the calculation process in which the voltage detection circuit 4 detects the voltage corresponding to the potential difference in accordance with the 96 conversion patterns can be expressed by the following equation (12). Note that the terms VCOM and VDD / Cf in equation (11) are irrelevant to the capacitance calculation and the touch position detection, and are therefore omitted for simplification.
Figure JPOXMLDOC01-appb-M000013
Figure JPOXMLDOC01-appb-M000013
 この容量算出回路6Bが行う演算処理は、次の(14)式で表すことができる。 The calculation process performed by the capacity calculation circuit 6B can be expressed by the following equation (14).
Figure JPOXMLDOC01-appb-M000014
Figure JPOXMLDOC01-appb-M000014
 但し、Hは(13A)式で表されるように8行×8列のアダマール変換行列の第8列目(一番右の列)を削除して列数をX軸方向の電極数に一致させたもので、(11)式のsmiの行列表現である。なお、削除する列の位置はどこでもよく、列を削除した結果列数がX軸方向の電極数に一致していれば良い。この転置行列H とHは互いにムーア・ペンローズの一般化逆行列(のスカラー倍)の関係になっている。また、Hは(13B)式で表されるように12行×12列のアダマール変換行列の第10~12列目(一番右側の3列)を削除して列数をY軸方向の電極数に一致させたもので、(11)式のsnj’の行列表現である。なお、削除する列の位置はどこでも良く、列を削除した結果列数がY軸方向の電極数に一致していれば良い。また削除する列が隣り合っていなくても良い。この転置行列H とHは互いにムーア・ペンローズの一般化逆行列(のスカラー倍)の関係になっている。 However, H x is the 8th row × 8th column Hadamard transformation matrix as shown in the equation (13A), and the 8th column (the rightmost column) is deleted to make the number of columns the number of electrodes in the X-axis direction. This is a matrix representation of s mi in equation (11). Note that the position of the column to be deleted may be anywhere, and the number of columns as a result of deleting the column only needs to match the number of electrodes in the X-axis direction. The transposed matrices H x T and H x are in a Moore-Penrose generalized inverse matrix (scalar multiple). Also, H y is the number of columns in the Y-axis direction to remove the 10-12 column of the Hadamard transform matrix of 12 rows × 12 columns as expressed by (13B) (3 rows of rightmost) This corresponds to the number of electrodes, and is a matrix representation of s nj ′ in equation (11). Note that the position of the column to be deleted may be anywhere, and the number of columns as a result of deleting the column only needs to match the number of electrodes in the Y-axis direction. The columns to be deleted need not be adjacent to each other. The transposed matrices H y T and H y are in a Moore-Penrose generalized inverse matrix (scalar multiple).
 電圧検出回路4から出力される出力電圧は96個と電極数63個よりも多いが、(14)式のH ,Hはそれぞれ(12)式のH,H の一般化逆行列であるため、得られたCijは(11)式を満たす最小二乗解になっている。そのため電圧検出回路4の出力電圧の個数が多ければ多いほどS/Nも改善される。
 なお、変形例2ではH,Hはアダマール変換行列の一部の行を削除したものを使用しているが、アダマール変換行列のみならず、直交変換行列および直交変換行列のスカラー倍の一部の列を削除した行列もその転置行列が元の行列と互いにムーア・ペンローズの一般化逆行列(のスカラー倍)の関係になるので、本変形例が適用可能である。
Although the output voltage output from the voltage detection circuit 4 is 96 and more than 63 electrodes, H x T and H y in the equation (14) are generalizations of H x and H y T in the equation (12), respectively. Since it is an inverse matrix, the obtained C ij is a least squares solution that satisfies the equation (11). Therefore, the greater the number of output voltages of the voltage detection circuit 4, the better the S / N.
In Modification 2, H x and H y are obtained by deleting some of the rows of the Hadamard transformation matrix, but not only the Hadamard transformation matrix but also an orthogonal transformation matrix and a scalar multiple of the orthogonal transformation matrix. Since the transposed matrix of the matrix from which a part of the column is deleted becomes a Moore-Penrose generalized inverse matrix (scalar multiple) of the original matrix, this variation can be applied.
 タッチ位置検出回路7Bは、容量算出回路6Bが算出した63個の静電容量に基づいて、タッチパネル1のタッチ位置を検出する。
 なお、本変形例は第4実施例の変形例1でグループ分けによる電極グループ数が2、または4の倍数でない場合においても適用可能である。
The touch position detection circuit 7B detects the touch position of the touch panel 1 based on the 63 electrostatic capacitances calculated by the capacitance calculation circuit 6B.
This modification can be applied even when the number of electrode groups by grouping is not 2 or a multiple of 4 in Modification 1 of the fourth embodiment.
(第5実施形態)
 第5実施形態は、図1に示すように、タッチパネル1、選択回路2、駆動回路3、電圧検出回路4、A/D変換回路5、容量算出回路6、タッチ位置検出回路7、制御回路8、アドレス生成回路9、メモリ10、およびラッチ11を備えている。しかし、容量算出回路6、タッチ位置検出回路7、制御回路8などは、コンピュータに置き換えることが可能である。
(Fifth embodiment)
In the fifth embodiment, as shown in FIG. 1, the touch panel 1, the selection circuit 2, the drive circuit 3, the voltage detection circuit 4, the A / D conversion circuit 5, the capacitance calculation circuit 6, the touch position detection circuit 7, and the control circuit 8. , An address generation circuit 9, a memory 10, and a latch 11. However, the capacity calculation circuit 6, the touch position detection circuit 7, the control circuit 8, and the like can be replaced with a computer.
 そこで、この第5実施形態は、図1に示す容量算出回路6、タッチ位置検出回路7、制御回路8などの機能をコンピュータ(図示せず)に置き換え、コンピュータが、選択回路2、駆動回路3、電圧検出回路4などの動作の制御を行うとともに、容量算出回路6やタッチ位置検出回路7の演算処理を行うようにした。
 このため、この第5実施形態では、図37に示すように、予め定めた各種の制御や演算などの各処理の手順(プログラム)が例えば図1のメモリ10に予め格納され、その手順によって、コンピュータが各種の制御や演算などの処理を行うようにした。
Therefore, in the fifth embodiment, functions such as the capacity calculation circuit 6, the touch position detection circuit 7, and the control circuit 8 shown in FIG. 1 are replaced with a computer (not shown), and the computer performs the selection circuit 2 and the drive circuit 3 The operation of the voltage detection circuit 4 and the like are controlled, and the calculation processing of the capacitance calculation circuit 6 and the touch position detection circuit 7 is performed.
For this reason, in the fifth embodiment, as shown in FIG. 37, procedures (programs) of various processes such as various predetermined controls and calculations are stored in advance in, for example, the memory 10 of FIG. The computer performed various processing such as control and calculation.
 次に、図1および図37を参照して、第5実施形態のコンピュータによる各部の制御や演算の各処理について説明する。
 ここで、図1のメモリ10の複数の各アドレスには、予め定めてある駆動パターンおよび予め定めてある変換行列(例えばアダマール変換行列)に応じて定められた検出パターンごとに、選択回路2、駆動回路3、および電圧検出回路4の動作を制御する制御データが予め格納されているものとする。
Next, with reference to FIG. 1 and FIG. 37, each process of control of each part and calculation by the computer of 5th Embodiment is demonstrated.
Here, each of the plurality of addresses of the memory 10 of FIG. 1 includes a selection circuit 2 for each detection pattern determined according to a predetermined drive pattern and a predetermined conversion matrix (for example, Hadamard conversion matrix). It is assumed that control data for controlling operations of the drive circuit 3 and the voltage detection circuit 4 is stored in advance.
 ステップS1では、メモリ10に格納される駆動パターンおよび検出パターンに応じた制御データを読み出すために、メモリ10のアドレスを開始アドレスにセットする。
 ステップS2では、そのセットされたメモリ10の開始アドレスに格納される駆動および検出のパターンに応じた制御データを読み出す。
 ステップS3では、その制御データを基に、選択回路2のスイッチ部21-1~21-8のスイッチSW11~SW15がオンオフ制御されて、その選択回路2のスイッチが設定される。
In step S1, in order to read out control data corresponding to the drive pattern and detection pattern stored in the memory 10, the address of the memory 10 is set to the start address.
In step S2, control data corresponding to the drive and detection patterns stored at the start address of the set memory 10 is read.
In step S3, the switches SW11 to SW15 of the switch units 21-1 to 21-8 of the selection circuit 2 are on / off controlled based on the control data, and the switches of the selection circuit 2 are set.
 この結果、タッチパネル1のYラインY1~Y8のうち、予め定めてあるラインが駆動ラインとして選択され、駆動回路3の出力端子と接続される。また、タッチパネル1のXラインのX1~X8のうち、その一部が電圧検出回路4の一方の入力端子と接続され、その残りが電圧検出回路4の他方の入力端子と接続される。
 ステップS4では、メモリ10の開始アドレスに格納される制御データを基に、駆動回路3と電圧検出回路4の動作を「状態1」になるように設定する(図5参照)。この設定は、駆動回路3のスイッチSW1~SW4および電圧検出回路4のスイッチSW5、SW6を制御することにより行う。
As a result, a predetermined line among the Y lines Y1 to Y8 of the touch panel 1 is selected as a drive line and connected to the output terminal of the drive circuit 3. A part of the X lines X 1 to X 8 of the touch panel 1 is connected to one input terminal of the voltage detection circuit 4, and the rest is connected to the other input terminal of the voltage detection circuit 4.
In step S4, the operation of the drive circuit 3 and the voltage detection circuit 4 is set to “state 1” based on the control data stored at the start address of the memory 10 (see FIG. 5). This setting is performed by controlling the switches SW1 to SW4 of the drive circuit 3 and the switches SW5 and SW6 of the voltage detection circuit 4.
 その設定後、ステップS5では一定時間待機し、この待機が終了すると次のステップS6に進む。
 ステップS6では、メモリ10の開始アドレスに格納される制御データを基に、駆動回路3と電圧検出回路4の動作を「状態2」になるように設定する(図5参照)。この設定後、ステップS7では一定時間待機し、この待機が終了する。
After the setting, the process waits for a predetermined time in step S5, and when this standby is completed, the process proceeds to the next step S6.
In step S6, the operation of the drive circuit 3 and the voltage detection circuit 4 is set to “state 2” based on the control data stored at the start address of the memory 10 (see FIG. 5). After this setting, in step S7, the process waits for a predetermined time, and this standby is completed.
 上記の設定により、電圧検出回路4は、自己の2つの入力端子に入力される入力電圧の差分の電圧を検出し、この検出電圧をA/変換回路5に出力する。
 ステップS8では、A/D変換回路5から出力されるA/D変換値を取得する。
 ステップS9では、取得されたA/D変換値を記憶する。
 ステップS10では、メモリ10の現在のアドレスが終了アドレスか否かを判定する。この判定の結果、終了アドレスでない場合には(NO)、アドレスをインクリメントして(ステップS11)ステップS2に戻り、ステップS2~S10の一連の処理を行う。一方、終了アドレスの場合には(YES)、ステップS12に進む。
With the above setting, the voltage detection circuit 4 detects the voltage difference between the input voltages input to its two input terminals, and outputs the detected voltage to the A / conversion circuit 5.
In step S8, an A / D conversion value output from the A / D conversion circuit 5 is acquired.
In step S9, the acquired A / D conversion value is stored.
In step S10, it is determined whether or not the current address of the memory 10 is an end address. As a result of this determination, if it is not the end address (NO), the address is incremented (step S11), the process returns to step S2, and a series of processes of steps S2 to S10 is performed. On the other hand, in the case of an end address (YES), the process proceeds to step S12.
 ステップS12では、ステップS9で記憶されたA/D変換値を基に、アダマール逆変換を行うことにより、静電容量差の算出を行う。この算出は、図1の容量算出回路6の機能に相当する。
 ステップS13では、ステップS12で算出した静電容量差に基づいてタッチ位置の検出を行う。この検出は、図1のタッチ位置検出回路7の機能に相当する。
In step S12, the capacitance difference is calculated by performing Hadamard inverse transformation based on the A / D conversion value stored in step S9. This calculation corresponds to the function of the capacity calculation circuit 6 of FIG.
In step S13, the touch position is detected based on the capacitance difference calculated in step S12. This detection corresponds to the function of the touch position detection circuit 7 in FIG.
 ステップS14では、ステップS13で検出したタッチ位置の座標を出力する。
 以上のように、第5実施形態は、図1に示す容量算出回路6、タッチ位置検出回路7、制御回路8などの機能をコンピュータに置き換えたものである。
 しかし、図11の第2実施形態おいて、容量算出回路6A、タッチ位置検出回路7A、制御回路8Aなどの機能をコンピュータに置き換えても良い。また、図16の第3実施形態において、容量算出回路6A、タッチ位置検出回路7A、制御回路8Bなどの機能をコンピュータに置き換えても良い。さらに、図20の第4実施形態について、容量算出回路6B、タッチ位置検出回路7B、制御回路88Cなどの機能をコンピュータに置き換えても良い。
In step S14, the coordinates of the touch position detected in step S13 are output.
As described above, in the fifth embodiment, functions such as the capacity calculation circuit 6, the touch position detection circuit 7, and the control circuit 8 shown in FIG. 1 are replaced with a computer.
However, in the second embodiment of FIG. 11, the functions of the capacitance calculation circuit 6A, the touch position detection circuit 7A, the control circuit 8A, and the like may be replaced with a computer. In the third embodiment shown in FIG. 16, the functions of the capacitance calculation circuit 6A, the touch position detection circuit 7A, the control circuit 8B, and the like may be replaced with a computer. Furthermore, in the fourth embodiment of FIG. 20, the functions of the capacity calculation circuit 6B, the touch position detection circuit 7B, the control circuit 88C, and the like may be replaced with a computer.
 このようにコンピュータに置き換えた場合に、第2~第4の各実施形態のコンピュータによる各部の制御や演算の各処理は、図37に示すフローチャートと同様の手順で実現できる。
 しかし、第2~第4の各実施形態では、図11、図16または図20に示すように、静電容量回路12、12Aを含む。このため、図37のフローチャートにおいて、ステップS3とステップS4との間に、静電容量回路のスイッチと容量値の設定を行う処理が追加される。
When the computer is replaced in this way, the control of each part and the calculation processing by the computer of each of the second to fourth embodiments can be realized by the same procedure as the flowchart shown in FIG.
However, each of the second to fourth embodiments includes capacitance circuits 12 and 12A as shown in FIG. 11, FIG. 16, or FIG. For this reason, in the flowchart of FIG. 37, a process for setting the capacitance circuit switch and the capacitance value is added between step S3 and step S4.
 本発明のタッチセンサの信号処理回路は、タッチセンサに適用できる上に、そのタッチセンサを含む表示装置にも適用することができる。 The signal processing circuit of the touch sensor of the present invention can be applied not only to the touch sensor but also to a display device including the touch sensor.
 1・・・タッチパネル
 2・・・選択回路
 3・・・駆動回路
 4、4A・・・電圧検出回路
 5・・・A/D変換回路
 6、6A、6B・・・容量算出回路
 7、7A、7B・・・タッチ位置検出回路
 8、8A~8C・・・制御回路
 9・・・アドレス生成回路
 10・・・メモリ
 11・・・ラッチ
 12、12A・・・静電容量回路
 21-1~21-8、22-1~22-8・・・スイッチ部
 23-1~23-8、24-1~24-8・・・デコーダ
 25~29・・・接続ライン
 SW1~SW6・・・スイッチ
 SW11~SW15・・・スイッチ
DESCRIPTION OF SYMBOLS 1 ... Touch panel 2 ... Selection circuit 3 ... Drive circuit 4, 4A ... Voltage detection circuit 5 ... A / D conversion circuit 6, 6A, 6B ... Capacity calculation circuit 7, 7A, 7B: Touch position detection circuit 8, 8A to 8C ... Control circuit 9 ... Address generation circuit 10 ... Memory 11 ... Latch 12, 12A ... Capacitance circuit 21-1 to 21 -8, 22-1 to 22-8 ... Switch section 23-1 to 23-8, 24-1 to 24-8 ... Decoder 25 to 29 ... Connection line SW1 to SW6 ... Switch SW11 ~ SW15 ... Switch

Claims (33)

  1.  複数の第1のラインと、前記複数の第1のラインと絶縁層を介して交差するように配置される複数の第2のラインと、を備えるタッチパネルを含むタッチセンサの信号処理回路であって、
     第1の駆動端子および第2の駆動端子と、第1の検出端子および第2の検出端子と、出力端子とを有し、前記第1の駆動端子および前記第1の検出端子の間に接続された第1の静電容量と、前記第2の駆動端子および前記第1の検出端子の間に接続された第2の静電容量との差を第1の容量差として求め、前記第1の駆動端子および前記第2の検出端子の間に接続された第3の静電容量と、前記第2の駆動端子および前記第2の検出端子の間に接続された第4の静電容量との差を第2の容量差として求め、前記第1の容量差と第2の容量差との差を所定の信号に変換して出力する容量測定回路と、
     前記複数の第1のラインの中から、1つ以上のラインを第1の駆動ライン群として選択し、または前記第1の駆動ライン群に加えて前記第1の駆動ライン群とは異なる0本以上のラインを第2の駆動ライン群として選択し、前記第1の駆動ライン群を前記第1の駆動端子に接続し、前記第2の駆動ライン群を前記第2の駆動端子に接続し、かつ、前記複数の第2のラインの中から、0本以上のラインを第1の検出ライン群として選択し、前記第1の検出ライン群とは異なる1つ以上のラインを第2の検出ライン群として選択し、前記第1の検出ライン群を前記第1の検出端子に接続し、前記第2の検出ライン群を前記第2の検出端子に接続する選択回路と、
     を備えることを特徴とするタッチセンサの信号処理回路。
    A signal processing circuit of a touch sensor including a touch panel comprising: a plurality of first lines; and a plurality of second lines arranged to intersect the plurality of first lines via an insulating layer. ,
    A first drive terminal and a second drive terminal, a first detection terminal and a second detection terminal, and an output terminal, connected between the first drive terminal and the first detection terminal The first capacitance difference is obtained as a difference between the measured first capacitance and the second capacitance connected between the second drive terminal and the first detection terminal. A third capacitance connected between the second drive terminal and the second detection terminal, and a fourth capacitance connected between the second drive terminal and the second detection terminal. A capacitance measurement circuit that obtains the difference between the first capacitance difference and the second capacitance difference as a second signal, converts the difference between the first capacitance difference and the second capacitance difference into a predetermined signal, and outputs the difference.
    One or more lines are selected as the first drive line group from among the plurality of first lines, or 0 different from the first drive line group in addition to the first drive line group Selecting the above lines as a second drive line group, connecting the first drive line group to the first drive terminal, connecting the second drive line group to the second drive terminal, In addition, zero or more lines are selected as the first detection line group from the plurality of second lines, and one or more lines different from the first detection line group are selected as the second detection lines. A selection circuit for selecting as a group, connecting the first detection line group to the first detection terminal, and connecting the second detection line group to the second detection terminal;
    A signal processing circuit for a touch sensor, comprising:
  2.  前記選択回路は、
     予め決めてある変換行列に応じて定められた複数の検出パターンのうちの1つの検出パターンが選択されるたびに、当該選択される検出パターンに応じて、前記複数の第2のラインの中から、少なくとも1つのラインを前記第1の駆動ライン群として選択し、前記第1の駆動ライン群とは異なる少なくとも1つのラインを前記第2の駆動ライン群として選択することを特徴とする請求項1に記載のタッチセンサの信号処理回路。
    The selection circuit includes:
    Each time one detection pattern is selected from among a plurality of detection patterns determined according to a predetermined conversion matrix, the plurality of second lines are selected according to the selected detection pattern. 2. At least one line is selected as the first drive line group, and at least one line different from the first drive line group is selected as the second drive line group. A signal processing circuit of the touch sensor as described in 1.
  3.  前記容量測定回路の出力信号と前記変換行列とを基に演算を行い、前記選択された第1の駆動ライン群と前記選択された第1と第2の各検出ライン群との各交差部における静電容量と、これに対応する、前記選択された第2の駆動ライン群と前記選択された第1と第2の各検出ライン群との各交差部における静電容量との差の静電容量をそれぞれ算出する容量算出回路を、さらに備えることを特徴とする請求項2に記載のタッチセンサの信号処理回路。 An operation is performed based on the output signal of the capacitance measuring circuit and the conversion matrix, and at each intersection between the selected first drive line group and the selected first and second detection line groups. The electrostatic capacity of the difference between the electrostatic capacity and the corresponding electrostatic capacity at each intersection of the selected second drive line group and the selected first and second detection line groups. The touch sensor signal processing circuit according to claim 2, further comprising a capacitance calculation circuit for calculating each capacitance.
  4.  前記選択回路は、
     予め決めてある変換行列に応じて定められた複数の検出パターンのうちの1つの検出パターンが選択されるたびに、当該選択される検出パターンに応じて、前記複数の第1のラインの中から、1つ以上のラインを前記第1の駆動ライン群として選択し、この選択した第1の駆動ライン群を前記第1の駆動端子に接続し、前記第2の駆動端子と前記第1の検出端子の間に予め定めた静電容量値を有する第1のオフセット調整コンデンサを接続し、前記第2の駆動端子と前記第2の検出端子の間に予め定めた静電容量値を有する第2のオフセット調整コンデンサを接続することを特徴とする請求項1に記載のタッチセンサの信号処理回路。
    The selection circuit includes:
    Each time one detection pattern is selected from among a plurality of detection patterns determined according to a predetermined transformation matrix, the plurality of first lines are selected according to the selected detection pattern. One or more lines are selected as the first drive line group, the selected first drive line group is connected to the first drive terminal, and the second drive terminal and the first detection are selected. A first offset adjustment capacitor having a predetermined capacitance value is connected between the terminals, and a second capacitance value having a predetermined capacitance value between the second drive terminal and the second detection terminal is connected. The touch sensor signal processing circuit according to claim 1, further comprising an offset adjustment capacitor connected thereto.
  5.  前記容量測定回路の出力信号と前記変換行列とを基に演算を行い、前記選択された駆動ラインと前記選択された各検出ラインとの各交差部における静電容量をそれぞれ算出する容量算出回路を、さらに備えることを特徴とする請求項4に記載のタッチセンサの信号処理回路。 A capacitance calculation circuit that performs an operation based on the output signal of the capacitance measurement circuit and the conversion matrix, and calculates a capacitance at each intersection of the selected drive line and each selected detection line; The touch sensor signal processing circuit according to claim 4, further comprising:
  6.  前記変換行列は、アダマール変換行列であることを特徴とする請求項2乃至請求項5のうちのいずれか1項に記載のタッチセンサの信号処理回路。 6. The touch sensor signal processing circuit according to claim 2, wherein the transformation matrix is a Hadamard transformation matrix.
  7.  前記アダマール変換行列はn行×n列からなり(n=2、4の倍数)、前記複数の検出パターンはn個の検出パターンであり、前記選択される第1と第2の検出ライン群に属する全ライン数はn個であることを特徴とする請求項6に記載のタッチセンサの信号処理回路。 The Hadamard transform matrix is composed of n rows × n columns (n = 2, multiple of 4), the plurality of detection patterns are n detection patterns, and the selected first and second detection line groups 7. The touch sensor signal processing circuit according to claim 6, wherein the total number of lines to which the number belongs is n.
  8.  前記選択回路は、
     予め決めてある変換行列に応じて定められた複数の駆動パターンのうちの1つの駆動パターンが選択されるたびに、当該選択される駆動パターンに応じて、前記複数の第1のラインの中から、1つ以上のラインを第1の駆動ライン群として選択し、前記複数の第1のラインの中で前記第1の駆動ライン群とは異なる0本以上のラインを第2の駆動ライン群として選択し、
     予め決めてある前記変換行列に応じて定められた複数の検出パターンのうちの1つの検出パターンが選択されるたびに、当該選択される検出パターンに応じて、前記複数の第2のラインの中から、1つ以上のラインを第1の検出ライン群として選択し、前記複数の第2のラインの中で前記第1の検出ライン群とは異なる0本以上のラインを第2の検出ライン群として選択することを特徴とする請求項1に記載のタッチセンサの信号処理回路。
    The selection circuit includes:
    Each time one drive pattern is selected from among a plurality of drive patterns determined according to a predetermined conversion matrix, the plurality of first lines are selected according to the selected drive pattern. One or more lines are selected as a first drive line group, and zero or more lines different from the first drive line group among the plurality of first lines as a second drive line group Selected,
    Each time one detection pattern is selected from among a plurality of detection patterns determined according to the predetermined conversion matrix, the plurality of second lines are selected according to the selected detection pattern. Then, one or more lines are selected as the first detection line group, and zero or more lines different from the first detection line group among the plurality of second lines are selected as the second detection line group. The signal processing circuit of the touch sensor according to claim 1, wherein:
  9.  前記容量測定回路の出力信号と前記変換行列とを基に演算を行い、前記複数の第1のラインと前記複数の第2ラインとの交差部に形成される容量マトリクスのそれぞれの静電容量を算出する容量算出回路を、さらに備えることを特徴とする請求項8に記載のタッチセンサの信号処理回路。 The calculation is performed based on the output signal of the capacitance measuring circuit and the conversion matrix, and the capacitances of the capacitance matrix formed at the intersections of the plurality of first lines and the plurality of second lines are calculated. 9. The signal processing circuit of the touch sensor according to claim 8, further comprising a capacitance calculating circuit for calculating.
  10.  前記変換行列は、アダマール変換行列であることを特徴とする請求項8または請求項9に記載のタッチセンサの信号処理回路。 10. The touch sensor signal processing circuit according to claim 8, wherein the transformation matrix is a Hadamard transformation matrix.
  11.  前記アダマール変換行列が、第1の方向にm行×m列(m=2、4の倍数)、第2の方向にn行×n列(n=2、4の倍数)の場合には、前記駆動パターンおよび前記検出パターンの組み合わせは(m×n)個となり、各駆動パターンおよび検出パターンに応じて、前記選択される第1と第2の駆動ライン群に属する全ライン数はm個、前記選択される第1と第2の検出ラインに属する全ライン数はn個であることを特徴とする請求項10に記載のタッチセンサの信号処理回路。 When the Hadamard transform matrix is m rows × m columns (m = 2, a multiple of 4) in the first direction and n rows × n columns (n = 2, a multiple of 4) in the second direction, The number of combinations of the drive patterns and the detection patterns is (m × n), and the total number of lines belonging to the selected first and second drive line groups is m in accordance with each drive pattern and detection pattern, 11. The touch sensor signal processing circuit according to claim 10, wherein the total number of lines belonging to the selected first and second detection lines is n.
  12.  前記選択回路は、
     前記複数の駆動パターンごとに、前記第1の駆動端子に接続するラインおよび前記第2の駆動端子に接続するラインを変更し、
     前記第1の駆動端子および第2の駆動端子に接続するラインの変更に応じて、前記第1の検出端子に接続するラインおよび前記第2の検出端子に接続するラインを変更することを特徴とする請求項8乃至請求項11のうちのいずれか1項に記載のタッチセンサの信号処理回路。
    The selection circuit includes:
    For each of the plurality of drive patterns, a line connected to the first drive terminal and a line connected to the second drive terminal are changed,
    The line connected to the first detection terminal and the line connected to the second detection terminal are changed according to the change of the line connected to the first drive terminal and the second drive terminal. The signal processing circuit of the touch sensor according to any one of claims 8 to 11.
  13.  前記選択回路は、
     前記第1の駆動端子に接続するラインとして選択したラインの前記第1の駆動端子への接続を前記第1の検出端子への接続に変更し、前記第2の駆動端子に接続するラインとして選択したラインの前記第2の駆動端子への接続を前記第2の検出端子への接続に変更し前記第1の検出端子に接続するラインとして選択したラインの前記第1の検出端子への接続を前記第1の駆動端子への接続に変更し、前記第2の検出端子に接続するラインとして選択したラインの前記第2の検出端子への接続を第2の駆動端子への接続に変更することを特徴とする請求項8乃至請求項11のうちのいずれか1項に記載のタッチセンサの信号処理回路。
    The selection circuit includes:
    The connection of the line selected as the line connected to the first drive terminal to the connection to the first detection terminal is changed to the connection to the first detection terminal and selected as the line connected to the second drive terminal The connection of the selected line to the second detection terminal is changed to the connection to the second detection terminal, and the connection of the line selected as the line to be connected to the first detection terminal is connected to the first detection terminal. The connection to the first drive terminal is changed, and the connection to the second detection terminal of the line selected as the line to be connected to the second detection terminal is changed to the connection to the second drive terminal. The signal processing circuit for a touch sensor according to claim 8, wherein the signal processing circuit is a touch sensor.
  14.  前記変換行列は、第1の変換行列と第2の変換行列とを使用し且つ、前記第1の変換行列および第2の変換行列のいずれか一方は、前記複数の第1のラインの個数以上のサイズの第1の変換行列であるかまたは前記複数の第2のラインの個数以上のサイズの第2の変換行列であって、前記複数の検出パターンは、前記第1の変換行列と前記第2の変換行列とを基に予め定め、且つ前記第1の変換行列のサイズが前記複数の第1のラインの個数以上のサイズである場合には、前記第1の変換行列の行ベクトルまたは列ベクトルの一部を除いた第3の変換行列を前記第1の変換行列として用い、前記第2の変換行列のサイズが前記複数の第2のラインの個数以上のサイズである場合には、前記第2の変換行列の行ベクトルまたは列ベクトルの一部を除いた第4の変換行列を前記第2の変換行列として用いて予め定め、
     前記容量算出部は、前記第1の変換行列および前記第2の変換行列の各転置行列またはそれらの各一般化逆行列を使用することを特徴とする請求項8乃至請求項11のうちのいずれか1項に記載のタッチセンサの信号処理回路。
    The transformation matrix uses a first transformation matrix and a second transformation matrix, and one of the first transformation matrix and the second transformation matrix is equal to or more than the number of the plurality of first lines. Or a second transformation matrix having a size equal to or larger than the number of the plurality of second lines, wherein the plurality of detection patterns include the first transformation matrix and the first transformation matrix. 2 in advance, and when the size of the first transformation matrix is equal to or larger than the number of the plurality of first lines, the row vector or column of the first transformation matrix When a third transformation matrix excluding a part of the vector is used as the first transformation matrix and the size of the second transformation matrix is equal to or larger than the number of the plurality of second lines, Part of the row or column vector of the second transformation matrix Determined in advance using a fourth transformation matrix except as the second conversion matrix,
    The said capacity | capacitance calculation part uses each transposed matrix of those of said 1st conversion matrix and said 2nd conversion matrix, or each of those generalized inverse matrix, The any one of Claims 8 thru | or 11 characterized by the above-mentioned. A signal processing circuit of the touch sensor according to claim 1.
  15.  前記容量算出回路で算出した各静電容量に基づいて前記タッチパネル上のタッチ位置を検出するタッチ位置検出回路を、さらに備えることを特徴とする請求項3、請求項5、請求項9のうちのいずれか1項に記載のタッチセンサの信号処理回路。 The touch position detection circuit for detecting the touch position on the touch panel based on each capacitance calculated by the capacitance calculation circuit is further provided. The signal processing circuit of the touch sensor according to any one of claims.
  16.  前記変換行列は、前記複数の第1のラインまたは前記複数の第2のラインの個数以上のサイズの変換行列を使用し、
     前記複数の検出パターンは、前記変換行列の行ベクトルまたは列ベクトルの一部を除いて行数または列数を前記複数の第1のラインまたは前記複数の第2のラインの個数に一致させた行列を基に予め定め、
     前記容量算出回路は、前記行列の転置行列または一般化逆行列を使用することを特徴とする請求項3、請求項5、請求項9のうちのいずれか1項に記載のタッチセンサの信号処理回路。
    The transformation matrix uses a transformation matrix having a size equal to or larger than the number of the plurality of first lines or the plurality of second lines,
    The plurality of detection patterns are a matrix in which the number of rows or columns is made equal to the number of the plurality of first lines or the plurality of second lines except for a part of the row vector or column vector of the transformation matrix. Predetermined based on
    The touch sensor signal processing according to claim 3, wherein the capacitance calculation circuit uses a transposed matrix or a generalized inverse matrix of the matrix. circuit.
  17.  前記容量算出回路は、
     前記複数の検出パターンのうち所定の検出パターンのときには、前記容量測定回路の出力信号を0として処理することを特徴とする請求項3、請求項5のうちのいずれか1項に記載のタッチセンサの信号処理回路。
    The capacity calculation circuit includes:
    6. The touch sensor according to claim 3, wherein when the detection pattern is a predetermined detection pattern among the plurality of detection patterns, the output signal of the capacitance measurement circuit is processed as 0. 7. Signal processing circuit.
  18.  前記容量算出回路は、
     前記複数の検出パターンおよび駆動パターンのうち所定の検出パターンおよび駆動パターンのときには、前記容量測定回路の出力信号を0として処理することを特徴とする請求項9に記載のタッチセンサの信号処理回路。
    The capacity calculation circuit includes:
    The touch sensor signal processing circuit according to claim 9, wherein an output signal of the capacitance measuring circuit is processed as 0 when a predetermined detection pattern and drive pattern among the plurality of detection patterns and drive patterns are used.
  19.  複数の第1のラインと、前記複数の第1のラインと絶縁層を介して交差するように配置される複数の第2のラインと、を備えるタッチパネルを含むタッチセンサの信号処理回路であって、
     第1の駆動端子および第2の駆動端子と、検出端子と、出力端子とを有し、前記第1の駆動端子および前記検出端子の間に接続された第1の静電容量と、前記第2の駆動端子および前記検出端子の間に接続された第2の静電容量との差を所定の信号に変換して出力する容量測定回路と、
     予め決めてある変換行列に応じて定められた複数の駆動パターンのうちの1つの駆動パターンが選択されるたびに、当該選択される駆動パターンに応じて、前記複数の第1のラインの中から、1つ以上のラインを第1の駆動ライン群として選択し、または前記第1の駆動ライン群に加えて前記第1の駆動ライン群とは異なる0本以上のラインを第2の駆動ライン群として選択し、前記第1の駆動ライン群を前記第1の駆動端子に接続し、前記第2の駆動ライン群を前記第2の駆動端子に接続し、かつ、前記複数の第2のラインの中から、1つ以上のラインを検出ライン群として選択し、前記検出ライン群を前記検出端子に接続する選択回路と、
     前記容量測定回路が検出した各所定の信号と前記変換行列とを基に演算を行い、前記選択された駆動ラインと前記選択された各検出ラインとの各交差部における静電容量をそれぞれ算出する容量算出回路と、
     を備えることを特徴とするタッチセンサの信号処理回路。
    A signal processing circuit of a touch sensor including a touch panel comprising: a plurality of first lines; and a plurality of second lines arranged to intersect the plurality of first lines via an insulating layer. ,
    A first capacitance having a first drive terminal and a second drive terminal, a detection terminal, and an output terminal, connected between the first drive terminal and the detection terminal; A capacitance measuring circuit that converts a difference between the second electrostatic capacitance connected between the two drive terminals and the detection terminal into a predetermined signal and outputs the predetermined signal;
    Each time one drive pattern is selected from among a plurality of drive patterns determined according to a predetermined conversion matrix, the plurality of first lines are selected according to the selected drive pattern. One or more lines are selected as the first drive line group, or in addition to the first drive line group, zero or more lines different from the first drive line group are selected as the second drive line group The first drive line group is connected to the first drive terminal, the second drive line group is connected to the second drive terminal, and the plurality of second lines A selection circuit that selects one or more lines as a detection line group from among them, and connects the detection line group to the detection terminal;
    Calculation is performed based on each predetermined signal detected by the capacitance measurement circuit and the conversion matrix, and capacitances at respective intersections of the selected drive line and the selected detection lines are respectively calculated. A capacity calculation circuit;
    A signal processing circuit for a touch sensor, comprising:
  20.  前記変換行列は、アダマール変換行列であることを特徴とする請求項19記載のタッチセンサの信号処理回路。 20. The touch sensor signal processing circuit according to claim 19, wherein the transformation matrix is a Hadamard transformation matrix.
  21.  前記アダマール変換行列はn行×n列からなり(n=2、4の倍数)、前記複数の検出パターンはn個の駆動パターンであり、前記選択される第1と第2の駆動ライン群に属する全ライン数はn個であることを特徴とする請求項20に記載のタッチセンサの信号処理回路。 The Hadamard transform matrix is composed of n rows × n columns (n = 2, a multiple of 4), the plurality of detection patterns are n drive patterns, and the selected first and second drive line groups 21. The touch sensor signal processing circuit according to claim 20, wherein the total number of lines to which the number belongs is n.
  22.  前記容量算出回路で算出した各静電容量に基づいて前記タッチパネル上のタッチ位置を検出するタッチ位置検出回路を、さらに備えることを特徴とする請求項19乃至請求項21のうちのいずれか1項に記載のタッチセンサの信号処理回路。 The touch position detection circuit for detecting a touch position on the touch panel based on each capacitance calculated by the capacity calculation circuit, further comprising: a touch position detection circuit. A signal processing circuit of the touch sensor as described in 1.
  23.  前記変換行列は、前記複数の第1のラインまたは前記複数の第2のラインの個数以上のサイズの変換行列を使用し、
     前記複数の検出パターンは、前記変換行列の行ベクトルまたは列ベクトルの一部を除いて行数または列数を前記複数の第1のラインまたは前記複数の第2のラインの個数に一致させた行列を基に予め定め、
     前記容量算出回路は、前記行列の転置行列または一般化逆行列を使用することを特徴とする請求項19乃至請求項21のうちのいずれか1項に記載のタッチセンサの信号処理回路。
    The transformation matrix uses a transformation matrix having a size equal to or larger than the number of the plurality of first lines or the plurality of second lines,
    The plurality of detection patterns are a matrix in which the number of rows or columns is made equal to the number of the plurality of first lines or the plurality of second lines except for a part of the row vector or column vector of the transformation matrix. Predetermined based on
    The signal processing circuit of the touch sensor according to any one of claims 19 to 21, wherein the capacitance calculation circuit uses a transposed matrix or a generalized inverse matrix of the matrix.
  24.  前記容量算出回路は、
     前記複数の駆動パターンのうち所定の駆動パターンのときには、前記容量測定回路の出力信号を0として処理することを特徴とする請求項19乃至請求項21のうちのいずれか1項に記載のタッチセンサの信号処理回路。
    The capacity calculation circuit includes:
    The touch sensor according to any one of claims 19 to 21, wherein an output signal of the capacitance measurement circuit is processed as 0 when the drive pattern is a predetermined drive pattern among the plurality of drive patterns. Signal processing circuit.
  25.  請求項1乃至請求項24のうちのいずれか1項に記載のタッチセンサの信号処理回路を備えることを特徴とするタッチセンサ。 A touch sensor comprising the touch sensor signal processing circuit according to any one of claims 1 to 24.
  26.  複数の第1のライン及び前記複数の第1のラインと絶縁層を介して交差するように配置される複数の第2のラインを備えるタッチパネルと、
     駆動電圧を出力する第1の出力端子及び第2の出力端子を有する駆動回路と、
     第1の入力端子の入力電圧に応じた第1の電圧と第2の入力端子の入力電圧に応じた第2の電圧との差分電圧を検出する電圧検出回路と、
     前記複数の第1のラインと前記駆動回路の第1の出力端子または第2の出力端子との間の選択的な接続と、前記複数の第2のラインと前記電圧検出回路の第1の入力端子または第2の入力端子との間の選択的な接続を行う選択回路と、
    を含むタッチセンサの信号処理方法であって、
     コンピュータが、
     予め決めてある変換行列に応じて定められた複数のパターンのうちの1つのパターンを選択し、当該選択されたパターンに応じて、前記複数の第1のラインの中から、1つ以上のラインを第1の駆動ライン群として選択し、または前記第1の駆動ライン群に加えて前記第1の駆動ライン群とは異なる0本以上のラインを第2の駆動ライン群として選択し、前記第1の駆動ライン群を前記駆動回路の第1の出力端子に接続し、前記第2の駆動ライン群を前記駆動回路の第2の出力端子に接続するように、前記選択回路の動作を制御する第1ステップと、
     前記複数の第2のラインの中から、1つ以上のラインを第1の検出ライン群として選択し、前記第1の検出ライン群とは異なる0本以上のラインを第2の検出ライン群として選択し、前記第1の検出ライン群を前記電圧検出回路の第1の入力端子に接続し、前記第2の検出ライン群を前記電圧検出回路の第2の入力端子に接続するように、前記選択回路の動作を制御する第2ステップと、
     前記駆動回路が所定の駆動電圧を出力するように前記駆動回路の動作を制御し、前記電圧検出回路が前記差分電圧を検出するように前記電圧検出回路の動作を制御する第3ステップと、
     前記電圧検出回路の出力信号と前記変換行列とを基に演算を行い、前記選択された駆動ラインと前記選択された各検出ラインとの各交差部における静電容量をそれぞれ算出する第4ステップと、
    を実行することを特徴とするタッチセンサの信号処理方法。
    A touch panel comprising a plurality of first lines and a plurality of second lines arranged to intersect the plurality of first lines via an insulating layer;
    A drive circuit having a first output terminal and a second output terminal for outputting a drive voltage;
    A voltage detection circuit that detects a differential voltage between a first voltage corresponding to the input voltage of the first input terminal and a second voltage corresponding to the input voltage of the second input terminal;
    A selective connection between the plurality of first lines and a first output terminal or a second output terminal of the drive circuit; and the plurality of second lines and a first input of the voltage detection circuit. A selection circuit for performing selective connection between the terminal or the second input terminal;
    A signal processing method for a touch sensor including:
    Computer
    One pattern is selected from a plurality of patterns determined according to a predetermined transformation matrix, and one or more lines are selected from the plurality of first lines according to the selected pattern. Is selected as the first drive line group, or in addition to the first drive line group, zero or more lines different from the first drive line group are selected as the second drive line group, and the first drive line group is selected. The operation of the selection circuit is controlled so that one drive line group is connected to the first output terminal of the drive circuit, and the second drive line group is connected to the second output terminal of the drive circuit. The first step;
    One or more lines are selected as the first detection line group from the plurality of second lines, and zero or more lines different from the first detection line group are used as the second detection line group. Selecting, connecting the first detection line group to a first input terminal of the voltage detection circuit, and connecting the second detection line group to a second input terminal of the voltage detection circuit, A second step for controlling the operation of the selection circuit;
    A third step of controlling the operation of the drive circuit so that the drive circuit outputs a predetermined drive voltage, and controlling the operation of the voltage detection circuit so that the voltage detection circuit detects the differential voltage;
    A fourth step of performing an operation based on the output signal of the voltage detection circuit and the conversion matrix, and calculating a capacitance at each intersection of the selected drive line and each selected detection line; ,
    The signal processing method of the touch sensor characterized by performing this.
  27.  前記第1ステップでは、前記複数のパターンごとに、前記複数の第1のラインと前記複数の第2のラインとを前記第1の駆動ライン群および前記第2の駆動ライン群として選択するのを変更し、
     前記第2ステップでは、前記第1ステップでの変更に応じて、前記複数の第1のラインと前記複数の第2のラインとを前記第1の検出ライン群および前記第2の検出ライン群として選択するのを変更するようにしたことを特徴とする請求項26に記載のタッチセンサの信号処理方法。
    In the first step, the plurality of first lines and the plurality of second lines are selected as the first drive line group and the second drive line group for each of the plurality of patterns. change,
    In the second step, the plurality of first lines and the plurality of second lines are used as the first detection line group and the second detection line group in accordance with the change in the first step. 27. The touch sensor signal processing method according to claim 26, wherein selection is changed.
  28.  前記複数のパターンのうちの所定のパターンのときには、
     前記第1ステップでは、前記選択した第1の駆動ライン群の前記駆動回路の第1の出力端子への接続を前記電圧検出回路の第1の入力端子への接続に変更し、前記選択した第2の駆動ライン群の前記駆動回路の第2の出力端子への接続を前記電圧検出回路の第2の入力端子への接続に変更し、
     前記第2ステップでは、前記選択した第1の検出ライン群の前記電圧検出回路の第1の入力端子への接続を前記駆動回路の第1の出力端子への接続に変更し、前記選択した第2の検出ライン群の前記電圧検出回路の第2の入力端子への接続を前記駆動回路の第2の出力端子への接続に変更することを特徴とする請求項26に記載のタッチセンサの信号処理方法。
    When the predetermined pattern of the plurality of patterns,
    In the first step, the connection of the selected first drive line group to the first output terminal of the drive circuit is changed to the connection to the first input terminal of the voltage detection circuit, and the selected first Changing the connection of the second drive line group to the second output terminal of the drive circuit to the second input terminal of the voltage detection circuit;
    In the second step, the connection of the selected first detection line group to the first input terminal of the voltage detection circuit is changed to the connection to the first output terminal of the drive circuit, and the selected first detection line group 27. The signal of the touch sensor according to claim 26, wherein the connection of the second detection line group to the second input terminal of the voltage detection circuit is changed to the connection to the second output terminal of the drive circuit. Processing method.
  29.  前記複数のパターンのうち所定のパターンのときには、
     前記第1ステップから前記第3ステップまでの各処理を省略し、前記第4ステップにおいて前記電圧検出回路の出力信号を0として処理することを特徴とする請求項26に記載のタッチセンサの信号処理方法。
    When the predetermined pattern among the plurality of patterns,
    27. The signal processing of the touch sensor according to claim 26, wherein each processing from the first step to the third step is omitted, and the output signal of the voltage detection circuit is processed as 0 in the fourth step. Method.
  30.  前記変換行列は、前記複数の第1のラインまたは前記複数の第2のラインの個数以上のサイズの変換行列を使用し、
     前記複数のパターンは、前記変換行列の行ベクトルまたは列ベクトルの一部を除いて行数または列数を前記複数の第1のラインまたは前記複数の第2のラインの個数に一致させた行列を基に予め定め、
     前記第1ステップと前記第2ステップの各処理では、前記定められている複数の検出パターンを使用し、
     前記第4ステップの処理では、前記行列の転置行列または一般化逆行列を使用することを特徴とする請求項26に記載のタッチセンサの信号処理方法。
    The transformation matrix uses a transformation matrix having a size equal to or larger than the number of the plurality of first lines or the plurality of second lines,
    The plurality of patterns is a matrix in which the number of rows or columns is made equal to the number of the plurality of first lines or the plurality of second lines excluding a part of the row vector or column vector of the transformation matrix. Predetermined based on
    In each process of the first step and the second step, the plurality of predetermined detection patterns are used,
    27. The touch sensor signal processing method according to claim 26, wherein a transpose matrix or a generalized inverse matrix of the matrix is used in the process of the fourth step.
  31.  前記変換行列は、第1の変換行列と第2の変換行列とを使用し且つ、前記第1の変換行列および第2の変換行列のいずれか一方は、前記複数の第1のラインの個数以上のサイズの第1の変換行列であるかまたは前記複数の第2のラインの個数以上のサイズの第2の変換行列であって、
     前記複数のパターンは、前記第1の変換行列と前記第2の変換行列とを基に予め定め、且つ前記第1の変換行列のサイズが前記複数の第1のラインの個数以上のサイズである場合には、前記第1の変換行列の行ベクトルまたは列ベクトルの一部を除いた第3の変換行列を前記第1の変換行列として用い、前記第2の変換行列のサイズが前記複数の第2のラインの個数以上のサイズである場合には、前記第2の変換行列の行ベクトルまたは列ベクトルの一部を除いた第4の変換行列を前記第2の変換行列として用いて予め定め、
     前記第1ステップと前記第2ステップの各処理では、前記第1の変換行列および第2の変換行列によって定められている複数のパターンを使用し、
     前記第4ステップの処理では、前記第1の変換行列および前記第2の変換行列の各転置行列またはそれらの各一般化逆行列を使用することを特徴とする請求項26に記載のタッチセンサの信号処理方法。
    The transformation matrix uses a first transformation matrix and a second transformation matrix, and one of the first transformation matrix and the second transformation matrix is equal to or more than the number of the plurality of first lines. Or a second transformation matrix having a size equal to or larger than the number of the plurality of second lines,
    The plurality of patterns are predetermined based on the first transformation matrix and the second transformation matrix, and the size of the first transformation matrix is equal to or larger than the number of the plurality of first lines. In this case, a third transformation matrix excluding a part of a row vector or a column vector of the first transformation matrix is used as the first transformation matrix, and the size of the second transformation matrix is the plurality of the second transformation matrices. When the size is equal to or larger than the number of lines of 2, a fourth transformation matrix excluding a part of a row vector or a column vector of the second transformation matrix is used as the second transformation matrix, and is determined in advance.
    In each process of the first step and the second step, a plurality of patterns defined by the first transformation matrix and the second transformation matrix are used,
    27. The touch sensor according to claim 26, wherein in the processing of the fourth step, transpose matrices of the first transformation matrix and the second transformation matrix or their respective generalized inverse matrices are used. Signal processing method.
  32.  前記変換行列は、アダマール変換行列であることを特徴とする請求項26乃至請求項31のうちのいずれか1項に記載のタッチセンサの信号処理方法。 32. The touch sensor signal processing method according to claim 26, wherein the transformation matrix is a Hadamard transformation matrix.
  33.  請求項26に記載のタッチセンサの信号処理方法における各ステップを、コンピュータに実行させることを特徴とするタッチセンサの信号処理プログラム。 27. A touch sensor signal processing program that causes a computer to execute each step in the touch sensor signal processing method according to claim 26.
PCT/JP2012/004610 2011-09-30 2012-07-19 Signal processing circuit for touch sensor and touch sensor WO2013046513A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013535836A JP5715703B2 (en) 2011-09-30 2012-07-19 Touch sensor signal processing circuit and touch sensor
TW101133379A TW201316236A (en) 2011-09-30 2012-09-12 Signal processing circuit for touch sensor and touch sensor

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2011-218649 2011-09-30
JP2011218649 2011-09-30
JP2012-104524 2012-05-01
JP2012104524 2012-05-01

Publications (1)

Publication Number Publication Date
WO2013046513A1 true WO2013046513A1 (en) 2013-04-04

Family

ID=47994609

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/004610 WO2013046513A1 (en) 2011-09-30 2012-07-19 Signal processing circuit for touch sensor and touch sensor

Country Status (3)

Country Link
JP (1) JP5715703B2 (en)
TW (1) TW201316236A (en)
WO (1) WO2013046513A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014035671A (en) * 2012-08-09 2014-02-24 Asahi Kasei Electronics Co Ltd Capacitance detection circuit of touch sensor
KR20150027529A (en) * 2013-09-04 2015-03-12 엘지디스플레이 주식회사 Touch ic and display device integrated with touch screen using the same
WO2015045867A1 (en) * 2013-09-27 2015-04-02 株式会社ワコム Position detection device
JP2020521971A (en) * 2017-05-25 2020-07-27 10103560 カナダ エルティーディー. High efficiency multiplexing

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9933903B2 (en) * 2014-10-02 2018-04-03 Semiconductor Energy Laboratory Co., Ltd. Input device and input/output device
CN108985150B (en) 2017-05-31 2022-05-27 联咏科技股份有限公司 Capacitive image sensor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009015489A (en) * 2007-07-03 2009-01-22 Hitachi Displays Ltd Touch panel-equipped display device
JP2011100215A (en) * 2009-11-04 2011-05-19 Seiko Instruments Inc Coordinate input device and information equipment
JP2012118957A (en) * 2010-11-12 2012-06-21 Sharp Corp Linear element column value estimation method, capacitance detection method, integrated circuit, touch sensor system, and electronic equipment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009015489A (en) * 2007-07-03 2009-01-22 Hitachi Displays Ltd Touch panel-equipped display device
JP2011100215A (en) * 2009-11-04 2011-05-19 Seiko Instruments Inc Coordinate input device and information equipment
JP2012118957A (en) * 2010-11-12 2012-06-21 Sharp Corp Linear element column value estimation method, capacitance detection method, integrated circuit, touch sensor system, and electronic equipment

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014035671A (en) * 2012-08-09 2014-02-24 Asahi Kasei Electronics Co Ltd Capacitance detection circuit of touch sensor
KR20150027529A (en) * 2013-09-04 2015-03-12 엘지디스플레이 주식회사 Touch ic and display device integrated with touch screen using the same
JP2015049889A (en) * 2013-09-04 2015-03-16 エルジー ディスプレイ カンパニー リミテッド Touch ic and touch screen integrated display device employing the same
CN104423757A (en) * 2013-09-04 2015-03-18 乐金显示有限公司 Touch integrated circuit and display device integrated with touch screen using the same
US9830025B2 (en) 2013-09-04 2017-11-28 Lg Display Co., Ltd. Integrated touch display device for displaying image and performing touch sensing through time-divisional multiplexing
CN104423757B (en) * 2013-09-04 2018-02-13 乐金显示有限公司 Touch integrated circuit and be integrated with the display device of the touch-screen using it
KR102081606B1 (en) 2013-09-04 2020-02-26 엘지디스플레이 주식회사 Touch ic and display device integrated with touch screen using the same
WO2015045867A1 (en) * 2013-09-27 2015-04-02 株式会社ワコム Position detection device
JP5697227B1 (en) * 2013-09-27 2015-04-08 株式会社ワコム Position detection device
CN105283827A (en) * 2013-09-27 2016-01-27 株式会社和冠 Position detection device
CN105283827B (en) * 2013-09-27 2020-04-14 株式会社和冠 Position detecting device
JP2020521971A (en) * 2017-05-25 2020-07-27 10103560 カナダ エルティーディー. High efficiency multiplexing

Also Published As

Publication number Publication date
JP5715703B2 (en) 2015-05-13
JPWO2013046513A1 (en) 2015-03-26
TW201316236A (en) 2013-04-16

Similar Documents

Publication Publication Date Title
JP5715703B2 (en) Touch sensor signal processing circuit and touch sensor
US9727187B2 (en) Capacitive touch panel with balanced parallel driving
JP6502690B2 (en) Touch panel and display device including the same
CN103649888B (en) Linear device value method of estimation, capacitance determining method, integrated circuit, touch sensor system and electronic equipment
JP6220067B2 (en) Touch input sensing method and apparatus for reducing parasitic capacitance effects
JP4945345B2 (en) Display device with touch panel
CN104205025B (en) Mutual capacitance touch screen device and the method being used for creating mutual capacitance touch screen device
KR101542397B1 (en) Touch sensible display device and driving method thereof
WO2012169454A1 (en) Coordinate location detection device
US9904407B2 (en) Touch sensor, display apparatus including the same, and method of sensing touch panel
CN111785228A (en) Touch display device, driving method thereof, driving circuit thereof, and data driving circuit thereof
US9417741B2 (en) Capacitance sensing apparatus and touchscreen apparatus
JP2009122969A (en) Screen input-type image-displaying device
JP6285832B2 (en) Touch panel input device and input detection method thereof
KR102600924B1 (en) Touch display device and touch driving circuit
JP2013246557A (en) Touch sensor signal processing circuit and touch sensor
CN206115408U (en) Touch detector, touch detect chip and touch input device
KR101537231B1 (en) Touch detecting apparatus and method
JP2019106179A (en) Integrator, touch display device, and driving method thereof
CN107430468A (en) The method for reducing the electrode path in single-layer touch sensor
CN109669568B (en) Active matrix touch panel with narrow bezel
KR20140105299A (en) Touch panel input apparatus and touch panel input detection method thereof
JP2013246556A (en) Touch sensor signal processing circuit and touch sensor
KR20140010788A (en) Touch detecting apparatus for minimizing deadzone and method
JP2013080290A (en) Signal processing circuit for touch sensor, and touch sensor

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12837358

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2013535836

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12837358

Country of ref document: EP

Kind code of ref document: A1