WO2013039136A1 - Image display device and image display method - Google Patents

Abstract

This image display device is provided with an LCD unit (5) for displaying an image, a display controller (14) for controlling the LCD unit (5), an HDMI receiver (10) for receiving image signal input, outputting the received image signal directly to the display controller (14) and detecting and outputting a vertical synchronization signal from the inputted image signal, and a CPU (9) having a function for receiving the input of the vertical synchronization signal outputted from the HDMI receiver (10) and detecting a synchronization signal stable state on the basis of a reference time set previously for the time in which the vertical synchronization signal becomes constant, and a function for outputting an image display signal for executing image display by the LCD unit (5) to the display controller (14) when the synchronization signal stable state is detected.

Description

Image display device and image display method

The present disclosure relates to an image display device and an image display method. Specifically, the present invention relates to an image display device and an image display method suitable for use in a relatively small image display device such as a head-mounted display.

Conventionally, as an image display device, a head mounted display (hereinafter referred to as “HMD”) used by being mounted on a user's head is known (for example, see Patent Document 1). The HMD generally includes a display unit that displays an image to be recognized by the user, and a support frame that supports the display unit and is attached to the user's head. As the support frame constituting the HMD, a glasses-type frame is preferably used because it can be easily mounted on the user's head.

Further, as the image display device, for example, a liquid crystal display device using a liquid crystal display (LCD) such as a display device of a personal computer (hereinafter referred to as “PC”) is widely used. In particular, in recent years, liquid crystal display devices have become widespread as home televisions and the like.

The liquid crystal display device includes an LCD composed of a liquid crystal panel, an LCD control unit including a drive circuit and a control circuit for controlling driving of the LCD, and a light source such as a backlight for performing image display on the LCD. Have. In the liquid crystal display device, when an image display command is executed to the LCD control unit, the light source is turned on and image display is performed. The LCD control unit controls the LCD based on a video signal input from an external device such as a PC. In general, a video signal used for controlling the LCD includes a vertical synchronization signal and a horizontal synchronization signal in addition to an image signal for displaying an image.

In such a liquid crystal display device, a video signal used for LCD control may be disturbed, for example, when the device starts up or when noise occurs for some reason during the operation of the device. As the disturbance of the video signal, for example, the vertical synchronization signal becomes unstable. When the disordered video signal is used and the LCD is controlled by the LCD control unit, normal image display cannot be performed.

For this reason, in a stationary liquid crystal display device such as a PC display device or a television, for example, an image processing circuit such as a scaler is generally mounted to correct the disturbance of the video signal. That is, the LCD control unit is provided with an image processing circuit, and the video signal input to the LCD control unit is processed into a normal state in advance by the image processing circuit, and the normal state of the video signal input to the LCD control unit Is secured.

As described above, the conventional liquid crystal display device adopts a configuration in which the video signal used for the control of the LCD control unit is processed in advance by a predetermined image processing circuit such as a scaler to cope with the disturbance of the video signal. Has been. For example, Patent Document 2 provides a block for periodically outputting correction data set in advance as a circuit for processing a video signal input to the LCD control unit, and the data output from this block is controlled by LCD control. A technique for canceling noise periodically riding on data input to the LCD control unit by adding an offset to the data input to the unit is disclosed.

JP 2010-134134 A JP 2002-108289 A

In an image display apparatus that is relatively small and requires mobility, such as an HMD, it is difficult to mount an image processing circuit such as a scaler as described above from the viewpoint of low power consumption and miniaturization. On the other hand, when an image display configuration using an LCD is adopted in an HMD or the like, depending on the specifications of the LCD control unit, etc., for example, when the device is started, the LCD When an image display command for the control unit is executed, there may be a problem that vertical stripes appear in the display image, for example.

As described above, when an image display configuration using an LCD is adopted in a relatively small HMD or the like, a display image may be defective due to a disturbance of a video signal, but in order to ensure a small configuration and mobility. However, there is a situation where it is difficult to cope with display image defects by a circuit configuration such as a scaler.

The present disclosure has been made in view of the circumstances as described above, and is an image display device capable of solving the problem of a display image caused by a disturbance of a video signal without using an image processing circuit such as a scaler. It is another object of the present invention to provide an image display method.

One aspect of the present disclosure receives and inputs image display means for displaying an image, display control means for controlling the image display means, and a video signal including a digital image signal, a vertical synchronization signal, and a horizontal synchronization signal. The video signal is directly output to the display control means, and at least one of the vertical sync signal and the horizontal sync signal is extracted from the input video signal, and the at least one sync signal is extracted. The video signal input / output means for output and the input of the at least one synchronization signal are input based on a comparison between a time when the output of the at least one synchronization signal is constant and a preset reference time The synchronization signal detection means for detecting that the synchronization signal is in a stable state, and the input of the video signal to the video signal input / output means is started. After that, when it is detected by the synchronization signal detection means that the synchronization signal is in a stable state, the display control means outputs an image display signal that causes the display control means to perform image display by the image display means. And an output unit.

Further, the synchronization signal detection means that the output of the input synchronization signal is constant during the reference time is a predetermined number of times set in advance, and that the synchronization signal is in a stable state. It may be detected.

The reference time has a predetermined width that is set based on the scanning frequency of the synchronization signal.

The image display means includes a liquid crystal display and a light source for displaying an image on the liquid crystal display, and the display control means controls the liquid crystal control unit that controls the liquid crystal display and the light source. A light source control unit, and the image display signal output means starts driving the liquid crystal display by outputting an image display signal to the liquid crystal control unit, and displays an image on the liquid crystal control unit. The light source may be turned on by outputting the image display signal to the light source control unit after a predetermined time has elapsed since the signal was output.

The image display signal output means outputs the image display signal to the display control means when the synchronization signal detection means no longer detects that the synchronization signal is in a stable state after outputting the image display signal. A signal for interrupting the image display by is output.

Another aspect of the present disclosure is an image display method for displaying an image on the liquid crystal display by directly inputting a video signal including a digital image signal, a vertical synchronization signal, and a horizontal synchronization signal to a means for controlling the liquid crystal display. A step of extracting at least one of the vertical synchronizing signal and the horizontal synchronizing signal from the video signal, and comparing a time at which the output of the synchronizing signal is constant with a preset reference time. Based on the step of detecting that the synchronization signal detected by the detecting step is in a stable state, and detecting that the synchronization signal is in a stable state by the detecting step, the image display And an image display method comprising:

According to the present disclosure, it is possible to solve the problem of the display image due to the disturbance of the video signal without using an image processing circuit such as a scaler.

The figure which shows the structure of a HMD system. The block diagram which shows the structure of a HMD system. Explanatory drawing about the malfunction of the display image in a HMD system. Explanatory drawing about the image display sequence in a HMD system. The flowchart about the image display sequence in a HMD system. Explanatory drawing about control of the LCD unit in a HMD system. The figure which shows the example of application of a HMD system.

The present disclosure is premised on a configuration in which a video signal for displaying an image is directly input to a display control unit that controls a configuration for displaying an image such as an LCD. By performing control such that the video signal is input to the display control unit after it is detected that the video signal is in a stable state, the problem of the display image due to the disturbance of the video signal is solved.

Hereinafter, embodiments of the present disclosure will be described. In the embodiment of the present invention described below, an HMD (head mounted display) which is an image display device of the type worn on the user's head will be described as an example of the image display device.

The HMD 1 according to the present embodiment displays a video based on a video signal on one eye of a user of the HMD 1 (hereinafter simply referred to as “user”) by a liquid crystal display (LCD), thereby giving the user Make the video visible.

As shown in FIGS. 1 and 2, the HMD 1 according to this embodiment constitutes an HMD system 50 together with the repeater 2. That is, the HMD system 50 includes the HMD 1 and the repeater 2 and displays an image on the LCD in the HMD 1 based on a video signal input from the outside to the repeater 2. The HMD 1 and the repeater 2 are connected to each other by a dedicated cable 51 as a wire harness.

The video signal input from the outside to the repeater 2 includes a digital image signal, a vertical synchronization signal (V_SYNC), and a horizontal synchronization signal (H_SYNC). The video signal input to the repeater 2 is output from, for example, an HDMI (High-Definition Multimedia Interface) terminal or a DVI-D (Digital Visual Interface-Digital) terminal of an external device such as a PC or a smartphone. For example, it is a signal including digital video data of 8 bits × 3 colors output from a terminal. The video signal input to the repeater 2 is sent to the HMD 1 via the cable 51. The cable 51 is a dedicated cable configured to be compatible with the repeater 2 and the HMD 1, for example. However, a general-purpose cable compatible with the repeater 2 and the HMD 1 may be used.

[Configuration of HMD]
The HMD 1 includes a display unit 3 and a frame 4 that supports the display unit 3.

First, the configuration of the display unit 3 will be described. As shown in FIG. 2, the display unit 3 includes an LCD unit 5 as an image display unit that performs image display using liquid crystal, and a control unit 6 that controls the LCD unit 5. The LCD unit 5 and the control unit 6 are accommodated in a housing 3a included in the display unit 3 (see FIG. 1).

As shown in FIG. 2, the LCD unit 5 includes an LCD 7 and a backlight 8. The LCD 7 has a liquid crystal panel including liquid crystals, a drive circuit for supplying electric signals to the liquid crystal panel, and the like. The backlight 8 is a light source for displaying an image on the LCD 7. In this embodiment, the backlight 8 is comprised by LED (Light Emitting Diode). However, the backlight 8 is not limited to the LED, and may be a cold cathode tube such as a small fluorescent tube using a cold cathode.

The LCD unit 5 performs liquid crystal display on the LCD 7 using light from the backlight 8 under the control of the control unit 6. The LCD 7 includes, for example, a color filter that decomposes white light from the backlight 8 into component light of three colors R (red), G (green), and B (blue) for each pixel. The transmittance of light in the pixel is controlled, and the transmittance of component light is controlled for each pixel. In the HMD 1 of the present embodiment, the LCD unit 5 having the LCD 7 and the backlight 8 functions as an image display unit that performs image display.

The control unit 6 includes a CPU (Central Processing Unit) 9, an HDMI receiver 10, an LCD controller 11, an LED backlight drive IC (Integrated Circuit) 12, and a power supply IC 13.

The CPU 9 is a main control unit that controls the operation of the display unit 3. The CPU 9 outputs control signals to the HDMI receiver 10, the LCD controller 11, and the LED backlight drive IC 12. The CPU 9 is connected to the HDMI receiver 10, the LCD controller 11, and the like through a data communication bus.

The HDMI receiver 10 receives an input of a video signal sent from the repeater 2 through the cable 51. The HDMI receiver 10 directly outputs the input video signal to the LCD controller 11. That is, the HDMI receiver 10 directly outputs the input video signal to the LCD controller 11 without passing through an image processing circuit such as a scaler that processes the video signal with the LCD controller 11. Therefore, the video signal output from the HDMI receiver 10 is directly input to the LCD controller 11. The HDMI receiver 10 is controlled by the CPU 9 by receiving a control signal from the CPU 9.

The LCD controller 11 controls the operation of the LCD 7 constituting the LCD unit 5 based on the control signal input from the CPU 9. Specifically, the LCD controller 11 includes a dot clock generation circuit that generates a dot clock, a video processor, a frame memory, an LCD drive circuit as an LCD driver, and the like. The dot clock generation circuit generates a dot clock signal for sampling each pixel of the digital image signal included in the video signal sent from the HDMI receiver 10. The vertical synchronization signal and horizontal synchronization signal output from the HDMI receiver 10 are input to the dot clock generation circuit.

The video processor included in the LCD controller 11 is a microprocessor that controls the writing and reading of images to and from the frame memory. The digital image signal sent from the HDMI receiver 10 is once written in the frame memory and read out from the frame memory as necessary by the video processor. The digital image signal read from the frame memory is supplied from the video processor to the LCD drive circuit included in the LCD controller 11. The digital image signal writing operation to the frame memory is performed in synchronization with the vertical synchronizing signal and the horizontal synchronizing signal. In addition, a digital image signal read operation from the frame memory by the video processor is performed in synchronization with a synchronization signal output from the LCD drive circuit.

The LCD drive circuit included in the LCD controller 11 generates an image signal for the LCD 7 in the LCD controller 11 in accordance with the digital image signal output from the video processor. When the image signal generated by the LCD drive circuit is input to the LCD 7, the image display by the LCD 7 is performed.

The LED backlight drive IC 12 controls the operation of the backlight 8 constituting the LCD unit 5 based on the control signal input from the CPU 9. Specifically, the LED backlight drive IC 12 controls the drive current that flows through the backlight 8 that is an LED, and controls the drive of the backlight 8 such as on / off of the backlight 8 and brightness setting. When the drive current output from the LED backlight drive IC 12 is supplied to the backlight 8, the backlight 8 emits light.

The LCD controller 11 and the LED backlight drive IC 12 constitute a display control unit 14 that controls the LCD unit 5 having the LCD 7 and the backlight 8 in the control unit 6. In the HMD 1 of the present embodiment, the display control unit 14 including the LCD controller 11 and the LED backlight drive IC 12 functions as display control means for controlling the LCD unit 5 having the LCD 7 and the backlight 8. The LCD controller 11 that controls the LCD 7 functions as a liquid crystal control unit, and the LED backlight drive IC 12 that controls the backlight 8 functions as a light source control unit.

The LCD controller 11 and the LED backlight drive IC 12 are controlled by the CPU 9 by receiving a control signal from the CPU 9. That is, the CPU 9 sends a control signal to the LCD controller 11 and the LED backlight drive IC 12 to cause the LCD controller 11 and the LED backlight drive IC 12 to control the operation of the LCD unit 5. Then, after executing an image display command for the LCD controller 11, the CPU 9 sends a control signal to the LED backlight drive IC 12 to turn on the backlight 8 and cause the LCD unit 5 to display an image.

The power supply IC 13 constitutes a power supply unit that receives the supply of power supplied from the repeater 2 via the cable 51 in the control unit 6 of the HMD 1. The electric power of this power supply unit is used to drive each unit constituting the HMD 1 such as the CPU 9 and the LCD controller 11 of the control unit 6. In addition, the control unit 6 is provided with a storage unit that stores a control program and the like in advance. This storage unit is connected to the CPU 9 by a data communication bus.

As shown in FIG. 1, the display unit 3 has a half mirror 15 for allowing the user to recognize the video. The half mirror 15 is provided so as to be positioned in front of the left eye of the user while being rotatably supported by a mirror holder 3b provided on one end side of the housing 3a of the display unit 3. The display unit 3 causes the user to recognize the video displayed by the LCD unit 5 by the half mirror 15. Further, the half mirror 15 transmits external light and makes it enter the user's eyes. Therefore, the user can visually recognize the video displayed by the display unit 3 on the background recognized by the external light.

As described above, the HMD 1 of the present embodiment is a see-through video display device that transmits external light and displays a video displayed by the display unit 3 to the user. Note that the HMD according to the present invention need not be a see-through type.

Next, the configuration of the frame 4 will be described. As shown in FIG. 1, the frame 4 is a spectacle-type frame, and is a mounting portion that supports the display unit 3 and is mounted on the user's head. The frame 4 supports the display unit 3 so that the display unit 3 can display an image to the user as described above while being mounted on the user's head.

In the HMD 1 of the present embodiment, the display unit 3 is attached to the left side of the user with the frame 4 mounted on the head with respect to the frame 4. Therefore, the HMD 1 of the present embodiment causes the user to visually recognize the video by displaying the video with respect to the left eye of the user.

As described above, the spectacle-shaped frame 4 is connected to the front part 41 located in front of the user's face, the armor part 42 extending rearward from the left and right ends of the front part 41, and the armor parts 42 to be rotatable. The temple part 43 is provided. The front part 41 has the left and right end sides on the side where the armor part 42 to which the pair of temple parts 43 are connected is provided. The front portion 41 has a shape that is gently curved so that the central portion thereof is convex on the side (front side) opposite to the side on which the temple portion 43 extends.

The armored portion 42 is a portion that is provided on the left and right ends of the front portion 41 and protrudes along the direction in which the temple portion 43 extends from the front portion 41. A temple portion 43 is rotatably attached to the rear end portion of each armor portion 42. The pair of temple portions 43 sandwich the user's face from both the left and right sides. The temple portion 43 has a cell portion 43a that becomes a portion that covers the user's ear in the latter half portion that faces inward from the front side to the rear side.

The armor part 42 and the temple part 43 are connected by a screw or the like at a hinge part 44 provided at the rear end part of the armor part 42. The temple part 43 is connected to the hinge part 44 so that the temple part 43 can be folded with respect to the configuration including the front part 41 and the armored part 42 with the vertical direction as the rotational axis direction.

In the frame 4, a cover sheet 45 for protecting the user's eyes is attached to the lower side of the front portion 41. The cover sheet 45 includes two sheet members 46 provided corresponding to the left and right eyes of the user, and a holding body 47 that holds the sheet members 46 against the frame 4.

The sheet member 46 is a sheet-like or plate-like member having transparency that covers the left and right eyes of the user. The sheet member 46 is provided in the spectacle-type frame 4 in a manner like a lens in general spectacles. The sheet member 46 is a plate-like member made of a synthetic resin material such as transparent plastic. As described above, the user of the see-through type HMD 1 recognizes the display by the display unit 3 and obtains the field of view by the external light transmitted through the transparent sheet member 46.

The holding body 47 includes a pair of holding portions 47a that hold the two sheet members 46, and a connecting portion 47b that connects these holding portions 47a. Each holding portion 47 a is a frame-like portion formed so that the lower side is open, and has a shape corresponding to the outer edge of the substantially half portion on the upper side of the sheet member 46. Accordingly, each sheet member 46 is held in a state in which the outer edge of the upper half portion is surrounded by the holding portion 47 a of the holding body 47. The connecting portion 47b is a portion that connects a pair of holding portions 47a that hold the sheet member 46 on both the left and right sides at the left and right central portions.

Also, in the cover sheet 45, a nose pad portion 48 that contacts the user's nose is provided in the connecting portion 47b of the holding body 47. The nose pad portion 48 has a pair of pads that come into contact with the nose of the user from both the left and right sides when the frame 4 is attached. The cover sheet 45 is attached to the frame 4 by attaching the portion of the holding body 47 to the front portion 41 of the frame 4.

The frame 4 supports the display unit 3 by the mounting member 49. The attachment member 49 is fixed to an inner portion of the housing 3a of the display unit 3. The attachment member 49 is attached to the left temple part 43 in a state in which the extension part extending forward of the user from the position of the hinge part 44 of the left temple part 43 is penetrated, whereby the display unit 3 is attached. The frame 4 is supported. In other words, the display unit 3 to which the attachment member 49 is fixed is attached to the frame 4 in a state in which the extension portion on the front side of the hinge portion 44 that is the front end portion of the temple portion 43 is inserted into the hole of the attachment member 49. Supported by In addition, the support part of the display unit 3 with respect to the frame 4 by the attachment member 49 is configured so that the position of the display unit 3 can be adjusted in the front-rear direction with respect to the frame 4, for example.

The frame 4 having the above-described configuration is applied to both ears of the user by the pair of temple parts 43, and the front side is supported by the user's nose muscles by the nose pad part 48 having two pads. Supported at four locations. The display unit 3 is supported by the glasses-type frame 4 so that the display unit 3 is disposed on the left front side of the user's head. In the present embodiment, the HMD 1 is configured for the left eye that displays an image on the left eye of the user, but the HMD according to the present invention has a right eye that displays an image on the right eye of the user. Or a configuration for left and right eyes.

[Configuration of repeater]
As shown in FIG. 1, the repeater 2 includes a video signal input terminal 21 that receives a video signal input from the outside, and a power supply input terminal 22 that receives a supply of power from the outside. As described above, the video signal input terminal 21 is a terminal for receiving an input of a video signal output from an output terminal such as an HDMI terminal or a DVI-D terminal included in an external device such as a PC. Therefore, an HDMI cable, an HDMI-DVI-D conversion cable, or the like is connected to the video signal input terminal 21. For example, a USB cable or an AC adapter of an external battery connected via USB is connected to the power supply input terminal 22. The repeater 2 may be configured to incorporate a battery.

As shown in FIG. 2, the repeater 2 has a CPU 23 and a power supply IC 24. The CPU 23 is a control unit that controls the operation of the repeater 2. The CPU 23 receives and outputs a video signal from the video signal input terminal 21. The video signal output from the CPU 23 is sent to the display unit 3 of the HMD 1 through the cable 51. The video signal sent to the display unit 3 by the cable 51 is received by the HDMI receiver 10 of the control unit 6.

Moreover, the repeater 2 has the operation part 25 operated by the user. The operation unit 25 includes, for example, a switch such as a dip switch, a button, and the like. An operation signal generated by the operation of the operation unit 25 is input to the CPU 23. In the present embodiment, in the operation unit 25 of the repeater 2, for example, brightness adjustment of the display image by the LCD unit 5, switching between right eye and left eye by rotating the display image, turning on / off the display image Switching off or the like is performed.

The power supply IC 24 constitutes a power supply unit that receives supply of power supplied from the outside by the power supply input terminal 22 in the repeater 2. The power of this power supply unit is used to drive the CPU 23 and the like. As the power supplied to the power supply unit including the power supply IC 24, for example, the above-described USB-connected external battery, AC adapter, or battery power is used. The power supply IC 24 converts the AC voltage supplied from the power supply input terminal 22 into a stable DC voltage.

In the HMD system 50 having the above-described configuration, in the HMD 1, a video signal (hereinafter referred to as “controller input video signal”) input from the HDMI receiver 10 to the LCD controller 11 is unstable, for example, when the apparatus is activated. It may become a state. Further, as described above, in the control unit 6 of the HMD 1, the video signal output from the HDMI receiver 10 is directly input to the LCD controller 11. Therefore, in the HMD 1 of the present embodiment, when the controller input video signal is in an unstable state, the unstable video signal is input to the LCD controller 11 as it is. Further, after the user turns on the power of the repeater 2, when an operation of outputting a video signal from the PC or the like connected to the video signal input terminal 21 via a cable to the repeater 2 is performed, the repeater When the display image ON is set in the operation unit 25, the image display command from the CPU 9 to the LCD controller 11 is executed in the HMD 1 before the video signal is input from the repeater 2 to the HMD 1. Become.

For example, when an image display command from the CPU 9 to the LCD controller 11 is executed before the controller input video signal is stabilized, that is, in a state where the controller input video signal is unstable, at the time of starting the apparatus, the LCD unit 5 There may be a problem with the display image. In this case, as a problem that occurs in the display image by the LCD unit 5, for example, vertical stripes may appear in the display image.

Fig. 3 shows an example of a normal image and an image with vertical stripes. FIG. 3A shows a schematic diagram of a normal image. On the other hand, FIG. 3B shows a schematic diagram of an image including vertical stripes as an example of a case where a defect occurs in the display image by the LCD unit 5. That is, the phenomenon that vertical stripes appear in the display image as shown in FIG. 3B occurs when the CPU 9 executes an image display command to the LCD controller 11 before the controller input video signal is stabilized as described above.

As described above, it has been found that the specification of the LCD controller 11 can be cited as one of the causes of the phenomenon of vertical stripes caused by the image display command being executed before the controller input video signal is stabilized. Yes. In particular, when the phenomenon of vertical stripes is caused by the specifications of the LCD controller 11, the vertical stripes generated on the display screen may be maintained without disappearing even after the controller input video signal is stabilized.

In order to avoid such a problem that occurs in the display image, it is conceivable to mount an image processing circuit such as a scaler in the control unit 6 of the HMD 1. When this image processing circuit is mounted, in the HMD 1 of this embodiment, the image processing circuit is provided so as to process the controller input video signal. Accordingly, the image processing circuit in this case is mounted at a position for receiving the controller input video signal output from the HDMI receiver 10 as indicated by reference numeral 11a in FIG. When the configuration in which the image processing circuit 11a is mounted in this manner is adopted, even if the controller input video signal output from the HDMI receiver 10 is in an unstable state, the image processing circuit 11a performs a processing process in advance to a normal state. Accordingly, a normal video signal is always input to the LCD controller 11.

However, the HMD 1 according to the present embodiment is a relatively small image display device that is used by being mounted on the user's head as described above. For this reason, in the HMD 1 of this embodiment, it is difficult to mount an image processing circuit such as a scaler as described above from the viewpoint of low power consumption and miniaturization. In particular, since a large amount of power is required for signal processing in the image processing circuit and the power consumption of the CPU 9 also increases, the configuration in which the image processing circuit is mounted is not applicable to a power saving configuration such as the HMD1. Have difficulty.

Therefore, in the HMD 1 of the present embodiment, a control sequence (hereinafter referred to as “image display sequence”) at the time of image display as described below is performed. When this image display sequence is performed, the above-described vertical stripes appear even in the configuration in which the controller input video signal from the HDMI receiver 10 is directly input to the LCD controller 11 as in the HMD 1 of the present embodiment. The problem of the display image due to the controller input video signal becoming unstable can be solved.

Here, regarding the video signal input by the HDMI receiver 10, “directly output” the video signal to the display control unit 14 (the LCD controller 11 thereof) means that the HDMI receiver 10 inputs the controller input video to the LCD controller 11. This means that the signal output path does not have a configuration for applying some processing to the video signal such as the image processing circuit 11a (see FIG. 2). In other words, it means that the controller input video signal output from the HDMI receiver 10 is input to the LCD controller 11 without being processed. Hereinafter, an image display sequence in the HMD 1 of the present embodiment will be described.

[Image display sequence]
In the image display sequence in the HMD 1 of the present embodiment, it is detected that the controller input video signal is in a stable state under a predetermined condition (hereinafter referred to as “video signal stable state”), and the video signal stable state is detected. Then, an image display command for the LCD controller 11 is executed from the CPU 9. That is, when the image display command from the CPU 9 to the LCD controller 11 is executed, if the controller input video signal is in an unstable state at the time of starting the apparatus, the image display command is output until the video signal becomes stable. Execution enters a standby state. This ensures that the image display command from the CPU 9 to the LCD controller 11 is executed in a state where the controller input video signal is stable.

In the HMD 1 of the present embodiment, the video signal stable state is detected based on the state of the synchronization signal included in the controller input video signal. In particular, in the HMD 1 of the present embodiment, since the disturbance of the controller input video signal is reflected in the vertical synchronization signal (V_SYNC), the video signal stable state is detected based on the vertical synchronization signal among the synchronization signals.

For this reason, in the HMD 1 of this embodiment, a vertical synchronization signal is extracted from the controller input video signal output from the HDMI receiver 10. The vertical synchronization signal is extracted from the controller input video signal by, for example, separating the vertical synchronization signal from the video signal by a synchronization separation circuit provided in an interface portion or the like inside the HDMI receiver 10.

As described above, in the HMD 1 of the present embodiment, the HDMI receiver 10 receives the input of the video signal output from the repeater 2, and directly outputs the input video signal to the display control unit 14 (the LCD controller 11 thereof). Then, a vertical synchronization signal (V_SYNC) is extracted from the input video signal, and functions as video signal input / output means for outputting the extracted vertical synchronization signal.

As shown in FIG. 2, the vertical synchronization signal extracted from the controller input video signal output from the HDMI receiver 10 is input to the CPU 9. The CPU 9 detects that the input vertical synchronization signal is in a stable state (hereinafter referred to as “synchronization signal stable state”) as the video signal stable state.

Specifically, as shown in FIG. 4, the vertical synchronization signal (V_SYNC) periodically repeats a high level (hereinafter referred to as “H level”) and a low level (hereinafter referred to as “L level”). It is a pulse signal. Regarding the output level of the vertical synchronizing signal, when the H level is the first value, the L level can be said to be a second value different from the first value. For the vertical synchronization signal, the CPU 9 detects the synchronization signal stable state from the transition state of the signal level between the H level and the L level. For example, the CPU 9 has an input port that receives an input of a vertical synchronizing signal, and detects on / off of the vertical synchronizing signal, that is, an H level / L level at this input port.

As shown in FIG. 4, in a state where the video signal is stable, it is regularly repeated that the state of the H level continues for the period ΔX with respect to the vertical synchronization signal (V_SYNC). That is, the state in which the H level continues during the period ΔX is stably repeated with the interval period ΔY. Note that the interval period ΔY is a period shorter than the period ΔX and the vertical synchronization signal is in the L level. On the other hand, in a state where the video signal is unstable, for example, the continuous time of the H level is not uniform for the vertical synchronization signal, or the continuous time of the H level is shorter than the period ΔX in the stable state.

4, in the transition mode of the vertical synchronization signal (V_SYNC), the period ΔX is a period determined by the scanning frequency of the vertical synchronization signal (hereinafter referred to as “vertical scanning frequency”). For example, when the vertical scanning frequency is 60 [Hz], the period required to scan once in the vertical direction, in other words, the period for drawing an image of one frame is (1/60) × 1000≈16.5 [ ms]. The interval period ΔY is a period that is not affected by the stable state of the controller input video signal or has a small effect. The interval period ΔY is, for example, 0.1 [ms]. In the present embodiment, description will be made assuming that ΔY = 0.1 [ms]. The period ΔX is set to ΔX = 16.4 [ms] by subtracting ΔY (= 0.1 [ms]) from 16.5 [ms], which is a drawing period of one frame.

From the input vertical synchronization signal, the CPU 9 continues from the H level to the L level from the time when the output of the vertical synchronization signal is kept at the H level, that is, from the time when the output level of the vertical synchronization signal changes from the L level to the H level. The synchronous signal stable state is detected based on a preset reference time with respect to the time until the point of time (hereinafter referred to as “continuous H level time”). Specifically, the CPU 9 measures the continuous H level time for the input vertical synchronization signal. The CPU 9 detects the synchronization signal stable state by comparing the measurement time of the continuous H level time with a preset reference time.

CPU9 detects a synchronous signal stable state, for example, when the measurement time of continuous H level time corresponds with the preset reference time. In this case, the reference time set in advance is set to 16.4 [ms], which is the same as the period ΔX, according to the example when the scanning frequency is 60 [Hz] as described above. That is, in this case, the synchronization signal stable state is detected when the measurement time of the continuous H level time by the CPU 9 is 16.4 [ms] which is the same as the period ΔX in the state where the video signal is stable. The reference time to be compared with the measurement time of the continuous H level time is set and stored in advance in a storage unit or the like included in the control unit 6.

CPU9 will output the image display signal which performs the image display by the LCD unit 5 with respect to the display control part 14, if a synchronous signal stable state is detected based on reference | standard time from the input vertical synchronizing signal. Here, the image display signal sent from the CPU 9 to the display control unit 14 includes an image display command signal from the CPU 9 to the LCD controller 11 and a control signal from the CPU 9 to the LED backlight drive IC 12.

Specifically, among the image display signals sent from the CPU 9 to the display control unit 14, an image display command signal from the CPU 9 to the LCD controller 11 turns on the display register of the LCD controller 11, and sends the LCD 7 to the LCD controller 11. This is a signal for starting the drive control for. Of the image display signals sent from the CPU 9 to the display control unit 14, the control signal from the CPU 9 to the LED backlight drive IC 12 is a signal for causing the LED backlight drive IC 12 to turn on the backlight 8.

Further, the control signal sent from the CPU 9 to the display control unit 14 includes an image non-display signal for stopping the image display by the LCD unit 5. The image non-display signal sent from the CPU 9 to the display control unit 14 includes an image non-display command signal from the CPU 9 to the LCD controller 11 and a control signal from the CPU 9 to the LED backlight drive IC 12.

Specifically, among the image non-display signals sent from the CPU 9 to the display control unit 14, an image non-display command signal from the CPU 9 to the LCD controller 11 turns off the display register of the LCD controller 11, and the LCD controller 11 This is a signal for stopping drive control for the LCD 7. Of the image non-display signals sent from the CPU 9 to the display control unit 14, the control signal from the CPU 9 to the LED backlight drive IC 12 is a signal for causing the LED backlight drive IC 12 to turn off the backlight 8.

In the HMD 1 of this embodiment in which such an image display sequence is performed, the CPU 9 functions as a synchronization signal detection unit. That is, in the present embodiment, the CPU 9 receives the vertical synchronization signal output from the HDMI receiver 10 and is based on a reference time set in advance for a time during which the output of the vertical synchronization signal is constant, that is, a continuous H level time. , It is detected that the input vertical synchronization signal is in a stable state (synchronization signal stable state).

Further, the CPU 9 functions as an image display signal output unit. That is, in this embodiment, when the CPU 9 detects the synchronization signal stable state after the input of the video signal to the HDMI receiver 10 is started, the CPU 9 causes the display control unit 14 to perform image display by the LCD unit 5. Output a signal. Here, after the input of the video signal to the HDMI receiver 10 is started, for example, immediately after the input of the video signal to the HDMI receiver 10 from a state in which no image display is performed, such as when the HMD 1 is turned on. is there. Further, the image display signal sent from the CPU 9 to the display control unit 14 includes the image display command signal for the LCD controller 11 and the control signal for the LED backlight drive IC 12 as described above.

An example of the image display sequence in the present embodiment will be described with reference to the flowcharts shown in FIG. 4 and FIG. When the image display sequence in the present embodiment is executed, the relay 2 is turned on by the user. The operation of turning on the power of the repeater 2 is, for example, an operation of a power switch of the repeater 2, or when an external battery is connected to the power supply input terminal 22 of the repeater 2, the power of the external battery is turned on. It is an operation to insert.

When the power of the repeater 2 is turned on, power supply to the HMD 1 by the cable 51 is started, the power of the HMD 1 is turned on, and processing in the HMD 1 is started. The image display sequence in the HMD 1 of the present embodiment is executed as an image display method for displaying an image on the LCD 7 by directly inputting the video signal input from the repeater 2 to the LCD controller 11 which is a means for controlling the LCD 7. Is done.

As shown in FIG. 5, the image display flag is turned off in the state where the processing in the HMD 1 is started (S10). That is, the display register of the LCD controller 11 is in an off state.

Then, in the image display sequence of this embodiment, it is determined whether the operation is an image display operation or an image non-display operation (S20). Here, whether the image display operation or the image non-display operation is determined is determined by the state of the operation unit 25 of the repeater 2. Specifically, an on / off switch for switching between image display and image non-display is provided as the operation unit 25. Then, depending on the on / off state of the changeover switch, it is determined whether the image display operation or the image non-display operation. That is, when the changeover switch of the operation unit 25 is in the on state, it is determined as an image display operation, and when the changeover switch is in the off state, it is determined as an image non-display operation.

First, the case where the image display operation is determined in step S20 will be described with reference to FIG. In FIG. 4, for example, the timing indicated by the arrow T <b> 1 corresponds to the timing when the user switches on the image display / image non-display switch of the operation unit 25 after the processing in the HMD 1 is started.

When the image display operation by the user, that is, when the changeover switch of the operation unit 25 is turned on, the video signal is input next. The video signal is input to the repeater 2 from an external device such as a PC via an HDMI cable or an HDMI-DVI-D conversion cable connected to the video signal input terminal 21 of the repeater 2. The video signal input to the repeater 2 is input to the HMD 1 through the cable 51. In the HMD 1, the video signal from the repeater 2 is received by the HDMI receiver 10. In FIG. 4, the timing when the video signal is input to the HMD 1 corresponds to the timing indicated by the arrow T2.

After the input of the video signal is started, it is determined whether or not the image display flag is off (S30). In this step S30, it is determined whether or not image display by the LCD unit 5 has already been performed. That is, the determination of the image display operation in step S20 is, for example, the first time after the repeater 2 is turned on and the processing of the HMD 1 is started, and the switch on the operation unit 25 is turned on by the user. It is determined whether it is a determination.

Therefore, when the image display flag is off in step S30 (S30, Yes), the image display is not yet performed, and the determination of the image display operation in step S20 is the first time after the processing of HMD1 is started. This is the case. On the other hand, if the image display flag is not off in step S30 (S30, No), that is, if the image display flag is on, the image is already being displayed.

In Step S30, when it is determined that the image display flag is off (S30, Yes), it is determined whether or not the video signal is stable (S40). The determination as to whether or not the video signal is stable here is performed by the detection of the video signal stable state by the CPU 9 as described above, that is, the detection of the synchronous signal stable state. Specifically, the CPU 9 detects a vertical synchronization signal extracted from the controller input video signal. The CPU 9 detects the synchronization signal stable state from the measurement time of the continuous H level time for the detected vertical synchronization signal and the preset reference time.

In step S40, when the CPU 9 detects the synchronization signal stable state, it is determined that the video signal is stable (S40, Yes). The process in step S40 is repeatedly performed until it is determined that the video signal is stable. That is, if it is determined in step S40 that the video signal is not stable (No in S40), it is determined again whether the video signal is stable. Therefore, according to step S40, waiting is performed until the video signal input to the HMD 1 is stabilized.

As described above, in step S40, the CPU 9 presets the step of detecting the vertical synchronization signal (V_SYNC) from the controller input video signal and the time (continuous H level time) during which the output of the vertical synchronization signal is constant. Based on the reference time, a step of detecting that the vertical synchronization signal detected by the detecting step is in a stable state is performed.

If it is determined in step S40 that the video signal is stable (S40, Yes), an image display command is executed (S50), and the backlight 8 is turned on (S60). In step S50, the CPU 9 sends an image display command signal to the LCD controller 11, and the LCD controller 11 starts driving the LCD 7. In step S60, a signal for turning on the backlight 8 with the set brightness is sent from the CPU 9 to the LED backlight drive IC 12.

Step S50 and Step S60 are steps performed when the synchronization signal stable state is detected by the CPU 9, and correspond to a step of executing image display by the LCD 7 of the LCD unit 5.

When the backlight 8 is turned on in step S60, the image display flag is turned on (S70). That is, the display register included in the LCD controller 11 is turned on. The case where it is determined in step S30 that the image display flag is not off (S30, No) will be described later.

Next, the case where the image non-display operation is determined in step S20 will be described. If it is determined in step S20 that the image is not displayed, it is determined whether or not the image display flag is off (S80). In step S80, as in step S30 described above, it is determined whether or not image display by the LCD unit 5 has already been performed.

Therefore, if the image display flag is off in step S80 (S80, Yes), the image display is not yet performed, and the determination of the image non-display operation in step S20 is made after the processing of HMD1 is started. This is the first time. On the other hand, if the image display flag is not off in step S80 (S80, No), that is, if the image display flag is on, the image is already being displayed.

Therefore, if it is determined in step S80 that the image display flag is not off (S80, No), an image non-display command is executed (S90), and the backlight 8 is turned off (S100). In step S <b> 90, an image non-display command signal is sent from the CPU 9 to the LCD controller 11, and the LCD controller 11 stops driving the LCD 7. In step 100, a signal for turning off the backlight 8 is sent from the CPU 9 to the LED backlight drive IC 12.

When the backlight 8 is turned off in step S100, the image display flag is turned off (S110). That is, the display register included in the LCD controller 11 is turned off.

On the other hand, if it is determined in step S80 that the image display flag is OFF (S80, Yes), the process proceeds to step S20. That is, in this case, since the image display is not yet performed, the backlight 8 is not turned off by the image non-display command.

In the HMD 1 of the present embodiment, the processing associated with the image display operation and the image non-display operation as described above is performed in accordance with the switching of the image display operation / image non-display operation in step S20. Then, in the processing flow shown in FIG. 5, the CPU 9 performs each of the processing when the image display operation is performed (S30 to S70) and the processing when the image non-display operation is performed (S80 to S110). This is performed by reading and executing a predetermined control program stored in the storage unit or the like of the control unit 6.

According to the HMD 1 of the present embodiment in which the image display sequence as described above is performed, it is possible to eliminate the problem of the display image caused by the disturbance of the video signal without using an image processing circuit such as a scaler. Specifically, in the HMD 1 of the present embodiment, after waiting for the controller input video signal to become stable in the processing flow described above (S40), an image display command for the LCD controller 11 is executed. (S50). Thereby, problems such as vertical stripes appearing in the display image can be avoided.

If an image display command for the LCD controller 11 is executed while the controller input video signal is unstable, for example, a phenomenon that vertical stripes appear in the display image (see FIG. 3B) may occur. Therefore, as in the image display sequence in the HMD 1 of the present embodiment, when the controller input video signal is in a stable state, an image display command to the LCD controller 11 is executed, thereby causing a display image defect such as a vertical stripe phenomenon. Therefore, normal image display (see FIG. 3A) can be ensured. In such an image display sequence, unlike the HMD 1 of the present embodiment, an image processing circuit 11a such as a scaler (see FIG. 2) does not exist between the HDMI receiver 10 and the LCD controller 11, and the controller input video signal Is effective in a configuration in which is input directly from the HDMI receiver 10 to the LCD controller 11.

Hereinafter, details of an image display sequence as a preferable aspect in the HMD 1 of the present embodiment will be described.

As shown in FIG. 4, when the video signal is unstable, the vertical synchronizing signal (V_SYNC) has a non-uniform continuous H level time or a time (period) in which the continuous H level time is derived from the vertical scanning frequency. Or shorter than [Delta] X). On the other hand, in a state where the video signal is stable, the continuous H level time of the length of the period ΔX is repeated together with the interval period ΔY in which the output level becomes the L level.

Therefore, in the image display sequence of the present embodiment, it is detected as the synchronization signal stable state that the continuous H level time is constant for the reference time for a predetermined number of times in the synchronization signal stable state detection process. Therefore, when a time having the same length as the period ΔX is set as the reference time, it is detected as the synchronization signal stable state that the continuous H level time has become the period ΔX continuously for a predetermined number of times.

Here, a case will be described as an example where the predetermined number of times is set to 3 times, the period ΔX is 16.4 [ms], and the reference time is set to 16.4 [ms] which is the same as the period ΔX. In this case, in step S20 in the processing flow shown in FIG. 5, the CPU 9 detects the synchronization signal stable state when the measured continuous H level time is 16.4 [ms] for three consecutive times.

In the example of the vertical synchronizing signal (V_SYNC) shown in FIG. 4, the timing indicated by the arrow T3 corresponds to the timing at which the continuous H level time of the period ΔX is generated three times in succession. That is, the synchronization signal stable state is detected by the CPU 9 at the timing indicated by the arrow T3 in FIG. 4, whereby the image display command is executed and the backlight 8 is turned on. In the case of this example, for example, when the continuous H level time continuously measured by the CPU 9 is the first 16.4 [ms], the second 16.4 [ms], and the third 14 [ms] The continuous H level time is measured again from the first time.

As described above, in the HMD 1 of the present embodiment, the CPU 9 functioning as the synchronization signal detection means that the output of the input vertical synchronization signal is constant for a reference time and continues for a predetermined number of times. Is detected as a synchronization signal stable state, whereby the synchronization signal stable state corresponding to the video signal stable state can be accurately detected. As a result, it is possible to effectively eliminate the display image defect caused by the disturbance of the video signal.

Note that the predetermined number of times that the continuous H level time of the reference time continues is preset and stored in a storage unit or the like included in the control unit 6. Further, the predetermined number of times that the continuous H level time of the reference time continues is not particularly limited, and is appropriately set according to the transition mode of the vertical synchronization signal (V_SYNC), the specification of the LCD controller 11, and the like.

Next, a preferable aspect of the reference time will be described. It is preferable that the reference time used in the sync signal stable state detection process has a predetermined width set based on the vertical scanning frequency. In other words, the reference time used for the synchronization signal stable state detection process is preferably a time defined by a predetermined numerical range.

Thus, when the reference time used for the detection process of the synchronization signal stable state is defined as a numerical range having a predetermined width, if the continuous H level time measured by the CPU 9 is a value within the numerical range, The signal of the continuous H level time is counted as one of the number of times required to continue for a predetermined number of times as described above.

Specifically, for example, when the reference time is set as 15.0 to 18.0 [ms], the continuous H level time measured by the CPU 9 is within the range of 15.0 to 18.0 [ms]. If it is a value, the signal of the continuous H level time is counted as one of the number of times required to continue for a predetermined number of times. In this example, for example, the continuous H level time continuously measured by the CPU 9 is 15.5 [ms] for the first time, 17.0 [ms] for the second time, and 16.5 [ms] for the third time. If there is, the output of the vertical synchronizing signal becomes constant for the reference time, that is, the continuous H level time becomes the reference time for three consecutive times.

The width (numerical range) of the reference time used for the sync signal stable state detection process is set based on the vertical scanning frequency. For example, when the vertical scanning frequency is 60 [Hz], the period ΔX in the vertical synchronization signal is 16.4 [ms] as described above. Therefore, when the vertical scanning frequency is 60 [Hz], the reference time is set as 16.4 ms ± several ms, for example. In this case, specifically, the reference time is set as 15.0 to 18.0 [ms], for example.

For example, when the vertical scanning frequency is 70 [Hz], which is larger than the above-described 60 [Hz], the drawing period of one frame is (1/70) × 1000≈14.3 [ms]. Therefore, the period ΔX is ΔX = 14.3−ΔY (= 0.1 [ms]) = 14.2 [ms]. In this case, the reference time is set as, for example, 14.2 ms ± several ms, and specifically, set as, for example, 13.0 to 16.0 [ms]. Further, for example, when the vertical scanning frequency is switched between 60 [Hz] and 70 [Hz] in accordance with the adjustment of the image resolution in the HMD 1, the reference time is 16.4 [ms that is the period ΔX at each vertical scanning frequency. ] And 14.2 [ms] are set. Accordingly, the reference time in this case is set as 13.0 to 18.0 [ms], for example.

As described above, the reference time used in the sync signal stable state detection process is set as a numerical range having a predetermined width set based on the vertical scanning frequency, so that the sync signal stable state detection process is performed. The error of the period ΔX with respect to the vertical synchronization signal when the video signal is stable is allowed. As a result, it is possible to avoid a situation in which the synchronization signal stable state is not detected due to a slight change in the period ΔX of the vertical synchronization signal, although the video signal is in a stable state. As a result, it is possible to accurately detect the synchronization signal stable state.

Subsequently, a preferable aspect of the output timing of the control signal from the CPU 9 to the display control unit 14 will be described. As described above, the HMD 1 of the present embodiment includes the LCD 7 and the backlight 8 in the LCD unit 5 that performs image display, and the LCD controller 11 that controls the LCD 7 in the display control unit 14 that controls the LCD unit 5. And an LED backlight drive IC 12 that controls the backlight 8.

The HMD 1 of the present embodiment, when causing the LCD unit 5 to perform image display based on the image display signal output from the CPU 9, starts control of the LCD 7 by the LCD controller 11, and then performs LED back-up after a predetermined time has elapsed. Control of the backlight 8 is started by the write drive IC 12. That is, when the LCD unit 5 displays an image, a predetermined time difference is provided between the output timing of the control signal from the CPU 9 to the LCD controller 11 and the output timing of the control signal from the CPU 9 to the LED backlight drive IC 12.

Specifically, in the image display sequence described above, when it is determined that the video signal is stable, the CPU 9 sends an image display command signal to the LCD controller 11 and the LCD controller 11 starts driving the LCD 7. Then, a signal for turning on the backlight 8 is sent from the CPU 9 to the LED backlight drive IC 12 (S60). In the flow of the image display command to the LCD controller 11 and the lighting of the backlight 8, the backlight 8 is turned on after a predetermined time has elapsed from the timing at which the image display command to the LCD controller 11 is executed. That is, the CPU 9 outputs a control signal to the LED backlight drive IC 12 after a predetermined time has elapsed after outputting the image display command signal to the LCD controller 11.

Here, the predetermined time (hereinafter referred to as “light lighting standby time”) from the output timing of the image display command signal by the CPU 9 to the output timing of the control signal for lighting the backlight 8 is, for example, several 10 to It is set as a time within a range of several hundred ms. The light turn-on standby time is set based on the time from when the LCD controller 11 receives the image display command from the CPU 9 until the display on sequence executed is completed.

The light lighting standby time will be described with reference to FIG. As shown in FIG. 6, in the LCD controller 11, when an image display command signal from the CPU 9 is input and the image display command is turned on at timing t1, execution of the display on sequence is started. . As a display on sequence in the LCD controller 11, for example, a built-in power supply is started up. When the display on sequence is completed, the LCD 7 is ready for image display. When the LCD 7 is capable of displaying an image, the backlight 8 is turned on to display the image on the LCD 7.

In such a series of operations in the LCD controller 11, the light lighting standby time in the CPU 9 is set to a time longer than the time from when the LCD controller 11 receives the image display command until the display on sequence is completed. . As shown in FIG. 6, the light lighting standby time is a time ΔZ from the timing t1 when the image display command is turned on in the LCD controller 11 to the timing t2 when the backlight 8 is turned on. Therefore, the light lighting standby time (time ΔZ) is set as a time longer than the time from the timing t1 when the image display command is turned on to the timing t3 when the display on sequence is completed.

According to the light lighting standby time, there is a slight time lag between the timing t3 when the display on sequence is completed in the LCD controller 11 and the timing t2 when the backlight 8 is turned on. In the case of the HMD 1 of the present embodiment, the light lighting standby time (time ΔZ) is set to 100 ms, for example. However, the light lighting standby time is appropriately set according to the specifications of the LCD controller 11 and the like. The light lighting standby time is set and stored in advance in a storage unit or the like included in the control unit 6.

As described above, after the image display command by the CPU 9 is turned on in the LCD controller 11, the lighting control of the backlight 8 is performed after a predetermined time has elapsed, thereby ensuring a normal image for the display image by the LCD unit 5. be able to. If the backlight 8 is turned on before the display on sequence is completed in the LCD controller 11, a normal image may not be displayed depending on the specifications of the LCD controller 11. Therefore, as described above, by providing a light turn-on standby time in the control of the LCD unit 5 by the CPU 9, when the backlight 8 is turned on, the completion state of the display on sequence in the LCD controller 11 is obtained. Normal image display according to 5 can be ensured.

Next, control executed in a state where image display by the LCD unit 5 is performed based on the above-described image display sequence will be described. The control described here is image display interruption control performed by the CPU 9 based on a predetermined control program. After outputting the image display signal to the LCD unit 5, the CPU 9 causes the display control unit 14 to interrupt the image display by the LCD unit 5 when the synchronization signal stable state is not detected, that is, the image non-display described above. Output the display signal.

The image display interruption control described here is executed in a state where image display is performed as described above. Therefore, the image display interruption control is executed when it is determined in step S30 that the image display flag is not OFF (No in S30), that is, when the image display flag is ON in the processing flow shown in FIG. Control.

Specifically, it is as follows. First, for example, when the determination of the image display operation in step S20 is the first time after the processing of the HMD1 is started, the image display is not yet performed. In S30, it is determined that the display flag is off (S30, Yes).

In step S40, when the synchronization signal stable state is detected and it is determined that the video signal is stable (S40, Yes), an image display command is executed (S50), and the backlight 8 is turned on. (S60) The image display flag is turned on (S70), and image display by the LCD unit 5 is performed. As described above, when the image display operation is determined in step S20, the determination on the video signal in step S40 performed when the image display flag is determined OFF in step S30 is as described above. This is performed immediately after the start of the input of the video signal to 10.

On the other hand, in the image display interruption control, when image display is once started in steps S50 to S70 and then it is determined in step S20 that the image display operation is performed, in step S30, the image display flag is not turned off (ON (Step S30, No), it is determined whether or not the video signal is stable (S120). Whether or not the video signal is stable in step S120 is determined by the same method as in step S40 described above.

If it is determined in step S120 that the video signal is stable (S120, Yes), the image display is continued as it is, and the process proceeds to step S20. On the other hand, when it is determined in step S120 that the video signal is not stable (S120, No), an image similar to that when the image non-display operation is determined in step S20 during image display (S80, No). Non-display processing (S90 to S110) is performed.

As described above, in a state where the video signal is stabilized and the image display by the LCD unit 5 is once started, the CPU 9 continues the determination process as to whether or not the video signal is stable, similarly to step S40. When it is determined that the video signal is not stable, that is, when the synchronization signal stable state is no longer detected by the CPU 9, an image non-display signal is output from the CPU 9 to the display control unit 14. That is, similar to the processing of steps S90 to S110 in the processing flow shown in FIG. 5, the image non-display command is executed and the backlight 8 is turned off, so that the image display by the LCD unit 5 is interrupted.

By performing the image display interruption control as described above, when the video signal is disturbed during the operation of the HMD 1, the image display by the LCD unit 5 can be stopped. Thereby, it is possible to prevent the image disturbed by the disturbance of the video signal from being displayed to the user, and it is possible to prevent the user from feeling uncomfortable due to the disturbance of the image.

In the embodiment of the present disclosure described above, the vertical synchronization signal (V_SYNC) is employed as the synchronization signal included in the video signal when detecting the stable state of the video signal, but is not limited thereto. That is, the synchronization signal used for detecting the video signal stable state may be a horizontal synchronization signal (H_SYNC) or both a vertical synchronization signal (V_SYNC) and a horizontal synchronization signal (H_SYNC). Therefore, the synchronization signal detected and output from the HDMI receiver 10 and received by the CPU 9 may be at least one of the vertical synchronization signal (V_SYNC) and the horizontal synchronization signal (H_SYNC).

In the embodiment of the present disclosure described above, the display unit 3 included in the HMD 1 employs a display method using the LCD 7, but is not limited thereto. The HMD 1 is, for example, a retinal scanning type image display device that projects scanned laser light onto a user's retina, a CRT (Cathode-ray tube), an organic EL (Electro Luminescence) element, or the like. The image display device used may be used. That is, the present invention can be applied to all display devices that handle synchronization signals such as vertical synchronization signals and horizontal synchronization signals.

In the above-described embodiment of the present disclosure, the repeater 2 is an external device connected to the HMD 1 with the cable 51. However, a configuration in which the repeater 2 is built in the HMD 1 can be realized by incorporating the configuration having the function of the repeater 2 in the HMD 1.

In the embodiment of the present disclosure described above, the video signal input from the repeater 2 to the HMD 1 is input from the external device such as a PC to the repeater 2, but the video signal input to the HMD 1 is It may be stored in the repeater 2. In this case, the video signal storage portion in the repeater 2 includes, for example, an internal storage device such as a RAM, an SD card, a USB flash memory, a CD (Compact Disk), an FD (Flexible Disk), and an MO (Magneto-Optical Disk). ), A storage device such as a DVD (Digital Versatile Disk), HD (Hard Disk), or the like is used as appropriate.

[Application example]
Below, the application example of the HMD system 50 containing HMD1 which concerns on embodiment mentioned above is demonstrated.

As shown in FIG. 7, the HMD system 50 </ b> A of this application example is a system that displays an image from the smartphone 71 on the HMD 1. In this application example, the HDMI cable 72 is connected to the video signal input terminal 21 of the repeater 2 via the Dock-HDMI conversion adapter 75 connected to the smartphone 71. An external battery 73 connected by USB is connected to the power supply input terminal 22 of the repeater 2 by a power supply USB cable 74. In this application example, the external battery 73 and the smartphone 71 are connected by the Dock-USB conversion cable 76 via the Dock-HDMI conversion adapter 75. As a result, power is supplied from the external battery 73 to the smartphone 71. If the Dock-USB conversion cable 76 is not connected between the external battery 73 and the smartphone 71, power is not supplied to the smartphone 71, but the operation of this system is not affected.

In the HMD system 50A of the application example, according to the specifications of the smartphone 71, the video signal is not output from the smartphone 71 on the image display side, that is, in a state where the power of the repeater 2 is not turned on. For this reason, in the HMD system 50A of this application example, the output operation of the video signal from the smartphone 71 to the repeater 2 is necessarily performed after the repeater 2 is turned on.

Therefore, in the HMD system 50A of the present application example, if the image display sequence of the present embodiment as described above is not executed, the output of the controller input video signal is unstable as in Application Example 1, There is a situation in which an image display command to the LCD controller 11 is being executed, causing problems such as vertical stripes appearing in the display image. Therefore, also in the HMD system 50A of this application example, an image display command to the LCD controller 11 is waited until the output of the controller input video signal is stabilized by executing the image display sequence of the present embodiment. become. Thereby, a normal image is secured for the display image by the LCD unit 5.

As described above, according to the HMD 1 and the image display method according to the present embodiment, the following effects can be expected.

(1) The HMD 1 of the present embodiment receives an input of an LCD unit 5 that performs image display, a display control unit 14 that controls the LCD unit 5, and a video signal including a digital image signal, a vertical synchronization signal, and a horizontal synchronization signal. In addition to directly outputting the input video signal to the display control unit 14, the HDMI receiver 10 that detects and outputs the vertical synchronization signal from the input video signal, and the input of the vertical synchronization signal output from the HDMI receiver 10. And a synchronization signal detecting means for detecting that the input vertical synchronization signal is in a stable state based on a reference time set in advance for a time when the output of the vertical synchronization signal is constant, and an image to the HDMI receiver 10 After the signal input is started, the synchronization signal detection means detects that the vertical synchronization signal is in a stable state. If that, the display control unit 14, and a CPU9 to function as each means of the image display signal output means for outputting an image display signal to perform image display by LCD unit 5. Thereby, the malfunction of the display image resulting from disturbance of a video signal can be eliminated, without using image processing circuits, such as a scaler.

(2) In the HMD 1 of the present embodiment, the CPU 9 as the synchronization signal detecting means indicates that the output of the input vertical synchronization signal is constant for a reference time, and that the predetermined number of times has been consecutively set. It is detected that the synchronization signal is in a stable state. As a result, the synchronization signal stable state corresponding to the video signal stable state can be accurately detected. As a result, it is possible to effectively eliminate the display image defect caused by the disturbance of the video signal.

(3) In the HMD 1 of the present embodiment, the reference time has a predetermined width set based on the vertical scanning frequency. Thereby, in the detection process of the synchronization signal stable state, an error of the period ΔX with respect to the vertical synchronization signal when the video signal is stable is allowed. As a result, it is possible to avoid a situation in which the synchronization signal stable state is not detected due to a slight change in the period ΔX of the vertical synchronization signal, although the video signal is in a stable state. As a result, it is possible to accurately detect the synchronization signal stable state.

(4) In the HMD 1 of the present embodiment, the LCD unit 5 includes the LCD 7 and the backlight 8 for performing image display by the LCD 7, and the display control unit 14 includes the LCD controller 11 that controls the LCD 7, And an LED backlight drive IC 12 that controls the backlight 8. Then, when the HMD 1 causes the LCD unit 5 to perform image display based on the image display signal output from the CPU 9 serving as the image display signal output means, the LCD controller 11 starts controlling the LCD 7 and then performs a predetermined time (write After the lighting standby time) elapses, control of the backlight 8 is started by the LED backlight drive IC 12. Thereby, a normal image can be ensured for the display image by the LCD unit 5.

(5) In the HMD 1 of the present embodiment, the CPU 9 functioning as the image display signal output means outputs the image display signal, and when the synchronization signal stable state is no longer detected, the display control unit 14 displays the LCD unit 5. A signal (image non-display signal) for interrupting the image display by is output. Thereby, it is possible to prevent the image disturbed by the disturbance of the video signal from being displayed to the user, and it is possible to prevent the user from feeling uncomfortable due to the disturbance of the image.

(6) In the image processing method of the present embodiment, an image for displaying an image on the LCD 7 by directly inputting a video signal including a digital image signal, a vertical synchronization signal, and a horizontal synchronization signal to the LCD controller 11 that controls the LCD 7. A method of display, in which a vertical synchronization signal detected by a step of detecting a vertical synchronization signal from a video signal and a detection time based on a reference time set in advance for a time when the output of the vertical synchronization signal is constant is stable. And a step of displaying an image when the vertical synchronization signal is detected to be stable by the detecting step. Thereby, the malfunction of the display image resulting from disturbance of a video signal can be eliminated, without using image processing circuits, such as a scaler.

1 HMD (image display device)
2 Repeater 5 LCD unit (image display means)
7 LCD (Liquid Crystal Display)
8 Backlight (light source)
9 CPU (synchronization signal detection means, image display signal output means)
10 HDMI receiver (video signal input / output means)
11 LCD controller (liquid crystal controller)
12 LED backlight drive IC (light source controller)
14 Display control unit (display control means)
50 HMD system

Claims (6)

1. Image display means for displaying an image;
   Display control means for controlling the image display means;
   A video signal including a digital image signal, a vertical synchronization signal, and a horizontal synchronization signal is input, the input video signal is directly output to the display control means, and the vertical synchronization signal and the horizontal signal are input from the input video signal. Video signal input / output means for extracting at least one of the synchronization signals and outputting the at least one synchronization signal;
   The input synchronization signal is in a stable state based on a comparison between a time when the at least one synchronization signal is input and the output of the at least one synchronization signal is constant and a preset reference time. Synchronization signal detecting means for detecting
   After the input of the video signal to the video signal input / output unit is started, when the synchronization signal detection unit detects that the synchronization signal is in a stable state, the display control unit displays the image display Image display signal output means for outputting an image display signal for executing image display by the means,
   Image display device.
2. The synchronization signal detecting means detects that the output of the input synchronization signal is constant during the reference time for a predetermined number of preset times as a state where the synchronization signal is stable. ,
   The image display device according to claim 1.
3. The reference time has a predetermined width set based on the scanning frequency of the synchronization signal,
   The image display device according to claim 1.
4. The image display means includes a liquid crystal display and a light source for displaying an image on the liquid crystal display,
   The display control means includes a liquid crystal control unit that controls the liquid crystal display, and a light source control unit that controls the light source,
   The image display signal output means includes
   By causing the liquid crystal display to start driving by outputting an image display signal to the liquid crystal control unit,
   The light source is turned on by outputting the image display signal to the light source controller after a predetermined time has elapsed since the image display signal was output to the liquid crystal controller.
   The image display device according to any one of claims 1 to 3.
5. The image display signal output means outputs the image by the image display means to the display control means when the synchronization signal detection means no longer detects that the synchronization signal is in a stable state after outputting the image display signal. Outputs a signal to interrupt the display,
   The image display device according to any one of claims 1 to 4.
6. An image display method for displaying an image on the liquid crystal display by directly inputting a video signal including a digital image signal, a vertical synchronization signal and a horizontal synchronization signal to a means for controlling the liquid crystal display,
   Extracting at least one of the vertical synchronization signal and the horizontal synchronization signal from the video signal;
   Detecting that the synchronization signal detected by the detecting step is in a stable state based on a comparison between a time at which the output of the synchronization signal is constant and a preset reference time;
   When the detecting step detects that the synchronization signal is in a stable state, the image display is performed.
   Image display method.

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