WO2013039101A1 - Method for producing solar cell, and solar cell - Google Patents

Method for producing solar cell, and solar cell Download PDF

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WO2013039101A1
WO2013039101A1 PCT/JP2012/073319 JP2012073319W WO2013039101A1 WO 2013039101 A1 WO2013039101 A1 WO 2013039101A1 JP 2012073319 W JP2012073319 W JP 2012073319W WO 2013039101 A1 WO2013039101 A1 WO 2013039101A1
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semiconductor region
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solar cell
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高橋　優
純也 嶋田
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シャープ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

Provided is a method for producing a solar cell, the method involving, in the following order, a first step for dispersing impurities of a first conductive type to a region to function as a high-concentration first conductivity-type semiconductor region and a region to function as a low-concentration second conductivity-type semiconductor region, and a second step for dispersing impurities of a second conductivity type to a region to function as a high-concentration second conductivity-type semiconductor region and the region to function as the low-concentration second conductivity-type semiconductor region, wherein, in the low-concentration second conductivity-type semiconductor region, the impurities of a second conductivity type is predominantly dispersed relative to the impurities of a first conductivity type. Also provided is a solar cell produced by means of the aforementioned production method.

Description

太陽電池の製造方法および太陽電池Solar cell manufacturing method and solar cell
　本発明は、太陽電池の製造方法、および太陽電池、特に、太陽電池の入射光側の反対の面である裏面構造に関する。 The present invention relates to a method for manufacturing a solar cell, and a solar cell, and in particular, a back surface structure that is a surface opposite to the incident light side of the solar cell.
　太陽光エネルギを直接電気エネルギに変換する太陽電池は、近年、特に地球環境問題の観点から、次世代のエネルギ源としての期待が急激に高まっている。太陽電池としては、化合物半導体または有機材料を用いたものなど様々な種類があるが、現在、主流となっているのは、シリコン結晶を用いたものである。 In recent years, expectations for solar cells that directly convert solar energy into electrical energy have increased rapidly as a next-generation energy source, particularly from the viewpoint of global environmental problems. There are various types of solar cells, such as those using compound semiconductors or organic materials, but the mainstream is currently using silicon crystals.
　現在、最も多く製造および販売されている太陽電池は、太陽光が入射する側の面である受光面と、受光面の反対側である裏面とに電極が形成された構造のものである。 Currently, the most manufactured and sold solar cells have a structure in which electrodes are formed on a light receiving surface that is a surface on which sunlight is incident and a back surface that is opposite to the light receiving surface.
　しかしながら、受光面に電極を形成した場合、電極における光の反射、吸収があることから、形成された電極の面積分だけ入射する太陽光が減少するので、裏面にのみ電極を形成した太陽電池が開発されている。この裏面にのみ電極を形成した太陽電池は、裏面電極型太陽電池とも呼ばれる。 However, when an electrode is formed on the light receiving surface, since there is reflection and absorption of light at the electrode, sunlight incident on the area of the formed electrode is reduced, so a solar cell having an electrode formed only on the back surface Has been developed. A solar cell in which an electrode is formed only on the back surface is also called a back electrode type solar cell.
　図９は、特開２００８－１８６９２７号公報（特許文献１）に開示されている従来の裏面接合型太陽電池の断面を表す模式図である。以下に、従来の裏面接合型太陽電池２００について説明する。 FIG. 9 is a schematic diagram showing a cross section of a conventional back junction solar cell disclosed in Japanese Patent Application Laid-Open No. 2008-186927 (Patent Document 1). The conventional back junction solar cell 200 will be described below.
　ｎ型シリコン基板２０１の受光面にはテクスチャ構造２０８が形成され、テクスチャ構造２０８の表面は窒化珪素膜または酸化珪素膜からなる反射防止膜２１０でおおわれている。この反射防止膜２１０はパッシベーション膜としての役割も果たす。 A texture structure 208 is formed on the light receiving surface of the n-type silicon substrate 201, and the surface of the texture structure 208 is covered with an antireflection film 210 made of a silicon nitride film or a silicon oxide film. This antireflection film 210 also serves as a passivation film.
　また、ｎ型シリコン基板２０１の裏面には、パッシベーション膜２１１が形成されている。そして、ｐ型電極２０４はコンタクトホールを通じてｐ++型拡散領域２０２と、ｎ型電極２０５はコンタクトホール２０７を通じてｎ+型拡散領域２０３と接続している。２０９は、ｐ+型拡散領域ある。ｐ++型拡散領域２０２はｐ+型拡散領域２０９よりもｐ型ドーパント濃度の高い領域である。 A passivation film 211 is formed on the back surface of the n-type silicon substrate 201. The p-type electrode 204 is connected to the p ++ -type diffusion region 202 through the contact hole, and the n-type electrode 205 is connected to the n + -type diffusion region 203 through the contact hole 207. Reference numeral 209 denotes a p + -type diffusion region. The p ++ type diffusion region 202 is a region having a higher p type dopant concentration than the p + type diffusion region 209.
　図１０は、特許文献１に開示されている、図９に示す従来の裏面接合型太陽電池の製造方法の一例である。図１０に示すように模式的断面図を参照して説明する。 FIG. 10 shows an example of a method for manufacturing the conventional back junction solar cell shown in FIG. This will be described with reference to a schematic cross-sectional view as shown in FIG.
　まず、図１０（ａ）に示すように、ｎ型シリコン基板２０１の受光面および裏面の全面にそれぞれ、酸化シリコン膜などの第１拡散マスク２２１を形成する。 First, as shown in FIG. 10A, a first diffusion mask 221 such as a silicon oxide film is formed on the entire light receiving surface and back surface of an n-type silicon substrate 201, respectively.
　次に、図１０（ｂ）に示すように、ｎ型シリコン基板２０１の裏面の第１拡散マスク２２１上に第１拡散マスク２２１をエッチングすることが可能な成分を含有するエッチングペースト２２４を所定の形状に印刷する。その後、エッチングペースト２２４の印刷後のｎ型シリコン基板２０１を加熱処理することによって、エッチングペースト２２４の印刷箇所に相当する第１拡散マスク２２１の部分を選択的に除去して第１拡散マスク２２１に開口部を形成する。 Next, as shown in FIG. 10B, an etching paste 224 containing a component capable of etching the first diffusion mask 221 on the first diffusion mask 221 on the back surface of the n-type silicon substrate 201 is predetermined. Print in shape. Thereafter, the n-type silicon substrate 201 after the printing of the etching paste 224 is heat-treated, thereby selectively removing the portion of the first diffusion mask 221 corresponding to the printing location of the etching paste 224 to form the first diffusion mask 221. An opening is formed.
　次に、図１０（ｃ）に示すように、第１拡散マスク２２１に形成された開口部から露出したｎ型シリコン基板２０１の裏面にたとえばＢＢｒ3などのｐ型ドーパントガス２３１を接触させることによってｐ型ドーパントを拡散させてｐ++型拡散領域２０２を形成する。その後、ｎ型シリコン基板２０１の受光面および裏面の第１拡散マスク２２１をそれぞれ除去する。 Next, as shown in FIG. 10C, a p-type dopant gas 231 such as BBr 3 is brought into contact with the back surface of the n-type silicon substrate 201 exposed from the opening formed in the first diffusion mask 221. A p ++ type diffusion region 202 is formed by diffusing the p type dopant. Thereafter, the first diffusion mask 221 on the light receiving surface and the back surface of the n-type silicon substrate 201 is removed.
　次に、図１０（ｄ）に示すように、ｎ型シリコン基板２０１の受光面および裏面の全面にそれぞれ第２拡散マスク２２２を形成する。その後、ｎ型シリコン基板２０１の裏面のｐ++型拡散領域２０２に対応する領域を包含する第２拡散マスク２２２上の領域にエッチングペースト２２４を印刷する。その後、エッチングペースト２２４の印刷後のｎ型シリコン基板２０１を再度加熱処理することによって、エッチングペースト２２４の印刷箇所に相当する第２拡散マスク２２２の部分を選択的に除去して第２拡散マスク２２２に開口部を形成する。 Next, as shown in FIG. 10D, a second diffusion mask 222 is formed on the entire light receiving surface and back surface of the n-type silicon substrate 201, respectively. Thereafter, an etching paste 224 is printed on a region on the second diffusion mask 222 including a region corresponding to the p ++ type diffusion region 202 on the back surface of the n-type silicon substrate 201. Thereafter, the n-type silicon substrate 201 after the printing of the etching paste 224 is heated again, so that the portion of the second diffusion mask 222 corresponding to the printing location of the etching paste 224 is selectively removed and the second diffusion mask 222 is removed. An opening is formed in
　次に、図１０（ｅ）に示すように、第２拡散マスク２２２に形成された開口部から露出したｎ型シリコン基板２０１の裏面にたとえばＢＢｒ3などのｐ型ドーパントガス２３１を再度接触させることによってｐ型ドーパントを拡散させてｐ++型拡散領域２０２の周囲にｐ+型拡散領域２０９を形成する。ここで、ｐ++型拡散領域２０２はｐ+型拡散領域２０９よりもｐ型ドーパント濃度の高い領域とする。その後、ｎ型シリコン基板２０１の受光面および裏面の第２拡散マスク２２２をそれぞれ除去する。 Next, as shown in FIG. 10E, a p-type dopant gas 231 such as BBr 3 is brought into contact with the back surface of the n-type silicon substrate 201 exposed from the opening formed in the second diffusion mask 222 again. The p + type diffusion region 209 is formed around the p ++ type diffusion region 202 by diffusing the p type dopant. Here, the p ++ type diffusion region 202 is a region having a higher p type dopant concentration than the p + type diffusion region 209. Thereafter, the second diffusion mask 222 on the light receiving surface and the back surface of the n-type silicon substrate 201 is removed.
　次に、図１０（ｆ）に示すように、ｎ型シリコン基板２０１の受光面および裏面の全面にそれぞれ第３拡散マスク２２３を形成する。その後、ｎ型シリコン基板２０１の裏面のｐ++型拡散領域２０２およびｐ+型拡散領域２０９に対応する領域以外の領域の第３拡散マスク２２３の一部に開口部を設けた後、たとえばＰＯＣｌ3などのｎ型ドーパントガス２３２を接触させることによってｎ型ドーパントを拡散させてｎ+型拡散領域２０３を形成する。その後、ｎ型シリコン基板２０１の受光面および裏面の第３拡散マスク２２３をそれぞれ除去する。 Next, as shown in FIG. 10F, a third diffusion mask 223 is formed on the entire light receiving surface and back surface of the n-type silicon substrate 201, respectively. Thereafter, an opening is provided in a part of the third diffusion mask 223 in a region other than the region corresponding to the p ++ type diffusion region 202 and the p + type diffusion region 209 on the back surface of the n-type silicon substrate 201, and then, for example, POCl The n + -type diffusion region 203 is formed by diffusing the n-type dopant by bringing an n-type dopant gas 232 such as 3 into contact therewith. Thereafter, the third diffusion mask 223 on the light receiving surface and the back surface of the n-type silicon substrate 201 is removed.
　次に、図１０（ｇ）に示すように、ｎ型シリコン基板２０１の受光面をテクスチャエッチングしてテクスチャ構造２０８を形成した後に、ｎ型シリコン基板２０１の受光面のテクスチャ構造２０８上には反射防止膜２１０を形成するとともに、ｎ型シリコン基板２０１の裏面上にはパッシベーション膜２１１を形成する。 Next, as shown in FIG. 10 (g), the light-receiving surface of the n-type silicon substrate 201 is texture-etched to form the texture structure 208, and then reflected on the texture structure 208 of the light-receiving surface of the n-type silicon substrate 201. A protective film 210 is formed, and a passivation film 211 is formed on the back surface of the n-type silicon substrate 201.
　次に、図１０（ｈ）に示すように、ｎ型シリコン基板２０１の裏面のｐ++型拡散領域２０２の一部が露出するようにパッシベーション膜２１１の一部を除去してコンタクトホール２０６を形成するとともに、ｎ+型拡散領域２０３の一部が露出するようにパッシベーション膜２１１の一部を除去してコンタクトホール２０７を形成する。 Next, as shown in FIG. 10H, a part of the passivation film 211 is removed so that a part of the p ++ type diffusion region 202 on the back surface of the n-type silicon substrate 201 is exposed, and a contact hole 206 is formed. At the same time, a part of the passivation film 211 is removed so that a part of the n + -type diffusion region 203 is exposed, and a contact hole 207 is formed.
　最後に、図１０（ｉ）に示すように、ｎ型シリコン基板２０１の裏面のパッシベーション膜２１１に形成されたコンタクトホール２０６を通してｐ++型拡散領域２０２に接するｐ型電極２０４を形成するとともに、ｎ型シリコン基板２０１の裏面のパッシベーション膜２１１に形成されたコンタクトホール２０７を通してｎ+型拡散領域２０３に接するｎ型電極２０５を形成する。以上により、裏面接合型太陽電池２００が作製される。 Finally, as shown in FIG. 10 (i), a p-type electrode 204 is formed in contact with the p ++ type diffusion region 202 through a contact hole 206 formed in the passivation film 211 on the back surface of the n-type silicon substrate 201. An n-type electrode 205 in contact with the n + -type diffusion region 203 is formed through a contact hole 207 formed in the passivation film 211 on the back surface of the n-type silicon substrate 201. Thus, the back junction solar cell 200 is manufactured.
特開２００８－１８６９２７号公報JP 2008-186927 A
　しかしながら、特許文献１に記載の裏面接合型太陽電池の製造方法においては、ｐ++型拡散領域、ｐ+型拡散領域、およびｎ+型拡散領域をそれぞれ個別の工程で形成し、さらに各拡散領域の形成工程ごとに拡散マスクを形成する必要があったため、工数が多くなり、裏面接合型太陽電池を効率的に製造することができないという問題があった。 However, in the method of manufacturing the back junction solar cell described in Patent Document 1, the p ++ type diffusion region, the p + type diffusion region, and the n + type diffusion region are formed in separate steps, and each diffusion is further performed. Since it was necessary to form a diffusion mask for each region forming step, there was a problem that man-hours were increased and a back junction solar cell could not be produced efficiently.
　本発明は、上記の問題に鑑みてなされたものであり、その目的は、工程数を低減して、効率的に製造することが可能な太陽電池の製造方法を提供することにある。 The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a solar cell that can be efficiently manufactured by reducing the number of steps.
　本発明の太陽電池の製造方法は、第１導電型のシリコン基板の一方の面に、高濃度第１導電型半導体領域、高濃度第２導電型半導体領域及び低濃度第２導電型半導体領域を形成する太陽電池の製造方法であって、高濃度第１導電型半導体領域となる領域及び低濃度第２導電型半導体領域となる領域に、第１導電型の不純物を拡散させる第１工程と、高濃度第２導電型半導体領域となる領域及び低濃度第２導電型半導体領域となる領域に、第２導電型の不純物を拡散させる第２工程を、この順に有し、低濃度第２導電型半導体領域は、第２導電型の不純物が第１導電型の不純物より優位であるように拡散されている。 In the method for manufacturing a solar cell of the present invention, a high-concentration first conductive semiconductor region, a high-concentration second conductive semiconductor region, and a low-concentration second conductive semiconductor region are formed on one surface of a first conductive type silicon substrate. A method for manufacturing a solar cell to be formed, the first step of diffusing impurities of a first conductivity type into a region to be a high concentration first conductivity type semiconductor region and a region to be a low concentration second conductivity type semiconductor region; A second step of diffusing impurities of the second conductivity type into the region to be the high concentration second conductivity type semiconductor region and the region to be the low concentration second conductivity type semiconductor region is provided in this order. The semiconductor region is diffused so that the second conductivity type impurity is superior to the first conductivity type impurity.
　ここで、本発明の太陽電池の製造方法は、太陽電池は、裏面電極型太陽電池であってもよい。 Here, in the method for manufacturing a solar cell of the present invention, the solar cell may be a back electrode type solar cell.
　また、本発明の太陽電池の製造方法は、第１工程の後に、シリコン基板に熱酸化法により酸化シリコン膜を形成する工程と、酸化シリコン膜をエッチングすることにより、酸化シリコン膜を高濃度第１導電型半導体領域上のみに残す工程とをさらに備えてもよい。 In addition, the method for manufacturing a solar cell of the present invention includes a step of forming a silicon oxide film on a silicon substrate by a thermal oxidation method after the first step, and etching the silicon oxide film so that the silicon oxide film has a high concentration. And a step of leaving only on the one conductivity type semiconductor region.
　また、本発明の太陽電池の製造方法は、第１工程において、高濃度第１導電型半導体領域は、第１導電型の不純物を含むドーピングペーストを塗布して熱処理により形成してもよい。 In the solar cell manufacturing method of the present invention, in the first step, the high-concentration first conductive type semiconductor region may be formed by applying a doping paste containing a first conductive type impurity and performing heat treatment.
　また、本発明の太陽電池の製造方法は、低濃度第２導電型半導体領域となる領域は、ドーピングペーストからのアウトディフュージョンにより、ドーパントがドーピングされてもよい。 Also, in the method for manufacturing a solar cell of the present invention, the region that becomes the low-concentration second conductivity type semiconductor region may be doped with a dopant by out-diffusion from a doping paste.
　本発明の太陽電池は、第１導電型のシリコン基板の裏面に形成された、第１導電型半導体領域、及び第２導電型半導体領域と、シリコン基板の裏面上に形成された裏面パッシベーション膜と、第１導電型半導体領域に接して形成された第１電極と、第２導電型半導体領域に接して形成された第２電極とを有し、第２導電型半導体領域は、高濃度第２導電型半導体領域と低濃度第２導電型半導体領域とを有し、低濃度第２導電型半導体領域は裏面パッシベーション膜に接し、第２電極は、高濃度第２導電型半導体領域に接している。 The solar cell of the present invention includes a first conductivity type semiconductor region and a second conductivity type semiconductor region formed on the back surface of the first conductivity type silicon substrate, and a back surface passivation film formed on the back surface of the silicon substrate. , A first electrode formed in contact with the first conductive type semiconductor region, and a second electrode formed in contact with the second conductive type semiconductor region, wherein the second conductive type semiconductor region has a second high concentration. A conductive semiconductor region and a low-concentration second conductive semiconductor region; the low-concentration second conductive semiconductor region is in contact with the back surface passivation film; and the second electrode is in contact with the high-concentration second conductive semiconductor region. .
　ここで、本発明の太陽電池は、低濃度第２導電型半導体領域は、高濃度第２導電型半導体領域より面積が大きくてもよい。 Here, in the solar cell of the present invention, the low concentration second conductivity type semiconductor region may have a larger area than the high concentration second conductivity type semiconductor region.
　また、本発明の太陽電池は、第１導電型半導体領域は、第２導電型半導体領域と接していてもよい。 In the solar cell of the present invention, the first conductivity type semiconductor region may be in contact with the second conductivity type semiconductor region.
　また、本発明の太陽電池は、第１導電型半導体領域と接している第２導電型半導体領域は、高濃度第２導電型半導体領域であってもよい。 In the solar cell of the present invention, the second conductivity type semiconductor region in contact with the first conductivity type semiconductor region may be a high concentration second conductivity type semiconductor region.
　また、本発明の太陽電池は、低濃度第２導電型半導体領域は、高濃度第２導電型半導体領域で囲まれていてもよい。 In the solar cell of the present invention, the low concentration second conductivity type semiconductor region may be surrounded by the high concentration second conductivity type semiconductor region.
　また、本発明の太陽電池は、高濃度第２導電型半導体領域は、第２電極に接する領域と、第１導電型半導体領域に接する領域とに分離していてもよい。 In the solar cell of the present invention, the high-concentration second conductivity type semiconductor region may be separated into a region in contact with the second electrode and a region in contact with the first conductivity type semiconductor region.
　本発明によれば、第１工程で、第１導電型の低濃度の不純物を拡散させ、第２工程で、第２導電型の不純物を拡散させることで、低濃度第２導電型半導体領域を形成することができるため、低濃度第２導電型半導体領域の形成工程をさらに設ける必要はなく、拡散マスクの形成工程も低減することができるので、工程数を削減して、効率的に製造することが可能な太陽電池の製造方法を提供することができる。 According to the present invention, the low-concentration second conductivity type semiconductor region is formed by diffusing the low-concentration impurity of the first conductivity type in the first step and diffusing the second-conductivity type impurity in the second step. Since it can be formed, it is not necessary to further provide a step of forming the low-concentration second conductivity type semiconductor region, and the step of forming the diffusion mask can also be reduced. Therefore, the number of steps can be reduced and manufacturing can be performed efficiently. The manufacturing method of the solar cell which can be provided can be provided.
本発明の太陽電池の一例の模式的な裏面図である。It is a typical back view of an example of the solar cell of this invention. 本発明の太陽電池の一例の模式的な断面構成図である。It is a typical section lineblock diagram of an example of the solar cell of the present invention. 本発明の太陽電池の一例の裏面側から見た半導体領域の模式的な図である。It is the typical figure of the semiconductor region seen from the back side of an example of the solar cell of the present invention. 図３の一部を拡大した模式図である。It is the schematic diagram which expanded a part of FIG. 本発明の太陽電池の製造方法の一例を示す模式的な図である。It is a schematic diagram which shows an example of the manufacturing method of the solar cell of this invention. 本発明の太陽電池の他の一例の模式的な断面構成図である。It is a typical cross-section figure of another example of the solar cell of this invention. 本発明の太陽電池の他の一例の裏面側から見た半導体領域の模式的な図である。It is the typical figure of the semiconductor region seen from the back surface side of another example of the solar cell of this invention. 図７の一部を拡大した模式図である。It is the schematic diagram which expanded a part of FIG. 従来技術の裏面接合型太陽電池の一例の模式的な断面構成図である。It is a typical cross-section block diagram of an example of the back junction type solar cell of a prior art. 従来技術の裏面接合型太陽電池の製造方法の一例を示す模式的な図である。It is a schematic diagram which shows an example of the manufacturing method of the back surface joining type solar cell of a prior art.
　＜実施の形態１＞
　図１、図２は、受光面と反対側の面である裏面にのみ電極を形成した本発明の一例である実施の形態１の太陽電池を表す図である。図１は、太陽電池１の裏面側から見た図であり、太陽電池１の裏面には、第１導電型のｎ型半導体領域に接しているｎ型用電極２、及び第２導電型のｐ型半導体領域に接しているｐ型用電極３がそれぞれ帯状に交互に形成されている。 <Embodiment 1>
FIG. 1 and FIG. 2 are diagrams showing the solar cell of Embodiment 1 which is an example of the present invention in which electrodes are formed only on the back surface which is the surface opposite to the light receiving surface. FIG. 1 is a view as seen from the back surface side of the solar cell 1. On the back surface of the solar cell 1, the n-type electrode 2 in contact with the first conductivity type n-type semiconductor region and the second conductivity type are shown. The p-type electrodes 3 in contact with the p-type semiconductor region are alternately formed in a strip shape.
　図２（ａ）は、図１で示したＡ－Ａ′の断面を表す図であり、図２（ｂ）は、図２（ａ）に示す太陽電池１の受光面の一部の模式的な拡大断面図であり、図２（ｃ）は、ｎ型シリコン基板４の裏面の凹凸を図解する模式的な拡大断面図である。 2A is a diagram showing a cross section taken along line AA ′ shown in FIG. 1, and FIG. 2B is a schematic view of a part of the light receiving surface of the solar cell 1 shown in FIG. 2A. FIG. 2C is a schematic enlarged cross-sectional view illustrating the unevenness of the back surface of the n-type silicon substrate 4.
　本実施の形態の太陽電池１では、ｐ型半導体領域に、ｐ++領域１０とｐ+領域５１を有する。以下に、本実施の形態の太陽電池１の構造を詳細に述べる。 In solar cell 1 of the present embodiment, p ++ region 10 and p + region 51 are provided in the p-type semiconductor region. Below, the structure of the solar cell 1 of this Embodiment is described in detail.
　単結晶シリコン基板であるｎ型シリコン基板４の受光面にはテクスチャ構造である凹凸形状５が形成されている。この凹凸は数μｍ～数十μｍである。受光面全面には受光面拡散層６であるｎ+層がＦＳＦ（Ｆｒｏｎｔ　Ｓｕｒｆａｃｅ　Ｆｉｅｌｄ）層として形成され、受光面拡散層６上には受光面パッシベーション膜１３が形成されている。さらに、受光面パッシベーション膜１３上には反射防止膜１２が形成されている。ここで、受光面パッシベーション膜１３は酸化シリコン膜で、その膜厚は５ｎｍ以上２００ｎｍ以下が好ましく、より好ましくは５ｎｍ以上６０ｎｍ以下である。また、反射防止膜１２はチタン酸化物からなる膜で形成されている。膜厚は、たとえば、１０ｎｍ以上４００ｎｍ以下である。さらに、反射防止膜１２にはリン酸化物が含まれており、リンの濃度はリン酸化物として１５ｗｔ％以上３５ｗｔ％以下含有することが好ましい。なお、リン酸化物として反射防止膜１２の１５ｗｔ％以上３５ｗｔ％以下含まれるとは、反射防止膜１２中のリン酸化物の含有量が反射防止膜１２全体の１５ｗｔ％以上３５ｗｔ％以下であることを意味する。 An uneven shape 5 having a texture structure is formed on the light receiving surface of an n-type silicon substrate 4 which is a single crystal silicon substrate. The unevenness is several μm to several tens μm. An n + layer, which is a light receiving surface diffusion layer 6, is formed as an FSF (Front Surface Field) layer on the entire light receiving surface, and a light receiving surface passivation film 13 is formed on the light receiving surface diffusion layer 6. Further, an antireflection film 12 is formed on the light receiving surface passivation film 13. Here, the light-receiving surface passivation film 13 is a silicon oxide film, and the film thickness is preferably 5 nm or more and 200 nm or less, more preferably 5 nm or more and 60 nm or less. The antireflection film 12 is formed of a film made of titanium oxide. The film thickness is, for example, 10 nm or more and 400 nm or less. Further, the antireflection film 12 contains a phosphorus oxide, and the phosphorus concentration is preferably 15 wt% or more and 35 wt% or less as the phosphorus oxide. The phrase “phosphorus oxide containing 15 wt% or more and 35 wt% or less of the antireflection film 12” means that the content of phosphorus oxide in the antireflection film 12 is 15 wt% or more and 35 wt% or less of the entire antireflection film 12. Means.
　また、ｎ型シリコン基板４の裏面には、ｎ型シリコン基板４側から、第２裏面パッシベーション膜８、第１裏面パッシベーション膜１１の２層からなる裏面パッシベーション膜１４が形成されている。ｎ型シリコン基板４の裏面において、ｎ型半導体領域とｐ型半導体領域とが形成され、ｎ型半導体領域にはｎ++領域９が、ｐ型半導体領域には、低濃度ｐ型半導体領域であるｐ+領域５１、及び高濃度ｐ型半導体領域であるｐ++領域１０が形成されており、ｎ型半導体領域とｐ型半導体領域とは隣接している。ｐ+領域５１はｐ++領域１０で囲まれており、ｐ+領域５１は、ｐ++領域１０よりも面積が大きい。なお、低濃度ｐ型半導体領域は、高濃度ｐ型半導体領域よりもｐ型不純物濃度が低い。ｎ++領域９の表面は、ｎ++領域９以外の表面よりも凹状になっている。図２に示す凹状の深さｄは数十ｎｍである。そして、ｎ++領域９にはｎ型用電極２が形成され、ｐ++領域１０にはｐ型用電極３が形成されている。 Further, on the back surface of the n-type silicon substrate 4, a back surface passivation film 14 composed of two layers of a second back surface passivation film 8 and a first back surface passivation film 11 is formed from the n-type silicon substrate 4 side. On the back surface of the n-type silicon substrate 4, an n-type semiconductor region and a p-type semiconductor region are formed, an n ++ region 9 is formed in the n-type semiconductor region, and a low-concentration p-type semiconductor region is formed in the p-type semiconductor region. A p + region 51 and a p ++ region 10 which is a high concentration p-type semiconductor region are formed, and the n-type semiconductor region and the p-type semiconductor region are adjacent to each other. The p + region 51 is surrounded by the p ++ region 10, and the p + region 51 has a larger area than the p ++ region 10. Note that the low-concentration p-type semiconductor region has a lower p-type impurity concentration than the high-concentration p-type semiconductor region. the surface of the n ++ region 9 has a concave than the surface other than the n ++ region 9. The concave depth d shown in FIG. 2 is several tens of nm. An n-type electrode 2 is formed in the n ++ region 9, and a p-type electrode 3 is formed in the p ++ region 10.
　ここで、ｎ型シリコン基板４に対してエミッタ領域となるｐ型半導体領域において、低濃度ｐ型半導体領域であるｐ+領域５１は、裏面パッシベーション膜１４と接しているので、裏面パッシベーション膜１４との界面でのキャリアの再結合を抑えパッシベーション効果を向上させることができ、ｐ型用電極３は、ｐ型半導体領域の高濃度ｐ型半導体領域であるｐ++領域１０と接しているので、直列抵抗を低減することができるので、太陽電池の特性を向上させることができる。また、より高い短絡電流を得るために、ｎ型シリコン基板に対して、エミッタ領域となるｐ型半導体領域の合計面積のほうが、ｎ型半導体領域の合計面積よりも大きい。 Here, in the p-type semiconductor region serving as an emitter region with respect to the n-type silicon substrate 4, the p + region 51, which is a low-concentration p-type semiconductor region, is in contact with the back surface passivation film 14. Since the recombination of carriers at the interface is suppressed and the passivation effect is improved, the p-type electrode 3 is in contact with the p ++ region 10 which is a high-concentration p-type semiconductor region of the p-type semiconductor region. Since the series resistance can be reduced, the characteristics of the solar cell can be improved. In order to obtain a higher short-circuit current, the total area of the p-type semiconductor region serving as the emitter region is larger than the total area of the n-type semiconductor region with respect to the n-type silicon substrate.
　なお、ｎ型不純物濃度は、ｎ型シリコン基板、受光面拡散層であるｎ+層、ｎ++領域の順に高くなり、ｐ型不純物濃度は、ｐ+領域、ｐ++領域の順に高くなる。 The n-type impurity concentration increases in the order of the n-type silicon substrate, the light-receiving surface diffusion layer n + layer, and the n ++ region, and the p-type impurity concentration increases in the order of the p + region and the p ++ region. .
　また、ｎ型半導体領域とｐ型半導体領域とを隣接して形成、すなわち、ｎ++領域９とｐ++領域１０とを隣接して形成することより、太陽電池１に逆方向のバイアスがかかったとき、部分的に電圧がかかることがなく、局所的な逆方向電流による発熱をさけることができる。さらに、ｎ++領域に対し、ｐ+領域でなくｐ++領域を隣接して形成しているため、太陽電池１に逆方向のバイアスがかかったとき、逆方向電流が流れやすくなる。また、ｎ++領域９上の裏面パッシベーション膜１４と、ｐ++領域１０上またはｐ+領域５１上との裏面パッシベーション膜１４とに膜厚差があり、ｎ++領域９上の裏面パッシベーション膜１４の方が厚くなっている。 Further, the n-type semiconductor region and the p-type semiconductor region are formed adjacent to each other, that is, the n ++ region 9 and the p ++ region 10 are formed adjacent to each other, so that a reverse bias is applied to the solar cell 1. When applied, voltage is not partially applied, and heat generation due to local reverse current can be avoided. Further, n ++ region to, because it formed adjacent the p ++ region not p + region, when the reverse bias is applied to the solar cell 1, a reverse current flows easily. Further, there is a film thickness difference between the back surface passivation film 14 on the n ++ region 9 and the back surface passivation film 14 on the p ++ region 10 or the p + region 51, and the back surface passivation on the n ++ region 9. The film 14 is thicker.
　さらに、ｎ型シリコン基板４の裏面の最も外側には、電極が形成されていない、すなわち、電極に接触していない半導体領域であるｐ+領域７１とｐ++領域５２とを形成している。 Furthermore, on the outermost outer surface of the back surface of the n-type silicon substrate 4, the p + region 71 and the p ++ region 52, which are semiconductor regions that are not formed with the electrodes, that is, are not in contact with the electrodes, are formed. .
　図３は、太陽電池１からｎ型用電極２とｐ型用電極３とを除去し、さらに裏面パッシベーション膜１４を除去して、ｎ型シリコン基板４を裏面側から見た図である。また、図４は、図３の一部を拡大した模式図である。 FIG. 3 is a view of the n-type silicon substrate 4 as seen from the back side, with the n-type electrode 2 and the p-type electrode 3 removed from the solar cell 1 and the back surface passivation film 14 removed. FIG. 4 is an enlarged schematic view of a part of FIG.
　ｎ型シリコン基板４の裏面の外周縁には、上記に示した電極に接触していない半導体領域であるｐ+領域７１とｐ++領域５２とを、それぞれ形成している（外周縁に形成した、電極に接触していない半導体領域を、以下「外周縁半導体領域」という。）。ｎ++領域９の周囲に、ｎ++領域９とは導電型の異なる上記の外周縁半導体領域を形成することで、太陽電池１のエッジ部等に半導体領域ができたとしても、その半導体領域と、ｎ++領域９、ｐ++領域１０及びｐ+領域５１とは、電気的に分離できている。また、外周縁半導体領域があるので、太陽電池１に逆方向のバイアスがかかったとき、外周縁を通して発生する逆方向電流を抑えることができる。また、外周縁半導体領域において大きな面積を占めるｐ+領域７１のｐ型不純物濃度を、ｐ++とせずｐ+とすることにより、裏面パッシベーション膜１４との界面でのキャリアの再結合を抑えパッシベーション効果を向上させることができる。図３では、ｎ++領域９は全てつながって１つの半導体領域を形成している。さらにまた、太陽電池の各辺の最も外側の電極が同じ導電型なので、形成した電極を回転対称構造にすることが可能になり、太陽電池を複数並べる太陽電池モジュールを作製する際、例えば、図１に示す太陽電池の上下が反対になっても問題ない。 On the outer peripheral edge of the back surface of the n-type silicon substrate 4, a p + region 71 and a p ++ region 52, which are semiconductor regions not in contact with the electrodes described above, are formed (formed on the outer peripheral edge). The semiconductor region that is not in contact with the electrode is hereinafter referred to as an “outer peripheral semiconductor region”). around the n ++ region 9 and the n ++ region 9 by forming a different said outer peripheral edge semiconductor region of a conductivity type, even could semiconductor region at the edge portion or the like of the solar cell 1, the semiconductor The region and the n ++ region 9, the p ++ region 10 and the p + region 51 can be electrically separated. Moreover, since there is an outer peripheral semiconductor region, reverse current generated through the outer peripheral edge when the reverse bias is applied to the solar cell 1 can be suppressed. Further, by setting the p-type impurity concentration of the p + region 71 occupying a large area in the outer peripheral semiconductor region to p + instead of p ++ , the recombination of carriers at the interface with the back surface passivation film 14 is suppressed. The effect can be improved. In FIG. 3, the n ++ regions 9 are all connected to form one semiconductor region. Furthermore, since the outermost electrode on each side of the solar cell has the same conductivity type, it is possible to make the formed electrode a rotationally symmetric structure, and when producing a solar cell module in which a plurality of solar cells are arranged, for example, FIG. There is no problem even if the solar cell shown in FIG.
　以下に、本発明の太陽電池の製造方法の一例を示す。
　図５は、図１、および図２に示す本発明の太陽電池の製造方法の一例である。図５に示すように模式的断面図を参照して説明する。 Below, an example of the manufacturing method of the solar cell of this invention is shown.
FIG. 5 is an example of a method for manufacturing the solar cell of the present invention shown in FIGS. 1 and 2. This will be described with reference to a schematic sectional view as shown in FIG.
　まず、図５（ａ）に示すように、１００μｍ厚のｎ型シリコン基板４の受光面となる面（以下「ｎ型シリコン基板の受光面」という。）の反対側の面である裏面（以下「ｎ型シリコン基板の裏面」という。）に、窒化シリコン膜等のテクスチャマスク２１をＣＶＤ法、またはスパッタ法等で形成する。その後、図５（ｂ）に示すように、ｎ型シリコン基板４の受光面にテクスチャ構造である凹凸形状５をエッチングにより形成する。エッチングは、たとえば、水酸化ナトリウムまたは水酸化カリウムなどのアルカリ水溶液にイソプロピルアルコールを添加し、７０℃以上８０℃以下に加熱した溶液により行われる。 First, as shown in FIG. 5A, the back surface (hereinafter referred to as the light receiving surface of the n-type silicon substrate) opposite to the surface serving as the light receiving surface of the n-type silicon substrate 4 having a thickness of 100 μm (hereinafter referred to as “light receiving surface of n-type silicon substrate”) A texture mask 21 such as a silicon nitride film is formed on the “back surface of the n-type silicon substrate” by a CVD method or a sputtering method. Thereafter, as shown in FIG. 5B, the uneven shape 5 having a texture structure is formed on the light receiving surface of the n-type silicon substrate 4 by etching. Etching is performed, for example, with a solution in which isopropyl alcohol is added to an alkaline aqueous solution such as sodium hydroxide or potassium hydroxide and heated to 70 ° C. or higher and 80 ° C. or lower.
　次に、図５（ｃ）を用いて次工程を説明する。図５（ｃ）は、ｎ型シリコン基板４の裏面側が上となっている。図５（ｃ）に示すように、ｎ型シリコン基板４の裏面に形成したテクスチャマスク２１を除去後、ｎ型シリコン基板４の受光面に酸化シリコン膜等の拡散マスク２２を形成する。その後、ｎ型シリコン基板４の裏面において、ｐ++領域１０及びｐ++領域５２を形成しようとする領域に、例えば、溶剤、増粘剤および酸化シリコン前駆体を少なくとも含むマスキングペーストをインクジェット、またはスクリーン印刷等で塗布し、熱処理により拡散マスク２３を形成する。次に、例えば、溶剤、増粘剤、酸化シリコン前駆体およびｎ型不純物であるリンを少なくとも含むドーピングペースト３１をインクジェット、またはスクリーン印刷等で塗布し形成する。そして、熱処理によって、ｎ型シリコン基板４の裏面に、高濃度ｎ型半導体領域であるｎ++領域９を形成し、ドーピングペースト３１からのアウトディフュージョンにより、ｎ++領域９よりもｎ型不純物濃度が低い低濃度ｎ型半導体領域であるｎ+領域３２を形成する。 Next, the next step will be described with reference to FIG. In FIG. 5C, the back side of the n-type silicon substrate 4 is on the top. As shown in FIG. 5C, after removing the texture mask 21 formed on the back surface of the n-type silicon substrate 4, a diffusion mask 22 such as a silicon oxide film is formed on the light-receiving surface of the n-type silicon substrate 4. Thereafter, on the back surface of the n-type silicon substrate 4, for example, a masking paste including at least a solvent, a thickener, and a silicon oxide precursor is jetted in a region where the p ++ region 10 and the p ++ region 52 are to be formed. Alternatively, it is applied by screen printing or the like, and the diffusion mask 23 is formed by heat treatment. Next, for example, a doping paste 31 containing at least a solvent, a thickener, a silicon oxide precursor, and phosphorus as an n-type impurity is applied and formed by ink jet or screen printing. Then, an n ++ region 9, which is a high concentration n type semiconductor region, is formed on the back surface of the n type silicon substrate 4 by heat treatment, and an n type impurity more than the n ++ region 9 by out diffusion from the doping paste 31. An n + region 32 that is a low concentration n-type semiconductor region having a low concentration is formed.
　次に、図５（ｄ）に示すように、熱処理後のドーピングペースト３１、ｎ型シリコン基板４に形成した拡散マスク２２、２３、および拡散マスク２２、２３にリンが拡散して形成されたガラス層をフッ化水素酸処理により除去した後、酸素または水蒸気による熱酸化を行い、酸化シリコン膜２４を形成する。この際、図５（ｄ）に示すように、ｎ型シリコン基板４の裏面のｎ++領域９上の酸化シリコン膜２４が厚くなる。本実施の形態では、９００℃で水蒸気による熱酸化を行い、ｎ++領域９上以外の酸化シリコン膜２４の膜厚が７０ｎｍ以上９０ｎｍ以下、ｎ++領域９上の酸化シリコン膜２４の膜厚は２５０ｎｍ以上３５０ｎｍ以下になった。ここで、熱酸化前のｎ++領域９のリンの表面濃度は、５×１０19／ｃｍ3以上であり、熱酸化の処理温度の範囲としては、たとえば、酸素による熱酸化で８００℃以上１０００℃以下、水蒸気による熱酸化で８００℃以上９５０℃以下である。 Next, as shown in FIG. 5D, the doping paste 31 after heat treatment, the diffusion masks 22 and 23 formed on the n-type silicon substrate 4, and the glass formed by diffusing phosphorus in the diffusion masks 22 and 23 After removing the layer by hydrofluoric acid treatment, thermal oxidation with oxygen or water vapor is performed to form the silicon oxide film 24. At this time, as shown in FIG. 5D, the silicon oxide film 24 on the n ++ region 9 on the back surface of the n-type silicon substrate 4 becomes thick. In the present embodiment, thermal oxidation is performed with water vapor at 900 ° C., and the film thickness of the silicon oxide film 24 other than on the n ++ region 9 is 70 nm or more and 90 nm or less, and the film of the silicon oxide film 24 on the n ++ region 9 The thickness became 250 nm or more and 350 nm or less. Here, the surface concentration of phosphorus in the n ++ region 9 before thermal oxidation is 5 × 10 19 / cm 3 or higher, and the processing temperature range of thermal oxidation is, for example, 800 ° C. or higher by thermal oxidation with oxygen. 1000 ° C. or less and 800 ° C. or more and 950 ° C. or less by thermal oxidation with water vapor.
　熱酸化時に、酸化シリコン膜の厚さが異なる理由は次の通りである。熱酸化による酸化シリコン膜の成長速度は、シリコン基板に拡散されている不純物の種類と濃度により異なる。特にｎ型不純物濃度が高い場合は、成長速度が速くなる。このため、ｎ型シリコン基板４よりもｎ型不純物濃度が高いｎ++領域９上の酸化シリコン膜２４の膜厚の方がｎ型シリコン基板４上よりも厚くなる。酸化シリコン膜２４は、熱酸化時にシリコンと酸素とが結びつくことで形成されるので、ｎ++領域９の表面は、ｎ++領域９が形成されていない領域の表面よりも凹状になる。 The reason why the thicknesses of the silicon oxide films are different during thermal oxidation is as follows. The growth rate of the silicon oxide film by thermal oxidation differs depending on the type and concentration of impurities diffused in the silicon substrate. In particular, when the n-type impurity concentration is high, the growth rate is increased. Therefore, the thickness of the silicon oxide film 24 on the n ++ region 9 having a higher n-type impurity concentration than the n-type silicon substrate 4 is thicker than that on the n-type silicon substrate 4. Silicon oxide film 24 is so formed by silicon and oxygen is linked at the time of thermal oxidation, the surface of the n ++ region 9 becomes concave than the surface of the region n ++ region 9 is not formed.
　次に、図５（ｅ）に示すように、ｎ型シリコン基板４の受光面の酸化シリコン膜２４および裏面のｎ++領域９上以外の酸化シリコン膜２４をエッチングにより除去する。裏面では、上記に示したように、酸化シリコン膜２４がｎ++領域９上に厚く形成されており、さらにｎ++領域９上の酸化シリコン膜２４とｎ++領域９上以外の酸化シリコン膜２４とのエッチングレートの差により、ｎ++領域９上だけ酸化シリコン膜２４が残るようにし、拡散マスクとして用いる。例えば、９００℃３０分の水蒸気による熱酸化で酸化シリコン膜２４を形成し、ｎ++領域９上以外の酸化シリコン膜２４を除去するためにフッ化水素酸処理をした場合、ｎ++領域９上の酸化シリコン膜２４の膜厚は１２０ｎｍ程度となる。なお、酸化シリコン膜２４を、ｐ++領域及びｐ+領域形成時のｎ++領域の拡散マスクとして使用するには、ｎ++領域９上とｎ++領域９上以外との酸化シリコン膜２４の膜厚差は、６０ｎｍ以上必要となる。 Next, as shown in FIG. 5E, the silicon oxide film 24 on the light-receiving surface of the n-type silicon substrate 4 and the silicon oxide film 24 other than on the n ++ region 9 on the back surface are removed by etching. The back side, as indicated above, the oxidation of other than the above silicon oxide film 24 and the n ++ region 9 on the silicon oxide film 24 is thickly formed on the n ++ region 9, further n ++ region 9 Due to the difference in etching rate with the silicon film 24, the silicon oxide film 24 remains only on the n ++ region 9, and is used as a diffusion mask. For example, when the silicon oxide film 24 is formed by thermal oxidation with water vapor at 900 ° C. for 30 minutes and hydrofluoric acid treatment is performed to remove the silicon oxide film 24 other than the n ++ region 9, the n ++ region The thickness of the silicon oxide film 24 on 9 is about 120 nm. In order to use the silicon oxide film 24 as a diffusion mask for the p ++ region and the n ++ region when forming the p + region, silicon oxide on the n ++ region 9 and other than on the n ++ region 9 is used. The film thickness difference of the film 24 is required to be 60 nm or more.
　さらに、ｎ型シリコン基板４の受光面に酸化シリコン膜等の拡散マスク２５を形成し、その後、ｎ型シリコン基板４の裏面に、有機性高分子にホウ素化合物を反応させたポリマーをアルコール系溶媒に溶解させた溶液を塗布し、乾燥後、熱処理により、ｐ型不純物であるボロンが拡散して、ｎ型シリコン基板４の裏面の酸化シリコン膜２４で覆われていない領域に、高濃度ｐ型半導体領域であるｐ++領域１０、ｐ++領域５２、低濃度ｐ型半導体領域であるｐ+領域５１、及び、外周縁半導体領域であるｐ+領域７１を形成する。この時、ｐ+領域５１、及び、ｐ+領域７１は、先に拡散させたｎ型不純物であるリンよりもｐ型不純物であるボロンが優位となり、ｐ型領域となる。ｎ+領域３２では、ｎ型不純物濃度がｎ型シリコン基板４より高いので、低濃度ｐ型半導体領域であるｐ+領域が形成される。よって、ｐ+領域とｐ++領域の形成は、ｎ+領域３２の有無によって１工程で行うことが可能となることから、工程数を低減することが可能になる。 Further, a diffusion mask 25 such as a silicon oxide film is formed on the light-receiving surface of the n-type silicon substrate 4, and then a polymer obtained by reacting a boron compound with an organic polymer is formed on the back surface of the n-type silicon substrate 4 with an alcohol solvent. After the solution dissolved in is applied and dried, boron, which is a p-type impurity, is diffused by heat treatment, and a high-concentration p-type is formed in a region not covered with the silicon oxide film 24 on the back surface of the n-type silicon substrate 4. A p ++ region 10 and a p ++ region 52 that are semiconductor regions, a p + region 51 that is a low-concentration p-type semiconductor region, and a p + region 71 that is an outer peripheral semiconductor region are formed. At this time, in the p + region 51 and the p + region 71, boron, which is a p-type impurity, is dominant over phosphorus, which is an n-type impurity previously diffused, and becomes a p-type region. In the n + region 32, since the n type impurity concentration is higher than that of the n type silicon substrate 4, a p + region which is a low concentration p type semiconductor region is formed. Therefore, the formation of the p + region and the p ++ region can be performed in one process depending on the presence / absence of the n + region 32, so that the number of processes can be reduced.
　次に、図５（ｆ）を用いて次工程を説明する。図５（ｆ）は、ｎ型シリコン基板４の受光面側が上となっている。図５（ｆ）に示すように、ｎ型シリコン基板４に形成した酸化シリコン膜２４、拡散マスク２５、および酸化シリコン膜２４、拡散マスク２５にボロンが拡散して形成されたガラス層をフッ化水素酸処理により除去する。その後、ｎ型シリコン基板４の裏面にたとえば厚さ５０ｎｍ以上１００ｎｍ以下の酸化シリコン膜等の拡散マスクを兼ねた第１裏面パッシベーション膜１１を、ＣＶＤ法により形成、またはＳＯＧ（スピンオングラス）を塗布し焼成することにより形成する。その後、ｎ型シリコン基板４の受光面に受光面拡散層６であるｎ+層および反射防止膜１２を形成するため、ｎ型シリコン基板４の受光面にリン化合物、チタンアルコキシドおよびアルコールを少なくとも含む混合液２７の塗布を行い、乾燥する。ここで、混合液２７のリン化合物としては五酸化リン、チタンアルコキシドとしてはテトライソプロピルチタネート、およびアルコールとしてはイソプロピルアルコールを用いる。 Next, the next step will be described with reference to FIG. In FIG. 5F, the light receiving surface side of the n-type silicon substrate 4 is on the top. As shown in FIG. 5F, the silicon oxide film 24 and the diffusion mask 25 formed on the n-type silicon substrate 4 and the glass layer formed by diffusing boron into the silicon oxide film 24 and the diffusion mask 25 are fluorinated. Remove by hydroacid treatment. Thereafter, a first back surface passivation film 11 that also serves as a diffusion mask such as a silicon oxide film having a thickness of 50 nm to 100 nm is formed on the back surface of the n-type silicon substrate 4 by a CVD method, or SOG (spin on glass) is applied. It is formed by firing. Thereafter, in order to form the n + layer as the light-receiving surface diffusion layer 6 and the antireflection film 12 on the light-receiving surface of the n-type silicon substrate 4, the light-receiving surface of the n-type silicon substrate 4 contains at least a phosphorus compound, titanium alkoxide, and alcohol. The mixed liquid 27 is applied and dried. Here, phosphorus pentoxide is used as the phosphorus compound of the mixed liquid 27, tetraisopropyl titanate is used as the titanium alkoxide, and isopropyl alcohol is used as the alcohol.
　次に、図５（ｇ）に示すように、熱処理によりｎ型不純物であるリンが拡散して受光面側全面に受光面拡散層６であるｎ+層および反射防止膜１２が形成される。この熱処理は、窒素雰囲気で行い、処理温度は、たとえば８５０℃以上１０００℃以下である。 Next, as shown in FIG. 5G, phosphorus, which is an n-type impurity, is diffused by heat treatment to form an n + layer as the light-receiving surface diffusion layer 6 and an antireflection film 12 over the entire light-receiving surface side. This heat treatment is performed in a nitrogen atmosphere, and the treatment temperature is, for example, 850 ° C. or higher and 1000 ° C. or lower.
　ｎ型シリコン基板４の裏面に酸化シリコン膜による第２裏面パッシベーション膜８を形成するため、酸素による熱酸化を行う。この際、ｎ型シリコン基板４の裏面に第２裏面パッシベーション膜８である酸化シリコン膜が形成されながら、図５（ｊ）に示すように、ｎ型シリコン基板４の受光面全面にも、酸化シリコン膜が形成される。この受光面全面に形成された酸化シリコン膜は、受光面拡散層６と反射防止膜１２との間に形成され、受光面パッシベーション膜１３となる。受光面拡散層６と反射防止膜１２との間に受光面パッシベーション膜１３が形成される理由としては、受光面の凹凸形状５の凹部における反射防止膜１２の膜厚が厚くなって反射防止膜１２にクラックが生じ、そのクラックが生じている箇所から酸素が入り込んで受光面パッシベーション膜１３である酸化シリコン膜が成長すると考えられる。また、受光面の凹凸形状５の凸部では反射防止膜１２の膜厚が薄いため、酸素が透過し、受光面パッシベーション膜である酸化シリコン膜が成長すると考えられる。さらに、ｎ型シリコン基板４の裏面と第１裏面パッシベーション膜１１との間に第２裏面パッシベーション膜８が形成される理由としては、ｎ型シリコン基板４の裏面の第１裏面パッシベーション膜１１はＣＶＤ法等で形成した膜であるため、第１裏面パッシベーション膜１１の内部に酸素が透過し、これにより、第２裏面パッシベーション膜８である酸化シリコン膜が成長すると考えられる。なお、受光面パッシベーション膜１３の厚さは、たとえば１００ｎｍ以上２００ｎｍ以下であり、第２裏面パッシベーション膜８の厚さは、たとえばｎ++領域９上においては３０ｎｍ以上１００ｎｍ以下であり、ｐ+領域上においては１０ｎｍ以上４０ｎｍ以下である。 In order to form a second back surface passivation film 8 made of a silicon oxide film on the back surface of the n-type silicon substrate 4, thermal oxidation with oxygen is performed. At this time, a silicon oxide film, which is the second back surface passivation film 8, is formed on the back surface of the n-type silicon substrate 4, and the entire light-receiving surface of the n-type silicon substrate 4 is oxidized as shown in FIG. A silicon film is formed. The silicon oxide film formed on the entire light receiving surface is formed between the light receiving surface diffusion layer 6 and the antireflection film 12 and becomes the light receiving surface passivation film 13. The reason why the light-receiving surface passivation film 13 is formed between the light-receiving surface diffusion layer 6 and the antireflection film 12 is that the film thickness of the antireflection film 12 in the concave portion of the concavo-convex shape 5 on the light receiving surface increases and the antireflection film It is considered that a crack is generated in 12 and oxygen enters from the portion where the crack is generated and a silicon oxide film which is the light-receiving surface passivation film 13 grows. Further, it is considered that oxygen is permeated and a silicon oxide film, which is a light-receiving surface passivation film, grows because the film thickness of the antireflection film 12 is thin at the convex portion of the uneven shape 5 on the light-receiving surface. Furthermore, the reason why the second back surface passivation film 8 is formed between the back surface of the n-type silicon substrate 4 and the first back surface passivation film 11 is that the first back surface passivation film 11 on the back surface of the n-type silicon substrate 4 is CVD. Since it is a film formed by a method or the like, it is considered that oxygen permeates into the first back surface passivation film 11, thereby growing a silicon oxide film as the second back surface passivation film 8. The thickness of the light-receiving surface passivation film 13 is, for example, at 100nm or 200nm or less, the thickness of the second back surface passivation film 8 is 30nm or more 100nm or less in the example n ++ region 9, p + region Above, it is 10 nm or more and 40 nm or less.
　また、第２裏面パッシベーション膜８と受光面パッシベーション膜１３との形成は、受光面拡散層６および反射防止膜１２を形成する熱処理に引き続き、ガスを切り替えて酸素による熱酸化を行うことによっても可能である。すなわち、受光面拡散層６であるｎ+層および反射防止膜１２を形成する熱処理と、受光面パッシベーション膜１３を形成する熱処理とを、一連の熱処理によって形成することにより、工程数を減らすことができる。 The second back surface passivation film 8 and the light receiving surface passivation film 13 can also be formed by performing thermal oxidation with oxygen by switching the gas following the heat treatment for forming the light receiving surface diffusion layer 6 and the antireflection film 12. It is. That is, the number of steps can be reduced by forming a heat treatment for forming the n + layer and the antireflection film 12 as the light-receiving surface diffusion layer 6 and a heat treatment for forming the light-receiving surface passivation film 13 by a series of heat treatments. it can.
　そして、受光面パッシベーション膜１３である酸化シリコン膜形成温度を８５０℃より高く、より好ましくは９００℃以上にすることで、太陽電池１の受光面側の再結合電流を低減することができ、太陽電池特性を向上させることができる。加えて、上記工程で形成された受光面拡散層でのシート抵抗値が、１００Ω／□以上２５０Ω／□未満であれば、太陽電池１の受光面側の再結合電流を低減することができ、太陽電池特性を向上させる傾向にある。上記シート抵抗値の範囲における太陽電池の反射防止膜に含有するリン酸化物の濃度は、１５ｗｔ％以上であった。なお、リン酸化物濃度が３５ｗｔ％を超えると、反射防止膜は白く変色することがある。 The recombination current on the light-receiving surface side of the solar cell 1 can be reduced by setting the silicon oxide film forming temperature as the light-receiving surface passivation film 13 to a temperature higher than 850 ° C., more preferably 900 ° C. or higher. Battery characteristics can be improved. In addition, if the sheet resistance value in the light-receiving surface diffusion layer formed in the above process is 100Ω / □ or more and less than 250Ω / □, the recombination current on the light-receiving surface side of the solar cell 1 can be reduced, It tends to improve the solar cell characteristics. The concentration of phosphorous oxide contained in the antireflection film of the solar cell in the range of the sheet resistance value was 15 wt% or more. Note that when the phosphorous oxide concentration exceeds 35 wt%, the antireflection film may turn white.
　次に、図５（ｈ）に示すように、ｎ型シリコン基板４の裏面側に形成されたｎ++領域９、ｐ++領域１０に電極を形成するため、ｎ型シリコン基板の裏面に形成された裏面パッシベーション膜１４にパターニングを行う。パターニングは、エッチングペーストをスクリーン印刷法などで塗布し加熱処理により行われる。その後、パターニング処理を行ったエッチングペーストは超音波洗浄し酸処理により除去する。ここで、エッチングペーストとしては、例えば、エッチング成分としてリン酸、フッ化水素、フッ化アンモニウムおよびフッ化水素アンモニウムからなる群から選択された少なくとも１種を含み、水、有機溶媒および増粘剤を含むものである。 Next, as shown in FIG. 5 (h), in order to form electrodes in the n ++ region 9 and the p ++ region 10 formed on the back surface side of the n type silicon substrate 4, the back surface of the n type silicon substrate is formed. Patterning is performed on the formed back surface passivation film 14. The patterning is performed by applying an etching paste by a screen printing method or the like and performing a heat treatment. Thereafter, the etching paste subjected to the patterning process is ultrasonically cleaned and removed by acid treatment. Here, the etching paste includes, for example, at least one selected from the group consisting of phosphoric acid, hydrogen fluoride, ammonium fluoride, and ammonium hydrogen fluoride as an etching component, and includes water, an organic solvent, and a thickener. Is included.
　次に、図５（ｉ）に示すように、ｎ型シリコン基板４の裏面の所定の位置に銀ペーストをスクリーン印刷法により塗布し、乾燥する。その後、焼成により、ｎ++領域９にはｎ型用電極２が形成され、ｐ++領域１０にはｐ型用電極３が形成され、太陽電池１を作製した。 Next, as shown in FIG. 5I, a silver paste is applied to a predetermined position on the back surface of the n-type silicon substrate 4 by a screen printing method and dried. Thereafter, by baking, an n-type electrode 2 was formed in the n ++ region 9, and a p-type electrode 3 was formed in the p ++ region 10, thereby producing a solar cell 1.
　＜実施の形態２＞
　図６は、本発明の他の一例である実施の形態２の太陽電池の断面を表す図である。太陽電池８１の裏面側から見た図は、図１と同様である。図６（ａ）は、図２（ａ）と同様に、図１のＡ－Ａ′の断面に対応する図であり、図６（ｂ）は、図６（ａ）に示す太陽電池８１の受光面の一部の模式的な拡大断面図であり、図６（ｃ）は、ｎ型シリコン基板４１の裏面の凹凸を図解する模式的な拡大断面図である。 <Embodiment 2>
FIG. 6 is a diagram showing a cross section of the solar cell of the second embodiment which is another example of the present invention. The view seen from the back side of the solar cell 81 is the same as FIG. 6A is a view corresponding to the cross section taken along the line AA ′ of FIG. 1, as in FIG. 2A, and FIG. 6B is a view of the solar cell 81 shown in FIG. 6A. 6 is a schematic enlarged cross-sectional view of a part of the light-receiving surface, and FIG. 6C is a schematic enlarged cross-sectional view illustrating the unevenness of the back surface of the n-type silicon substrate 41.
　図７は、太陽電池８１からｎ型用電極２とｐ型用電極３とを除去し、さらに裏面パッシベーション膜１４を除去した場合に、ｎ型シリコン基板４１を裏面側から見た図である。また、図８は、図７の一部を拡大した模式図である。実施の形態１との違いは、高濃度ｐ型半導体領域が、ｐ++領域１０とｐ++領域５３に分離している点である。 FIG. 7 is a view of the n-type silicon substrate 41 as seen from the back surface side when the n-type electrode 2 and the p-type electrode 3 are removed from the solar cell 81 and the back surface passivation film 14 is further removed. FIG. 8 is an enlarged schematic view of a part of FIG. The difference from the first embodiment is that the high concentration p-type semiconductor region is separated into the p ++ region 10 and the p ++ region 53.
　太陽電池８１のｐ型半導体領域には、低濃度ｐ型半導体領域であるｐ+領域５１、及び高濃度ｐ型半導体領域であるｐ++領域１０、ｐ++領域５３が形成されており、ｐ+領域５１は、ｐ++領域１０とｐ++領域５３で挟まれ、ｐ++領域５３は、ｐ型用電極３とは接続していない。また、図８に示すように、ｐ+領域５１とｎ++領域９とが接する箇所がある。それ以外は、太陽電池１の構造と同様である。 In the p-type semiconductor region of the solar cell 81, a p + region 51 that is a low-concentration p-type semiconductor region, a p ++ region 10 and a p ++ region 53 that are high-concentration p-type semiconductor regions are formed. p + region 51 is sandwiched by the p ++ region 10 and the p ++ region 53, the p ++ region 53, the p-type electrode 3 is not connected. Further, as shown in FIG. 8, there is a place where the p + region 51 and the n ++ region 9 are in contact with each other. Other than that, it is the same as the structure of the solar cell 1.
　また、太陽電池１と同様に、太陽電池８１も、ｎ型半導体領域とｐ型半導体領域とを隣接して形成することより、太陽電池８１に逆方向のバイアスがかかったとき、部分的に電圧がかかることがなく、局所的な逆方向電流による発熱をさけることができる。 Similarly to the solar cell 1, the solar cell 81 also has an n-type semiconductor region and a p-type semiconductor region formed adjacent to each other, so that when the solar cell 81 is biased in the reverse direction, a voltage is partially applied. Therefore, heat generation due to a local reverse current can be avoided.
　太陽電池８１の製造方法については、実施の形態１と同様に、低濃度ｐ型半導体領域は、先に拡散させたｎ型不純物よりもｐ型不純物が優位となり、ｐ型領域となる。よって、低濃度ｐ型半導体領域と高濃度ｐ型半導体領域の形成を１工程で行うことが可能となることから、工程数を低減することが可能になる。そして、図８におけるｐ+領域５１の短辺とｎ++領域９との接する箇所に、図５（ｃ）に示す拡散マスク２３を形成しない以外は、図５に示す製造方法と同様である。 As for the manufacturing method of solar cell 81, as in the first embodiment, the low-concentration p-type semiconductor region has a p-type impurity over the previously diffused n-type impurity and becomes a p-type region. Therefore, the low-concentration p-type semiconductor region and the high-concentration p-type semiconductor region can be formed in one step, and the number of steps can be reduced. Then, the manufacturing method shown in FIG. 5 is the same as that shown in FIG. 5 except that the diffusion mask 23 shown in FIG. 5C is not formed at the place where the short side of the p + region 51 and the n ++ region 9 in FIG. .
　上記では、ｎ型シリコン基板について記載したが、ｐ型シリコン基板を用いることも可能である。その際、受光面拡散層が存在する場合はｐ型不純物を用いたｐ+層となり、反射防止膜はｐ型不純物が含まれた膜となり、ｐ型シリコン基板に対してエミッタ領域となるｎ型半導体領域においては、ｎ+領域とｎ++領域とが形成され、ｐ型半導体領域にはｐ++領域が形成される。また、外周縁半導体領域には、ｎ+領域とｎ++領域とがそれぞれ形成される。他の構造はｎ型シリコン基板について記載した上記構造と同様である。また、この場合、先に拡散させたｐ型不純物であるボロンよりもｎ型不純物であるリンが優位となり、ｎ型領域となった領域が形成される。加えて、ｐ型シリコン基板を用いる場合は、より高い短絡電流を得るために、ｎ型半導体領域のほうが、ｐ型半導体領域よりも大きい。 Although an n-type silicon substrate has been described above, a p-type silicon substrate can also be used. At this time, when the light-receiving surface diffusion layer exists, it becomes a p + layer using p-type impurities, and the antireflection film becomes a film containing p-type impurities, and becomes an n-type which becomes an emitter region with respect to the p-type silicon substrate. in the semiconductor region and the n + region and n ++ region is formed, the p-type semiconductor region p ++ region. In the outer peripheral semiconductor region, an n + region and an n ++ region are formed. Other structures are the same as those described above for the n-type silicon substrate. Further, in this case, phosphorus, which is an n-type impurity, is superior to boron, which is a p-type impurity that has been diffused earlier, and a region that is an n-type region is formed. In addition, when a p-type silicon substrate is used, the n-type semiconductor region is larger than the p-type semiconductor region in order to obtain a higher short-circuit current.
　１　太陽電池、２　ｎ型用電極、３　ｐ型用電極、４　ｎ型シリコン基板、５　凹凸形状、６　受光面拡散層、８　第２裏面パッシベーション膜、９　ｎ++領域、１０　ｐ++領域、１１　第１裏面パッシベーション膜、１２　反射防止膜、１３　受光面パッシベーション膜、１４　裏面パッシベーション膜、２１　テクスチャマスク、２２　拡散マスク、２３　拡散マスク、２４　酸化シリコン膜、２５　拡散マスク、２７　混合液、３１　ドーピングペースト、３２　ｎ+領域、４１　ｎ型シリコン基板、５１　ｐ+領域、５２　ｐ++領域、５３　ｐ++領域、７１　ｐ+領域、８１　太陽電池。 DESCRIPTION OF SYMBOLS 1 Solar cell, 2 n-type electrode, 3 p-type electrode, 4 n-type silicon substrate, 5 uneven | corrugated shape, 6 light-receiving surface diffused layer, 8 2nd back surface passivation film, 9 n ++ area | region, 10p ++ area | region , 11 First back surface passivation film, 12 Antireflection film, 13 Light receiving surface passivation film, 14 Back surface passivation film, 21 Texture mask, 22 Diffusion mask, 23 Diffusion mask, 24 Silicon oxide film, 25 Diffusion mask, 27 Mixed liquid, 31 Doping paste, 32 n + region, 41 n-type silicon substrate, 51 p + region, 52 p ++ region, 53 p ++ region, 71 p + region, 81 solar cell.

Claims (11)

  1. 　第１導電型のシリコン基板の一方の面に、高濃度第１導電型半導体領域、高濃度第２導電型半導体領域及び低濃度第２導電型半導体領域を形成する太陽電池の製造方法であって、
    　前記高濃度第１導電型半導体領域となる領域及び前記低濃度第２導電型半導体領域となる領域に、第１導電型の不純物を拡散させる第１工程と、
    　前記高濃度第２導電型半導体領域となる領域及び前記低濃度第２導電型半導体領域となる領域に、第２導電型の不純物を拡散させる第２工程を、この順に有し、
    　前記低濃度第２導電型半導体領域は、前記第２導電型の不純物が前記第１導電型の不純物より優位であるように拡散されている、太陽電池の製造方法。     A method of manufacturing a solar cell, wherein a high concentration first conductive type semiconductor region, a high concentration second conductive type semiconductor region, and a low concentration second conductive type semiconductor region are formed on one surface of a first conductive type silicon substrate. ,
    A first step of diffusing impurities of a first conductivity type into a region to be the high concentration first conductivity type semiconductor region and a region to be the low concentration second conductivity type semiconductor region;
    A second step of diffusing impurities of the second conductivity type in this order into the region to be the high concentration second conductivity type semiconductor region and the region to be the low concentration second conductivity type semiconductor region;
    The method of manufacturing a solar cell, wherein the low-concentration second conductivity type semiconductor region is diffused so that the second conductivity type impurity is superior to the first conductivity type impurity.
  2. 　前記太陽電池は、裏面電極型太陽電池である請求項１に記載の太陽電池の製造方法。 The method for manufacturing a solar cell according to claim 1, wherein the solar cell is a back electrode type solar cell.
  3. 　前記第１工程の後に、前記シリコン基板に熱酸化法により酸化シリコン膜を形成する工程と、
    　前記酸化シリコン膜をエッチングすることにより、前記酸化シリコン膜を前記高濃度第１導電型半導体領域上のみに残す工程と、をさらに備えた、請求項１または２に記載の太陽電池の製造方法。     Forming a silicon oxide film on the silicon substrate by a thermal oxidation method after the first step;
    The method for manufacturing a solar cell according to claim 1, further comprising: etching the silicon oxide film to leave the silicon oxide film only on the high-concentration first conductivity type semiconductor region.
  4. 　前記第１工程において、前記高濃度第１導電型半導体領域は、前記第１導電型の不純物を含むドーピングペーストを塗布して熱処理により形成する、請求項１～３のいずれかに記載の太陽電池の製造方法。 4. The solar cell according to claim 1, wherein, in the first step, the high-concentration first conductive type semiconductor region is formed by applying a doping paste containing the first conductive type impurity and performing heat treatment. Manufacturing method.
  5. 　前記低濃度第２導電型半導体領域となる領域は、前記ドーピングペーストからのアウトディフュージョンにより、前記ドーパントがドーピングされる、請求項４に記載の太陽電池の製造方法。 The method of manufacturing a solar cell according to claim 4, wherein the region to be the low-concentration second conductivity type semiconductor region is doped with the dopant by out-diffusion from the doping paste.
  6. 　第１導電型のシリコン基板の裏面に形成された、第１導電型半導体領域、及び第２導電型半導体領域と、
    　前記シリコン基板の裏面上に形成された裏面パッシベーション膜と、
    　前記第１導電型半導体領域に接して形成された第１電極と、
    　前記第２導電型半導体領域に接して形成された第２電極と、を有し、
    　前記第２導電型半導体領域は、高濃度第２導電型半導体領域と低濃度第２導電型半導体領域とを有し、
    　前記低濃度第２導電型半導体領域は前記裏面パッシベーション膜に接し、前記第２電極は、前記高濃度第２導電型半導体領域に接している、太陽電池。     A first conductivity type semiconductor region and a second conductivity type semiconductor region formed on the back surface of the first conductivity type silicon substrate;
    A back surface passivation film formed on the back surface of the silicon substrate;
    A first electrode formed in contact with the first conductivity type semiconductor region;
    A second electrode formed in contact with the second conductivity type semiconductor region,
    The second conductivity type semiconductor region has a high concentration second conductivity type semiconductor region and a low concentration second conductivity type semiconductor region,
    The low concentration second conductive type semiconductor region is in contact with the back surface passivation film, and the second electrode is in contact with the high concentration second conductive type semiconductor region.
  7. 　前記低濃度第２導電型半導体領域は、前記高濃度第２導電型半導体領域より面積が大きい、請求項６に記載の太陽電池。 The solar cell according to claim 6, wherein the low concentration second conductivity type semiconductor region has a larger area than the high concentration second conductivity type semiconductor region.
  8. 　前記第１導電型半導体領域は、前記第２導電型半導体領域と接している、請求項６または７に記載の太陽電池。 The solar cell according to claim 6 or 7, wherein the first conductive type semiconductor region is in contact with the second conductive type semiconductor region.
  9. 　前記第１導電型半導体領域と接している前記第２導電型半導体領域は、前記高濃度第２導電型半導体領域である、請求項８に記載の太陽電池。 The solar cell according to claim 8, wherein the second conductive semiconductor region in contact with the first conductive semiconductor region is the high-concentration second conductive semiconductor region.
  10. 　前記低濃度第２導電型半導体領域は、前記高濃度第２導電型半導体領域で囲まれている、請求項９に記載の太陽電池。 The solar cell according to claim 9, wherein the low-concentration second conductive semiconductor region is surrounded by the high-concentration second conductive semiconductor region.
  11. 　前記高濃度第２導電型半導体領域は、前記第２電極に接する領域と、前記第１導電型半導体領域に接する領域とに分離している、請求項９に記載の太陽電池。 The solar cell according to claim 9, wherein the high-concentration second conductivity type semiconductor region is separated into a region in contact with the second electrode and a region in contact with the first conductivity type semiconductor region.
PCT/JP2012/073319 2011-09-15 2012-09-12 Method for producing solar cell, and solar cell WO2013039101A1 (en)

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JP2011100919A (en) * 2009-11-09 2011-05-19 Sharp Corp Back electrode solar cell, solar cell string, and solar cell module

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JP2010267787A (en) * 2009-05-14 2010-11-25 Sharp Corp Method of manufacturing semiconductor device
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