WO2013023656A3 - Schaltungsanordnung und verfahren zum übertragen von signalen - Google Patents

Schaltungsanordnung und verfahren zum übertragen von signalen Download PDF

Info

Publication number
WO2013023656A3
WO2013023656A3 PCT/DE2012/200054 DE2012200054W WO2013023656A3 WO 2013023656 A3 WO2013023656 A3 WO 2013023656A3 DE 2012200054 W DE2012200054 W DE 2012200054W WO 2013023656 A3 WO2013023656 A3 WO 2013023656A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit arrangement
transmitting signals
type
signals
tools
Prior art date
Application number
PCT/DE2012/200054
Other languages
English (en)
French (fr)
Other versions
WO2013023656A2 (de
Inventor
Thomas Blon
Florian Jansen
Holger Hoeltke
Original Assignee
Silicon Line Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Line Gmbh filed Critical Silicon Line Gmbh
Priority to JP2014525318A priority Critical patent/JP6126603B2/ja
Priority to DE112012003363.9T priority patent/DE112012003363A5/de
Priority to EP12813749.4A priority patent/EP2745478B1/de
Publication of WO2013023656A2 publication Critical patent/WO2013023656A2/de
Publication of WO2013023656A3 publication Critical patent/WO2013023656A3/de
Priority to US14/181,465 priority patent/US9231756B2/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G06F1/105—Distribution of clock signals, e.g. skew in which the distribution is at least partially optical
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H04L25/0276—Arrangements for coupling common mode signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0091—Transmitter details
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
  • Optical Communication System (AREA)
  • Logic Circuits (AREA)

Abstract

Es werden auf Basis von single-ended, auf Logikpegeln basierenden Signalen sowie von differentiellen, insbesondere auf common mode basierenden, Signalen eine Schaltungsanordnung (S, E) sowie ein entsprechendes Verfahren vorgeschlagen, bei denen eine weitere Miniaturisierung von Gerätschaften, denen eine derartige Schaltungsanordnung (S, E) sowie ein derartiges Verfahren zugeordnet sind, ermöglicht wird.
PCT/DE2012/200054 2011-08-16 2012-08-16 Schaltungsanordnung und verfahren zum übertragen von signalen WO2013023656A2 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2014525318A JP6126603B2 (ja) 2011-08-16 2012-08-16 回路装置および信号を送信するための方法
DE112012003363.9T DE112012003363A5 (de) 2011-08-16 2012-08-16 Schaltungsanordnung und Verfahren zum Übertragen von Signalen
EP12813749.4A EP2745478B1 (de) 2011-08-16 2012-08-16 Schaltungsanordnung und verfahren zum übertragen von signalen
US14/181,465 US9231756B2 (en) 2011-08-16 2014-02-14 Circuit arrangement and method for transmitting signals

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102011052764.8 2011-08-16
DE102011052764 2011-08-16

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/181,465 Continuation US9231756B2 (en) 2011-08-16 2014-02-14 Circuit arrangement and method for transmitting signals

Publications (2)

Publication Number Publication Date
WO2013023656A2 WO2013023656A2 (de) 2013-02-21
WO2013023656A3 true WO2013023656A3 (de) 2013-05-30

Family

ID=47556997

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2012/200054 WO2013023656A2 (de) 2011-08-16 2012-08-16 Schaltungsanordnung und verfahren zum übertragen von signalen

Country Status (5)

Country Link
US (1) US9231756B2 (de)
EP (1) EP2745478B1 (de)
JP (1) JP6126603B2 (de)
DE (1) DE112012003363A5 (de)
WO (1) WO2013023656A2 (de)

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001103028A (ja) * 1999-10-01 2001-04-13 Nippon Telegr & Teleph Corp <Ntt> 信号多重方法
US7587537B1 (en) * 2007-11-30 2009-09-08 Altera Corporation Serializer-deserializer circuits formed from input-output circuit registers
JP4633547B2 (ja) * 2004-06-18 2011-02-16 パナソニック株式会社 携帯情報端末機器およびその機器内相互通信方法
KR101030768B1 (ko) * 2004-08-26 2011-04-27 삼성전자주식회사 소비전력이 적고 고주파 동작이 가능한 광범위 지연동기루프 회로 및 이를 구비하는 광학 구동 시스템
JP5223183B2 (ja) * 2006-10-31 2013-06-26 日立電線株式会社 光電気複合配線部品及びこれを用いた電子機器
JP2008160370A (ja) * 2006-12-22 2008-07-10 Kddi Corp データ伝送システム及び方法、データ送信装置並びにデータ受信装置
EP2159934A4 (de) * 2007-04-05 2013-05-01 Omron Tateisi Electronics Co Optisches übertragungsmodul
WO2009034516A2 (en) * 2007-09-10 2009-03-19 Nokia Corporation Changing hardware settings based on data preamble
JP4609552B2 (ja) * 2008-08-22 2011-01-12 オムロン株式会社 光伝送用並列直列変換器、光伝送システム、及び電子機器
JP5187277B2 (ja) * 2009-06-16 2013-04-24 ソニー株式会社 情報処理装置、及びモード切り替え方法

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
"MIPI Alliance Specification for D-PHY", 22 September 2009 (2009-09-22), pages 1 - 123, XP055057664, Retrieved from the Internet <URL:http://www.mipi.org/specifications/physical-layer> [retrieved on 20130325] *
"SL83014 by Silicon Line GmbH", 3 March 2011 (2011-03-03), XP055057661, Retrieved from the Internet <URL:http://www.silicon-line.com/SL83014.htm> [retrieved on 20130325] *
"Snapshots of SL83014 by Silicon Line GmbH - *Evidence of publication prior to priority date*", 3 March 2011 (2011-03-03), XP055057663, Retrieved from the Internet <URL:http://www.silicon-line.com/SL83014.htm> [retrieved on 20130325] *
DARTNELL P ET AL: "Serdes Framer Interface Level 5 (SFI-5): Implementation Agreement for 40Gb/s Interface for Physical Layer Devices (OIF-SF15-01.01)", 29 January 2002 (2002-01-29), pages 62pp, XP009119852, Retrieved from the Internet <URL:http://www.oiforum.com/public/documents/OIF-SFI5-01.0.pdf> [retrieved on 20090722] *

Also Published As

Publication number Publication date
EP2745478B1 (de) 2021-03-10
DE112012003363A5 (de) 2014-06-26
WO2013023656A2 (de) 2013-02-21
US20150043692A1 (en) 2015-02-12
JP6126603B2 (ja) 2017-05-10
US9231756B2 (en) 2016-01-05
JP2014529932A (ja) 2014-11-13
EP2745478A2 (de) 2014-06-25

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