WO2013022192A3 - Phase-locked loop and clock-generating system comprising same - Google Patents

Phase-locked loop and clock-generating system comprising same Download PDF

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Publication number
WO2013022192A3
WO2013022192A3 PCT/KR2012/005527 KR2012005527W WO2013022192A3 WO 2013022192 A3 WO2013022192 A3 WO 2013022192A3 KR 2012005527 W KR2012005527 W KR 2012005527W WO 2013022192 A3 WO2013022192 A3 WO 2013022192A3
Authority
WO
WIPO (PCT)
Prior art keywords
phase
locked loop
signal
basis
crystal oscillator
Prior art date
Application number
PCT/KR2012/005527
Other languages
French (fr)
Korean (ko)
Other versions
WO2013022192A2 (en
Inventor
황인준
Original Assignee
주식회사 아이덴코아
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 아이덴코아 filed Critical 주식회사 아이덴코아
Publication of WO2013022192A2 publication Critical patent/WO2013022192A2/en
Publication of WO2013022192A3 publication Critical patent/WO2013022192A3/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
    • H03L7/235—Nested phase locked loops
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A phase-locked loop according to one embodiment of the present invention comprises: a phase sensor for generating a phase sensor signal by sensing the phase difference between a reference clock signal and an output clock signal; a charge pump for providing a pumping current on the basis of the phase sensor signal; a loop filter for providing filtered pumping voltage corresponding to the pumping current; a voltage controlled crystal oscillator, comprising a crystal vibrator, for generating a crystal oscillator signal on the basis of the filtered pumping voltage; and a supplementary phase-locked loop for locking the phase of the output clock signal on the basis of the crystal oscillator signal and then providing same.
PCT/KR2012/005527 2011-08-05 2012-07-12 Phase-locked loop and clock-generating system comprising same WO2013022192A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020110078261A KR20130015924A (en) 2011-08-05 2011-08-05 Phase locked loop and clock generating system including the same
KR10-2011-0078261 2011-08-05

Publications (2)

Publication Number Publication Date
WO2013022192A2 WO2013022192A2 (en) 2013-02-14
WO2013022192A3 true WO2013022192A3 (en) 2013-04-04

Family

ID=47669033

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2012/005527 WO2013022192A2 (en) 2011-08-05 2012-07-12 Phase-locked loop and clock-generating system comprising same

Country Status (2)

Country Link
KR (1) KR20130015924A (en)
WO (1) WO2013022192A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677823A (en) * 1992-08-24 1994-03-18 Oki Electric Ind Co Ltd Frequency synthesizer
US20020033736A1 (en) * 1999-03-23 2002-03-21 Roland Heymann Frequency synthesizer and method of providing a mixing oscillator signal to a mixer
US20060001494A1 (en) * 2004-07-02 2006-01-05 Bruno Garlepp Cascaded locked-loop circuits deriving high-frequency, low noise clock signals from a jittery, low-frequency reference
US7148753B1 (en) * 2003-04-11 2006-12-12 Silicon Laboratories Inc. Method and apparatus for generating a clock signal in holdover mode

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677823A (en) * 1992-08-24 1994-03-18 Oki Electric Ind Co Ltd Frequency synthesizer
US20020033736A1 (en) * 1999-03-23 2002-03-21 Roland Heymann Frequency synthesizer and method of providing a mixing oscillator signal to a mixer
US7148753B1 (en) * 2003-04-11 2006-12-12 Silicon Laboratories Inc. Method and apparatus for generating a clock signal in holdover mode
US20060001494A1 (en) * 2004-07-02 2006-01-05 Bruno Garlepp Cascaded locked-loop circuits deriving high-frequency, low noise clock signals from a jittery, low-frequency reference

Also Published As

Publication number Publication date
WO2013022192A2 (en) 2013-02-14
KR20130015924A (en) 2013-02-14

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