WO2013007083A1 - Two-layer printed circuit board, printing method thereof, and mobile communication terminal - Google Patents

Two-layer printed circuit board, printing method thereof, and mobile communication terminal Download PDF

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Publication number
WO2013007083A1
WO2013007083A1 PCT/CN2011/083665 CN2011083665W WO2013007083A1 WO 2013007083 A1 WO2013007083 A1 WO 2013007083A1 CN 2011083665 W CN2011083665 W CN 2011083665W WO 2013007083 A1 WO2013007083 A1 WO 2013007083A1
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WO
WIPO (PCT)
Prior art keywords
printed circuit
circuit board
layer printed
pads
capacitor
Prior art date
Application number
PCT/CN2011/083665
Other languages
French (fr)
Chinese (zh)
Inventor
刘玉鹏
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201110190890.3A external-priority patent/CN102300398B/en
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Priority to KR1020137033731A priority Critical patent/KR20140010991A/en
Publication of WO2013007083A1 publication Critical patent/WO2013007083A1/en

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • H05K1/0243Printed circuits associated with mounted high frequency components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09218Conductive traces
    • H05K2201/09227Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting

Definitions

  • the present invention relates to mobile communication technologies, and more particularly to a mobile communication terminal and a two-layer printed circuit board therefor, and a method of printing the two-layer printed circuit board.
  • the printed circuit is a conductive pattern for connection between components formed on the surface of the insulating substrate or by a printing method in accordance with a pre-designed circuit.
  • Printed circuit boards play an important role in electronics.
  • the printed circuit boards used in low-end mobile communication terminals are mainly six-layer printed circuit boards (referred to as six-layer boards) and four-layer printed circuit boards (referred to as four-layer boards).
  • the cost of a two-layer printed circuit board is only half that of a four-layer printed circuit board, and only one-third of a six-layer printed circuit board. Therefore, applying two-layer printed circuit boards to low-end mobile communication. On the terminal, the cost of the mobile communication terminal will be significantly reduced.
  • the technical problem to be solved by the present invention is to provide a two-layer printed circuit board that can be applied to a mobile communication terminal, which overcomes the existing low-end mobile communication terminal and uses a six-layer printed circuit board or a four-layer printed circuit board.
  • the disadvantage of higher board cost is to provide a two-layer printed circuit board that can be applied to a mobile communication terminal, which overcomes the existing low-end mobile communication terminal and uses a six-layer printed circuit board or a four-layer printed circuit board.
  • the present invention provides a two-layer printed circuit board based on the MT6251 platform, in the two-layer printed circuit board:
  • the pad diameter is 0.27 mm
  • the line width between the two pads is 0.075 mm
  • the minimum spacing between the traces and the pads is 0.075 mm
  • the pads in the inner row are threaded from the outer pads.
  • the main ground pad of the main chip is a complete ground plane
  • the C7 pin and C8 pin are led out to the ground.
  • a first capacitor is disposed on the VBAT (power supply) line on the two-layer printed circuit board.
  • a second capacitor is disposed on the VBAT line on the two-layer printed circuit board.
  • the second capacitor is a tantalum capacitor.
  • the clock line and the data line of the memory on the two-layer printed circuit board are taken out from the baseband chip, and the clock line of the memory and the back side of the data line are a complete ground plane.
  • the present invention also provides a two-layer printed circuit board printing method for printing a two-layer printed circuit board based on the MT6251 platform, the method comprising:
  • the pads of the inner row are threaded out from the outer row pads, and the back surface of the main pad of the main chip is set to a complete ground plane, and the C7 pin and the C8 pin are led out to the outside ground hole.
  • a first capacitance is provided on the VBAT line on the two-layer printed circuit board.
  • a second capacitor is provided on the VBAT line on the two-layer printed circuit board.
  • the clock line and the data line of the memory are disposed at a position leading from the baseband chip on the two-layer printed circuit board, and the clock line of the memory and the back side of the data line are set to a complete ground plane.
  • the present invention also provides a mobile communication terminal comprising any of the above two layers of printed circuit boards.
  • the two-layer printed circuit board of the embodiment of the present invention can ensure the function of the mobile communication terminal is normal when applied to the mobile communication terminal, compared with the existing four-layer printed circuit board or six-layer printing.
  • the mobile communication terminal of the circuit board significantly reduces the cost without increasing the function, and improves the competitive advantage of the product.
  • FIG. 1 is a schematic diagram of a main chip outlet in an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a first capacitor and a second capacitor on a VBAT line in an embodiment of the present invention.
  • 3 is a schematic view of a pad of a main chip in an embodiment of the present invention.
  • FIG. 4 is a schematic view showing the setting of a high speed signal line in the embodiment of the present invention.
  • FIG. 5 is a schematic flow chart of printing a two-layer printed circuit board according to an embodiment of the present invention. Preferred embodiment of the invention
  • the embodiment of the present invention is based on the MT6251 platform, and the implemented two-layer printed circuit board reduces the diameter of the ball grid array (BGA) peripheral pad compared to the prior art, and reduces the line and the pad. The spacing between them. This is convenient for the inside of the pad to exit the surface.
  • BGA ball grid array
  • the existing BGA pads have a diameter of 0.3 mm mm and the center distance between the two pads is 0.5 mm. According to the current industry regulations, the width of the trace is 0.1mm, and the safety distance between the trace and the pad is 0.1 mm. This way there is no way to thread between the two pads.
  • the embodiment of the present invention is as shown in FIG. 1.
  • the center distance between the pad and the pad is 0.5 mm as in the prior art, and the pad diameter is set to 0.27 mm, and the line between the two pads of the BGA is traced.
  • the width is set to 0.075mm, the rest is not the line from the BGA pad, the line width is set to 0.1mm; and the minimum spacing rule between the trace and the pad is set to 0.075mm.
  • the minimum pitch is 0.075mm, which allows the pads of the inner row to be routed from between the outer pads. Verified, adjust pad diameter and go The spacing between the lines and the pads can meet the functional requirements and mass production requirements of the mobile communication terminal.
  • the positions indicated by the two ellipses are more commonly used.
  • the above-mentioned pad diameter is set to 0.27 mm and the line width between the two pads of the BGA is set to 0.075 mm. Process.
  • the main chip shown in Figure 1, the rest of the place also has the application of this process.
  • the VB AT line is on the surface layer, and a first capacitor having a capacity of 22 microfarads (uF) or more is provided on the VBAT line, and the first capacitor is, for example, a tantalum capacitor or a ceramic capacitor.
  • the first capacitor can effectively eliminate the interference on the power supply, prevent the voltage drop of the VBAT from significantly affecting the RF phase, and greatly improve the stability of the RF index and the system.
  • the first capacitor on the VBAT line is as close as possible to the battery connector.
  • PCB A Print Cirruit Board + Assembly
  • the embodiment of the present invention further sets a second capacitor having a capacity of 22 uF or more on the VBAT line, which can effectively eliminate the sound that may be emitted from the PCBA line; wherein the second capacitor is a tantalum capacitor.
  • 2 is a schematic structural view of a first capacitor and a second capacitor according to an embodiment of the present invention, wherein the second capacitor is disposed as close as possible to the baseband processing chip. In the embodiment shown in FIG.
  • the ellipse on the left side indicates the position of the first capacitor
  • the ellipse on the right side indicates the position of the second capacitor
  • the first capacitor and the second capacitor are tantalum capacitors.
  • the main pad back of the master chip is a complete ground plane.
  • some of the easily disturbed ground pads are led out to the outside, such as pulling the C7 and C8 pins to the outside.
  • Time Division Distortion (TDD) NOISE is generated on the audio (a noise generated by the radio frequency module periodically transmitting and receiving information generated by the time division duplex communication mode).
  • the copper area in the ellipse in Figure 3 is the ground plane
  • the ground pin in the ellipse is the main grounding pin of the chip.
  • the memory has a high clock frequency that can reach tens or hundreds of megahertz (MHz). If the clock and data lines of the memory are exposed outside, or are placed back to back with other sensitive traces, there may be some risk to the stability of the system.
  • the clock line and the data line of the memory (MEMORY) (the high-brightness line shown in the ellipse in Fig. 4) are taken out from the baseband chip, and the back side thereof is a complete ground plane.
  • FIG. 5 is a schematic flow chart of printing a two-layer printed circuit board according to an embodiment of the present invention. As shown in Figure 5, the embodiment of the present invention mainly includes the following steps:
  • the first capacitor such as tantalum capacitor or ceramic capacitor
  • Its capacity is 22uF or more, which can effectively eliminate the interference on the power supply.
  • the RF indicators and the stability of the system have been greatly improved.
  • the second capacitor (tantalum capacitor) is placed on the VBAT line on the two-layer printed circuit board as close as possible to the baseband processing chip. Its capacity is 22uF or more, which can effectively eliminate the sound of the PCBA line.
  • the main ground pad back of the main chip on the two-layer printed circuit board is set to a complete ground plane, and some easily disturbed ground pads are led out to punch holes, for example, the C7 pin and the C8 pin are taken out to the outside. Playing the hole, effectively avoiding TDD NOISE on the audio.
  • the clock line and the data line of the memory (MEMORY) on the two-layer printed circuit board are taken out from the baseband chip, and the back side of the clock line and the data line are set to a complete ground plane, which reduces the clock line and data line exposure of the memory.
  • Embodiments of the present invention also include applying the aforementioned two-layer printed circuit board to a mobile communication terminal.
  • a mobile communication terminal For details, refer to the description of the two-layer printed circuit board in the foregoing embodiment, which is not mentioned here.
  • the embodiment of the present invention realizes the threading of the inner row of pads from the outer row pads by reducing the pad diameter and the line width of the inner portion of the BGA, thereby ensuring the functional requirements and mass production requirements of the mobile communication terminal. .
  • the embodiment of the invention effectively eliminates the interference on the power supply by setting the first tantalum capacitor on the VBAT line, and greatly improves the stability of the radio frequency index and the system.
  • Embodiments of the present invention effectively eliminate the possible sound of the PCBA line by providing a second tantalum capacitor on the VBAT line.
  • Embodiments of the present invention set the back surface of the ground pad of the main chip to be relatively complete The ground plane avoids the generation of TDD NOISE on the audio.
  • the embodiment of the present invention improves the stability of the system by setting a complete ground plane on the back of the MEMORY clock and data lines.
  • the two-layer printed circuit board of the embodiment of the present invention can ensure that the function of the mobile communication terminal is normal, compared with the existing four-layer printed circuit board or six-layer printed circuit board.
  • the mobile communication terminal significantly reduces the cost and improves the competitive advantage of the product without losing the function.

Abstract

A two-layer printed circuit board, a printing method thereof, and a mobile communication terminal overcome the disadvantage of the high cost of a six-layer printed circuit board or a four-layer printed circuit board used by the existing low-end mobile communication terminal. The two-layer printed circuit board is based on the MT6251 platform. The diameter of a bonding pad is 0.27 millimeters. The line width of a wiring between two bonding pads is 0.075 millimeters. A minimum interval between the wiring and the bonding pad is 0.075 millimeters. A wire from a bonding pad in an inner row is threaded through a place between bonding pads in an outer row. The back of a main ground bonding pad of a main chip is a whole ground plane. A ground hole is opened after a C7 pin and a C8 pin are led outward. When the two-layer printed circuit board of the embodiment of the present invention is applied to the mobile communication terminal, compared with a mobile communication terminal using a four-layer printed circuit board or a six-layer printed circuit board, the cost is obviously reduced in the premise of no loss of functions and the competitive advantage of the product is improved.

Description

两层印制电路板及其印刷方法、 移动通信终端  Two-layer printed circuit board and printing method thereof, mobile communication terminal
技术领域 Technical field
本发明涉及移动通信技术, 尤其涉及一种移动通信终端及其中的两层印 制电路板, 以及该两层印制电路板的印制方法。  The present invention relates to mobile communication technologies, and more particularly to a mobile communication terminal and a two-layer printed circuit board therefor, and a method of printing the two-layer printed circuit board.
背景技术 Background technique
印制电路就是按照预先设计的电路, 利用印刷法在绝缘基板的表面或其 内部形成的用于元器件之间连接的导电图形。 印制电路板在电子产品中占有 很重要的地位。  The printed circuit is a conductive pattern for connection between components formed on the surface of the insulating substrate or by a printing method in accordance with a pre-designed circuit. Printed circuit boards play an important role in electronics.
印制电路板的主要应用之一就是低端的移动通信终端。 低端的移动通信 终端的竟争, 主要集中在性能的稳定和价格的低廉上。 目前, 低端的移动通 信终端中所使用的印制电路板, 主要是六层印制电路板(简称六层板)和四 层印制电路板(简称四层板) 。  One of the main applications of printed circuit boards is low-end mobile communication terminals. The competition of low-end mobile communication terminals is mainly concentrated on the stability of performance and low price. At present, the printed circuit boards used in low-end mobile communication terminals are mainly six-layer printed circuit boards (referred to as six-layer boards) and four-layer printed circuit boards (referred to as four-layer boards).
发明内容 Summary of the invention
总体上看, 两层印制电路板的成本只有四层印制电路板的一半, 只有六 层印制电路板的三分之一, 因此将两层印制电路板应用到低端的移动通信终 端上, 将会明显降低移动通信终端的成本。  In general, the cost of a two-layer printed circuit board is only half that of a four-layer printed circuit board, and only one-third of a six-layer printed circuit board. Therefore, applying two-layer printed circuit boards to low-end mobile communication. On the terminal, the cost of the mobile communication terminal will be significantly reduced.
本发明所要解决的技术问题是需要提供一种可以应用到移动通信终端中 的两层印制电路板, 克服现有低端的移动通信终端釆用六层印制电路板或者 四层印制电路板成本较高的缺陷。  The technical problem to be solved by the present invention is to provide a two-layer printed circuit board that can be applied to a mobile communication terminal, which overcomes the existing low-end mobile communication terminal and uses a six-layer printed circuit board or a four-layer printed circuit board. The disadvantage of higher board cost.
为了解决上述技术问题, 本发明提供了一种两层印制电路板, 基于 MT6251平台, 在该两层印制电路板中:  In order to solve the above technical problems, the present invention provides a two-layer printed circuit board based on the MT6251 platform, in the two-layer printed circuit board:
焊盘直径为 0.27毫米, 两个焊盘之间走线的线宽为 0.075毫米, 走线与 焊盘之间的最小间距为 0.075 毫米, 内排的焊盘是从外排焊盘之间穿线出来 的, 主芯片的主要地焊盘背面为完整的地平面, C7管脚和 C8管脚是引出到 外面后打地孔的。 优选地, 所述两层印制电路板上的 VBAT (供电电源)线路上设置有第 一电容。 The pad diameter is 0.27 mm, the line width between the two pads is 0.075 mm, the minimum spacing between the traces and the pads is 0.075 mm, and the pads in the inner row are threaded from the outer pads. Out, the main ground pad of the main chip is a complete ground plane, and the C7 pin and C8 pin are led out to the ground. Preferably, a first capacitor is disposed on the VBAT (power supply) line on the two-layer printed circuit board.
优选地, 所述两层印制电路板上的 VBAT线路上设置有第二电容。  Preferably, a second capacitor is disposed on the VBAT line on the two-layer printed circuit board.
优选地, 所述第二电容为钽电容。  Preferably, the second capacitor is a tantalum capacitor.
优选地, 在所述两层印制电路板上存储器的时钟线和数据线从基带芯片 引出的位置, 所述存储器的时钟线和数据线的背面为完整的地平面。  Preferably, the clock line and the data line of the memory on the two-layer printed circuit board are taken out from the baseband chip, and the clock line of the memory and the back side of the data line are a complete ground plane.
本发明还提供了一种两层印制电路板的印刷方法,用于印刷基于 MT6251 平台的两层印制电路板, 该方法包括:  The present invention also provides a two-layer printed circuit board printing method for printing a two-layer printed circuit board based on the MT6251 platform, the method comprising:
将两层印制电路板上的焊盘直径设置为 0.27毫米, 将两个焊盘之间走线 的线宽设置为 0.075毫米, 将走线与焊盘之间的最小间距设置为 0.075毫米, 内排的焊盘从外排焊盘之间穿线出来, 将主芯片的主要地焊盘背面设置为完 整的地平面, 将 C7管脚和 C8管脚引出到外面打地孔。  Set the pad diameter on the two-layer printed circuit board to 0.27 mm, the line width between the two pads to 0.075 mm, and the minimum distance between the trace and the pad to 0.075 mm. The pads of the inner row are threaded out from the outer row pads, and the back surface of the main pad of the main chip is set to a complete ground plane, and the C7 pin and the C8 pin are led out to the outside ground hole.
优选地, 在所述两层印制电路板上的 VBAT线路上设置第一电容。  Preferably, a first capacitance is provided on the VBAT line on the two-layer printed circuit board.
优选地, 在所述两层印制电路板上的 VBAT线路上设置第二电容。  Preferably, a second capacitor is provided on the VBAT line on the two-layer printed circuit board.
优选地, 在所述两层印制电路板上存储器的时钟线和数据线从基带芯片 引出的位置, 将所述存储器的时钟线和数据线的背面设置为完整的地平面。  Preferably, the clock line and the data line of the memory are disposed at a position leading from the baseband chip on the two-layer printed circuit board, and the clock line of the memory and the back side of the data line are set to a complete ground plane.
本发明还提供了一种移动通信终端, 包含上述任一两层印制电路板。 与现有技术相比, 本发明实施例的二层印制电路板在应用到移动通信终 端时, 可以保证移动通信终端功能正常, 相比现有釆用四层印制电路板或者 六层印制电路板的移动通信终端, 在不损失功能的前提下明显降低了成本, 提高了产品竟争优势。  The present invention also provides a mobile communication terminal comprising any of the above two layers of printed circuit boards. Compared with the prior art, the two-layer printed circuit board of the embodiment of the present invention can ensure the function of the mobile communication terminal is normal when applied to the mobile communication terminal, compared with the existing four-layer printed circuit board or six-layer printing. The mobile communication terminal of the circuit board significantly reduces the cost without increasing the function, and improves the competitive advantage of the product.
本发明的其它特征和优点将在随后的说明书中阐述, 并且, 部分地从说 明书中变得显而易见, 或者通过实施本发明而了解。 本发明的目的和其他优 点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。 附图概述  Other features and advantages of the invention will be set forth in the description which follows, The objectives and other advantages of the invention may be realized and obtained by the structure particularly pointed in the appended claims. BRIEF abstract
附图用来提供对本发明技术方案的进一步理解, 并且构成说明书的一部 分, 与本发明的实施例一起用于解释本发明的技术方案, 并不构成对本发明 技术方案的限制。 在附图中: The drawings serve to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. The technical solutions of the present invention are used to explain the technical solutions of the present invention, and do not constitute a limitation of the technical solutions of the present invention. In the drawing:
图 1是本发明实施例中主芯片出线示意图。  1 is a schematic diagram of a main chip outlet in an embodiment of the present invention.
图 2是本发明实施例中 VBAT线路上第一电容和第二电容的示意图。 图 3是本发明实施例中主芯片地焊盘示意图。  2 is a schematic diagram of a first capacitor and a second capacitor on a VBAT line in an embodiment of the present invention. 3 is a schematic view of a pad of a main chip in an embodiment of the present invention.
图 4是本发明实施例中高速信号线的设置示意图。  4 is a schematic view showing the setting of a high speed signal line in the embodiment of the present invention.
图 5是本发明实施例印刷二层印制电路板的流程示意图。 本发明的较佳实施方式  FIG. 5 is a schematic flow chart of printing a two-layer printed circuit board according to an embodiment of the present invention. Preferred embodiment of the invention
以下将结合附图及实施例来详细说明本发明的实施方式, 借此对本发明 如何应用技术手段来解决技术问题, 并达成技术效果的实现过程能充分理解 并据以实施。  The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and embodiments, by which the present invention can be applied to the technical solutions to the technical problems, and the implementation of the technical effects can be fully understood and implemented.
本发明的实施例基于 MT6251平台, 所实现的两层印制电路板中, 相比 现有技术缩小了球栅列阵(Ball Grid Array, BGA )外围焊盘直径, 减小了线 和焊盘之间的间距。 如此处理方便里面的焊盘从表层出线。  The embodiment of the present invention is based on the MT6251 platform, and the implemented two-layer printed circuit board reduces the diameter of the ball grid array (BGA) peripheral pad compared to the prior art, and reduces the line and the pad. The spacing between them. This is convenient for the inside of the pad to exit the surface.
由于两层印制电路板上只能打机械孔, 而机械孔的孔径又比较大, 所以 不能在 BGA焊盘上直接打孔, 所有焊盘需要从表层把线拉到外面,再在外面 打孔换层。 这样, 在焊盘之间就不可避免的要穿线。  Since only two mechanical layers can be punched on the two-layer printed circuit board, and the hole diameter of the mechanical hole is relatively large, it cannot be directly punched on the BGA pad. All the pads need to be pulled from the surface to the outside, and then played outside. Hole change layer. In this way, it is inevitable to thread between the pads.
现有的 BGA焊盘的直径是 0.3 毫米 mm, 两个焊盘之间的中心距离是 0.5mm。 按照目前行业内的规定, 走线的宽度是 0.1mm, 走线和焊盘之间的 安全距离是 0.1 mm。 这样在两个焊盘之间没有办法穿线出来。  The existing BGA pads have a diameter of 0.3 mm mm and the center distance between the two pads is 0.5 mm. According to the current industry regulations, the width of the trace is 0.1mm, and the safety distance between the trace and the pad is 0.1 mm. This way there is no way to thread between the two pads.
本发明的实施例如图 1所示, 焊盘与焊盘之间的中心距离与现有技术一 样同为 0.5mm, 将焊盘直径设置为 0.27mm, BGA两个焊盘之间走线的线宽 设置为 0.075mm, 其余不是从 BGA焊盘之间走的线, 线宽设置为 0.1mm; 并 且将走线和焊盘之间的最小间距规则设为 0.075mm。 通过更改焊盘直径和焊 盘之间走线的宽度, 走线和焊盘之间的间距是( 0.5mm-0.27mm-0.075mm ) /2=0.0775mm, 可以满足走线和焊盘之间最小间距是 0.075mm的要求, 实现 了将内排的焊盘从外排焊盘之间穿线出来。 经过验证, 调整焊盘直径以及走 线与焊盘之间的间距, 可以满足移动通信终端的功能需求和量产需求。 The embodiment of the present invention is as shown in FIG. 1. The center distance between the pad and the pad is 0.5 mm as in the prior art, and the pad diameter is set to 0.27 mm, and the line between the two pads of the BGA is traced. The width is set to 0.075mm, the rest is not the line from the BGA pad, the line width is set to 0.1mm; and the minimum spacing rule between the trace and the pad is set to 0.075mm. By changing the pad diameter and the width of the trace between the pads, the spacing between the trace and the pad is (0.5mm-0.27mm-0.075mm) /2=0.0775mm, which can satisfy the trace between the trace and the pad. The minimum pitch is 0.075mm, which allows the pads of the inner row to be routed from between the outer pads. Verified, adjust pad diameter and go The spacing between the lines and the pads can meet the functional requirements and mass production requirements of the mobile communication terminal.
图 1所示的主芯片中, 两个椭圓所标识的位置较多地釆用了上述将焊盘 直径设置为 0.27mm以及 BGA两个焊盘之间走线的线宽设置为 0.075mm的工 艺。 当然图 1所示的主芯片, 其余地方也有该种工艺的应用。  In the main chip shown in FIG. 1, the positions indicated by the two ellipses are more commonly used. The above-mentioned pad diameter is set to 0.27 mm and the line width between the two pads of the BGA is set to 0.075 mm. Process. Of course, the main chip shown in Figure 1, the rest of the place also has the application of this process.
本发明实施例的两层印制电路板中, VB AT线路在表层, 在 VBAT线路 上设置容量大于等于 22微法(uF )的第一电容, 该第一电容比如是钽电容或 者陶瓷电容。 该第一电容可以有效消除电源上的干扰, 防止 VBAT电压下降 明显影响射频相位, 对射频指标和系统的稳定性均有很大程度的提升。 在本 实施例中, VBAT线路上的该第一电容尽量靠近电池连接器。  In the two-layer printed circuit board of the embodiment of the present invention, the VB AT line is on the surface layer, and a first capacitor having a capacity of 22 microfarads (uF) or more is provided on the VBAT line, and the first capacitor is, for example, a tantalum capacitor or a ceramic capacitor. The first capacitor can effectively eliminate the interference on the power supply, prevent the voltage drop of the VBAT from significantly affecting the RF phase, and greatly improve the stability of the RF index and the system. In this embodiment, the first capacitor on the VBAT line is as close as possible to the battery connector.
另外, 在两层印制电路板中, PCB A ( Printed Cirruit Board + Assembly , In addition, in a two-layer printed circuit board, PCB A (Printed Cirruit Board + Assembly,
PCB空板经过表面组装技术上件, 再经过 DIP插件的整个制程)线路在上电 后, 存在着板子发出声音的可能。 本发明的实施例在 VBAT线路上再设置容 量大于等于 22uF的第二电容, 可以有效消除 PCBA线路可能发出的声响; 其 中该第二电容为钽电容。 图 2为本发明的实施例设置有第一电容和第二电容 的结构示意图, 其中第二电容设置在尽量靠近基带处理芯片的位置。 图 2所 示的实施例中, 左侧的椭圓标识的是第一电容的位置, 右侧的椭圓标识的是 第二电容的位置, 其中第一电容和第二电容均为钽电容。 在本发明的实施例中, 主芯片的主要地焊盘背面是一个完整的地平面。 另外, 将有些容易受到干扰的地焊盘引出到外面打孔, 比如将 C7管脚和 C8 管脚拉到外面打地孔。如此处理, 避免了音频上产生时分双工(Time Division Distortion, TDD ) NOISE (时分双工通讯方式下产生的一种因射频模块周期 性地发送和接收信息而引起的噪声) 。 图 3中的椭圓中的铺铜区是地平面, 椭圓中的接地管脚是芯片的主要接地管脚。 After the PCB empty board passes the surface assembly technology and then passes through the entire process of the DIP plug-in, after the power is turned on, there is a possibility that the board emits sound. The embodiment of the present invention further sets a second capacitor having a capacity of 22 uF or more on the VBAT line, which can effectively eliminate the sound that may be emitted from the PCBA line; wherein the second capacitor is a tantalum capacitor. 2 is a schematic structural view of a first capacitor and a second capacitor according to an embodiment of the present invention, wherein the second capacitor is disposed as close as possible to the baseband processing chip. In the embodiment shown in FIG. 2, the ellipse on the left side indicates the position of the first capacitor, and the ellipse on the right side indicates the position of the second capacitor, wherein the first capacitor and the second capacitor are tantalum capacitors. In an embodiment of the invention, the main pad back of the master chip is a complete ground plane. In addition, some of the easily disturbed ground pads are led out to the outside, such as pulling the C7 and C8 pins to the outside. In this way, Time Division Distortion (TDD) NOISE is generated on the audio (a noise generated by the radio frequency module periodically transmitting and receiving information generated by the time division duplex communication mode). The copper area in the ellipse in Figure 3 is the ground plane, and the ground pin in the ellipse is the main grounding pin of the chip.
存储器 (MEMEORY ) 的时钟频率比较高, 可以达到几十或上百兆赫兹 ( MHz ) 。 如果存储器的时钟线和数据线暴露在外面, 或者跟其它敏感走线 背靠背地设置在一起, 则可能会给系统的稳定性带来一定风险。 在本发明的 实施例如图 4所示, 存储器(MEMORY )的时钟线和数据线(图 4中椭圓内 显示的高亮度线)在从基带芯片引出来时, 其背面是完整的地平面。  The memory (MEMEORY) has a high clock frequency that can reach tens or hundreds of megahertz (MHz). If the clock and data lines of the memory are exposed outside, or are placed back to back with other sensitive traces, there may be some risk to the stability of the system. In the embodiment of the present invention, as shown in Fig. 4, the clock line and the data line of the memory (MEMORY) (the high-brightness line shown in the ellipse in Fig. 4) are taken out from the baseband chip, and the back side thereof is a complete ground plane.
图 5是本发明实施例印刷二层印制电路板的流程示意图。 如图 5所示, 本发明的实施例在印刷基于 MT6251平台的两层印制电路板中的过程中, 主 要包含了如下步骤: FIG. 5 is a schematic flow chart of printing a two-layer printed circuit board according to an embodiment of the present invention. As shown in Figure 5, In the process of printing a two-layer printed circuit board based on the MT6251 platform, the embodiment of the present invention mainly includes the following steps:
将两层印制电路板上的焊盘与焊盘之间的中心距离设置为与现有技术一 样同为 0.5mm, 将焊盘直径设置为 0.27mm, 且将两个焊盘之间走线的线宽设 置为 0.075mm, 将走线与焊盘之间的最小间距设置为 0.075毫米。 这样, 走 线和焊盘之间的间 巨是 ( 0.5mm-0.27mm-0.075mm ) /2=0.0775mm, 将内排的 焊盘从外排焊盘之间穿线出来。  Set the center distance between the pad and the pad on the two-layer printed circuit board to be 0.5 mm as in the prior art, set the pad diameter to 0.27 mm, and route the two pads. The line width is set to 0.075 mm, and the minimum spacing between the trace and the pad is set to 0.075 mm. Thus, the space between the trace and the pad is (0.5mm-0.27mm-0.075mm) /2=0.0775mm, and the pads of the inner row are routed from the outer pads.
在两层印制电路板上的 VBAT线路上尽量靠近电池连接器的位置设置第 一电容(比如钽电容, 也可以是陶瓷电容等) , 其容量大于等于 22uF, 可以 有效消除电源上的干扰, 对射频指标和系统的稳定性均有很大程度的提升。  Set the first capacitor (such as tantalum capacitor or ceramic capacitor) on the VBAT line on the two-layer printed circuit board as close as possible to the battery connector. Its capacity is 22uF or more, which can effectively eliminate the interference on the power supply. The RF indicators and the stability of the system have been greatly improved.
在两层印制电路板上的 VBAT线路上尽量靠近基带处理芯片的位置设置 第二电容(钽电容) , 其容量大于等于 22uF, 可以有效消除 PCBA线路可能 发出的声响。  The second capacitor (tantalum capacitor) is placed on the VBAT line on the two-layer printed circuit board as close as possible to the baseband processing chip. Its capacity is 22uF or more, which can effectively eliminate the sound of the PCBA line.
将两层印制电路板上主芯片的主要地焊盘背面设置为完整的地平面, 将 有些容易受到干扰的地焊盘引出到外面打孔, 比如将 C7管脚和 C8管脚引出 到外面打地孔, 有效避免了音频上产生 TDD NOISE。  The main ground pad back of the main chip on the two-layer printed circuit board is set to a complete ground plane, and some easily disturbed ground pads are led out to punch holes, for example, the C7 pin and the C8 pin are taken out to the outside. Playing the hole, effectively avoiding TDD NOISE on the audio.
在两层印制电路板上存储器(MEMORY )的时钟线和数据线从基带芯片 引出的位置, 将时钟线和数据线的背面设置为完整的地平面, 降低了存储器 的时钟线和数据线暴露在外面, 或者跟其它敏感走线背靠背地设置在一起而 带来的系统稳定性方面的风险。  The clock line and the data line of the memory (MEMORY) on the two-layer printed circuit board are taken out from the baseband chip, and the back side of the clock line and the data line are set to a complete ground plane, which reduces the clock line and data line exposure of the memory. The risk of system stability on the outside, or with other sensitive traces placed back to back.
本发明的实施例还包括将前述的二层印制电路板应用到移动通信终端 中。 详情参见前述实施例中二层印制电路板的描述, 此处不做赞述。  Embodiments of the present invention also include applying the aforementioned two-layer printed circuit board to a mobile communication terminal. For details, refer to the description of the two-layer printed circuit board in the foregoing embodiment, which is not mentioned here.
本发明的实施例通过缩小焊盘直径以及 BGA内部部分走线的线宽,实现 了将内排的焊盘从外排焊盘之间穿线出来, 保证了移动通信终端的功能需求 和量产需求。 本发明的实施例通过在 VBAT线路上设置第一钽电容, 有效消 除了电源上的干扰, 对射频指标和系统的稳定性均有很大程度的提升。 本发 明的实施例通过在 VBAT线路上设置第二钽电容, 有效消除了 PCBA线路可 能发出的声响。 本发明的实施例通过将主芯片的地焊盘背面设置成相对完整 的地平面 ,避免了音频上产生 TDD NOISE„本发明的实施例通过在 MEMORY 的时钟和数据线的背面设置完整的地平面, 提高了系统的稳定性。 The embodiment of the present invention realizes the threading of the inner row of pads from the outer row pads by reducing the pad diameter and the line width of the inner portion of the BGA, thereby ensuring the functional requirements and mass production requirements of the mobile communication terminal. . The embodiment of the invention effectively eliminates the interference on the power supply by setting the first tantalum capacitor on the VBAT line, and greatly improves the stability of the radio frequency index and the system. Embodiments of the present invention effectively eliminate the possible sound of the PCBA line by providing a second tantalum capacitor on the VBAT line. Embodiments of the present invention set the back surface of the ground pad of the main chip to be relatively complete The ground plane avoids the generation of TDD NOISE on the audio. The embodiment of the present invention improves the stability of the system by setting a complete ground plane on the back of the MEMORY clock and data lines.
虽然本发明所揭露的实施方式如上, 但所述的内容只是为了便于理解本 发明而釆用的实施方式, 并非用以限定本发明。 任何本发明所属技术领域内 的技术人员, 在不脱离本发明所揭露的精神和范围的前提下, 可以在实施的 形式上及细节上作任何的修改与变化, 但本发明的专利保护范围, 仍须以所 附的权利要求书所界定的范围为准。  While the embodiments of the present invention have been described above, the described embodiments are merely for the purpose of understanding the invention and are not intended to limit the invention. Any modification and variation of the form and details of the invention may be made by those skilled in the art without departing from the spirit and scope of the invention. It is still subject to the scope defined by the appended claims.
工业实用性 本发明实施例的二层印制电路板在应用到移动通信终端时, 可以保证移 动通信终端功能正常, 相比现有釆用四层印制电路板或者六层印制电路板的 移动通信终端, 在不损失功能的前提下明显降低了成本, 提高了产品竟争优 势。 INDUSTRIAL APPLICABILITY When applied to a mobile communication terminal, the two-layer printed circuit board of the embodiment of the present invention can ensure that the function of the mobile communication terminal is normal, compared with the existing four-layer printed circuit board or six-layer printed circuit board. The mobile communication terminal significantly reduces the cost and improves the competitive advantage of the product without losing the function.

Claims

权 利 要 求 书 Claim
1、 一种两层印制电路板, 基于 MT6251平台, 在该两层印制电路板中: 焊盘直径为 0.27毫米, 两个焊盘之间走线的线宽为 0.075毫米, 走线与 焊盘之间的最小间距为 0.075 毫米, 内排的焊盘是从外排焊盘之间穿线出来 的, 主芯片的主要地焊盘背面为完整的地平面, C7管脚和 C8管脚是引出到 外面后打地孔的。 1. A two-layer printed circuit board based on the MT6251 platform. In the two-layer printed circuit board: the pad diameter is 0.27 mm, and the line width between the two pads is 0.075 mm. The minimum spacing between the pads is 0.075 mm. The pads in the inner row are routed from the outer pad. The main pad on the main chip has a complete ground plane. The C7 and C8 pins are Lead out to the outside and hit the hole.
2、 根据权利要求 1所述的两层印制电路板, 其中: 2. A two-layer printed circuit board according to claim 1, wherein:
所述两层印制电路板上的供电电源 VBAT线路上设置有第一电容。  A first capacitor is disposed on the power supply VBAT line of the two-layer printed circuit board.
3、 根据权利要求 1所述的两层印制电路板, 其中: 3. The two-layer printed circuit board of claim 1 wherein:
所述两层印制电路板上的 VBAT线路上设置有第二电容。  A second capacitor is disposed on the VBAT line on the two-layer printed circuit board.
4、 根据权利要求 3所述的两层印制电路板, 其中: 4. The two-layer printed circuit board of claim 3, wherein:
所述第二电容为钽电容。  The second capacitor is a tantalum capacitor.
5、 根据权利要求 1所述的两层印制电路板, 其中: 5. The two-layer printed circuit board of claim 1 wherein:
在所述两层印制电路板上存储器的时钟线和数据线从基带芯片引出的位 置, 所述存储器的时钟线和数据线的背面为完整的地平面。  The clock lines and data lines of the memory on the two-layer printed circuit board are taken out from the baseband chip, and the clock lines of the memory and the back side of the data lines are complete ground planes.
6、 一种两层印制电路板的印刷方法, 用于印刷基于 MT6251平台的两层 印制电路板, 该方法包括: 6. A two-layer printed circuit board printing method for printing a two-layer printed circuit board based on the MT6251 platform, the method comprising:
将两层印制电路板上的焊盘直径设置为 0.27毫米, 将两个焊盘之间走线 的线宽设置为 0.075毫米, 将走线与焊盘之间的最小间距设置为 0.075毫米, 内排的焊盘从外排焊盘之间穿线出来, 将主芯片的主要地焊盘背面设置为完 整的地平面, 将 C7管脚和 C8管脚引出到外面打地孔。  Set the pad diameter on the two-layer printed circuit board to 0.27 mm, the line width between the two pads to 0.075 mm, and the minimum distance between the trace and the pad to 0.075 mm. The pads of the inner row are threaded out from the outer row pads, and the back surface of the main pad of the main chip is set to a complete ground plane, and the C7 pin and the C8 pin are led out to the outside ground hole.
7、 根据权利要求 6所述的印刷方法, 其中: 7. The printing method according to claim 6, wherein:
在所述两层印制电路板上的供电电源 VBAT线路上设置第一电容。  A first capacitor is disposed on the power supply VBAT line of the two-layer printed circuit board.
8、 根据权利要求 6所述的印刷方法, 其中: 在所述两层印制电路板上的 VBAT线路上设置第二电容。 8. The printing method according to claim 6, wherein: A second capacitor is disposed on the VBAT line on the two-layer printed circuit board.
9、 根据权利要求 6所述的印刷方法, 其中: 9. The printing method according to claim 6, wherein:
在所述两层印制电路板上存储器的时钟线和数据线从基带芯片引出的位 置, 将所述存储器的时钟线和数据线的背面设置为完整的地平面。  The clock lines and data lines of the memory are placed at a position from the baseband chip on the two-layer printed circuit board, and the clock lines of the memory and the back side of the data lines are set to a complete ground plane.
10、 一种移动通信终端, 包含如权利要求 1至 5中任一项权利要求所述 的两层印制电路板。 A mobile communication terminal comprising the two-layer printed circuit board according to any one of claims 1 to 5.
PCT/CN2011/083665 2011-07-08 2011-12-08 Two-layer printed circuit board, printing method thereof, and mobile communication terminal WO2013007083A1 (en)

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