WO2012176031A1 - Method of fabrication of a semiconductor substrate and a semiconductor substrate - Google Patents
Method of fabrication of a semiconductor substrate and a semiconductor substrate Download PDFInfo
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- WO2012176031A1 WO2012176031A1 PCT/IB2012/001129 IB2012001129W WO2012176031A1 WO 2012176031 A1 WO2012176031 A1 WO 2012176031A1 IB 2012001129 W IB2012001129 W IB 2012001129W WO 2012176031 A1 WO2012176031 A1 WO 2012176031A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
Definitions
- the method further comprises a seventh step consisting .in reusing the donor substrate resulting from the sixth step and including the porous support layer for the fabrication of a new receiver substrate including at least part of a strained layer constituted of a third semiconductor material; - the seed layer has, after the third step, a lattice parameter having a maximum difference of 0.5% in absolute value relative to the lattice parameter of the material of the seed layer in the relaxed state; - the third material is silicon, the second material is SiGe, and the first material is silicon;
- FIG. 2 is a diagrammatic representation of an electrochemical anodization method
- FIG. 3 is a diagrammatic representation of another embodiment of the electrochemical anodization method
- the first material and the second material have different lattice parameters in the relaxed state.
- the results of the treatment enabling the support layer 2 to be made porous depend on various parameters, such as the type and the level of doping, the crystal orientation of the material of the layer, the current density, the composition and the concentration of the electrolyte, the temperature and the anodization time.
- the seed layer 3 has a lattice parameter equal to the lattice parameter of the material of the seed layer 3 in the relaxed state, or
- the seed layer 3' having in one embodiment a thickness in the range
- the method includes a sixth step E6 consisting in transferring at least part of the strained layer 5 constituted of the third material from the donor substrate 1 to a receiver substrate 8.
- Bonding the donor substrate 1 and the receiver substrate 8 is generally preceded by cleaning the surfaces of the substrates to enable improved molecular bonding.
- the confinement structure 23 comprising the confinement layer 25 is generally produced by epitaxial growth and is formed during the first step E1 of formation of the donor substrate 1.
- the confinement structure is generally disposed in the seed layer 3.
- a confinement layer is produced in one or more materials adapted to attract the ions introduced into the substrate towards said confinement layer during this temperature increasing heat treatment.
- Typical heat treatment temperatures are in the range 200°C to 700°C.
- the seed layer 3' constituted of the second material remains relaxed or in a state close to a relaxed state (as defined above) before its reuse, in contrast to the first embodiment.
- the seventh step E7 of reusing the donor substrate 1 includes the steps consisting in repeating the fifth and sixth steps of the fabrication method to fabricate a new receiver substrate including at least part of a strained layer 5 constituted of the third material.
- the donor substrate 1 still includes, after the sixth step E6, part of the strained layer 5, i.e. not all of the latter has been transferred after the sixth step E6.
- the method includes the steps consisting in applying cyclically the second, third, fourth, fifth, sixth and seventh steps for the fabrication of a plurality of receiver substrates including a strained layer 5 of the third material from a donor substrate 1 formed in the first step.
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Abstract
The invention concerns a fabrication method comprising the steps' consisting in forming a donor substrate (1) comprising a support layer (2) and a Strained seed layer (3), rendering the support layer (2) porous, treating the donor substrate (1) to deform in expansion or jn contraction the porous support layer (2') constituted of the first material, said deformation inducing relaxation in the seed layer (3'), increasing the thickness of the seed layer (3'), forming a strained layer (5) in contact with said seed layer (3'), and transferring at least part of the strained layer (5) from the donor substrate (1) to a receiver substrate (8).
Description
METHOD OF FABRICATION OF A SEMICONDUCTOR SUBSTRATE AND A SEMICONDUCTOR SUBSTRATE
GENERAL TECHNICAL FIELD
The invention concerns a method of fabrication of a semiconductor substrate and a semiconductor substrate.
PRIOR ART
Silicon on insulator (SOI) substrates are widely used in the microelectronics industry.
In particular, strained silicon on insulator (sSOl) substrates are of great benefit for the fabrication of electronic components, notably because sSOl substrates offer increased mobility of electrons and holes and thus higher performance.
A strained layer of a material is a layer of a material in which the crystal structure is strained in tension or in compression relative to the natural crystal structure of the material.
The strained silicon is generally, required to have the lowest possible density of defects.
A known prior art method of fabrication of strained silicon consists in epitaxial growth of a strained silicon layer on a first layer the lattice parameter whereof is different from the lattice parameter of the relaxed silicon. This first layer may be a buffer layer the composition of which may vary with its thickness.
Another known strained silicon fabrication method consists in using a substrate comprising a porous silicon layer in contact with a non-porous superficial silicon layer and expanding the porous silicon layer to induce stress in the superficial silicon layer.
By porous layer of a semiconductor material, such as a porous silicon layer, for example, means a layer of a microstructured material comprising pores.
A drawback common to the known sSOI fabrication methods, and more generally methods for fabrication of strained active layers, is that they are costly and lengthy.
The invention aims to overcome this drawback at least in part.
SUMMARY OF THE INVENTION
To this end, the invention proposes a method of fabrication of a semiconductor substrate, characterized in that it comprises:
- a first step consisting in forming a donor substrate comprising a support layer constituted of a first semiconductor material and a strained seed layer constituted of a second semiconductor material,
- a second step consisting in rendering the support layer porous,
- a third step consisting in treating the donor substrate to deform in expansion or in contraction the porous support layer constituted of the first material, said deformation inducing a relaxation in the seed layer,
- a fourth step consisting in increasing the thickness of the seed layer constituted of the second material by a step of growing said second material,
- a fifth step consisting in forming a strained layer constituted of a third semiconductor material in contact with said seed layer, and
- a sixth step consisting in transferring at least part of the strained layer constituted of the third material from the donor substrate to a receiver substrate.
The. invention is advantageously complemented by the following features, separately or in any technically feasible combination:
- the method further comprises a seventh step consisting .in reusing the donor substrate resulting from the sixth step and including the porous support layer for the fabrication of a new receiver substrate including at least part of a strained layer constituted of a third semiconductor material; - the seed layer has, after the third step, a lattice parameter having a maximum difference of 0.5% in absolute value relative to the lattice parameter of the material of the seed layer in the relaxed state;
- the third material is silicon, the second material is SiGe, and the first material is silicon;
- the seventh step of reuse of the donor substrate includes the steps consisting in:
- treating the donor substrate with a chemical solution to restrain the seed layer,
- with the donor substrate treated in this way, repeating the third, fourth, fifth and sixth steps of the fabrication method to fabricate a new receiver substrate including at least part of a strained layer constituted of a third semiconductor material;
- the seventh step of reuse of the donor substrate comprises the steps consisting in:
- polishing the seed layer constituted of the second material to obtained a polished donor substrate,
- with the polished donor substrate, repeating the fourth, fifth and sixth steps of the fabrication method to fabricate a new receiver substrate including at least part of a strained layer constituted of a third semiconductor material;
- the seventh step of reuse of the donor substrate comprises the steps consisting in repeating the fifth and sixth steps of the fabrication method to fabricate a new receiver substrate including at least part of a strained layer constituted of a third semiconductor material;
- the sixth step consisting in transferring the strained layer constituted of the third material from the donor substrate to the receiver substrate comprises the steps consisting in:
- creating a weakened area in the donor substrate by implantation of ions,
- bonding the donor substrate and the receiver substrate,
- producing a fracture in said weakened area to detach the donor substrate from the receiver substrate;
- the first step comprises a step of formation of a confinement structure comprising a semiconductor confinement layer in the donor substrate, said
confinement layer having a chemical composition different from the strained layer constituted of the third material, and the sixth step consisting in transferring the strained layer constituted of the third material from the donor substrate to the receiver substrate comprises the steps consisting in introducing ions into the donor substrate, bonding the donor substrate and the receiver substrate, and submitting the donor substrate and the receiver substrate to a heat treatment including an increase in temperature during which the confinement layer attracts the ions to concentrate them in said confinement layer, and detaching the donor substrate of the receiver substrate by fracture at the level of said confinement layer;
- the introduction of the ions into the donor substrate is effected by immersing the donor substrate in a plasma containing said ions;
- the method includes the steps consisting in cyclically applying the second, third, fourth, fifth, sixth and seventh steps to the fabrication of a plurality of receiver substrates comprising a strained layer of a third semiconductor material from a donor substrate formed in the first step.
The invention also provides a semiconductor substrate comprising successively a porous support layer constituted of a first semiconductor material, a seed layer constituted of a second semiconductor material having a lattice parameter in the relaxed state different from the lattice parameter in the relaxed state of the first material and having a lattice parameter having a maximum difference of 0.5% in absolute value relative to the lattice parameter of the material of the seed layer in the relaxed state, and a strained layer constituted of a third semiconductor material.
The substrate advantageously has the following features, separately or in combination:
- the seed layer has a thickness in the range 10 nm to 5 microns.
- the seed layer has a lattice parameter equal to the lattice parameter of the material of the seed layer in the relaxed state.
- the first material is silicon, the second material is SiGe, and the third material is silicon.
The invention has numerous advantages and notably makes it possible to reduce the fabrication time of strained layers of good crystalline quality and likewise the associated fabrication costs. BRIEF DESCRIPTION OF THE DRAWINGS
Other features, objects and advantages of the invention will emerge from the following description, which is purely illustrative and non-limiting, and which should be read with reference to the appended drawings, in which:
- Figure 1 is a diagrammatic representation of one embodiment of the method of the invention;
- Figure 2 is a diagrammatic representation of an electrochemical anodization method;
- Figure 3 is a diagrammatic representation of another embodiment of the electrochemical anodization method;
- Figure 4 is a diagrammatic representation of one way to transfer a strained layer;
- Figure 5 is a diagrammatic representation of the distribution of ions in a substrate after their introduction by diffusion and implantation;
- Figure 6 is a diagrammatic representation of one embodiment of a recycling step of the method of the invention;
- Figure 7 is a diagrammatic representation of another embodiment of a recycling step of the method of the invention; and
- Figure 8 is a diagrammatic representation of a further embodiment of a recycling step of the method of the invention.
DETAILED DESCRIPTION
There is shown in Figure 1 one embodiment of a semiconductor substrate fabrication method of the invention.
The method includes a first step E1 consisting in forming a donor substrate 1.
The donor substrate 1 comprises:
a support layer 2 constituted of a first semiconductor material, and
a strained seed layer 3 constituted of a second semiconductor material.
The expression "strained layer" refers to any layer of a semiconductor material the crystal structure of which is strained in tension or in compression relative to the natural crystal structure of the material. For example, it is possible to obtain strained layers during crystal growth, such as epitaxial growth, which modifies the crystal lattice.
Conversely, the expression "relaxed layer" refers to any layer of a semiconductor material that has a crystal structure free of any applied external strain, i.e. that has a lattice parameter identical to the lattice parameter of a layer of this material in solid monocrystalline form.
The first material and the second material have different lattice parameters in the relaxed state.
Accordingly, these may be materials constituted of different chemical elements (for example Si and SiGe) or materials constituted of identical chemical elements but with different chemical element proportions (for example two layers of SiGe with a different proportion of germanium).
The first material is for example silicon, germanium or a material of type lll-V (an alloy of an element from the third column of the periodic table of the elements and an element from the fifth column of the periodic table of the elements).
The seed layer 3 constituted of the second semiconductor material is generally fabricated by epitaxial growth on the support layer 2 constituted of the first semiconductor material.
It is for example an SiGe seed layer 3 obtained by epitaxial growth from a silicon support layer 2.
In one advantageous embodiment, the seed layer 3 constituted of the second material is formed with a thickness less than its critical thickness to prevent strain relaxation and the appearance of defects.
The critical thickness of a layer of a given material is known to the person skilled in the art and corresponds to the thickness from which strain relaxation is observed.
For example, in the situation where the second material is SiGe, i.e. in the case of an SiGe seed layer 3, the critical thickness of said layer 3 is of the order of 50 nm if the germanium content of this alloy is around 20%.
The method includes a second step E2 consisting in rendering the support layer 2 porous.
A porous layer of a semiconductor material is a layer of a microstructured material comprising pores. The pores constitute voids between the crystallites of the material.
The porosity of the material is defined as the unoccupied volume (pores) fraction within the material. Other parameters may be used to characterize the porous layer (pore size, morphology, thickness, pore diameter, size of crystallites, specific surface area, etc.).
For example, in the situation where the material is silicon, it is a matter of porous silicon, generally classified into three categories by the person skilled in the art:
- macroporous silicon, generally obtained from weakly doped type n silicon;
- mesoporous silicon, generally obtained from strongly doped p+ or n+ silicon, and
- nanoporous silicon, generally obtained from weakly doped type p silicon.
The second step E2 advantageously includes a step of electrochemical anodization of the donor substrate 1 , shown in Figure 2.
One embodiment of such electrochemical anodization is shown in Figure 2.
The donor substrate 1 is placed in an enclosure 10 containing an electrolyte 11.
The electrolyte 11 is for example a solution containing hydrofluoric (HF) acid.
An anode 12 and a cathode 13, dipping into the electrolyte 11 , are connected to an electrical current source 14.
The donor substrate 1 is positioned so that the support layer 2 is turned toward the cathode 13 and so that the layer 3 is turned toward the anode 12.
An electric current is applied between the anode 12 and the cathode 13 by the electrical current source 14.
This electric current is generally constant.
At the end of anodization, the donor substrate 1 is rinsed.
The support layer 2 is advantageously p-doped, which enables acceleration of anodization.
Another electrochemical anodization method, known as the "double bath" cell method, is shown in Figure 3.
The enclosure 10 comprises two half-reservoirs each containing an electrolyte 11 , for example an HF/ethanol mixture.
The donor substrate 1 acts as a barrier between the two half- reservoirs, which do not communicate with each other.
The enclosure 10 is generally a PTFE tank and includes O-rings 16 disposed between the donor substrate 1 and the electrolyte 11.
As in the previous embodiment, two electrodes 12 and 13, for example of platinum, constitute the anode and the cathode and are connected to an electrical current source 14.
In all cases, the results of the treatment enabling the support layer 2 to be made porous depend on various parameters, such as the type and the level of doping, the crystal orientation of the material of the layer, the current density, the composition and the concentration of the electrolyte, the temperature and the anodization time.
The method includes a third step E3 consisting in treating the donor substrate 1 so as to deform by expansion or by contraction the porous support layer 2' constituted of the first material, said, deformation inducing relaxation in the seed layer 3.
The porous support layer 2' deformed in this way will induce strains in the seed layer 3, causing relaxation in said seed layer 3.
The deformation of the porous support layer 2' may be either an expansion or a contraction. Expansion corresponds to an expansion of the material, i.e. a deformation of the material in tension, while contraction corresponds to retraction of the material, i.e. deformation of the material in compression.
Depending on the degree of deformation of the porous support layer 2' constituted of the first material, the seed layer 3 constituted of the second material may become:
- relaxed, i.e. the seed layer 3 has a lattice parameter equal to the lattice parameter of the material of the seed layer 3 in the relaxed state, or
- in a state close to the relaxed state, i.e. the seed layer 3 has a lattice parameter having a maximum difference of 0.5% in absolute value relative to the lattice parameter of the material of the seed layer 3 in the relaxed state.
The seed layer E3 resulting from the third step is designated by the reference 3' in the figures.
In the situation where the seed layer 3 is relaxed, the critical thickness is virtually infinite.
In the situation where the seed layer 3 is in a state close to the relaxed state (0.5% relative difference - see above), the seed layer 3 has a strain sufficiently small for its critical thickness to be greatly increased. Accordingly, the critical thickness of the seed layer 3 may in this case reach several hundred nanometres, or even several micrometres, depending on circumstances.
In one embodiment, the third step E3 may consist in subjecting the donor substrate 1 to a heat treatment (for example at a temperature in the range 200°C to 800°C), in an atmosphere that may be an oxidizing atmosphere (for example containing 02, N02, etc.)
In another embodiment, the third step E3 may include nitriding, which generally enables generation of compression strains and thus deformation in contraction of the support layer 2', which induces relaxation in the seed layer 3 (for example, deformation in contraction of a porous silicon support layer 2').
The third step E3 causes deformation of the porous support layer 2' constituted of the first material and thus induces relaxation in the seed layer 3 constituted of the second material.
The method includes a fourth step E4 consisting in increasing the thickness of said seed layer 3' constituted of the second material by a step of growth of said second material. This is generally epitaxial growth.
Thanks to the relaxed state, or the state close to the relaxed state, of the seed layer 3', it is possible to grow a thick layer of the second material without being limited by the critical thickness.
For example, the fourth step E4 includes the formation of a seed layer 3' constituted of the second semiconductor material with a thickness in the range 10 nm to 500 nm, or up to several micrometres (for example 5 micrometers) depending on the method of recycling the substrate that is to be used. Remember, of course, that when the seed layer 3 is relaxed, the critical thickness is virtually infinite, and that the thickness of the seed layer 3 may thus be increased at will during the fourth step E4.
The method further includes a fifth step E5 consisting in forming a strained layer 5 constituted of a third semiconductor material in contact with said seed layer 3' constituted of the second material.
The third material and the second material have different lattice parameters in the relaxed state.
Accordingly, it may be a question of materials constituted of different chemical elements (for example Si and SiGe) or of materials constituted of identical chemical elements but with different chemical element proportions (for example SiGe with 40% germanium for the third material and SiGe with 20% germanium for the second material).
This strained layer 5 is generally formed by epitaxial growth.
After the fifth step E5, there is obtained a semiconductor substrate comprising successively:
- a porous support layer 2 constituted of the first semiconductor material,
- a seed layer 3'
- constituted of a second semiconductor material, having a lattice parameter in the relaxed state different from the lattice parameter in the relaxed state of the first material, and having a lattice parameter having a maximum difference of 0.5% in absolute value relative to the lattice parameter of the material of the seed layer 3 in the relaxed state, and
- a strained layer 5 constituted of the third semiconductor material.
The seed layer 3' having in one embodiment a thickness in the range
10 nm to 5 microns.
The seed layer 3' advantageously has a lattice parameter equal to the lattice parameter of the material of the seed layer 3 in the relaxed state. It is thus a matter of complete relaxation of the seed layer 3'.
It is advantageous if the first material is silicon, the second material is SiGe, and the third material is silicon.
Thus the invention enables a substrate to be obtained at this stage including the strained layer 5, which is in fact the active layer of the semiconductor substrate, notably for the fabrication of micro-electronic devices, said strained layer 5 having been obtained by growing it on the thick relaxed seed layer.
This thick relaxed seed layer, not limited by its critical thickness, has been obtained by the method described above, notably including the porous support layer of the first material.
Given that this relaxed seed layer is thick, it may be reused and recycled, as explained hereinafter, and likewise the porous support layer.
Moreover, as the seed layer 3' is relaxed, or in a state close to the relaxed state, this enables growth of a strained layer 5 constituted of a third semiconductor material without creating defects.
In one embodiment, the third material is silicon, but it may be other materials, for example germanium, depending on the intended applications of the strained layer. In one embodiment the second material is SiGe. In one embodiment the first material is silicon. These embodiments may be combined.
The method includes a sixth step E6 consisting in transferring at least part of the strained layer 5 constituted of the third material from the donor substrate 1 to a receiver substrate 8.
In one embodiment, the sixth step E6 comprises the steps consisting in:
- creating a weakened area 20 in the donor substrate 1 by ion implantation,
- , bonding the donor substrate 1 and the receiver substrate 8, and
- producing a fracture at the level of said weakened area 20 to detach the donor substrate 1 from the receiver substrate 8.
The weakened area 20 is generally created in the seed layer 3' constituted of the second material.
The weakened area 20 is created by implanting ions, such as hydrogen ions, helium ions, boron ions, or a combination of hydrogen ions and the latter ions. The Smart Cut™ method is advantageously used.
Bonding the donor substrate 1 and the receiver substrate 8 is generally preceded by cleaning the surfaces of the substrates to enable improved molecular bonding.
Fracture is produced by an increase in temperature, generally in the range 200°C to 700°C.
The receiver substrate 8 advantageously includes an oxide layer 4 and the bonding of the donor substrate 1 and the receiver substrate 8 is effected between the oxide layer 4 and the strained layer 5 constituted of the third material.
Alternatively, or in addition, the donor substrate 1 also includes an oxide layer on top of the strained layer 5 constituted of the third material.
The weakened area 20 may also be created within the strained layer 5 itself.
The strained semiconductor layer 5 may be transferred from the donor substrate 1 to the receiver'substrate 8 after constituting in the donor substrate a weakened area at the level of which a fracture may be produced to effect the transfer.
The weakened area may have been constituted by implantation in the donor substrate as described above.
In this case, the ions are accelerated in the direction of the donor substrate surface. The mean depth of penetration of the atoms is generally in the range 100 A to~1 μιη; this depth may be determined as a function of the species implanted and the implantation energy. In the case of implantation, this features an implantation peak in the donor substrate. The ions implanted have an energy selected to enable them to pass through the material of the donor substrate. The implantation peak depends on the energy of the ions.
It may equally have been constituted differently, for example in the manner described hereinafter.
Thus an embodiment is described of the sixth step E6 of transferring the strained layer 5 constituted of the third semiconductor material from the donor substrate 1 to a receiver substrate 8.
This embodiment is shown in Figure 4.
In this embodiment, the donor substrate 1 further includes a confinement structure 23 comprising a confinement layer 25 formed of a semiconductor material.
The role of this confinement layer 25 is to attract the ions subsequently introduced into the donor substrate (for example by diffusion) during thermal annealing of the donor substrate after this introduction and during which the ions will migrate preferentially to the confinement layer 25.
The confinement structure 23 comprising the confinement layer 25 is generally produced by epitaxial growth and is formed during the first step E1
of formation of the donor substrate 1. The confinement structure is generally disposed in the seed layer 3.
The epitaxial process enables precise control of the thickness of the confinement layer 23 and enables small thicknesses thereof to be obtained.
Moreover, epitaxial growth enables preservation of the crystallinity of the seed layer 3' destined to serve as a seed for the fabrication of the strained layer 5 constituted of the third semiconductor material.
The material of the confinement layer is advantageously chosen from doped or undoped SiGe, or doped silicon. Other materials notably include germanium doped with boron, SiC doped with boron, and doped or undoped InGaN, AIGaN, InGaAs, AIGaAs.
Doping with boron, arsenic or antimony may be used, for example.
Other materials and other dopants may be used. In all cases, the confinement layer is constituted of a material having a different chemical composition to the strained layer 5 to be transferred, which includes a difference at least in the proportions of the chemical elements (e.g. SiGe with a different proportion of germanium), or in the type of material (e.g. SiGe for the layer 25 and Si for the layer 5), or in the fact that the confinement layer is more highly doped than the strained layer 5 to be transferred (e.g. SiGe doped with boron for the layer 25 and undoped or less doped SiGe for the layer 3), or a combination of these differences.
To enable transfer of the strained layer 5, the sixth transfer step E6 includes a step E61 of introduction of ions 24 into the donor substrate 1.
These ions are advantageously hydrogen and/or helium ions.
They may be introduced in various ways.
The ions 24 are advantageously introduced into the donor substrate 1 by diffusion of the ions 24 into the donor substrate 1 following immersion of the donor substrate 1 in a plasma containing said ions. This introduction of ions 24into the donor substrate 1 may be effected by techniques other than diffusion, for example by implantation.
The donor substrate 1 immersed in the plasma is subjected to electrical pulses. Positive ions present in the plasma are then accelerated
toward the surface of the substrate into which they are introduced. As the plasma surrounds the substrate, all of the surface receives ions at the same time.
Another advantage of this ion introduction is its capacity to be applied on an industrial scale/as well as the short implementation time.
Another advantage of this ion implantation is that the area of diffusion of the ions into the donor substrate is very concentrated, of the order of a few nanometres thick in the direction normal to the main faces of the substrate (for example in the range 10 nm to 200 nm).
Ion introduction by plasma diffusion thus enables good results to be obtained in the transfer step in that this technique notably enables enrichment of the donor substrate 1 with ions of low acceleration voltage (about 10 V to 50 kV) with a high dosage (up to 1018 atoms/cm2) in a shallow region (with a depth from a few tens of nanometres to around 200 nanometres, as mentioned above), which is not always accessible with an implantation technique. This is advantageous for subsequently transferring thin layers of the layer 5 to be transferred. As explained hereinafter, this is advantageous for reducing the defects and roughness present in the transferred layer.
Even if the region is accessible for implantation, the high energy of the ions in the implantation process leads to the introduction of crystal defects into the layer 5 to be transferred, making its subsequent use difficult.
Figure 5 shows the concentration profile of the ions 24 in the donor substrate 1 as a function of the depth in the donor substrate 1 , in the case of diffusion (curve 26) and in the case of ion implantation (curve 27).
The sixth transfer step further includes a step E62 consisting in bonding the donor substrate 1 and the receiver substrate 8.
This bonding is effected by bringing into contact free surfaces of the donor substrate and the receiver substrate. These surfaces have usually been cleaned beforehand to ensure molecular adhesion of said surfaces.
The sixth transfer step then includes a step E63 of heat treatment of the donor substrate and the receiver substrate consisting in subjecting thern to an increase in temperature.
If a confinement layer has been constituted, that layer is produced in one or more materials adapted to attract the ions introduced into the substrate towards said confinement layer during this temperature increasing heat treatment. Typical heat treatment temperatures are in the range 200°C to 700°C.
For example, if the material of the confinement layer is silicon doped with boron and the ions introduced into the donor substrate are hydrogen ions, chemical interactions between the boron and the hydrogen will notably enable attraction of the hydrogen ions into the confinement layer. Another ion attraction factor may result from the strain difference (in tension or compression).
Accordingly, during the heat treatment of the donor substrate and the receiver substrate, the confinement layer attracts the ions to concentrate them in said confinement layer.
Another function of this heat treatment may be to strengthen the bonding energy between the donor substrate and the receiver substrate.
Annealing is carried out so that different effects are produced:
- the bonding energy between the donor substrate and th4e receiver substrate is increased,
- the ions are concentrated in the confinement layer until a critical concentration is reached,
- these ions create cavities, which will coalesce,
- the pressure in these cavities increases until it causes a fracture in the confinement layer, which enables separation of the donor substrate from the receiver substrate.
These four effects may be obtained during a single thermal annealing step or during separate individual thermal annealing steps.
Accordingly, the next step of the heat treatment is a step E64 consisting in detaching the donor substrate 1 from the receive substrate 8 by fracture at the level of said confinement layer 25.
Thus the layer 5 constituted of the third semiconductor material is transferred:
The receiver substrate 8 is then treated by cleaning and polishing (CMP or otherwise) in order to eliminate residues of unwanted layers. This means in particular the residual confinement layer that has been transferred with the strained semiconductor layer.
The donor substrate 1 is also treated in order to be recycled, where appropriate, in the context of transferring a hew strained layer 5 constituted of a third semiconductor material (step E7).
An advantage of this transfer method using the constitution of a confinement layer is that the fracture is highly localized, and occurs virtually uniquely or even uniquely only at the level of the confinement layer.
The post-fracture AFM roughnesses obtained with no confinement layer are typically of the order of 3 to 6 nm, but the confinement layer enables this roughness to be reduced to values of the order of 0.5 to 1 nm. This prevents the propagation of defects towards the strained semiconductor layer to be transferred. In the case of a classic transfer by ion implantation and fracture at the level of a weakened area without using a confinement layer, it is common for defects to appear in the substrate after fracture. This is notably caused by the extensive presence of ions in the substrate, which induces a fracture that is not localized and therefore a higher roughness.
The strained semiconductor layer 5 transferred by this method therefore has a reduced roughness. In the case of a donor structure 1 including a silicon layer 5 to be transferred and a confinement layer 23 of silicon doped with boron, for example, a roughness of the transferred silicon layer of 5 Angstrom units may be obtained (RMS value).
Moreover, it is often necessary to transfer strained semiconductor layers 5 having a small thickness (for example in the range 20 nm to
500 nm). It is known that there exists a compromise between the strain present in the layer and the thickness of said layer. For a given strain, there exists a thickness beyond which the strain is relaxed through the appearance of defects.
This embodiment of the sixth step thus notably enables transfer of strained semiconductor layers 5 having a thickness in the range 10 nm to 200 nm.
A confinement layer having a thickness in the range 2 nm to 20 nm is advantageously used. The thinner the confinement layer, the more localized the fracture. For example, a confinement layer approximately 4 nm thick will enable the fracture to be confined within this area.
Given the small thickness of the confinement layer, this layer does not interfere much if at all with the lattice parameter of the donor substrate.
It is generally possible to use a confinement structure 23 comprising a confinement layer 25 as described above and two protection layers disposed in contact with and on either side of the confinement layer, each of these protection layers being formed of a semiconductor material with a different chemical composition to the material of the confinement layer. The expression "different chemical composition" means that the materials are different or have chemical element proportions and/or are doped with a different dopant.
The transfer is implemented with the confinement structure in a similar manner to what has been described for the confinement layer.
These protection layers further limit the propagation of defects resulting from the fracture. The latter notably act as shields protecting the strained semiconductor layer 5 to be transferred and confine defects liable to propagate toward the strained layer 5 after the fracture in the confinement layer.
The materials of the protection layers advantageously also adapted to attract the ions introduced into the donor substrate toward the confinement layer during a heat treatment of said donor substrate increasing its temperature.
Embodiments include for the protection layers, by way of nonlimiting example:
- material of protection layers: Si(1.X)Gex, material of confinement layer:
Si(i-y)Gey (advantageous, the difference between x and y is at least 3%, preferably greater than 5%, even 10%), SiGe doped with boron or silicon doped with boron. There may also be cited the situation where the protection layers are of SiGe and the confinement layer of boron-doped silicon, and likewise the situation in which the protection layers are of SiGe and the confinement layer is of Ge doped with boron;
- material of protection layers: silicon, material of confinement layer:
Si(i.y)Gey, SiGe doped with boron or silicon doped with boron;
- material of protection layers: germanium, material of confinement layer: SiGe doped with boron or silicon doped with boron or germanium doped with boron or SiGe;
- material of protection layers: SiGe, material of confinement layer: SiC doped with boron;
- material of protection layers: AIGaN, material of confinement layer:
InGaN doped (Si, Mg) or not;
- material of protection layers: AIGaAs, material of confinement layer InGaAs doped (Si, Zn, S, Sn) or not.
The materials of the protection layers are advantageously also adapted to attract the ions introduced into the donor substrate toward the confinement layer during the heat treatment that increases the temperature of said donor substrate, for example doped or undoped SiGe enabling attraction of hydrogen ions.
Additionally, or alternatively, it is advantageous for at least one of the protection layers to be an etch stop layer, constituted of a material enabling selective chemical etching of the protection layer vis a vis the strained layer 5 constituted of the third material. This is generally a protection layer in • contact with the strained layer 5.
This enables implementation of a step consisting in selectively etching the protection layer present on the receiver substrate 8 after detachment of the donor substrate 1.
Additionally, or alternatively, one of the protection layers may be a chemical etch stop layer, constituted of a material enabling selective chemical etching of the protection layer vis a vis the seed layer 3'.
The method may include a step consisting in selectively etching the protection layer present on the donor substrate after fracture, which enables reuse of the donor substrate.
Following the sixth step E6, there is obtained a receiver substrate including at least part of the strained layer 5 constituted of the third material.
The receiver substrate 8 is then treated in the classic manner, according to the intended application. The residue of the seed layer 3' constituted of the second material present on the receiver substrate 8 is eliminated, for example by selective etching.
The receiver substrate 8 generally undergoes a finishing treatment notably including polishing.
In the situation where the third material is silicon and the receiver substrate 8 and/or the donor substrate 1 includes an oxide layer facilitating the bonding thereof, the receiver substrate 8 is, after the sixth step, a strained silicon on insulator sSOI) substrate, known to the person skilled in the art.
It will be noted that the transfer step E6 is configured to preserve the whole of (or possibly part of) the porous support layer 2, which enables recycling of the donor substrate.
In one embodiment the method includes, in addition to the first, second, third, fourth, fifth and sixth steps described above, a seventh step of recycling the donor substrate 1.
This seventh step E7 consists in reusing the donor substrate 1 obtained after the sixth step E6 for the fabrication of a new receiver substrate 8 including at least part of a strained layer 5 constituted of a third material. This is generally a strained layer 5 created during the seventh
recycling step (i.e. during the fifth step as repeated during said seventh recycling step).
Note that the strained layer 5, formed during recycling of the donor substrate 1 to be transferred to a new receiver substrate 8, and constituted of a third semiconductor material, may include a third material different from the third material of the strained layer 5 obtained in the preceding iteration of the fabrication method.
Thanks to the invention, the donor substrate 1 includes the porous layer 2' preserved during the fabrication process. It also includes, at least in part, the relaxed seed layer 3' constituted of the second material. This enables fabrication costs and times to be reduced.
In a first embodiment, shown in Figure 4, the seventh step of reutilization of the donor substrate 1 comprises the steps consisting in:
- treating the donor substrate 1 with a chemical solution so as to restrain the relaxed seed layer 3' constituted of the second material, said seed layer 3' constituted of the second material being transformed in this way into a strained layer 3 constituted of the second material,
- with the donor substrate 1 treated in this way, repeating the. third, fourth, fifth and sixth steps of the fabrication method to fabricate a new receiver substrate 8 including at least part of a strained layer 5 constituted of the third material.
The chemical solution is advantageously hydrofluoric acid or a buffered solution based on hydrofluoric acid.
The use of the chemical solution enables desorption of the surface layer produced in the porous support layer 2' constituted of the first material during the first step E3, which restrains the seed layer 3' constituted of the second material. The support layer 2' may contain oxygen in one embodiment because a thermal oxidation step has been effected during the second step E2. In another embodiment the support layer 2' may contain silicon nitride because nitriding of the support layer has been carried out during the third step.
The seventh step advantageously includes a step of polishing the donor substrate 1 , i.e. the surface layer 3' of the donor substrate 1 (for example in the situation where the weakened area 20 has been created in the layer 3' during the step E6).
In the case where the donor substrate 1 still includes part of the strained layer 5 (for example in the case where the weakened area 20 was created in the layer 5 during the step E6), this is generally removed, for example by selective etching, after which the donor substrate 1 , i.e. the, surface layer 3', is polished.
The polishing is CMP polishing, for example. This polishing aims to reduce or even eliminate the post-fracture roughness that has appeared on the surface of the seed layer 3' constituted of the second material.
This first embodiment is highly advantageous, and enables recycling of the substrate including the porous support layer 2 constituted of the first material and at least part of the seed layer 3' constituted of the second material. Thus the fabrication cost and the fabrication times of strained semiconductor material, notably silicon, layers without defect are reduced thanks to the invention. In particular the invention enables sSOI fabrication with reduced fabrication costs and times.
In a second embodiment, shown in Figure 5, the seventh step E7 of reusing the donor substrate 1 including the porous support layer 2' constituted of the first material comprises the steps consisting in:
- polishing the seed layer 3' constituted of the second material, to obtain a polished donor substrate ,
- with the polished donor substrate 1 , repeating the fourth, fifth and sixth steps of the fabrication method to fabricate a new receiver substrate 8 including a strained layer 5 of a third material.
In the case where the donor substrate 1 still includes part of the strained layer 5 (for example in the case where the weakened area 20 was created in the layer 5 during the step E6), the latter is generally removed, for example by selective etching, after which the donor substrate 1 , i.e. the surface layer 3', is polished.
The polishing is for example CMP polishing. This polishing aims to reduce or even eliminate the post-fracture roughness that has appeared on the surface of the seed layer 3' constituted of the second material.
Note that in this second embodiment the strained layer 5 formed during the recycling of the donor substrate 1 and constituted of a third material may feature a third material different from the third material of the strained layer 5 obtained in the previous iteration of the fabrication method.
In this embodiment, the seed layer 3' constituted of the second material remains relaxed or in a state close to a relaxed state (as defined above) before its reuse, in contrast to the first embodiment.
This second embodiment is highly advantageous and enables recycling of the substrate including the porous support layer 2. constituted of the first material and at least part of the seed layer 3' constituted of the second material.
According to the fabrication cost and the fabrication times of strained semiconductor, notably silicon, layers without defects are reduced thanks to the invention. In particular, the fabrication steps and the fabrication times are minimized. The invention in particular enables sSOI fabrication with reduced fabrication costs and times.
In a third embodiment, shown in Figure 8, the seventh step E7 of reusing the donor substrate 1 includes the steps consisting in repeating the fifth and sixth steps of the fabrication method to fabricate a new receiver substrate including at least part of a strained layer 5 constituted of the third material.
This may be applied in the case where the seed layer 3' has been sufficiently thickened during the fourth step, which thus enables a plurality of strained layer 5 transfers to be effected without having to regrow the seed layer during each recycling. This is possible thanks to the invention, since the seed layer 3' is not limited much if at all by its critical thickness, depending on its state of relaxation.
In another embodiment the donor substrate 1 still includes, after the sixth step E6, part of the strained layer 5, i.e. not all of the latter has been transferred after the sixth step E6.
In this case, the seventh recycling step may consist only in repeating the sixth step to fabricate a new receiver substrate including part of said strained layer.
It is advantageous to apply the steps consisting in the fabrication method of the invention cyclically. In this case, the method includes the steps consisting in applying cyclically the second, third, fourth, fifth, sixth and seventh steps for the fabrication of a plurality of receiver substrates including a strained layer 5 of the third material from a donor substrate 1 formed in the first step.
On each iteration of the cycle it is possible to choose for the seventh recycling step the first embodiment, the second embodiment or the third embodiment, which offers additional flexibility.
The invention is therefore seen to offer the possibility of effecting a plurality of strained layer transfers from the same substrate including a porous semiconductor layer.
The invention has numerous advantages as much in terms of costs and times as of flexibility.
The invention finds numerous applications in the microelectronics industry for the fabrication of constrained active layers and in particular sSOI substrates.
Claims
1. Method of fabrication of a semiconductor substrate (8), characterized it comprises:
- a first step (E1) consisting in forming a donor substrate (1) comprising o a support layer (2) constituted of a first semiconductor material, and
o a strained seed layer (3) constituted of a second semiconductor material,
- a second step (E2) consisting in rendering the support layer (2) porous,
- a third step (E3) consisting in treating the donor substrate (1) to deform in expansion or in contraction the porous support layer (2') constituted of the first material,
o . said deformation inducing a relaxation in the seed layer (3 ), - a fourth step (E4) consisting in increasing the thickness of the seed layer (3') constituted of the second material by a step of growing said second material,
- a fifth step (E5) consisting in forming a strained layer (5) constituted of a third semiconductor material in contact with said seed layer (3'), and - a sixth step (E6) consisting in transferring at least part of the strained layer (5) constituted of the third material from the donor substrate (1) to a receiver substrate (8).
2. Method according to Claim 1 , further comprising a seventh step (E7) consisting in
reusing the donor substrate (1) resulting from the sixth step (E6) and including the porous support layer (2')
for the fabrication of a new receiver substrate (8) including at least part of a strained layer (5) constituted of a third semiconductor material.
3. Method according to either of Claims 1 or 2, wherein the seed layer (3') has, after the third step (E3), a lattice parameter having a maximum difference of 0.5% in absolute value relative to the lattice parameter of the material of the seed layer (3) in the relaxed state.
4. Method according to any one of Claims 1 to 3, wherein:
- the third material is silicon,
- the second material is SiGe, and
- the first material is silicon.
5. Method according to any one of Claims 1 to 4, wherein the seventh step (E7) of reuse of the donor substrate (1 ) includes the steps consisting in:
- treating the donor substrate (1 ) with a chemical solution to restrain the seed layer (3'),
- with the donor substrate (1 ) treated in this way, repeating the third, fourth, fifth and sixth steps of the fabrication method to fabricate a new receiver substrate including at least part of a strained layer (5') constituted of a third semiconductor material.
6. Method according to any of Claims 1 to 4, wherein the seventh step (E7) of reuse of the donor substrate (1 ) comprises the steps consisting in:
- polishing the seed layer (3') constituted of the second material to obtained a polished donor substrate (1 ),
- with the polished donor substrate (1 ), repeating the fourth, fifth and sixth steps of the fabrication method to fabricate a new receiver substrate including at least part of a strained layer (5) constituted of a third semiconductor material.
7. Method according to any one of Claims 1 to 4 wherein the seventh step (E7) of reuse of the donor substrate (1 ) comprises the steps consisting in repeating the fifth and sixth- steps of the fabrication method to fabricate a new receiver substrate including at least part of a strained layer (5) constituted of a third semiconductor material.
8. Method according to any one of Claims 1 to 7, wherein the sixth step (E6) consists in transferring the strained layer (5) constituted of the third material of the donor substrate (1 ) to the receiver substrate (8) comprises the steps consisting in:
- creating a weakened area (20) in the donor substrate (1 ) by implantation of ions,
- bonding the donor substrate (1 ) and the receiver substrate (8),
- producing a fracture in said weakened area (20) to detach the donor substrate (1) from the receiver substrate (8).
9. Method according to any one of Claims 1 to 8, wherein:
- the first step (E1 ) comprises a step of formation of a confinement structure (23) comprising a semiconductor confinement layer (25) in the donor substrate (1 ), said confinement layer (25) having a chemical composition different from the strained layer (5) constituted of the third material, and
- the sixth step (E6) consisting in transferring the strained layer (5) constituted of the third material from the donor substrate (1 ) to the receiver substrate (8) comprises the steps consisting in:
o introducing (E61 ) ions (24) into the donor substrate (1 ),
o bonding (E62) the donor substrate (1) and the receiver substrate (8), and
o submitting (E63) the donor substrate (1 ) and the receiver substrate (8) to a heat treatment including an increase in temperature during which the confinement couch (25) attracts the ions (24) to concentrate them in said confinement layer (25), and - detaching (E64) the donor substrate (1 ) of the receiver substrate (8) by fracture at the level of said confinement layer (25).
10. Method according to Claim 9, wherein the introduction of the ions (24) into the donor substrate (1 ) is effected by immersing the donor substrate (1 ) in a plasma containing said ions.
11. Method according to any one of Claims 1 to 10, consisting in cyclically applying the second, third, fourth, fifth, sixth and seventh steps to the fabrication of a plurality of receiver substrates comprising a strained layer (5) of a third semiconductor material from a donor substrate formed in the first step.
12. Semiconductor substrate comprising successively:
- a porous support layer (2) constituted of a first semiconductor material,
- a seed layer (3')
o constituted of a second semiconductor material having a lattice parameter in the relaxed state different from the lattice parameter in the relaxed state of the first material, and having a lattice parameter having a maximum difference of 0.5% in absolute value relative to the lattice parameter of the material of the seed layer (3) in the relaxed state, and
- a strained layer (5) constituted of a third semiconductor material.
13. Substrate according to Claim, 12 wherein the seed layer (3') has a thickness in the range 10 nm to 5 microns.
14. Substrate according to either of Claims 12 or 13, wherein the seed layer (3') has a lattice parameter equal to the lattice parameter of the material of the seed layer in the relaxed state. 5. Substrate according to any one of Claims 12 to 14, wherein the first material is silicon, the second material is SiGe, and the third material is silicon.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1155574 | 2011-06-23 | ||
| FR1155574A FR2977070A1 (en) | 2011-06-23 | 2011-06-23 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE COMPRISING POROUS SILICON, AND SEMICONDUCTOR SUBSTRATE |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2012176031A1 true WO2012176031A1 (en) | 2012-12-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/IB2012/001129 Ceased WO2012176031A1 (en) | 2011-06-23 | 2012-06-11 | Method of fabrication of a semiconductor substrate and a semiconductor substrate |
Country Status (3)
| Country | Link |
|---|---|
| FR (1) | FR2977070A1 (en) |
| TW (1) | TW201301372A (en) |
| WO (1) | WO2012176031A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022538463A (en) * | 2019-07-02 | 2022-09-02 | ソイテック | Semiconductor structures containing embedded porous layers for high frequency applications |
| EP4576165A1 (en) * | 2023-12-21 | 2025-06-25 | Imec VZW | A method for growing epitaxial layers on an engineered substrate |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3024587B1 (en) * | 2014-08-01 | 2018-01-26 | Soitec | METHOD FOR MANUFACTURING HIGHLY RESISTIVE STRUCTURE |
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| US20040115900A1 (en) * | 2002-12-13 | 2004-06-17 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance |
| US20060118870A1 (en) * | 2004-12-08 | 2006-06-08 | Samsung Electronics Co., Ltd. | Structure of strained silicon on insulator and method of manufacturing the same |
| US20060124961A1 (en) * | 2003-12-26 | 2006-06-15 | Canon Kabushiki Kaisha | Semiconductor substrate, manufacturing method thereof, and semiconductor device |
| US20060144323A1 (en) * | 2004-12-30 | 2006-07-06 | Samsung Electronics Co., Ltd. | Substrate with locally integrated single crystalline silicon layer and method of fabricating the same |
-
2011
- 2011-06-23 FR FR1155574A patent/FR2977070A1/en active Pending
-
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- 2012-05-16 TW TW101117426A patent/TW201301372A/en unknown
- 2012-06-11 WO PCT/IB2012/001129 patent/WO2012176031A1/en not_active Ceased
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040115900A1 (en) * | 2002-12-13 | 2004-06-17 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance |
| US20060124961A1 (en) * | 2003-12-26 | 2006-06-15 | Canon Kabushiki Kaisha | Semiconductor substrate, manufacturing method thereof, and semiconductor device |
| US20060118870A1 (en) * | 2004-12-08 | 2006-06-08 | Samsung Electronics Co., Ltd. | Structure of strained silicon on insulator and method of manufacturing the same |
| US20060144323A1 (en) * | 2004-12-30 | 2006-07-06 | Samsung Electronics Co., Ltd. | Substrate with locally integrated single crystalline silicon layer and method of fabricating the same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022538463A (en) * | 2019-07-02 | 2022-09-02 | ソイテック | Semiconductor structures containing embedded porous layers for high frequency applications |
| JP7464631B2 (en) | 2019-07-02 | 2024-04-09 | ソイテック | Semiconductor structures including buried porous layers for high frequency applications - Patents.com |
| US12119258B2 (en) | 2019-07-02 | 2024-10-15 | Soitec | Semiconductor structure comprising a buried porous layer for RF applications |
| EP4576165A1 (en) * | 2023-12-21 | 2025-06-25 | Imec VZW | A method for growing epitaxial layers on an engineered substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201301372A (en) | 2013-01-01 |
| FR2977070A1 (en) | 2012-12-28 |
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