WO2012169000A1

WO2012169000A1 - Analog circuit simulator and analog circuit verification method

Info

Publication number: WO2012169000A1
Application number: PCT/JP2011/062981
Authority: WO
Inventors: 聡松原
Original assignee: 富士通株式会社
Priority date: 2011-06-06
Filing date: 2011-06-06
Publication date: 2012-12-13
Also published as: US20140096096A1; JP5768880B2; US9009636B2; JPWO2012169000A1

Abstract

This analog circuit simulator (100) includes search units (111 and 112) for retrieving an analog circuit from design data in order to retrieve an analog node in which analog circuits are connected to each other, a variable information collection unit (113) for collecting variable information for a voltage and a current related to input and output of the retrieved analog node, a function conversion unit (114) for converting variable information for an analog node to a function of time, and a simulation execution unit (116) which computes the function of time at each time of occurrence of a predetermined event in order to perform a simulation of the analog node.

Description

Analog circuit simulator and analog circuit verification method

The present invention relates to an analog circuit simulator and an analog circuit verification method for verifying the function of an analog circuit.

Conventionally, an analog circuit simulator such as SPICE (Simulation Program with Integrated Circuit Emphasis, registered trademark) is used for functional verification of an analog circuit. Such an analog circuit simulator can calculate analog characteristics with high accuracy, but uses a huge memory for calculation. In addition, since the number of calculation steps is small, it takes tens of thousands of times longer than the verification time in the normal operation model, and cannot be used for verification of a large-scale circuit. For this reason, an operation model in which an analog circuit is expressed in a hardware description language is generally used.

For example, for the matrix constantization method of circuit division type simulation that divides the circuit into blocks, the circuit is divided into blocks, and the current variable of the current variable independent element is excluded from the internal variable of the block between the external nodes of the block. (For example, refer to Patent Document 1 below). Further, in order to simulate a transient state of a signal waveform in a circuit in which an analog circuit and a digital circuit coexist by numerical calculation, there is a technique of dividing an analog circuit into a plurality of circuit blocks and modeling (for example, Patent Document 2 below). reference.).

JP-A-6-124317 JP 2010-92434 A

However, in order to verify the function of an analog circuit, it is necessary to perform a simulation by replacing the analog circuit with a high abstraction behavior model described in a hardware description language. However, in the hardware description language used in large-scale verification, the direction of the signal flow is clearly determined by the input and output definitions, so the interaction with the outside of the model and the function of the circuit with impedance are described in hardware. There was a problem that it could not be expressed in language.

For example, in the case of a circuit configuration in which a grounded resistor input is connected to the output of the operational amplifier and has a predetermined impedance, if the output destination circuit of the operational amplifier is not determined, the voltage and current of the output and input nodes are It will not be determined. For this reason, for example, an analog circuit simulator is used to verify the function of a circuit having an impedance, and it takes an enormous amount of time.

The disclosed analog circuit simulator and analog circuit verification method are intended to solve the above-described problems, and an object of the present invention is to easily and functionally verify an analog circuit having an impedance.

In order to solve the above-described problems and achieve the object, the disclosed technology searches for an analog circuit from design data, searches for an analog node to which the analog circuits are connected, and the searched analog node. A variable information collecting unit that collects variable information of voltage and current related to input and output, a function converting unit that converts variable information of the analog node into a time function, and performing the calculation of the time function every time a predetermined event occurs, A simulation execution unit that executes simulation of the analog node.

According to the disclosed analog circuit simulator and analog circuit verification method, there is an effect that an analog circuit having impedance can be verified easily and in a short time.

FIG. 1 is a block diagram illustrating a configuration of an analog circuit simulator according to an embodiment. FIG. 2 is a flowchart showing the processing operation of the analog circuit simulator according to the embodiment. FIG. 3 is a diagram illustrating an example of an analog model. FIG. 4 is a timing chart showing the operation of the simulator. FIG. 5A is a circuit diagram illustrating an example of a functionalization model. FIG. 5-2 is a diagram for explaining the functionalization of the upper layer of FIG. 5-1. FIG. 5C is a diagram illustrating the current waveform of FIG. FIG. 6 is a circuit diagram showing another model example of functionalization. FIG. 7A is a circuit diagram illustrating still another example of functionalization. FIG. 7-2 is a diagram for explaining the functionalization of the upper layer of FIG. 7-1. FIG. 7C is a diagram illustrating the current waveform of FIG. FIG. 8 is a circuit diagram showing still another model example of functionalization. FIG. 9 is a timing chart showing discrete modeling of an analog circuit.

(Device configuration)
Hereinafter, preferred embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram illustrating a configuration of an analog circuit simulator according to an embodiment. The analog circuit simulator 100 includes a CPU 101, memories 102 and 103, and the like. The CPU 101 operates the apparatus as an analog circuit simulator by executing an analog circuit verification program (not shown) stored in a memory (not shown) such as a ROM.

In the illustrated first memory 102, design data 104 of the designed circuit and variable-function correspondence information 105 are stored. The design data 104 includes a digital circuit model included in the circuit and an analog circuit model.

The CPU 101 has each function of reading design data 104 by executing a program, modeling a circuit, and executing a simulation. When described by function, the search unit 1 (111) reads the design data 104 such as a net list, searches for an analog circuit in the highest hierarchy of the circuit to be verified, and further outputs an analog port (output of the analog circuit in the previous stage). The analog nodes to which the inputs of the analog circuits in the subsequent stage are connected are searched, and the extracted analog nodes are stored in the memory 1 (121).

The search unit 2 (112) sequentially searches the analog nodes stored in the memory 1 (121), searches for model names corresponding to each analog node, and stores the searched model names in the memory 2 (122). Store.

The variable information collection unit 113 collects variable information corresponding to the model name stored in the memory 2 (122) from the variable information group corresponding to the model prepared in advance, and stores it in the memory 3 (123). The variable information includes a voltage variable and a current variable that are determined in advance corresponding to the model name. The variable information collection unit 113 stores variable information (voltage variable and current variable) corresponding to the model name in the memory 3 (123).

The function conversion unit 114 reads variable information (voltage variable and current variable) corresponding to the model name from the memory 3 (123), and converts the variable information into a function of a predetermined time corresponding to the variable. Since the circuit configuration is determined from the information on the voltage variable and current variable of the model, the function converter 114 determines the time function of the voltage and current corresponding to the model. Then, the voltage and current of the analog node are converted into a function of time, and the converted function is stored in the memory 4 (124). The function conversion process is not always necessary, and a function corresponding to a plurality of models may be prepared in advance, and a function corresponding to the model may be selected.

The model processing unit 115 reads the current and voltage functions from the memory 4 (124), and obtains the current value and voltage value of the model at the occurrence of a predetermined event. Among the functions obtained by the function conversion unit 114, Extract only the value when the event occurred. When the predetermined event occurs, in the simulation performed by the simulation execution unit 116, for example, the current value and voltage value of the model when the event occurs at the next stage of the model is output to the simulation execution unit 116. For example, in accordance with the cycle operation of the analog circuit operation of the model, the function of the voltage value and the current value only at the starting point of the cycle operation of the next stage FF circuit is extracted, and the corrected model is the memory 5 (125). Stored in

The simulation execution unit 116 performs a simulation for verifying the function of the analog circuit. Based on the corrected model stored in the memory 5 (125), an operation based on the function of the voltage value and the current value only at the time of event occurrence is performed. Execute. For example, the simulation execution unit 116 can execute a simulation using a model expressed in a hardware description language such as a general-purpose Verilog. However, continuous analysis of the transient state in the analog circuit is not performed, and analysis is performed only when a predetermined event occurs. As a result, event-driven voltage / current analysis in consideration of impedance (voltage and current) can be performed on the analog circuit while being discrete in time, and functional verification is performed at high speed.

(Device operation)
FIG. 2 is a flowchart showing the processing operation of the analog circuit simulator according to the embodiment. The process shown in FIG. 2 describes the pre-process before the simulation execution by the simulation execution unit 116. First, the design data 104 is read from the memory 102 by the search unit 1 (111), an analog circuit is searched in the highest hierarchy of the circuit to be verified, and the analog ports (the output at the previous stage and the input at the subsequent stage) are connected to each other. An analog node to be searched is searched (step S201). The extracted analog node is stored in the memory 1 (121).

Next, the search unit 2 (112) searches the analog nodes stored in the memory 1 (121) sequentially, and searches for the model name corresponding to each analog node (step S202). The searched model name is stored in the memory 2 (122).

Thereafter, the variable information collecting unit 113 collects variable information corresponding to the model name stored in the memory 2 (122) (step S203). The collected variable information is stored in the memory 3 (123).

Then, the function conversion unit 114 reads variable information (voltage variable and current variable) corresponding to the model name from the memory 3 (123), and converts the variable information into a function of a predetermined time corresponding to the variable (step S204). ). Thereby, the converted voltage and current of the analog node are converted into a function of time, and the converted function is stored in the memory 4 (124). Thus, the preprocessing ends.

After the preprocessing, simulation execution is performed in the simulation execution unit 116. At this time, the model processing unit 115 reads out the current and voltage functions from the memory 4 (124), and simulates the value at the time of the event out of the functions obtained by the function conversion unit 114 every time a predetermined event occurs. The data is output to the execution unit 116. Thus, the simulation execution unit 116 only needs to have a general-purpose simulator function, and can execute a calculation based on a function of a voltage value and a current value only when an event occurs and output a calculation result.

As described above, the analog circuit simulator according to the present embodiment is realized by the cooperation of the analog circuit model and the simulator.
1-1. In the analog circuit model, a voltage variable and a current variable are given to the analog port of each analog circuit.
1-2. An analog node to which analog ports are connected is searched for in the highest hierarchy of the circuit to be verified.
1-3. Then, the voltage and current of the analog node are converted into functions of time from the relationship between the voltage variable and current variable of all models connected to each analog node.
2. In the simulator, when an event occurs, a necessary analog value (voltage value, current value) is calculated by a function, and a verification result is obtained.

(About analog models)
The processing content of each component described above will be described. First, the analog model will be described. FIG. 3 is a diagram illustrating an example of an analog model. The model 300 shown in the figure is an example in which the analog port input of the model 2 (302) having the grounded resistor 302a is connected to the analog port output of the model 1 (301) including the power supply 301a and the operational amplifier 301b. In this model 300, R2 is an input impedance and R1 is an output impedance. The search unit 1 (111) to the variable information collection unit (113) search for the voltage variable V1- (I1 × R1) and the current variable I1 for the output port of the model 1. For the input port of model 2, a voltage variable I2 × R2 and a current variable I2 are obtained.

(About simulator operation)
FIG. 4 is a timing chart showing the operation of the simulator. As shown in the model 300 in FIG. 3, an example in which changes in voltage and current remain within one cycle during simulation execution by the simulation execution unit 116 will be described. The voltage transient V (t) at this time is expressed by the following function V (t) = V1 + (V2−V1) [1/2 + (ft−tk) −1/2) × (−1) ^k ]
It is represented by

As a result of the input to the model 300, the output increases transiently with respect to the reference voltage V1 up to V2 according to a function of the RC characteristic. Here, the simulation execution unit 116 sets the value of the above function only at the times t0, t1, t2, t3,... As the event occurs, in accordance with the cycle of one cycle corresponding to the rising edge of the next stage FF input clock. Calculate it. In this way, the simulation execution unit 116 does not calculate the entire transient characteristic, but in accordance with the model after processing stored in the memory 5 (125), the timings t0, t1, t2, t3 of designated events. By performing the function calculation f (t) only when..., The calculation of the simulation execution unit 116 can be easily executed with a low load.

Also, examples of correspondence to other models will be described. When the simulation is executed, if the voltage and current changes (function values) extend over multiple cycles and affect other cycles, the following functions are used. 1. If the effect continues indefinitely, it can be expressed as: (-1) corresponds to waveform inversion.

Also, if the impact is up to 3 cycles,
Vn (t) = V1 + (V2−V1) (− 1) ⁿ (f (t−t _n ) −f (t−t _n−1 ) + f (t−t _n−2 ))
And it is sufficient. In this way, it is only necessary to add functions for the number of cycles that are affected.

(Specific examples of functionalization)
FIG. 5A is a circuit diagram illustrating an example of a functionalization model. The model 500 shown in the figure is an example in which the analog port input of the model 2 (502) having the grounded capacitor 502a is connected to the analog port output of the model 1 (501) including the power source 501a and the operational amplifier 501b. In this example, the output impedance R1 and the total capacitance C2 are included. Search unit 1 (111) to variable information collection unit (113) search for and obtain voltage variable V1-I1 × R1 and current variable I1 for the output port of model 1. Further, the voltage variable I2 / jωC2 and the current variable I2 are searched for the input port of the model 2. Then, the function conversion unit 114 converts the function into an upper layer function.

Fig. 5-2 is a diagram for explaining the functionalization of the upper layer of Fig. 5-1, and Fig. 5-3 is a diagram showing the current waveform of Fig. 5-2. As shown in FIG. 5B, in the function expressed in the upper hierarchy, a resistor R1 is connected to a power source 501a via a switch 510, and a grounded capacitor C2 is connected. The voltage V1 of this model 500 is

Which can be expressed as:
R ₁ (di / dt) + 1 / C ₂ · i = 0
1 / i · (di / dt) = − 1 / C ₂ R ₁
Integrate both sides,
1n | i | = −t / C ₂ R ₁ + A (A: integral constant)
i = e ^A · e- ^{(t / C2R1)}

From V = V1-Ri

It becomes. The function converter 114 converts the voltage V and the current i into time functions. Then, when the simulation is executed by the simulation execution unit 116, when an event occurs in the next stage (see FIG. 4), a value to which the above function is applied is output as a model output, and the simulation is executed. The switch 510 shown in FIG. 5B repeats the switch operation that opens and closes every event execution, thereby obtaining a waveform corresponding to the output of the model shown in FIG.

FIG. 6 is a circuit diagram showing another model example of functionalization. A model 1 (601) of the model 600 shown in the figure is connected to an analog port output of a model 1 (601) composed of a power source 601a and an operational amplifier 601b as an analog port input of a model 2 (602A to 602N). A capacitor 602a is connected. As described above, when connected in parallel, the model 2 may be converted into a function by the sum C of the capacitance values of the capacitor 602a. That is, the capacity C = C2 × N. As a result, the function converter 114 performs the voltage V and the current i.

To a function of time.

FIG. 7-1 is a circuit diagram showing still another model example of functionalization. The model 700 shown is an example in which the analog port input of the model 2 (702) having the grounded voltage dividing resistor 702a is connected to the analog port output of the model 1 (701) including the power source 701a and the operational amplifier 701b. . The search unit 1 (111) to the variable information collection unit (113) search for and obtain the voltage variable V1-I1 × R1 and the current variable I1 for the output port of the model 1. Further, the voltage variable I2 × R2 and the current variable I2 are searched for the input port of the model 2. Then, the function conversion unit 114 converts the function into an upper layer function.

FIG. 7-2 is a diagram for explaining the functionalization of the upper layer of FIG. 7-1, and FIG. 7-3 is a diagram showing the current waveform of FIG. 7-2. The model 700 shown in FIG.
The voltage V is V = (R2 · V1) / (R1 + R2)
The current i is i = V1 / (R1 + R2)
Indicated by The function converter 114 uses the current i and voltage V as functions. As shown in FIG. 7C, in this model 700, the current and voltage are DC values independent of time (values independent of time).

FIG. 8 is a diagram showing still another model example of functionalization. The model 800 shown in the figure is an example in which the analog port output of the operational amplifier 802a having no input load is connected to the analog port output of the model 1 (801) including the power source 801a and the operational amplifier 801b. is there. Functionalization can be applied even in a model in which the influence of impedance does not occur at a node, such as the model 800, or when it is not necessary to calculate impedance. As described above, when the impedance calculation is not necessary, the model output can be used as it is.

In the case of the configuration of FIG. 8, the search unit 1 (111) to the variable information collection unit (113) are simply obtained by searching the output port of the model 1 for the voltage variable V = V1 and the current variable i = V1 / R1. It's okay. In the function conversion unit 114, the voltage and current of the output port of the model 1 can be used as a function in the upper layer as they are.

FIG. 9 is a timing chart showing discrete modeling of an analog circuit. As described above, the analog circuit having impedance is discretely modeled in time by the components of the search unit 1 (111) to the model processing unit 115. As a result, the simulation execution unit 116 only needs to perform an operation when an event occurs, so that the verification time can be significantly reduced. In the conventional simulation (for example, Verilog-A), the time on the horizontal axis is continuously verified with respect to the voltage fluctuation on the vertical axis shown in FIG. On the other hand, in the above embodiment, the model of the previous stage is generated only when an event such as every operation timing in the next stage circuit (FF) occurs (for each point shown in the figure) by discrete modeling of the analog circuit. It suffices to perform an operation using the value obtained by applying the obtained function as an output. As a result, the verification time can be greatly shortened.

According to the disclosed technology described above, analog circuits are modeled, current and voltage variables are collected for circuits having impedance when input / output ports are connected, and these currents and voltages are temporally changed at higher levels. Is converted into a function. This makes it possible to verify the function of an analog circuit having impedance easily and in a short time. Also, the simulation time can be greatly shortened by performing simulation calculations only when an event occurs. These enable functional verification not only for digital circuits but also for large-scale mixed signal designs including analog circuits. In addition, the function verification of the analog circuit can be performed using a general-purpose simulation calculation method.

100 Analog circuit simulator 101 CPU
102, 103 Memory 104 Design data 105 Variable-function correspondence information 111 Search unit 1
112 Search unit 2
113 Variable information collection unit 114 Function conversion unit 115 Model processing unit 116 Simulation execution unit 121 to 125 Memory 1 to 5

Claims

A search unit that searches for analog circuits from design data and searches for analog nodes to which the analog circuits are connected;
A variable information collecting unit for collecting voltage and current variable information related to input and output of the searched analog node;
A function converter that converts the variable information of the analog node into a time function;
Performing a calculation of the time function every time a predetermined event occurs, and executing a simulation of the analog node;
An analog circuit simulator characterized by comprising:
2. The search unit according to claim 1, wherein the search unit searches for the variable information corresponding to the model name using a model name corresponding to the analog node prepared in advance and voltage and current variable information. Analog circuit simulator.
The function conversion unit aggregates the variable information of voltage and current in the upper layer of the model and converts the analog node into a function of time prepared in advance corresponding to the variable information. Item 4. The analog circuit simulator according to Item 1.
2. The analog circuit simulator according to claim 1, wherein the simulation execution unit performs the calculation of the time function at an event occurrence cycle of a next-stage circuit of the target analog node.
5. The analog circuit simulator according to claim 4, wherein the simulation execution unit performs calculation in units of one cycle when the function value of the analog node converges within one cycle of the event generation period.
5. The simulation execution unit according to claim 4, wherein when the convergence of the function value of the analog node extends over a plurality of cycles of the event generation period, the simulation execution unit adds and calculates a function corresponding to the number of cycles over which the event has occurred. The analog circuit simulator described.
Searching for analog circuits from design data, searching for analog nodes to which the analog circuits are connected, and
A variable information collecting step of collecting voltage and current variable information related to input and output of the searched analog node;
A function conversion step of converting the variable information of the analog node into a time function;
A simulation execution step of performing the calculation of the time function every time a predetermined event occurs, and executing a simulation of the analog node;
An analog circuit verification method comprising: