WO2012167451A1 - 薄膜晶体管矩阵结构及液晶显示面板 - Google Patents

薄膜晶体管矩阵结构及液晶显示面板 Download PDF

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Publication number
WO2012167451A1
WO2012167451A1 PCT/CN2011/075956 CN2011075956W WO2012167451A1 WO 2012167451 A1 WO2012167451 A1 WO 2012167451A1 CN 2011075956 W CN2011075956 W CN 2011075956W WO 2012167451 A1 WO2012167451 A1 WO 2012167451A1
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Prior art keywords
pixel unit
control module
transistor
scan line
data line
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Ceased
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PCT/CN2011/075956
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English (en)
French (fr)
Inventor
李仕琦
姜佳丽
何海英
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/203,753 priority Critical patent/US8797249B2/en
Publication of WO2012167451A1 publication Critical patent/WO2012167451A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • the present patent application relates to a transistor matrix structure and a display panel thereof, and in particular to a thin film transistor matrix structure and a liquid crystal display panel.
  • FIG. 1 is a schematic structural view of a prior art thin film transistor matrix structure 100.
  • the thin film transistor matrix structure 100 is mainly composed of a plurality of pixel units (pixel
  • the unit 102 is composed of a plurality of scan lines 104 and a plurality of data lines 106.
  • the pixel units 102 are electrically connected to the scan lines 104 and the data lines 106.
  • Each of the pixel units 102 has a transistor 108 and a liquid crystal capacitor (liquid-crystal).
  • Capacitor, CLC)110 and storage capacitor (CS) 112 wherein each transistor 108 has a gate G, a source S, and a drain D, and the gate G is connected to the scan line 104, the source S is connected to the data line 106, and The drain D is commonly connected to a liquid crystal capacitor (CLC) 110 and a storage capacitor (CS) 112.
  • the liquid crystal capacitor (CLC) 110 and the storage capacitor (CS) 112 are grounded (as shown in FIG. 1) or connected to a shared line ( Common Line) (not shown).
  • the thin film transistor 108 connected to the first scan line (SL1) is turned on (switch On, the pixel electrodes of the liquid crystal capacitors are electrically connected to the data lines 106 in the vertical direction, and the corresponding video signals are fed through the vertical data lines to charge the liquid crystal capacitors to an appropriate voltage level; in other words, to these
  • the liquid crystal capacitor corresponding to the pixel unit is charged to drive liquid crystal molecules in the liquid crystal layer to display an image on the liquid crystal display; and at the same time, the storage capacitors 112 connected to the data line are charged, and the storage capacitor 112 is a liquid crystal capacitor
  • the voltage across the 110 is maintained at a constant value, that is, the voltage across the liquid crystal capacitor 110 is maintained by the storage capacitor 112 before the data update is performed.
  • the patent application provides a thin film transistor matrix structure and a liquid crystal display panel to solve the problem that the pixel charging time is too long.
  • the purpose of this patent application is to provide a thin film transistor matrix structure and a liquid crystal display panel to solve the problem that the pixel charging time is too long, and the charging time of the pixel is shortened by a pre-charged capacitor.
  • the present patent application provides a thin film transistor matrix structure and a liquid crystal display panel.
  • the thin film transistor matrix structure includes a plurality of scan lines, a plurality of first data lines, a plurality of second data lines, a plurality of pixel units, and a plurality of control modules.
  • a plurality of first data lines are interleaved with the plurality of scan lines; a plurality of second data lines are interleaved with the plurality of scan lines; a plurality of pixel units, each of the pixel units being coupled to a scan line and a first a data line; and a plurality of control modules, each control module being coupled between a scan line, a second data line, and a pixel unit, when a scan line is turned on to enable a first data line to charge the pixel unit Passing the second data line to charge the lower level control module, when the scan line is turned off and another scan line is turned on to charge the first data line to another pixel unit, the lower stage of charging The control module charges the other pixel unit.
  • the lower level control module further includes a first control transistor, a second control transistor, and a capacitor.
  • the first control transistor is coupled to the scan line, the second data line, the pixel unit, and an upper control module; the second control transistor is coupled to the another scan line and the another pixel unit And a capacitor coupled to the first control transistor and the second control transistor of the lower stage control module.
  • the second data line and the first control transistor are used to make a capacitor to the lower control module. Charging, when the scan line is turned off and another scan line is turned on to charge the first data line to another pixel unit, the capacitor of the charged lower level control module charges the other pixel unit.
  • the superior control module further includes a first control transistor, a second control transistor, and a capacitor. a first control transistor; a second control transistor coupled to the scan line, the pixel unit and a gate of the first control transistor of the lower stage control module; and a capacitor coupled to the second control transistor.
  • the pixel unit further includes a switching transistor, a liquid crystal capacitor, and a storage capacitor.
  • the switching transistor is coupled to the scan line, the first data line, and the second control transistor of the upper control module and the gate of the first control transistor of the lower control module; the liquid crystal capacitor is coupled to the switching transistor; And a storage capacitor coupled to the switching transistor and in parallel with the liquid crystal capacitor.
  • the present patent application further provides a liquid crystal display panel, including a scan driving module and a data driving module, wherein the liquid crystal display panel is further provided with a thin film transistor matrix structure, and the scan driving module and the data driving module are used to drive the
  • the thin film transistor matrix structure includes a plurality of scan lines, a plurality of first data lines, a plurality of second data lines, a plurality of pixel units, and a plurality of control modules.
  • a plurality of first data lines are interleaved with the plurality of scan lines; a plurality of second data lines are interleaved with the plurality of scan lines; a plurality of pixel units, each of the pixel units being coupled to a scan line and a first a data line; and a plurality of control modules, each control module being coupled between a scan line, a second data line, and a pixel unit, when a scan line is turned on to enable a first data line to charge the pixel unit Passing the second data line to charge the lower level control module, when the scan line is turned off and another scan line is turned on to charge the first data line to another pixel unit, the lower stage of charging The control module charges the other pixel unit.
  • the lower level control module further includes a first control transistor, a second control transistor, and a capacitor.
  • the first control transistor is coupled to the scan line, the second data line, the pixel unit, and an upper control module; the second control transistor is coupled to the another scan line and the another pixel unit And a capacitor coupled to the first control transistor and the second control transistor of the lower stage control module.
  • the second data line and the first control transistor are used to make a capacitor to the lower control module. Charging, when the scan line is turned off and another scan line is turned on to charge the first data line to another pixel unit, the capacitor of the charged lower level control module charges the other pixel unit.
  • the superior control module further includes a first control transistor, a second control transistor, and a capacitor. a first control transistor; a second control transistor coupled to the scan line, the pixel unit and a gate of the first control transistor of the lower stage control module; and a capacitor coupled to the second control transistor.
  • the pixel unit further includes a switching transistor, a liquid crystal capacitor, and a storage capacitor.
  • the switching transistor is coupled to the scan line, the first data line, and the second control transistor of the upper control module and the gate of the first control transistor of the lower control module; the liquid crystal capacitor is coupled to the switching transistor; And a storage capacitor coupled to the switching transistor and in parallel with the liquid crystal capacitor.
  • the thin film transistor matrix structure and the liquid crystal display panel of the patent application shorten the charging time of the pixel by turning on the control transistor, driving the pixel through the pre-charged capacitor and the two data lines.
  • the thin film transistor matrix structure and the liquid crystal display panel of the patent application shorten the charging time of the pixel by turning on the control transistor, driving the pixel through the pre-charged capacitor and the two data lines.
  • FIG. 1 is a schematic view showing a matrix structure of a thin film transistor of the prior art.
  • FIG. 2 is a schematic diagram of a matrix structure of a thin film transistor in accordance with an embodiment of the present patent application.
  • FIG. 3 is a schematic diagram of a liquid crystal display panel having a thin film transistor matrix structure in accordance with an embodiment of the present patent application.
  • FIG. 1 is a schematic view showing a matrix structure of a thin film transistor of the prior art.
  • FIG. 2 is a schematic diagram of a matrix structure of a thin film transistor in accordance with an embodiment of the present patent application.
  • FIG. 3 is a schematic diagram of a liquid crystal display panel having a thin film transistor matrix structure in accordance with an embodiment of the present patent application.
  • the thin film transistor matrix structure 200 includes a plurality of scan lines 202, a plurality of first data lines 204a, a plurality of second data lines 204b, a plurality of pixel units 206, and a plurality of control modules 208.
  • the plurality of scan lines 202 are arranged in a staggered manner with the plurality of first data lines 204a and the plurality of second data lines 204b, respectively.
  • SL(n-1), SLn 202 is arranged in a staggered manner with a first data line DL1 204a and a second data line DL2 204b, and two pixel units P(n-1), Pn 206, and two control modules CT(n-1), CTn 208 are exemplified, but the number is not limited thereto.
  • Each pixel unit P(n-1), Pn 206 is respectively coupled between a scan line 202, a first data line 204a and a control module 208, the plurality of pixel units P(n-1), Pn 206 are respectively disposed near the interlaced positions of the two scan lines SL(n-1), SLn 202 and one of the first data lines DL1 204a and one of the second data lines DL2 204b.
  • a plurality of control modules 208a, 208b are disposed in the pixel unit P(n-1), Pn Between 206.
  • One of the control modules 208a is coupled to a scan line SL(n-1) 202, a second data line 204b, and a pixel unit P(n-1).
  • the other control module 208b is coupled between the other scan line SLn 202, a second data line 204b, and another pixel unit Pn 206.
  • the lower level control module 208b further includes a first control transistor 210a, a second control transistor 210b, and a capacitor 212.
  • the first control transistor 210a is coupled to the scan line SL(n-1) 202.
  • the second control transistor 210b is coupled to the other scan line SLn 202 and the other pixel unit Pn 206.
  • the capacitor 212 is coupled to the first control transistor 210a and the second control transistor 210b of the lower stage control module 208b.
  • the upper control module 208a is similar to the lower control module 208b, and the upper control module 208a further includes a first control transistor 210a, a second control transistor 210b, and a capacitor 212.
  • the second control transistor 210b is coupled to the scan line SL(n-1) 202.
  • the capacitor 212 is coupled to the second control transistor 210b.
  • two data lines 204a, 204b are used between two pixel units 206, and one data line 204a is used to charge two pixel units (ie, transfer)
  • the video signal 204) is used to precharge the capacitor 212.
  • a voltage (eg, a positive voltage) is applied to the scan line SL(n-1) 202, by turning on the switching transistor 214 of the pixel unit P(n-1) 206 to the pixel unit P(n-1) 206 is charged, and the first control transistor 210b of the control module 208a is turned on to make the second data line DL 2 204b
  • the video signal is transmitted to precharge the capacitor 212 of the lower control module 208b through the first control transistor 210a of the lower level control module 208b.
  • another voltage (eg, a negative voltage) is applied to the scan line SL(n-1) 202 to turn off the pixel unit P(n-1)
  • a voltage is applied to the other scan line SLn 202 by turning on the switching transistor 214 of the pixel unit Pn 206 to the pixel unit Pn.
  • the pixel unit Pn 206 is charged while the pixel unit Pn 206 is charged by the charged capacitor 212 of the lower level control module 208b, thus saving the pixel unit Pn
  • the charging time of 206 is performed for fast charging of pixels.
  • the switching transistor 214 is turned on, in addition to the first data line DL1 204 to the pixel unit Pn
  • the pixel unit Pn 206 can be further charged by the charged capacitor 212 of the lower level control module 208b to achieve the purpose of fast charging, effectively shortening the charging time of the pixel.
  • the pixel unit P(n-1) 206 further includes a switching transistor 214 and a liquid crystal capacitor (liquid-crystal) Capacitor, CLC) 216 and storage capacitor (CS) 218.
  • the switching transistor 214 is coupled to the scan line SL(n-1) 202. The first data line DL1 204a.
  • the liquid crystal capacitor 216 is coupled to the drain of the switching transistor 214 and the source of the second control transistor 210b of the upper control module 208a.
  • the storage capacitor 218 is coupled to the drain of the switching transistor 214 and the source of the second control transistor 210b of the upper control module 208a, and stores a capacitor 218 and is connected in parallel with the liquid crystal capacitor 216.
  • the pixel unit Pn 206 is the same as the pixel unit P(n-1) 206, and the pixel unit Pn 206 also includes a switching transistor 214, a liquid crystal capacitor 216, and a storage capacitor 218.
  • the switching transistor 214 is coupled to the scan line SLn 202 and the first data line DL1 204a and a second control transistor 210b of the lower level control module 208b.
  • the liquid crystal capacitor 216 is coupled to the drain of the switching transistor 214 and the source of the second control transistor 210b of the lower stage control module 208b.
  • the storage capacitor 218 is coupled to the drain of the switching transistor 214 and the source of the second control transistor 210b of the lower stage control module 208b, and stores a capacitor 218 and is connected in parallel with the liquid crystal capacitor 216.
  • FIG. 3 is a schematic diagram of a liquid crystal display panel 300 having a thin film transistor matrix structure 200 according to an embodiment of the present patent application.
  • the liquid crystal display panel 300 includes a scan driving module 302, a data driving module 304, and a thin film transistor matrix structure 200.
  • the scan driving module 302 and the data driving module 304 are used to drive the thin film transistor matrix structure 200, that is, the scan driving module 302 applies a voltage to the scan line 202 to control the switching transistor 214 connected to the scan line 202 and the first transistor of the control module.
  • the 210a and the second transistor 210b are turned on or off.
  • the data driving module 304 transmits the video signal to the pixel units Pn, Pn(-1) 206. Further, the liquid crystal capacitors corresponding to the pixel units Pn and P(n-1) 206 are charged to drive liquid crystal molecules in the liquid crystal layer to display an image on the liquid crystal display.
  • the thin film transistor matrix structure 200 includes a plurality of scan lines 202, a plurality of first data lines 204a, a plurality of second data lines 204b, a plurality of pixel units 206, and a plurality of control modules 208.
  • the plurality of scan lines 202 are arranged in a staggered manner with the plurality of first data lines 204a and the plurality of second data lines 204b, respectively.
  • SL(n-1), SLn 202 is arranged in a staggered manner with a first data line DL1 204a and a second data line DL2 204b, and two pixel units P(n-1), Pn 206, and two control modules CT(n-1), CTn 208 are exemplified, but the number is not limited thereto.
  • Each pixel unit P(n-1), Pn 206 is respectively coupled between a scan line 202, a first data line 204a and a control module 208, the plurality of pixel units P(n-1), Pn 206 are respectively disposed near the interlaced positions of the two scan lines SL(n-1), SLn 202 and one of the first data lines DL1 204a and one of the second data lines DL2 204b.
  • a plurality of control modules 208a, 208b are disposed in the pixel unit P(n-1), Pn Between 206.
  • One of the control modules 208a is coupled to a scan line SL(n-1) 202, a second data line 204b, and a pixel unit P(n-1).
  • the other control module 208b is coupled between the other scan line SLn 202, a second data line 204b, and another pixel unit Pn 206.
  • the technical solution adopted by the patent application is to use two data lines between two pixel units, one of which is used for charging two pixel units (that is, transmitting video signals), Another data line is used to pre-charge capacitor 212. That is, in addition to charging the pixel unit by the first data line, the pixel unit can be further charged by the charged capacitor of the lower level control module to achieve the purpose of fast charging, thereby effectively shortening the charging time of the pixel.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种薄膜晶体管矩阵结构（200）及液晶显示面板，所述薄膜晶体管矩阵结构（200）包括若干扫描线（202）、若干数据线、若干第一数据线（204a）、若干第二数据线（204b）、若干像素单元（206）以及若干控制模块（208）。每一控制模块（208）耦接于一扫描线（202）、一第二数据线（204b）以及一像素单元（206），当开启一扫描线（202）以使一第一数据线（204a）对所述像素单元（206）充电时，通过所述第二数据线（204b）以同时对下级控制模块（208）作充电，当关闭所述扫描线（202）且开启另一扫描线（202）以使所述第一数据线（204a）对另一像素单元（206）作充电时，所述充电的下级控制模块（208）对所述另一像素单元（206）作快速充电，以缩短像素的充电时间。

Description

薄膜晶体管矩阵结构及液晶显示面板 技术领域
本专利申请涉及一种晶体管矩阵结构及其显示面板，且特别是涉及一种薄膜晶体管矩阵结构及液晶显示面板。
 背景技术
薄膜晶体管矩阵结构(Thin-Film Transistor Array, TFT Array)是液晶显示器(Liquid Crystal Display, LCD)不可或缺的重要显示组件，图1是现有技术的薄膜晶体管矩阵结构100的结构示意图。其中薄膜晶体管矩阵结构100主要是由若干个像素单元(pixel unit)102、若干条扫描线(scan line)104以及若干条数据线(data line)106所组成。
这些像素单元102电性连接这些扫描线104与数据线106，每一像素单元102具有一晶体管108、液晶电容(liquid-crystal capacitor, CLC)110以及储存电容(storage capacitor, CS) 112，其中每一晶体管108具有一闸极(gate)G、一源极(source)S以及一汲极(drain)D，而闸极G连接扫描线104，源极S连接数据线106，且汲极D共同连接液晶电容(CLC)110以及储存电容(CS)112，所述液晶电容(CLC)110以及储存电容(CS)112接地(如图1所示)或是共同连接至共享线(common line)(未图示)。
当第一扫描线(SL1)上施加足够大的正电压时，连接所述第一扫描线(SL1)上的薄膜晶体管108会被开启(switch on)，使这些液晶电容的像素电极与垂直方向的资料线106电性导通，而经由垂直数据线送入对应的视频信号，以将这些液晶电容充电至适当的电压水平；换言之，对这些像素单元所对应的液晶电容进行充电，以驱动液晶层内的液晶分子，使液晶显示器显示影像；同时，对连接所述数据线的这些储存电容112进行充电，所述储存电容112在于使液晶电容110两端的电压维持在一定值下，亦即在未进行数据更新之前，液晶电容110的两端电压藉由储存电容112维持住。接着，施加足够大的负电压，关闭(switch off)薄膜晶体管108，直到下次再重新写入视频信号，其间使得电荷保存在液晶电容110上，此时再启动次一条水平扫描线(SL2)104，而经由垂直数据线106送入其对应的视频信号。
然而，必须在目前扫描线(SL1)上的薄膜晶体管108关闭之后，才能对次扫描线(SL2)的像素单元(P2)的液晶电容110以及储存电容充电，耗费较长的充电时间。因此需要发展一种新式的薄膜晶体管矩阵结构，以解决上述充电时间过长的问题。
 技术问题
本专利申请提供一种薄膜晶体管矩阵结构及液晶显示面板，以解决上述像素充电时间过长的问题。
 技术解决方案
本专利申请的目的在于提供一种薄膜晶体管矩阵结构及液晶显示面板，以解决上述像素充电时间过长的问题，其通过预先充电的电容器，缩短像素的充电时间。
为达到上述发明目的，本专利申请提供一种薄膜晶体管矩阵结构及液晶显示面板，薄膜晶体管矩阵结构包括若干扫描线、若干第一数据线、若干第二数据线、若干像素单元以及若干控制模块。若干第一数据线，以与所述若干扫描线交错设置；若干第二数据线，以与所述若干扫描线交错设置；若干像素单元，每一像素单元分别耦接一扫描线以及一第一数据线；以及若干控制模块，每一控制模块耦接于一扫描线、一第二数据线以及一像素单元之间，当开启一扫描线以使一第一数据线对所述像素单元充电时，通过所述第二数据线以对下级控制模块作充电，当关闭所述扫描线且开启另一扫描线以使所述第一数据线对另一像素单元作充电时，所述充电的下级控制模块对所述另一像素单元作充电。
在一实施例中，下级控制模块还包括第一控制晶体管、第二控制晶体管以及电容器。第一控制晶体管耦接于所述扫描线、所述第二数据线、所述像素单元、以及一上级控制模块；第二控制晶体管，耦接所述另一扫描线以及所述另一像素单元；以及电容器，耦接所述下级控制模块的所述第一控制晶体管以及第二控制晶体管。
在一实施例中，当开启一扫描线以使所述第一数据线对所述像素单元充电时，通过所述第二数据线与所述第一控制晶体管，以对下级控制模块的电容器作充电，当关闭所述扫描线并且开启另一扫描线以使所述第一数据线对另一像素单元充电时，所述充电的下级控制模块的电容器对所述另一像素单元充电。
在一实施例中，上级控制模块还包括第一控制晶体管、第二控制晶体管以及电容器。第一控制晶体管；第二控制晶体管，耦接所述扫描线、所述像素单元以及所述下级控制模块的第一控制晶体管的闸极；以及电容器，耦接所述第二控制晶体管。
在一实施例中，像素单元还包括切换晶体管、液晶电容以及储存电容。切换晶体管耦接所述扫瞄线、所述第一数据线以及所述上级控制模块的第二控制晶体管以及下级控制模块的第一控制晶体管的闸极；液晶电容，耦接所述切换晶体管；以及储存电容耦接所述切换晶体管并且与所述液晶电容并联。
本专利申请另提供一种液晶显示面板，包括扫描驱动模块以及数据驱动模块，其特征在于，所述液晶显示面板还设置一薄膜晶体管矩阵结构，所述扫描驱动模块以及数据驱动模块用以驱动所述薄膜晶体管矩阵结构，所述薄膜晶体管矩阵结构包括若干扫描线、若干第一数据线、若干第二数据线、若干像素单元以及若干控制模块。若干第一数据线，以与所述若干扫描线交错设置；若干第二数据线，以与所述若干扫描线交错设置；若干像素单元，每一像素单元分别耦接一扫描线以及一第一数据线；以及若干控制模块，每一控制模块耦接于一扫描线、一第二数据线以及一像素单元之间，当开启一扫描线以使一第一数据线对所述像素单元充电时，通过所述第二数据线以对下级控制模块作充电，当关闭所述扫描线且开启另一扫描线以使所述第一数据线对另一像素单元作充电时，所述充电的下级控制模块对所述另一像素单元作充电。
在一实施例中，下级控制模块还包括第一控制晶体管、第二控制晶体管以及电容器。第一控制晶体管耦接于所述扫描线、所述第二数据线、所述像素单元、以及一上级控制模块；第二控制晶体管，耦接所述另一扫描线以及所述另一像素单元；以及电容器，耦接所述下级控制模块的所述第一控制晶体管以及第二控制晶体管。
在一实施例中，当开启一扫描线以使所述第一数据线对所述像素单元充电时，通过所述第二数据线与所述第一控制晶体管，以对下级控制模块的电容器作充电，当关闭所述扫描线并且开启另一扫描线以使所述第一数据线对另一像素单元充电时，所述充电的下级控制模块的电容器对所述另一像素单元充电。
在一实施例中，上级控制模块还包括第一控制晶体管、第二控制晶体管以及电容器。第一控制晶体管；第二控制晶体管，耦接所述扫描线、所述像素单元以及所述下级控制模块的第一控制晶体管的闸极；以及电容器，耦接所述第二控制晶体管。
在一实施例中，像素单元还包括切换晶体管、液晶电容以及储存电容。切换晶体管耦接所述扫瞄线、所述第一数据线以及所述上级控制模块的第二控制晶体管以及下级控制模块的第一控制晶体管的闸极；液晶电容，耦接所述切换晶体管；以及储存电容耦接所述切换晶体管并且与所述液晶电容并联。
本专利申请薄膜晶体管矩阵结构及液晶显示面板通过开启控制晶体管，通过预先充电的电容器以及两条数据线驱动像素，缩短像素的充电时间。
 有益效果
本专利申请薄膜晶体管矩阵结构及液晶显示面板通过开启控制晶体管，通过预先充电的电容器以及两条数据线驱动像素，缩短像素的充电时间。
 附图说明
图1为现有技术的薄膜晶体管矩阵结构的示意图。
图2为根据本专利申请实施例中薄膜晶体管矩阵结构的示意图。
图3为根据本专利申请实施例中具有薄膜晶体管矩阵结构的液晶显示面板的示意图。
 本发明的最佳实施方式
图1为现有技术的薄膜晶体管矩阵结构的示意图。
图2为根据本专利申请实施例中薄膜晶体管矩阵结构的示意图。
图3为根据本专利申请实施例中具有薄膜晶体管矩阵结构的液晶显示面板的示意图。
具体实施方式
本专利申请提供不同的实施例来说明本专利申请不同实施方式的技术特征。实施例中的各组件的配置是为了清楚说明本专利申请揭示的内容，并非用以限制本专利申请。在不同的图式中，相同的组件符号表示相同或相似的组件。
参考图2，其为根据本专利申请实施例中薄膜晶体管矩阵结构200的示意图。所述薄膜晶体管矩阵结构200包括若干扫描线202、若干第一数据线204a、若干第二数据线204b、若干像素单元206以及若干控制模块208。若干扫描线202分别与若干第一数据线204a及若干第二数据线204b互相交错排列设置。此处是以两条扫描线SL(n-1)、SLn 202与一条第一资料线DL1 204a、一条第二资料线DL2 204b交错排列设置，两个像素单元P(n-1)、Pn 206，以及两个控制模块CT(n-1)、CTn 208为例作说明，但是其数量不限于此。
每一像素单元P(n-1)、Pn 206分别耦接于一扫描线202、一第一数据线204a以及控制模块208之间，所述若干像素单元P(n-1)、Pn 206分别设置于两条扫描线SL(n-1)、SLn 202与一条第一资料线DL1 204a及一条第二资料线DL2 204b交错位置附近。
若干控制模块208a、208b设置于像素单元P(n-1)、Pn 206之间。其中一控制模块208a耦接于一扫描线SL(n-1) 202、一第二数据线204b以及一像素单元P(n-1) 206之间；另一控制模块208b耦接于另一扫描线SLn 202、一第二数据线204b以及另一像素单元Pn 206之间。当开启一扫描线SL(n-1) 202以使第一资料线DL1 204a对所述像素单元P(n-1) 206充电时，通过所述第二数据线DL2 204b以对下级控制模块208b作充电，当关闭所述扫描线SL(n-1) 202且开启另一扫描线SLn 202以使所述第一资料线DL1 204a对另一像素单元Pn 206作充电时，所述充电的下级控制模块208b对所述另一像素单元Pn 206作充电。
所述下级控制模块208b还包括第一控制晶体管210a、第二控制晶体管210b以及电容器212。第一控制晶体管210a耦接于所述扫描线SL(n-1) 202、所述第二资料线DL2 204b、所述像素单元P(n-1) 206、以及一上级控制模块208a。第二控制晶体管210b耦接所述另一扫描线SLn 202以及所述另一像素单元Pn 206。电容器212耦接所述下级控制模块208b的所述第一控制晶体管210a以及第二控制晶体管210b。当开启一扫描线SL(n-1) 202以使所述第一资料线DL1 204a对所述像素单元P(n-1) 206充电时，通过所述第二数据线DL2 204b与所述下级控制模块208b的第一控制晶体管210a，以对下级控制模块208b的电容器212作充电，当关闭所述扫描线SL(n-1) 202并且开启另一扫描线SLn 202以使所述第一资料线DL1 204a对另一像素单元Pn 206充电时，所述充电的下级控制模块208b的电容器212对所述另一像素单元Pn 206充电。
所述上级控制模块208a与所述下级控制模块208b类似，所述上级控制模块208a还包括第一控制晶体管210a、第二控制晶体管210b以及电容器212。第二控制晶体管210b耦接所述扫描线SL(n-1) 202、所述像素单元P(n-1) 206以及所述下级控制模块208b的第一控制晶体管210a的闸极。电容器212耦接所述第二控制晶体管210b。
根据上述，本专利申请之薄膜晶体管矩阵结构200运作时，在两个像素单元206之间利用两条数据线204a、204b，其中一条资料线204a用于对两个像素单元进行充电(亦即传送视频讯号)，另一条数据线204b用于对电容器212预先充电。具体来说，施加一电压(例如正电压)至所述扫描线SL(n-1) 202，藉由开启像素单元P(n-1) 206的切换晶体管214，以对像素单元P(n-1) 206作充电，并且开启控制模块208a的第一控制晶体管210b，以使第二数据线DL 2 204b 传送视频信号，以通过下级控制模块208b的第一控制晶体管210a而对下级控制模块208b的电容器212预先进行充电。
接着，施加另一电压(例如负电压)至所述扫描线SL(n-1) 202，以关闭像素单元P(n-1) 206的切换晶体管214、上级控制模块208a的第二控制晶体管210b、以及下级控制模块208b的第一控制晶体管210a，亦即关闭与扫描线SL(n-1) 202连接的晶体管。然后，施加电压至所述另一扫描线SLn 202，藉由开启像素单元Pn 206的切换晶体管214，以对像素单元Pn 206作充电，同时通过下级控制模块208b的已充电电容器212对像素单元Pn 206作充电，如此可以节省像素单元Pn 206的充电时间，进行像素的快速充电。换言之，当切换晶体管214开启时，除了第一数据线DL1 204对像素单元Pn 206充电之外，可以进一步利用下级控制模块208b的已充电电容器212对像素单元Pn 206作充电，以达到快速充电的目的，有效缩短像素的充电时间。
所述像素单元P(n-1) 206还包括切换晶体管214、液晶电容(liquid-crystal capacitor, CLC)216以及储存电容(storage capacitor, CS)218。切换晶体管214耦接所述扫瞄线SL(n-1) 202、所述第一数据线DL1 204a、所述上级控制模块208a的第二控制晶体管210b以及下级控制模块208b的第一控制晶体管210a的闸极。液晶电容216耦接所述切换晶体管214的汲极以及所述上级控制模块208a的第二控制晶体管210b的源极。储存电容218耦接所述切换晶体管214的汲极以及所述上级控制模块208a的第二控制晶体管210b的源极，储存电容218并且与所述液晶电容216并联。
所述像素单元Pn 206与所述像素单元P(n-1) 206相同，所述像素单元Pn 206还包括切换晶体管214、液晶电容216以及储存电容218。切换晶体管214耦接所述扫瞄线SLn 202、所述第一数据线DL1 204a以及所述下级控制模块208b的第二控制晶体管210b。液晶电容216耦接所述切换晶体管214的汲极以及所述下级控制模块208b的第二控制晶体管210b的源极。储存电容218耦接所述切换晶体管214的汲极以及所述下级控制模块208b的第二控制晶体管210b的源极，储存电容218并且与所述液晶电容216并联。
参考图2以及图3，图3为根据本专利申请实施例中具有薄膜晶体管矩阵结构200的液晶显示面板300的示意图。液晶显示面板300包括扫描驱动模块302、数据驱动模块304以及薄膜晶体管矩阵结构200。扫描驱动模块302以及数据驱动模块304用以驱动薄膜晶体管矩阵结构200，亦即扫描驱动模块302施加电压至扫描线202上，以控制连接于扫描线202的切换晶体管214、控制模块的第一晶体管210a与第二晶体管210b之开启或是关闭状态。数据驱动模块304传送视频信号至像素单元Pn、Pn(-1) 206，进而对这些像素单元Pn、P(n-1) 206所对应的液晶电容进行充电，以驱动液晶层内的液晶分子，使液晶显示器显示影像。
所述薄膜晶体管矩阵结构200包括若干扫描线202、若干第一数据线204a、若干第二数据线204b、若干像素单元206以及若干控制模块208。若干扫描线202分别与若干第一数据线204a及若干第二数据线204b互相交错排列设置。此处是以两条扫描线SL(n-1)、SLn 202与一条第一资料线DL1 204a、一条第二资料线DL2 204b交错排列设置，两个像素单元P(n-1)、Pn 206，以及两个控制模块CT(n-1)、CTn 208为例作说明，但是其数量不限于此。
每一像素单元P(n-1)、Pn 206分别耦接于一扫描线202、一第一数据线204a以及控制模块208之间，所述若干像素单元P(n-1)、Pn 206分别设置于两条扫描线SL(n-1)、SLn 202与一条第一资料线DL1 204a及一条第二资料线DL2 204b交错位置附近。
若干控制模块208a、208b设置于像素单元P(n-1)、Pn 206之间。其中一控制模块208a耦接于一扫描线SL(n-1) 202、一第二数据线204b以及一像素单元P(n-1) 206之间；另一控制模块208b耦接于另一扫描线SLn 202、一第二数据线204b以及另一像素单元Pn 206之间。当开启一扫描线SL(n-1) 202以使第一资料线DL1 204a对所述像素单元P(n-1) 206充电时，通过所述第二数据线DL2 204b以对下级控制模块208b作充电，当关闭所述扫描线SL(n-1) 202且开启另一扫描线SLn 202以使所述第一资料线DL1 204a对另一像素单元Pn 206作充电时，所述充电的下级控制模块208b对所述另一像素单元Pn 206作充电。
为达到缩短像素的充电时间，本专利申请采取的技术方案是在两个像素单元之间利用两条数据线，其中一条数据线用于对两个像素单元进行充电(亦即传送视频讯号)，另一条数据线用于对电容器212预先充电。亦即除了第一数据线对像素单元充电之外，可以进一步利用下级控制模块的已充电电容器对像素单元作充电，以达到快速充电的目的，有效缩短像素的充电时间。
虽然本专利申请已用较佳实施例揭露如上，然其并非用以限定本专利申请，本专利申请所属技术领域中具有通常知识者，在不脱离本专利申请的精神和范围内，当可作各种的更动与润饰，因此本专利申请的保护范围当视后附的权利要求范围所界定者为准。
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Claims (10)

  1. 一种薄膜晶体管矩阵结构，其特征在于，所述薄膜晶体管矩阵结构包括：
    若干扫描线；
    若干第一数据线，以与所述若干扫描线交错设置；
    若干第二数据线，以与所述若干扫描线交错设置；
    若干像素单元，每一像素单元分别耦接一扫描线以及一第一数据线；以及
    若干控制模块，每一控制模块耦接于一扫描线、一第二数据线以及一像素单元之间，当开启一扫描线以使一第一数据线对所述像素单元充电时，通过所述第二数据线以对下级控制模块作充电，当关闭所述扫描线且开启另一扫描线以使所述第一数据线对另一像素单元作充电时，所述充电的下级控制模块对所述另一像素单元作充电。
  2. 根据权利要求1所述的薄膜晶体管矩阵结构，其特征在于，所述下级控制模块还包括：
    一第一控制晶体管，耦接于所述扫描线、所述第二数据线、所述像素单元、以及一上级控制模块；
    一第二控制晶体管，耦接所述另一扫描线以及所述另一像素单元；以及
    一电容器，耦接所述下级控制模块的所述第一控制晶体管以及第二控制晶体管。
  3. 根据权利要求2所述的薄膜晶体管矩阵结构，其特征在于，当开启一扫描线以使所述第一数据线对所述像素单元充电时，通过所述第二数据线与所述第一控制晶体管，以对下级控制模块的电容器作充电，当关闭所述扫描线并且开启另一扫描线以使所述第一数据线对另一像素单元充电时，所述充电的下级控制模块的电容器对所述另一像素单元充电。
  4. 根据权利要求2所述的薄膜晶体管矩阵结构，其特征在于，所述上级控制模块还包括：
    一第一控制晶体管；
    一第二控制晶体管，耦接所述扫描线、所述像素单元以及所述下级控制模块的第一控制晶体管的闸极；以及
    一电容器，耦接所述第二控制晶体管。
  5. 根据权利要求4所述的薄膜晶体管矩阵结构，其特征在于，所述像素单元还包括：
    一切换晶体管，耦接所述扫瞄线、所述第一数据线以及所述上级控制模块的第二控制晶体管以及下级控制模块的第一控制晶体管的闸极；
    一液晶电容，耦接所述切换晶体管；以及
    一储存电容，耦接所述切换晶体管并且与所述液晶电容并联。
  6. 一种液晶显示面板，包括扫描驱动模块以及数据驱动模块，其特征在于，所述液晶显示面板还设置一薄膜晶体管矩阵结构，所述扫描驱动模块以及数据驱动模块用以驱动所述薄膜晶体管矩阵结构，所述薄膜晶体管矩阵结构包括：
    若干扫描线；
    若干第一数据线，以与所述若干扫描线交错设置；
    若干第二数据线，以与所述若干扫描线交错设置；
    若干像素单元，每一像素单元分别耦接一扫描线以及一第一数据线；以及
    若干控制模块，每一控制模块耦接于一扫描线、一第二数据线以及一像素单元之间，当开启一扫描线以使一第一数据线对所述像素单元充电时，通过所述第二数据线以对下级控制模块作充电，当关闭所述扫描线且开启另一扫描线以使所述第一数据线对另一像素单元作充电时，所述充电的下级控制模块对所述另一像素单元作充电。
  7. 根据权利要求5所述的液晶显示面板，其特征在于，所述下级控制模块还包括：
    一第一控制晶体管，耦接于所述扫描线、所述第二数据线、所述像素单元、以及一上级控制模块；
    一第二控制晶体管，耦接所述另一扫描线以及所述另一像素单元；以及
    一电容器，耦接所述下级控制模块的所述第一控制晶体管以及第二控制晶体管。
  8. 根据权利要求7所述的液晶显示面板，其特征在于当开启一扫描线以使所述第一数据线对所述像素单元充电时，通过所述第二数据线与所述第一控制晶体管，以对下级控制模块的电容器作充电，当关闭所述扫描线并且开启另一扫描线以使所述第一数据线对另一像素单元充电时，所述充电的下级控制模块的电容器对所述另一像素单元充电。
  9. 根据权利要求7所述的液晶显示面板，其特征在于，所述上级控制模块还包括：
    一第一控制晶体管；
    一第二控制晶体管，耦接所述扫描线、所述像素单元以及所述下级控制模块的第一控制晶体管的闸极；以及
    一电容器，耦接所述第二控制晶体管。
  10. 根据权利要求9所述的液晶显示面板，其特征在于，所述像素单元还包括：
    一切换晶体管，耦接所述扫瞄线、所述第一数据线以及所述上级控制模块的第二控制晶体管以及下级控制模块的第一控制晶体管的闸极；
    一液晶电容，耦接所述切换晶体管；以及
    一储存电容，耦接所述切换晶体管并且与所述液晶电容并联。
PCT/CN2011/075956 2011-06-08 2011-06-20 薄膜晶体管矩阵结构及液晶显示面板 Ceased WO2012167451A1 (zh)

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104460144A (zh) * 2013-09-24 2015-03-25 业鑫科技顾问股份有限公司 薄膜晶体管基板、驱动薄膜晶体管基板的方法及显示装置
CN103985342B (zh) * 2014-05-09 2017-01-04 深圳市华星光电技术有限公司 显示面板及其驱动方法
CN107255894B (zh) * 2017-08-09 2020-05-05 深圳市华星光电技术有限公司 阵列基板及液晶显示面板
CN109917595B (zh) * 2017-12-12 2021-01-22 京东方科技集团股份有限公司 像素结构及其驱动方法、显示面板、显示装置
WO2019186320A1 (ja) * 2018-03-30 2019-10-03 株式会社半導体エネルギー研究所 表示装置、及び表示装置の駆動方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201072484Y (zh) * 2007-07-30 2008-06-11 胜华科技股份有限公司 主动元件阵列基板以及液晶显示面板
CN101446722A (zh) * 2008-10-17 2009-06-03 友达光电股份有限公司 液晶显示面板与液晶显示装置
CN101598879A (zh) * 2009-07-10 2009-12-09 昆山龙腾光电有限公司 液晶显示面板及液晶显示器
CN101697055A (zh) * 2009-11-07 2010-04-21 福州华映视讯有限公司 具有电荷分享架构的显示面板的画素结构及其驱动方法
CN101866087A (zh) * 2009-04-14 2010-10-20 群康科技(深圳)有限公司 子像素结构及液晶显示面板

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003108055A (ja) * 2001-09-28 2003-04-11 Toshiba Corp 表示装置
JP2003228080A (ja) * 2002-01-31 2003-08-15 Toshiba Corp 表示画素回路および平面表示装置
CN1987979A (zh) * 2005-12-21 2007-06-27 群康科技(深圳)有限公司 液晶显示面板驱动电路和采用该驱动电路的液晶显示面板
KR101358334B1 (ko) * 2007-07-24 2014-02-06 삼성디스플레이 주식회사 액정 표시 장치 및 그 구동 방법
US8648782B2 (en) * 2007-10-22 2014-02-11 Semiconductor Energy Laboratory Co., Ltd. Display device
KR101518325B1 (ko) * 2008-12-18 2015-05-11 삼성디스플레이 주식회사 액정 표시 장치
TWM419123U (en) * 2011-01-18 2011-12-21 Chunghwa Picture Tubes Ltd Pixel structure with pre-charge function

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201072484Y (zh) * 2007-07-30 2008-06-11 胜华科技股份有限公司 主动元件阵列基板以及液晶显示面板
CN101446722A (zh) * 2008-10-17 2009-06-03 友达光电股份有限公司 液晶显示面板与液晶显示装置
CN101866087A (zh) * 2009-04-14 2010-10-20 群康科技(深圳)有限公司 子像素结构及液晶显示面板
CN101598879A (zh) * 2009-07-10 2009-12-09 昆山龙腾光电有限公司 液晶显示面板及液晶显示器
CN101697055A (zh) * 2009-11-07 2010-04-21 福州华映视讯有限公司 具有电荷分享架构的显示面板的画素结构及其驱动方法

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