WO2012163294A1 - Passive electronic tag - Google Patents

Passive electronic tag Download PDF

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Publication number
WO2012163294A1
WO2012163294A1 PCT/CN2012/076389 CN2012076389W WO2012163294A1 WO 2012163294 A1 WO2012163294 A1 WO 2012163294A1 CN 2012076389 W CN2012076389 W CN 2012076389W WO 2012163294 A1 WO2012163294 A1 WO 2012163294A1
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WO
WIPO (PCT)
Prior art keywords
substrate
passive electronic
electronic tag
hole
chip
Prior art date
Application number
PCT/CN2012/076389
Other languages
French (fr)
Chinese (zh)
Inventor
刘智佳
Original Assignee
Liu Zhijia
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Liu Zhijia filed Critical Liu Zhijia
Publication of WO2012163294A1 publication Critical patent/WO2012163294A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0723—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
    • G06K19/0726—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs the arrangement including a circuit for tuning the resonance frequency of an antenna on the record carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2208—Supports; Mounting means by structural association with other equipment or articles associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems
    • H01Q1/2225—Supports; Mounting means by structural association with other equipment or articles associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems used in active tags, i.e. provided with its own power source or in passive tags, i.e. deriving power from RF signal

Definitions

  • the invention relates to a passive electronic tag. Background technique
  • the electronic tags are mainly classified into active tags, semi-active tags and passive tags.
  • Active tags and semi-active tags have an external battery that provides energy for the operation of the tag chip via an external battery.
  • Passive tags rely on the reader's RF signal to provide energy to operate, and passive tags have the advantages of low cost and large-scale production.
  • the chip is generally directly exposed on the surface of the substrate. Therefore, the electronic tag is easily affected by the external environment (such as moisture or high temperature), and the electronic tag is easily worn during handling or installation.
  • the passive electronic tag includes: a radiating surface, a second substrate, a ground plane, and a label chip, wherein the second substrate is located below the radiating surface, the ground plane is located below the second substrate, and the passive electronic tag a first substrate, between the radiating surface and the second substrate, an opening (13) passing through the radiating surface and the first substrate; a label chip located on the upper surface of the second substrate and the first Between the lower surfaces of the substrate and in the openings (13).
  • Another object of the present invention is to provide a passive electronic tag comprising: a radiating surface; a first substrate located below the radiating surface; a second substrate located below the first substrate; a ground plane, located at the second a label chip, between the upper surface of the second substrate and the lower surface of the first substrate, a tuning via (6) on the surface of the passive electronic tag for adjusting the substrate
  • the frequency of the passive electronic tag, the tuning via (6) is composed of a plurality of first through holes, wherein the tuning via (6) is located on the radiation surface (1), the first substrate (2), the second substrate (3) and the ground plane (11), the plurality of first through holes passing through the first substrate (2) and the second
  • the substrate (3) electrically connects the radiating surface (1) and the ground plane (11).
  • the present invention improves the tag's ability to protect against chip data and corrects for frequency offsets due to production errors.
  • FIG. 1 is an exploded perspective view of a passive electronic tag 100
  • FIG. 2 is an overall schematic view of a passive electronic tag 100. detailed description
  • a passive electronic tag disclosed in the present invention includes a radiating surface 1, a first substrate 2, a second substrate 3, a ground plane 11, a label chip 12, and a circle.
  • the first substrate 2 of the passive electronic tag is located below the radiating surface 1
  • the second substrate 3 is located below the first substrate 2
  • the grounding surface 11 is located below the second substrate 3
  • the radiating surface 1 and A substrate 2 has the circular opening 13
  • the label chip 12 is located in the circular opening 13, that is, between the upper surface of the second substrate 3 and the lower surface of the first substrate 2.
  • the first through hole unit 4 and the second through hole unit 5 are respectively located on both sides of the radiation surface 1, the first substrate 2, the second substrate 3, and the ground plane 11, and are formed by a plurality of diameters of, for example, 0.2 mm to 1.5 mm.
  • the second through hole is configured to electrically connect the radiation surface 1 and the ground surface 4 through the first substrate 2 and the second substrate 3.
  • the first bonding via hole and the second bonding via 8 respectively pass through the tag chip 12, the first substrate 2 and the radiating surface 1, so that the first bonding via 7 can be connected to the first feeding line 9, the second state
  • the fixed through hole 8 can be connected to the second feed line 10, but the first bonding through hole ⁇ and the second bonding through hole 8 are not connected to the ground plane 11, and the grounding surface 11 is made to be hollowed out to prevent the connection.
  • the first bonding through hole 7 and the second bonding through hole 8 can also pass through the second substrate 3, and the main reason for this is that if the second substrate 2 is not passed, the processing process is complicated and the manufacturing cost is relatively high. High, of course, it is also possible to choose not to pass through the second substrate 3 as the case may be.
  • the first feed line 9 and the second feed line 10 are located on the upper surface of the second substrate 3, are arranged on both sides of the label chip 12, and the label chip 12 is bonded to the first feed line 9 and the second feed line 10, the first feed line 9 and The second feed line 10 is connected to the radiating surface 1 through the first bonding through hole 7 and the second tuning through hole bonding through hole 8.
  • the tag chip 12 is preferably located in the center of the circular opening 13, but may be slightly offset.
  • the opening 13 is circular in this embodiment, it will be understood by those skilled in the art that the opening may be any other shape such as a square, a rectangle or a polygon as long as it can accommodate the tag chip 12.
  • the tag chip Since the present invention embeds the tag chip in the opening of the substrate, the tag chip can be effectively protected from the external ring.
  • the passive electronic tag of the present invention can include a tuned via 6.
  • the tuning via 6 is located on the surface of the passive electronic tag for adjusting the frequency of the passive electronic tag, and the tuning via 6 is formed by a plurality of first vias.
  • the passive electronic tag of the present invention further comprises a radiating surface 1; a first substrate 2, located below the radiating surface 1; a second substrate 3, located below the first substrate 2; a grounding surface 11, located at the second substrate a lower portion of the labeling chip 12, located between the upper surface of the second substrate 3 and the lower surface of the first substrate 2; wherein the tuning via 6 is located on the radiation surface 1, the first substrate 2, the second substrate 3 and the ground plane 11 are formed by, for example, seven first through holes having a diameter of 0.2 mm to 1.5 mm on each side, and the tuning through holes 6 are electrically connected to the radiating surface 1 through the first substrate 2 and the second substrate 3 Ground 4.
  • the passive electronic tag of the present invention may further include a first through hole unit 4, a second through hole unit 5, a first bonding through hole 7, a second bonding through hole 8, a first feeding line 9, and a second feeding line 10. .
  • the first through hole unit 4 and the second through hole unit 5 are respectively located on both sides of the radiation surface 1, the first substrate 2, the second substrate 3, and the ground plane 11, and are formed by a plurality of second through holes having a diameter of, for example, 0.2 mm.
  • the second through hole electrically connects the radiation surface 1 and the ground surface 4 through the first substrate 2 and the second substrate 3.
  • the first bonding via 7 and the second bonding via 8 respectively pass through the tag chip 12, the first substrate 2, and the radiating surface 1, so that the first bonding via 7 can be connected to the first feeding line 9, the second state
  • the fixed through hole 8 can be connected to the second feed line 10, but the first bonding through hole 7 and the second bonding through hole 8 are not connected to the ground plane 11, and the grounding surface 11 is made to be hollowed out to prevent the connection.
  • the first bonding through hole 7 and the second bonding through hole 8 can also pass through the second substrate 3, and the main reason for this is that if the second substrate 2 is not passed, the processing process is complicated and the manufacturing price is relatively high. High, of course, it is also possible to choose not to pass through the second substrate 3 as the case may be.
  • the first feed line 9 and the second feed line 10 are located on the upper surface of the second substrate 3, are arranged on both sides of the label chip 12, and the label chip 12 is bonded to the first feed line 9 and the second feed line 10, and the first feed line 9 and The second feed line 10 is connected to the radiating surface 1 through the first bonding through hole 7 and the second tuning through hole bonding through hole 8.
  • the tuning vias 6 are preferably located on the radiating surface 1, the first substrate 2, the second substrate 3, and the ground plane 11 on both sides perpendicular to the second via unit 5 and adjacent to the second via unit 5. .
  • the tuning via 6 may also be adjacent to the first via unit 4 or may be placed near the center line.
  • the tuning vias may be placed only on one side or on the other side (e.g., the tuning vias 6 on one side of Figure 1 are removed, leaving only one side).
  • the distribution of the tuning vias 6 is preferably evenly distributed.
  • the first feed line 9 and the second feed line 10 are coincident polygons having a distance greater than a pin width equal to the chip 12, preferably a pin width just for conveniently mounting the chip 12.
  • the thickness of the first substrate 2 is larger than the thickness of the label chip 12 and is less than 3 mm.
  • the material of the second feed line 10 is all metal, such as copper.
  • the first substrate 2 and the second substrate 3 are made of a dielectric material having a dielectric constant of 2 to 150.
  • the tuning via is tuned by: Using a special tool, by damaging the metal layer in the via, the tuning via is no longer able to connect the radiating surface to the ground plane, which will cause the tag resonant frequency to drop.
  • Debugging previously "destruction"
  • An example of the sequence of tuning vias begins with a tuning via that is remote from the second via unit, increasing the amount of debugging, symmetrical tuning of the left and right tuning vias, and the resonant frequency is decreasing.
  • the target frequency is at a position of several tuning vias that are in the middle of debugging, i.e., the first vias in the middle of the plurality of first vias. Because in actual production, there will be a large number of parameters, so that the actual frequency and the target frequency are inconsistent, so using this method can make the tag resonate at the target frequency.
  • the present invention also includes a technical solution combining the first embodiment and the second embodiment.
  • the passive electronic tag of the present invention is preferably applicable to the aviation industry, and in particular to the SAE AS5678 standard for the development of aerospace components with strict quality requirements, so that it not only conforms to international standards, but also adapts to various environmental conditions and adapts. Metal surface and fireproof properties. In addition, it can be used in countries all over the world because it can support different frequency bands specified by each country.
  • the progress of the label is that the chip is buried in the substrate by using the opening, which can effectively protect the chip from the external environment, and can have high tolerance to conventional wear and improve the label pair.
  • the present invention also employs a through-hole matching tuning via design that corrects for frequency offsets due to production errors.

Abstract

Disclosed is a passive electronic tag, including: a radiation surface and a second substrate thereunder; a ground surface under the second substrate; a first substrate between the radiation surface and the second substrate; an opening passing through the radiation surface and the first substrate; a tag chip located between the upper surface of the second substrate and the lower surface of the first substrate and in the opening; a first and a second through-hole unit respectively located on either side of the radiation surface, the first substrate, the second substrate and the ground surface and consisting of a plurality of second through-holes, the second through-holes being electrically connected to the radiation surface and the ground surface through the first and second substrate; a first and second binding through-hole passing through the tag chip, the first substrate and the radiation surface instead of the ground surface; and a first and second feeder arranged on either side of the tag chip for binding same and connecting the radiation surface via the first and second binding through-holes. The present invention improves the ability of the tag to protect the chip data and corrects the frequency offset generated by production errors.

Description

无源电子标签  Passive electronic tag
技术领域 Technical field
本发明涉及一种无源电子标签。 背景技术  The invention relates to a passive electronic tag. Background technique
目前， 电子标签技术广泛应用于很多领域， 比如物流管理领域， 医疗产业， 货物和危 险品的追踪管理监控， 航空工业， 强制性的检验产品， 证件防伪， 路桥的不停车收费， 电 子门票等方面。 按照电子标签供电系统的不同结构， 电子标签主要分为有源标签、 半有源 标签和无源标签。有源标签和半有源标签具有外置的电池， 通过外置的电池为标签芯片的 工作提供能量。无源标签依靠阅读器的射频信号提供能量使其工作， 无源标签有着成本低 和大规模生产的优点。  At present, electronic label technology is widely used in many fields, such as logistics management, medical industry, tracking management monitoring of goods and dangerous goods, aviation industry, mandatory inspection products, document security, road and bridge non-stop charging, electronic tickets, etc. . According to the different structures of the electronic tag power supply system, the electronic tags are mainly classified into active tags, semi-active tags and passive tags. Active tags and semi-active tags have an external battery that provides energy for the operation of the tag chip via an external battery. Passive tags rely on the reader's RF signal to provide energy to operate, and passive tags have the advantages of low cost and large-scale production.
现有的无源电子标签中存在以下结构设计的缺陷：  The following structural design defects exist in existing passive electronic tags:
其一： 在现有技术中， 芯片一般直接暴露在基材表面。 因此， 电子标签容易受到外界 环境 （如湿气或者高温等） 的影响， 并且电子标签在搬运或安装过程中容易受到磨损。  One: In the prior art, the chip is generally directly exposed on the surface of the substrate. Therefore, the electronic tag is easily affected by the external environment (such as moisture or high temperature), and the electronic tag is easily worn during handling or installation.
其二： 在生产过程中， 电子标签常常会具有一定的频率偏移， 并且难以进行纠正。 发明内容 本发明的目的是提供一种能解决至少一种上述弊端的无源电子标签。  Second: In the production process, electronic tags often have a certain frequency offset and are difficult to correct. SUMMARY OF THE INVENTION It is an object of the present invention to provide a passive electronic tag that addresses at least one of the above disadvantages.
在一个方案中， 无源电子标签包括： 辐射面、 第二基材、 接地面以及标签芯片， 其中 第二基材位于辐射面的下方，接地面位于第二基材的下方，无源电子标签还包括第一基材， 位于辐射面与第二基材之间， 开孔 （13 ) ， 穿过所述辐射面和第一基材； 标签芯片， 位于 第二基材的上表面与第一基材的下表面之间， 且位于开孔 （13 ) 中。  In one aspect, the passive electronic tag includes: a radiating surface, a second substrate, a ground plane, and a label chip, wherein the second substrate is located below the radiating surface, the ground plane is located below the second substrate, and the passive electronic tag a first substrate, between the radiating surface and the second substrate, an opening (13) passing through the radiating surface and the first substrate; a label chip located on the upper surface of the second substrate and the first Between the lower surfaces of the substrate and in the openings (13).
本发明的另一目的在于提供一种无源电子标签， 包括： 辐射面； 第一基材， 位于辐射 面的下方； 第二基材， 位于第一基材的下方； 接地面， 位于第二基材的下方； 标签芯片， 所述第二基材的上表面与第一基材的下表面之间， 调谐通孔 （6) ， 位于所述无源电子标 签的表面上， 用于调节所述无源电子标签的频率， 所述调谐通孔 （6) 由多个第一通孔构 成， 其中， 所述调谐通孔 （6) 位于所述辐射面 （1 ) 、 所述第一基材 （2) 、 所述第二基 材 （3 ) 以及所述接地面 （11 ) 上， 所述多个第一通孔穿过所述第一基材 （2)和所述第二 基材 （3 ) 电气连接所述辐射面 （1 ) 和所述接地面 （11 ) 。 Another object of the present invention is to provide a passive electronic tag comprising: a radiating surface; a first substrate located below the radiating surface; a second substrate located below the first substrate; a ground plane, located at the second a label chip, between the upper surface of the second substrate and the lower surface of the first substrate, a tuning via (6) on the surface of the passive electronic tag for adjusting the substrate The frequency of the passive electronic tag, the tuning via (6) is composed of a plurality of first through holes, wherein the tuning via (6) is located on the radiation surface (1), the first substrate (2), the second substrate (3) and the ground plane (11), the plurality of first through holes passing through the first substrate (2) and the second The substrate (3) electrically connects the radiating surface (1) and the ground plane (11).
本发明提高了标签对芯片数据的保护能力，且对于因为生产误差造成的频率偏移进行 纠正。 附图说明  The present invention improves the tag's ability to protect against chip data and corrects for frequency offsets due to production errors. DRAWINGS
图 1是无源电子标签 100的分解透视图；  1 is an exploded perspective view of a passive electronic tag 100;
图 2是无源电子标签 100的整体示意图。 具体实施方式  2 is an overall schematic view of a passive electronic tag 100. detailed description
下面结合附图和实施例对本发明作进一步说明。  The invention will now be further described with reference to the accompanying drawings and embodiments.
在第一实施例中， 参照图 1和图 2， 本发明公开的一种无源电子标签包括辐射面 1， 第一基材 2， 第二基材 3， 接地面 11， 标签芯片 12， 圆形开孔 13， 第一通孔单元 4， 第二 通孔单元 5， 第一邦定通孔 7， 第二邦定通孔 8， 第一馈线 9， 第二馈线 10。  In the first embodiment, referring to FIG. 1 and FIG. 2, a passive electronic tag disclosed in the present invention includes a radiating surface 1, a first substrate 2, a second substrate 3, a ground plane 11, a label chip 12, and a circle. The opening hole 13, the first through hole unit 4, the second through hole unit 5, the first bonding through hole 7, the second bonding through hole 8, the first feeding line 9, and the second feeding line 10.
此外， 无源电子标签的第一基材 2位于辐射面 1的下方， 第二基材 3位于第一基材 2 的下方， 接地面 11位于第二基材 3的下方， 辐射面 1和第一基材 2有该圆形开孔 13， 标 签芯片 12位于该圆形开孔 13中， 也即第二基材 3的上表面与第一基材 2的下表面之间。 第一通孔单元 4和第二通孔单元 5分别位于辐射面 1、 第一基材 2、 第二基材 3以及接地 面 11的两侧， 由若干个直径例如 0.2mm-1.5mm的第二通孔构成， 第二通孔穿过第一基材 2和第二基材 3电气连接辐射面 1和接地面 4。 第一邦定通孔 Ί和第二邦定通孔 8分别穿 过标签芯片 12、 第一基材 2以及辐射面 1， 从而第一邦定通孔 7可连接第一馈线 9， 第二 邦定通孔 8可连接第二馈线 10，但是第一邦定通孔 Ί和第二邦定通孔 8没有连接到接地面 11，接地面 11处做镂空防止连接。第一邦定通孔 7和第二邦定通孔 8也可穿过第二基材 3， 这么做的主要原因是， 如果不穿过第二基材 2， 加工工艺比较复杂， 制造价格较高， 当然 也可根据具体情况选择不穿过第二基材 3。第一馈线 9和第二馈线 10位于第二基材 3的上 表面， 分列在标签芯片 12两侧， 标签芯片 12邦定到第一馈线 9和第二馈线 10上， 第一 馈线 9和第二馈线 10通过第一邦定通孔 7和第二调谐通孔邦定通孔 8连接辐射面 1。  In addition, the first substrate 2 of the passive electronic tag is located below the radiating surface 1, the second substrate 3 is located below the first substrate 2, and the grounding surface 11 is located below the second substrate 3, the radiating surface 1 and A substrate 2 has the circular opening 13, and the label chip 12 is located in the circular opening 13, that is, between the upper surface of the second substrate 3 and the lower surface of the first substrate 2. The first through hole unit 4 and the second through hole unit 5 are respectively located on both sides of the radiation surface 1, the first substrate 2, the second substrate 3, and the ground plane 11, and are formed by a plurality of diameters of, for example, 0.2 mm to 1.5 mm. The second through hole is configured to electrically connect the radiation surface 1 and the ground surface 4 through the first substrate 2 and the second substrate 3. The first bonding via hole and the second bonding via 8 respectively pass through the tag chip 12, the first substrate 2 and the radiating surface 1, so that the first bonding via 7 can be connected to the first feeding line 9, the second state The fixed through hole 8 can be connected to the second feed line 10, but the first bonding through hole Ί and the second bonding through hole 8 are not connected to the ground plane 11, and the grounding surface 11 is made to be hollowed out to prevent the connection. The first bonding through hole 7 and the second bonding through hole 8 can also pass through the second substrate 3, and the main reason for this is that if the second substrate 2 is not passed, the processing process is complicated and the manufacturing cost is relatively high. High, of course, it is also possible to choose not to pass through the second substrate 3 as the case may be. The first feed line 9 and the second feed line 10 are located on the upper surface of the second substrate 3, are arranged on both sides of the label chip 12, and the label chip 12 is bonded to the first feed line 9 and the second feed line 10, the first feed line 9 and The second feed line 10 is connected to the radiating surface 1 through the first bonding through hole 7 and the second tuning through hole bonding through hole 8.
此外， 标签芯片 12优选位于圆形开孔 13中央， 然而可以略有偏移。  Furthermore, the tag chip 12 is preferably located in the center of the circular opening 13, but may be slightly offset.
此外， 虽然在本实施例中开孔 13为圆形， 然而本领域普通技术人员应当理解， 开孔 可以是任何其它形状， 例如正方形、 长方形或多边形， 只要其能容纳标签芯片 12即可。  Further, although the opening 13 is circular in this embodiment, it will be understood by those skilled in the art that the opening may be any other shape such as a square, a rectangle or a polygon as long as it can accommodate the tag chip 12.
由于本发明将标签芯片埋入基材的开孔当中，从而可以有效保护标签芯片不受外界环 境的影响， 并且可以对常规磨损有很高的耐受能力， 提高了电子标签对标签芯片数据的保 护能力。 Since the present invention embeds the tag chip in the opening of the substrate, the tag chip can be effectively protected from the external ring. The impact of the environment, and can be highly resistant to conventional wear and improve the ability of electronic tags to protect the data of the tag chip.
在第二实施例中， 本发明的无源电子标签可包括调谐通孔 6。 调谐通孔 6位于无源电 子标签的表面上， 用于调节无源电子标签的频率， 调谐通孔 6由多个第一通孔构成。  In a second embodiment, the passive electronic tag of the present invention can include a tuned via 6. The tuning via 6 is located on the surface of the passive electronic tag for adjusting the frequency of the passive electronic tag, and the tuning via 6 is formed by a plurality of first vias.
本发明的无源电子标签还包括辐射面 1 ; 第一基材 2， 位于辐射面 1的下方； 第二基 材 3， 位于第一基材 2的下方； 接地面 11， 位于第二基材 3的下方； 标签芯片 12， 位于第 二基材 3的上表面与第一基材 2的下表面之间； 其中， 调谐通孔 6位于辐射面 1、 第一基 材 2、第二基材 3以及接地面 11上， 由每边例如 7个直径 0.2mm-1.5mm的第一通孔构成， 调谐通孔 6穿过第一基材 2和第二基材 3电气连接辐射面 1和接地面 4。  The passive electronic tag of the present invention further comprises a radiating surface 1; a first substrate 2, located below the radiating surface 1; a second substrate 3, located below the first substrate 2; a grounding surface 11, located at the second substrate a lower portion of the labeling chip 12, located between the upper surface of the second substrate 3 and the lower surface of the first substrate 2; wherein the tuning via 6 is located on the radiation surface 1, the first substrate 2, the second substrate 3 and the ground plane 11 are formed by, for example, seven first through holes having a diameter of 0.2 mm to 1.5 mm on each side, and the tuning through holes 6 are electrically connected to the radiating surface 1 through the first substrate 2 and the second substrate 3 Ground 4.
本发明的无源电子标签还可包括第一通孔单元 4，第二通孔单元 5，，第一邦定通孔 7， 第二邦定通孔 8， 第一馈线 9， 第二馈线 10。 第一通孔单元 4和第二通孔单元 5分别位于 辐射面 1、 第一基材 2、 第二基材 3以及接地面 11的两侧， 由若干个直径例如 0.2mm的 第二通孔构成， 第二通孔穿过第一基材 2和第二基材 3电气连接辐射面 1和接地面 4。 第 一邦定通孔 7和第二邦定通孔 8分别穿过标签芯片 12、第一基材 2以及辐射面 1， 从而第 一邦定通孔 7可连接第一馈线 9， 第二邦定通孔 8可连接第二馈线 10， 但是第一邦定通孔 7和第二邦定通孔 8没有连接到接地面 11，接地面 11处做镂空防止连接。第一邦定通孔 7 和第二邦定通孔 8也可穿过第二基材 3， 这么做的主要原因是， 如果不穿过第二基材 2， 加工工艺比较复杂， 制造价格较高， 当然也可根据具体情况选择不穿过第二基材 3。 第一 馈线 9和第二馈线 10位于第二基材 3的上表面， 分列在标签芯片 12两侧， 标签芯片 12 邦定到第一馈线 9和第二馈线 10上，第一馈线 9和第二馈线 10通过第一邦定通孔 7和第 二调谐通孔邦定通孔 8连接辐射面 1。  The passive electronic tag of the present invention may further include a first through hole unit 4, a second through hole unit 5, a first bonding through hole 7, a second bonding through hole 8, a first feeding line 9, and a second feeding line 10. . The first through hole unit 4 and the second through hole unit 5 are respectively located on both sides of the radiation surface 1, the first substrate 2, the second substrate 3, and the ground plane 11, and are formed by a plurality of second through holes having a diameter of, for example, 0.2 mm. The second through hole electrically connects the radiation surface 1 and the ground surface 4 through the first substrate 2 and the second substrate 3. The first bonding via 7 and the second bonding via 8 respectively pass through the tag chip 12, the first substrate 2, and the radiating surface 1, so that the first bonding via 7 can be connected to the first feeding line 9, the second state The fixed through hole 8 can be connected to the second feed line 10, but the first bonding through hole 7 and the second bonding through hole 8 are not connected to the ground plane 11, and the grounding surface 11 is made to be hollowed out to prevent the connection. The first bonding through hole 7 and the second bonding through hole 8 can also pass through the second substrate 3, and the main reason for this is that if the second substrate 2 is not passed, the processing process is complicated and the manufacturing price is relatively high. High, of course, it is also possible to choose not to pass through the second substrate 3 as the case may be. The first feed line 9 and the second feed line 10 are located on the upper surface of the second substrate 3, are arranged on both sides of the label chip 12, and the label chip 12 is bonded to the first feed line 9 and the second feed line 10, and the first feed line 9 and The second feed line 10 is connected to the radiating surface 1 through the first bonding through hole 7 and the second tuning through hole bonding through hole 8.
此外， 调谐通孔 6优选位于辐射面 1、 第一基材 2、 第二基材 3以及接地面 11上的与 第二通孔单元 5垂直且与第二通孔单元 5相邻的两边上。然而， 调谐通孔 6也可以与第一 通孔单元 4相邻， 也可以放置在中心线附近。 并且， 调谐通孔还可以仅放置在一边或多边 上 （如将附图 1中一边的调谐通孔 6去除， 仅保留一边） 。 此外， 调谐通孔 6的分布优选 为等距均匀分布。 此外， 第一馈线 9和第二馈线 10为契合的多边形， 二者的距离大于等 于芯片 12的引脚宽度， 优选为恰好方便安装芯片 12的引脚宽度。  In addition, the tuning vias 6 are preferably located on the radiating surface 1, the first substrate 2, the second substrate 3, and the ground plane 11 on both sides perpendicular to the second via unit 5 and adjacent to the second via unit 5. . However, the tuning via 6 may also be adjacent to the first via unit 4 or may be placed near the center line. Also, the tuning vias may be placed only on one side or on the other side (e.g., the tuning vias 6 on one side of Figure 1 are removed, leaving only one side). Further, the distribution of the tuning vias 6 is preferably evenly distributed. In addition, the first feed line 9 and the second feed line 10 are coincident polygons having a distance greater than a pin width equal to the chip 12, preferably a pin width just for conveniently mounting the chip 12.
此外， 第一基材 2厚度大于标签芯片 12的厚度并小于 3mm。  Further, the thickness of the first substrate 2 is larger than the thickness of the label chip 12 and is less than 3 mm.
此外， 辐射面 1、 接地面 11、 第一通孔单元 4、 第二通孔单元 5、 调谐通孔 6、 第一邦 定通孔 7， 第二邦定通孔 8、 第一馈线 9、 第二馈线 10的材料均为金属， 例如为铜。 此外， 第一基材 2和第二基材 3由介电常数为 2〜150的介电材料构成。 In addition, the radiating surface 1, the grounding surface 11, the first through hole unit 4, the second through hole unit 5, the tuning through hole 6, the first bonding through hole 7, the second bonding through hole 8, the first feeding line 9, The material of the second feed line 10 is all metal, such as copper. In addition, The first substrate 2 and the second substrate 3 are made of a dielectric material having a dielectric constant of 2 to 150.
由于采用通孔配合调谐通孔的设计，从而可以对于因为生产误差造成的频率偏移进行 纠正。 在本发明中， 调谐通孔的调谐原理为： 使用专用工具， 通过破坏调谐通孔中的金属 层， 使得调谐通孔不再能够连接辐射面和接地面， 它将使得标签谐振频率下降。 调试（前 文"破坏"）调谐通孔的顺序的一个例子为从远离第二通孔单元的调谐通孔开始， 不断增加 调试， 左右调谐通孔对称同步调试， 谐振频率不断下降。 根据本发明的一个实施例， 在设 计之初， 让目标频率在处于调试到中部的几个调谐通孔的位置， 即所述多个第一通孔的中 部的第一通孔。 因为在实际生产中， 会存在很大参数上的原因， 使得实际频率和目标频率 不一致， 所以使用这种方法就可以使得标签谐振于目标频率。  Thanks to the design of the vias for tuning the vias, it is possible to correct the frequency offset due to production errors. In the present invention, the tuning via is tuned by: Using a special tool, by damaging the metal layer in the via, the tuning via is no longer able to connect the radiating surface to the ground plane, which will cause the tag resonant frequency to drop. Debugging (previously "destruction") An example of the sequence of tuning vias begins with a tuning via that is remote from the second via unit, increasing the amount of debugging, symmetrical tuning of the left and right tuning vias, and the resonant frequency is decreasing. In accordance with an embodiment of the present invention, at the beginning of the design, the target frequency is at a position of several tuning vias that are in the middle of debugging, i.e., the first vias in the middle of the plurality of first vias. Because in actual production, there will be a large number of parameters, so that the actual frequency and the target frequency are inconsistent, so using this method can make the tag resonate at the target frequency.
此外， 本发明还包括将第一实施例和第二实施例结合的技术方案。  Further, the present invention also includes a technical solution combining the first embodiment and the second embodiment.
本发明中的无源电子标签较佳适用于航空工业，尤其可采用对质量要求严格的用于航 空零部件制订的 SAE AS5678标准，因此不但符合国际标准，还实现了适应各种环境条件、 适应金属表面及防火等性能。 另外， 由于可以支持各个国家规定的不同频段， 所以在世界 各国均可使用。  The passive electronic tag of the present invention is preferably applicable to the aviation industry, and in particular to the SAE AS5678 standard for the development of aerospace components with strict quality requirements, so that it not only conforms to international standards, but also adapts to various environmental conditions and adapts. Metal surface and fireproof properties. In addition, it can be used in countries all over the world because it can support different frequency bands specified by each country.
在本发明中， 标签的进步性在于， 采用开孔将芯片埋入基材当中， 可以有效保护芯 片不受外界环境的影响， 并且可以对常规磨损有很高的耐受能力， 提高了标签对芯片数据 的保护能力。 进一步而言， 本发明还采用通孔配合调谐通孔的设计， 可以对于因为生产误 差造成的频率偏移进行纠正。 上面以实施例对本发明进行了说明， 但需要说明的是， 以上 实施例仅用以说明本发明的技术方案， 而并非是对本发明保护范围的限制。尽管参照以上 优选实施例对本发明作了尽可能详尽的说明， 但本领域的技术人员应当理解， 对本发明的 技术方案进行修改或者等同替换， 仍然属于本发明技术方案的实质和范围。 只要对本发明 所做的任何改进或变型， 均应属于本发明权利要求主张保护的范围之内。  In the present invention, the progress of the label is that the chip is buried in the substrate by using the opening, which can effectively protect the chip from the external environment, and can have high tolerance to conventional wear and improve the label pair. Chip data protection. Further, the present invention also employs a through-hole matching tuning via design that corrects for frequency offsets due to production errors. The present invention has been described in the above embodiments, but it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention and are not intended to limit the scope of the present invention. While the present invention has been described in detail with reference to the preferred embodiments of the present invention, it should be understood by those skilled in the art that the modifications and equivalents of the embodiments of the present invention still fall within the spirit and scope of the invention. Any modifications or variations of the present invention are intended to be within the scope of the appended claims.

Claims

1. 一种无源电子标签， 包括： 辐射面 （1) 、 第二基材 （3) 、 接地面 （11) 以及标 签芯片（12)，其中所述的第二基材（3)位于所述辐射面（1)的下方，所述的接地面（11) 位于所述第二基材 （3) 的下方， 其特征在于所述无源电子标签还包括： A passive electronic tag comprising: a radiating surface (1), a second substrate (3), a ground plane (11), and a label chip (12), wherein the second substrate (3) is located Below the radiating surface (1), the grounding surface (11) is located below the second substrate (3), characterized in that the passive electronic label further comprises:
第一基材 （2) ， 位于所述辐射面 （1) 与所述第二基材 （3) 之间；  a first substrate (2) located between the radiation surface (1) and the second substrate (3);
开孔 （13) ， 穿过所述辐射面 （1) 和所述第一基材 （2) ；  Opening (13) through the radiation surface (1) and the first substrate (2);
所述的标签芯片 （12) ， 位于所述第二基材 （3) 的上表面与所述第一基材 （2) 的 下表面之间， 且位于所述开孔 （13) 中。  The label chip (12) is located between the upper surface of the second substrate (3) and the lower surface of the first substrate (2) and is located in the opening (13).
2. 如权利要求 1所述的无源电子标签， 其特征在于， 还包括：  2. The passive electronic tag of claim 1, further comprising:
调谐通孔 （6) ， 位于所述辐射面 （1) 、 所述第一基材 （2) 、 所述第二基材 （3) 以 及所述接地面 （11) 上， 用于调节所述无源电子标签的频率， 所述调谐通孔 （6) 由多个 第一通孔构成， 所述多个第一通孔穿过所述第一基材（2)和所述第二基材（3) 电气连接 所述辐射面 （1) 和所述接地面 （11) 。  Tuning vias (6) on the radiating surface (1), the first substrate (2), the second substrate (3), and the ground plane (11) for adjusting the The frequency of the passive electronic tag, the tuning via (6) is composed of a plurality of first through holes, the plurality of first through holes passing through the first substrate (2) and the second substrate (3) Electrically connect the radiating surface (1) and the ground plane (11).
3. 如权利要求 2所述的无源电子标签， 其特征在于还包括：  3. The passive electronic tag of claim 2, further comprising:
第一通孔单元 （4) 和第二通孔单元 （5) ， 分别位于所述辐射面 （1) 、 所述第一基 材（2) 、 所述第二基材（3) 以及所述接地面 （11) 的两侧， 由多个第二通孔构成， 所述 多个第二通孔穿过所述第一基材 （2) 和所述第二基材 （3) 电气连接所述辐射面 （1) 和 所述接地面 （11) ；  a first through hole unit (4) and a second through hole unit (5) located at the radiating surface (1), the first substrate (2), the second substrate (3), and the Two sides of the ground plane (11) are formed by a plurality of second through holes, and the plurality of second through holes are electrically connected through the first substrate (2) and the second substrate (3) Said radiation surface (1) and said ground plane (11);
第一邦定通孔（7)和第二邦定通孔 （8) ， 穿过所述标签芯片 （12) 、 所述第一基材 (2) 以及所述辐射面 （1) 而不穿过所述接地面 （11) ; a first bonding via (7) and a second bonding via (8) passing through the tag chip (12), the first substrate (2), and the radiating surface (1) without wearing Passing the ground plane (11) ;
第一馈线 （9) 与第二馈线 （10) ， 分列在所述标签芯片 （12) 的两侧， 邦定所述标 签芯片 （12) ， 并通过所述第一邦定通孔 （7)和所述第二邦定通孔 （8)连接所述辐射面 (1) 。  a first feed line (9) and a second feed line (10) are arranged on both sides of the label chip (12), bonding the label chip (12), and passing through the first bonding through hole (7) And the second bonding via (8) is connected to the radiating surface (1).
4. 如权利要求 1所述的无源电子标签， 其特征在于所述开孔 （13)是圆形、 正方形、 长方形或多边形。  4. Passive electronic tag according to claim 1, characterized in that the opening (13) is circular, square, rectangular or polygonal.
5. 如权利要求 2所述的无源电子标签， 其特征在于所述无源电子标签的目标频率是 由所述多个第一通孔的中部的第一通孔来调试得到的。  5. The passive electronic tag of claim 2, wherein the target frequency of the passive electronic tag is debugged by a first through hole in a middle portion of the plurality of first through holes.
6. 如权利要求 3 所述的无源电子标签， 其特征在于所述第二通孔的直径为 0.2mm-1.5mm。  6. The passive electronic tag of claim 3, wherein the second through hole has a diameter of 0.2 mm to 1.5 mm.
7. 如权利要求 2所述的无源电子标签，其特征在于所述第一通孔在所述两边上每边 7 个， 直径为 0.2mm-1.5mm。 7. The passive electronic tag of claim 2 wherein said first through hole is on each side of said two sides 7 The diameter is 0.2mm-1.5mm.
8. 如权利要求 3所述的无源电子标签， 其特征在于所述第一馈线 （9)和所述第二馈 线 （10) 为契合的多边形， 所述第一馈线 （9) 和所述第二馈线 （10) 的距离大于等于所 述标签芯片 （12) 的引脚宽度。  8. The passive electronic tag of claim 3, wherein the first feed line (9) and the second feed line (10) are coincident polygons, the first feed line (9) and the The distance of the second feed line (10) is greater than or equal to the pin width of the tag chip (12).
9. 如权利要求 1所述的无源电子标签， 其特征在于所述第一基材（2)厚度大于所述 标签芯片 （12) 的厚度并小于 3mm。  9. Passive electronic tag according to claim 1, characterized in that the thickness of the first substrate (2) is greater than the thickness of the tag chip (12) and less than 3 mm.
10. 如权利要求 3所述的无源电子标签， 其特征在于所述辐射面 （1 ) 、 第一通孔单 元（4)、 第二通孔单元（5 ) 、 调谐通孔（6)、 第一邦定通孔（7)， 第二邦定通孔（8 ) 、 所述第一馈线 （9) 、 所述第二馈线 （10) 、 所述接地面 （11 ) 的材料均为铜、 铝或者银。  10. The passive electronic tag of claim 3, wherein the radiating surface (1), the first through hole unit (4), the second through hole unit (5), the tuned through hole (6), The first bonding via hole (7), the second bonding via hole (8), the first feeding line (9), the second feeding line (10), and the grounding surface (11) are all made of copper. , aluminum or silver.
11. 如权利要求 1所述的无源电子标签， 其特征在于所述第一基材 （2) 和所述第二 基材 （3 ) 由介电常数为 2〜150的介电材料构成。  The passive electronic tag of claim 1, wherein the first substrate (2) and the second substrate (3) are composed of a dielectric material having a dielectric constant of 2 to 150.
PCT/CN2012/076389 2011-06-03 2012-06-01 Passive electronic tag WO2012163294A1 (en)

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Publication number Priority date Publication date Assignee Title
CN1503400A (en) * 2002-11-19 2004-06-09 ��ʽ����Partron Mediu filter and duplex medium filter and mfg method
CN201845353U (en) * 2010-06-28 2011-05-25 上海铁勋智能识别系统有限公司 Metal-resistant ultrahigh-frequency electronic tag consisting of stacked antenna
CN202084069U (en) * 2011-06-03 2011-12-21 刘智佳 Passive electronic label

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1503400A (en) * 2002-11-19 2004-06-09 ��ʽ����Partron Mediu filter and duplex medium filter and mfg method
CN201845353U (en) * 2010-06-28 2011-05-25 上海铁勋智能识别系统有限公司 Metal-resistant ultrahigh-frequency electronic tag consisting of stacked antenna
CN202084069U (en) * 2011-06-03 2011-12-21 刘智佳 Passive electronic label

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