WO2012161032A1 - Semiconductor integrated circuit device and high-frequency module - Google Patents
Semiconductor integrated circuit device and high-frequency module Download PDFInfo
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- WO2012161032A1 WO2012161032A1 PCT/JP2012/062420 JP2012062420W WO2012161032A1 WO 2012161032 A1 WO2012161032 A1 WO 2012161032A1 JP 2012062420 W JP2012062420 W JP 2012062420W WO 2012161032 A1 WO2012161032 A1 WO 2012161032A1
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- transistor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/44—Transmit/receive switching
- H04B1/48—Transmit/receive switching in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter
Definitions
- the present invention relates to a semiconductor integrated circuit device and a high frequency module, and more particularly to a technology effective when applied to a semiconductor integrated circuit device and a high frequency module including an antenna switch mounted on a mobile communication device or the like.
- Patent Document 1 in a transistor that is equivalently represented by a parallel connection of a plurality of partial transistors in accordance with a meander structure layout, the gate width of a partial transistor positioned closest to the gate input terminal is set to other portions. A configuration in which the gate width is larger than that of the transistor is shown.
- a plurality of frequency bands are defined with a frequency band in the vicinity of 2 GHz as a representative.
- a so-called multiband / multimode technology is indispensable for supporting a plurality of communication systems and a plurality of frequency bands.
- the antenna switch device selectively transmits transmission signals of multiple frequency bands from the inside to the antenna by switching multiple switches, and internally receives reception signals of multiple frequency bands received by the antenna. It is a device that selectively transmits to the device.
- Important characteristics that determine the performance of the antenna switch device include high-order harmonic distortion (HD) and intermodulation distortion (IMD). In particular, it is important to reduce second-order harmonic distortion (2HD) and third-order harmonic distortion (3HD) in the GSM system, and it is important to reduce IMD in the W-CDMA system.
- HD high-order harmonic distortion
- IMD intermodulation distortion
- the Vin is connected to PNant and at the both ends of the receiving switch series connection circuit (Q_RXcom and Q_RX2 (Q_RX1)). Is applied.
- Q_RXcom is a common transistor for the reception switch, and one end is connected to PNant, and here, it has a single-stage configuration of a triple gate transistor.
- Q_RX2 and Q_RX1 are reception switch transistors, which are branched in parallel from the other end of Q_RXcom, and have a single-stage configuration of single gate transistors here.
- a single-stage configuration of a triple gate transistor is equivalently considered as a three-stage configuration of a single gate transistor. Therefore, Vin is divided by the three-stage single gate transistor by Q_RXcom and the one-stage single gate transistor by Q_RX2 (Q_RX1).
- FIG. 10 shows an example of the gate-source voltage dependence of the source-drain current and the gate-source capacitance of the single gate transistor in the semiconductor integrated circuit device (antenna switch device) studied as a premise of the present invention.
- FIG. Each of the transistors described above is composed of, for example, a HEMT (High-Electron-Mobility-Transistor) element using gallium arsenide (GaAs) or the like for high performance.
- the threshold voltage Vth of a GaAs transistor is generally about ⁇ 1 V, and the transistor is turned off when the gate-source voltage Vgs becomes Vth or less.
- the gate-source capacitance (off-capacitance) Cgs at that time has a non-linear characteristic that rapidly decreases from the vicinity of Vth with the spread of the depletion layer of the heterojunction (Schottky junction) in the gate. This non-linearity causes high-order harmonic distortion (HD) and intermodulation distortion (IMD).
- HD high-order harmonic distortion
- IMD intermodulation distortion
- a high voltage (V_TX2c) is applied to the gate to control the transmission switch transistor (Q_TX2) to be on, and each of the transistors (Q_RXcom, Q_RX2, Q_RX1) is controlled to be off.
- a low voltage for example, 0 V
- the high voltage of Q_TX2 is applied to PNant via the Schottky junction (equivalently a forward diode) of the gate, the bias voltage of each transistor (Q_RXcom, Q_RX2, Q_RX1) in the off state is As shown in FIG. 10, it is approximately ⁇ V_TX2c.
- the gate width per stage of the single gate transistor in Q_RXcom is, for example, about three times larger than the gate width of Q_RX2 (and Q_RX1) in order to reduce insertion loss when turning on Q_RXcom during reception. Is set.
- the waveforms of the gate-source voltage Vgs1 per stage of the single gate transistor in Q_RXcom and the gate-source voltage Vgs2 of Q_RX2 (and Q_RX1 connected in parallel thereto) have the relationship shown in FIG. .
- the off capacitance increases as the gate width increases, the off capacitance is relatively smaller on the Q_RX2 and Q_RX1 sides than on the Q_RXcom side (impedance increases), and Vgs2 is more than Vgs1 accordingly. Becomes larger. Note that even if the number of multi-gates of Q_RXcom changes, the magnitude relationship between Vgs1 and Vgs2 does not change, and both amplitudes change similarly. As can be seen from FIG. 10, the higher-order harmonic distortion (HD) and intermodulation distortion (IMD) increase in proportion to the amplitude value of the gate-source voltage Vgs applied to the off-capacitance (Cgs). Therefore, distortion generated from Q_RX2 (Q_RX1) having a large Vgs becomes dominant, and there is a possibility that the HD characteristics and IMD characteristics of the antenna switch device cannot be improved.
- HD harmonic distortion
- IMD intermodulation distortion
- the present invention has been made in view of the above, and one of its purposes is to provide a semiconductor integrated circuit device capable of improving distortion characteristics in a high-frequency signal and a high-frequency module including the same. It is in.
- the above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
- the semiconductor integrated circuit device includes an antenna terminal, first to Nth (N is an integer of 2 or more) terminals, a common transistor, and first to Nth transistors.
- the antenna terminal is for antenna connection, and a first transmission signal directed to the antenna is transmitted.
- the common transistor has a source / drain path coupled between the antenna terminal and the common node, and is controlled to be turned off when the first transmission signal is transmitted to the antenna terminal.
- the first to Nth transistors have their source / drain paths coupled between the common node and the first to Nth terminals, respectively, and are controlled to be off when the common transistor is controlled to be off.
- the gate width of the common transistor is in a range of ⁇ 20% of the total value of the gate widths of the first to Nth transistors.
- the voltage level of the first transmission signal is substantially uniform between the off-capacitance of the common transistor and the off-capacitances of the first to Nth transistors. Since the pressure is divided, the distortion characteristics can be improved.
- FIG. 1 is a circuit diagram showing a configuration example of a main part of a semiconductor integrated circuit device according to a first embodiment of the present invention.
- 2 is a schematic diagram illustrating an example of an equivalent circuit of each transistor in an off state in the semiconductor integrated circuit device of FIG.
- FIG. 3 is a diagram showing an example of the gate-source voltage dependence of the source-drain current and the gate-source capacitance of each single gate transistor in FIGS. is there.
- FIG. 2 is a cross-sectional view showing a device structure example of each switch transistor in the semiconductor integrated circuit device of FIG. 1.
- the high frequency module of Embodiment 1 of this invention it is a block diagram which shows an example of the whole structure.
- FIG. 1 is a circuit diagram showing a configuration example of a main part of a semiconductor integrated circuit device according to a first embodiment of the present invention.
- FIG. 3 is a diagram showing an example of the gate-source voltage dependence of the source-drain current and the gate-source capacitance of each single gate transistor
- FIG. 6 is a circuit diagram illustrating a detailed configuration example of the antenna switch device in the high-frequency module of FIG. 5.
- FIG. 7 is an explanatory diagram showing an example of the dependence of the insertion loss and isolation characteristics of each switch transistor in FIG. 6 on the gate width.
- FIG. 7 is an explanatory diagram illustrating an example of a result of verifying various effects in the antenna switch device of FIG. 6.
- FIG. 6 is a circuit diagram showing a configuration example of an antenna switch device included in a high-frequency module according to a second embodiment of the present invention. In the semiconductor integrated circuit device examined as a premise of the present invention, it is a diagram showing an example of the gate-source voltage dependence of the source-drain current and the gate-source capacitance of the single gate transistor.
- the constituent elements are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.
- the shapes, positional relationships, etc. of the components, etc. when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.
- FIG. 1 is a circuit diagram showing a configuration example of a main part of a semiconductor integrated circuit device according to Embodiment 1 of the present invention.
- the semiconductor integrated circuit device (antenna switch device) shown in FIG. 1 includes an antenna connection terminal PNant, a transmission terminal TX2, reception terminals RX1 and RX2, and on / off control terminals RXcomc, RX2c, and RX1c.
- the antenna switch device further includes a transmission switch transistor Q_TX2, a reception switch common transistor Q_RXcom, and reception switch transistors Q_RX1 and Q_RX2.
- Each transistor is not particularly limited, but includes, for example, a HEMT element that can realize low insertion loss, high isolation, low noise, and the like in a high frequency band.
- a transmission switch transistor Q_TX1 and transmission / reception switch transistors Q_TRX1 to Q_TRX3 are additionally shown, but these are not necessarily required.
- TX2 receives a transmission high-frequency signal from the power amplifier circuit PA or the like at the previous stage.
- Q_TX2 is coupled between TX2 and PNant, and transmits a transmission high-frequency signal from TX2 to PNant when controlled to ON.
- Q_RXcom has a single-stage configuration of a triple gate transistor, and one of the source and the drain is coupled to PNant.
- the source and drain of a transistor can be appropriately changed according to the signal level actually applied to the source and / or drain. However, in this embodiment, for convenience of explanation, the side closer to PNant is used.
- the node of is the drain. In this case, the drain of Q_RXcom is coupled to PNant.
- the triple gate transistor of Q_RXcom can be regarded as a three-stage configuration of a single gate transistor equivalently. Between the source and drain of each single gate transistor, resistors Rd1a, Rd1b, and Rd1c having relatively high resistance values for biasing are coupled. At this time, the coupling node of Rd1a and Rd1b is coupled to the node between the gate on the drain side and the middle gate, and the coupling node of Rd1b and Rd1c is coupled to the node between the gate on the source side and the middle gate. .
- the drain of the triple gate transistor of Q_RXcom is coupled to the gate closest to the drain side in the triple gate via the capacitor C1a, and the source of the triple gate transistor is closest to the source side in the triple gate via the capacitor C1b. Coupled to the gate.
- the gate closest to the drain side in the triple gate is coupled to RXcomc via resistors Rg1a and Rg1b in series, and the gate closest to the source side within the triple gate is connected via resistors Rg1c and Rg1b in series. It is bound to RXcomc.
- the middle gate in the triple gate is coupled to RXcomc via Rg1b.
- Q_RX2 has a single-stage configuration of a single gate transistor, the drain is coupled to the source of Q_RXcom, and the source is coupled to RX2.
- a resistor Rd2 having a relatively high bias value is coupled between the source and the drain of Q_RX2, and the gate of Q_RX2 is coupled to RX2c via the resistor Rg2.
- Q_RX1 has a single-stage configuration of a single gate transistor, the drain is coupled to the source of Q_RXcom, and the source is coupled to RX1.
- a resistor Rd3 having a relatively high bias value is coupled between the source and the drain of Q_RX1, and the gate of Q_RX1 is coupled to RX1c via the resistor Rg3.
- Q_TX2 when a transmission high-frequency signal from TX2 is transmitted to PNant, Q_TX2 is controlled to be on and other transistors (Q_RXcom, Q_RX2, Q_RX1, etc.) are controlled to be off.
- a high voltage for example, about 3 V
- a low voltage for example, RXcomc, RX2c, RX1c
- RXcomc, RX2c, RX1c is applied to the gates (RXcomc, RX2c, RX1c) of other transistors (Q_RXcom, Q_RX2, Q_RX1). 0V etc.
- a high voltage of Q_TX2 is applied to PNant via a Schottky junction (equivalently a forward diode) of the gate, and the voltage is applied to the resistance (Rd1a, Q_RX2, Q_RX1, respectively) at the source and drain of Q_RXcom, Q_RX2, and Q_RX1.
- Rd1b, Rd1c, Rd2, Rd3 the gate-source voltages of the other transistors (Q_RXcom, Q_RX2, Q_RX1) are biased to the off state.
- Q_RXcom is configured such that power is supplied to the node between the gates.
- a stable potential can be supplied to each inter-gate node, and the distortion characteristics (HD, IMD) can be improved. That is, when power is not supplied to each inter-gate node, for example, the bias point in the middle transistor of the three single gate transistors constituting the triple gate transistor can be unstable. If the bias point becomes shallow (that is, ⁇ V_TX2c in FIG. 10 approaches Vth), distortion characteristics deteriorate, but such a situation can be prevented by feeding the node between the gates.
- C1a and C1b coupled to Q_RXcom are mainly used for high frequency coupling. For example, when the voltage of PNant fluctuates in the negative direction and the positive direction accompanying the transmission high frequency signal described above, Q_RXcom changes from the off state to the on state. Prevent transitions.
- Rg1a, Rg1b, Rg1c coupled to Q_RXcom, and Rg2, Rg3 coupled to Q_RX2, Q_RX1 mainly have a relatively high resistance value for high-frequency cutoff.
- a transmission high-frequency signal from PNant is RXcomc, RX2c.
- RX1c is prevented from leaking.
- Rg1a, Rg1b, and Rg1c are arranged such that the resistance value from RXcomc to the gates at both ends of Q_RXcom is high and the resistance value from RXcomc to the middle gate of Q_RXcom is low. Yes.
- each gate resistor is arranged so that the resistance values are all the same, each gate resistor is not supplied with a high-frequency leakage signal of an equal level in the OFF state, and the modified U-shaped standing This is because the inventors have found that a high-frequency leakage signal that becomes a wave is supplied.
- a common transistor Q_RXcom
- the circuit area is reduced as compared with the case where the common transistor (Q_RXcom) is not provided (that is, when the RX2 transistor and the RX1 transistor are directly connected to PNant).
- the load capacity of the antenna connection terminal PNant can be reduced.
- the load capacity of the PNant it is possible to improve distortion characteristics such as reduction of harmonic distortion (HD) or reduction of intermodulation distortion (IMD).
- each of the reception switch transistors Q_RX2, Q_RX1 is formed of a single gate transistor from the viewpoint of reducing insertion loss at the time of ON.
- the gate width of Q_RXcom is set to be, for example, about three times larger than the gate width of Q_RX2 (or Q_RX1). It was. However, this may cause Q_RX2 (or Q_RX1) to dominate and cause deterioration of distortion characteristics.
- FIG. 2 is a schematic diagram showing an example of an equivalent circuit of each transistor in the off state in the semiconductor integrated circuit device of FIG.
- FIG. 3 shows an example of the gate-source voltage dependence of the source-drain current and the gate-source capacitance of each single gate transistor in FIGS. 1 and 2 in the semiconductor integrated circuit device according to the first embodiment of the present invention.
- FIG. FIG. 3 shows the characteristics of the source-drain current Ids of the HEMT device having a threshold voltage Vth of about ⁇ 1 V, and the gate-source capacitance (off capacitance) in the off state, as in FIG. The characteristics of Cgs are shown.
- the transistor in the off state is biased to approximately ⁇ V_TX2c with the high voltage (V_TX2c (for example, about 3V)) applied to the gate of Q_TX2 described in FIG.
- FIG. 2 shows an equivalent circuit of the common transistor Q_RXcom for reception switch and the transistors Q_RX2 and Q_RX1 for reception switch in FIG.
- Q_RXcom in the off state is represented by a gate-drain capacitance Cg1, a gate-source capacitance Cg2, and a source-drain resistance Rd1.
- the off-state Q_RX2 is represented by the gate-drain capacitance Cg3, the gate-source capacitance Cg4, and the source-drain resistance Rd2
- the off-state Q_RX1 is represented by the gate-drain capacitance Cg5 and the gate.
- -It is represented by the source-to-source capacitance Cg6 and the aforementioned source-drain resistance Rd3.
- Q_RXcom is a triple gate transistor, it is represented by a three-stage single gate transistor Qa, Qb, Qc.
- Qa is represented by the gate-drain capacitance Cg1a, the gate-source capacitance Cg2a, and the aforementioned source-drain resistance Rd1a.
- Qb is represented by a gate-drain capacitance Cg1b, a gate-source capacitance Cg2b, and the source-drain resistance Rd1b described above
- Qc is a gate-drain capacitance Cg1c and a gate-source capacitance. Cg2c and the source-drain resistance Rd1c described above.
- the reception terminals RX2 and RX1 are connected to the ground power supply voltage GND in an AC manner via, for example, a shunt switch transistor (not shown).
- a transmission high-frequency signal having the maximum voltage Vin (for example, a large voltage corresponding to a transmission power of 35 dBm in the GSM system) is transmitted to the antenna connection terminal PNant via Q_TX2 in FIG.
- Vin is applied between PNant and GND (corresponding to RX2 and RX1).
- the high-frequency signal having the Vin is mainly applied to the gate-drain capacitance and the gate-source capacitance (that is, off capacitance) of each transistor. Applied and divided by the off-capacitance.
- the off-capacitance that is, off capacitance
- an equal gate-source voltage Vgs (gate-drain voltage Vgd) is applied to each gate-source capacitance Cgs (each gate-drain capacitance Cgd). If configured, the distortion characteristics (HD, IMD) can be improved as compared with the case of FIG.
- the impedance value of the parallel connection of Q_RX2 and Q_RX1 and the impedance values of Qa to Qc are both equal. That is, the total value associated with the parallel connection of the combined capacitance values of Cg3 and Cg4 and the combined capacitance values of Cg5 and Cg6 is equal to the combined capacitance value of Cg1c and Cg2c, equal to the combined capacitance value of Cg1b and Cg2b, and , Cg1a and Cg2a may be equal to the combined capacitance value.
- the signal amplitude of the gate-source voltage Vgs2 of Q_RX2 (Q_RX1) and the gate-source voltage Vgs1 per single gate transistor of Q_RXcom can be taken as the minimum amplitude.
- the distortion characteristics (HD, IMD) can be improved most effectively.
- FIG. 4 is a cross-sectional view showing a device structure example of each switch transistor in the semiconductor integrated circuit device of FIG.
- Each switching transistor shown in FIG. 1 is composed of, for example, a high electron mobility transistor (HEMT) element as shown in FIG.
- HEMT high electron mobility transistor
- the semi-insulating substrate SUB is a substrate as shown below composed of a gallium arsenide (GaAs) substrate which is a compound semiconductor. That is, in a compound semiconductor having a large forbidden band, when a certain type of impurity is added, a deep level is formed inside the forbidden band.
- GaAs gallium arsenide
- the deep level electrons and holes are fixed, and the electron density in the conduction band or the hole density in the valence band becomes very small, becoming closer to an insulator.
- a substrate is called a semi-insulating substrate.
- deep levels are formed by adding Cr, In, oxygen or the like, or introducing arsenic excessively, thereby forming a semi-insulating substrate.
- the epitaxial layer EP formed on the semi-insulating substrate SUB is formed of, for example, a GaAs layer.
- a buffer layer BF is formed on the epitaxial layer EP, and a semiconductor layer LY2 such as AlGaAs is formed on the buffer layer BF.
- This LY2 is processed into a mesa shape for element isolation, and an insulating film ISL such as PSG (Phosphorus Silicon Glass) / SiO is formed in the processed portion.
- a plurality of gate electrodes G1, G2 are formed on LY2.
- G1 and G2 are formed of a metal layer having Pt (platinum) as the lowermost layer, and a stacked film in which Pt, Ti (titanium), Pt, and Au (gold) are sequentially stacked from the lower layer is used.
- LY2 and G1, G2 lowermost layer Pt
- LY3 semiconductor layers
- LY3 such as n-type GaAs are formed on the LY2 so as to sandwich the plurality of gate electrodes G1, G2 apart from each other, and the ohmic electrodes OE1 are respectively formed on the two LY3.
- OE2 are formed. These OE1 and OE2 are configured to make ohmic contact with LY3.
- the semiconductor layer LY3 is also formed between the plurality of gate electrodes G1, G1.
- n + electrode SH12 n + type GaAs or the like is formed on this LY3, n + electrode SH12 n + type GaAs or the like is formed.
- This SH 12 is for supplying power to the inter-gate node as described in FIG.
- a resistance layer (resistance) R is formed on the insulating film ISL.
- This resistance layer R corresponds to each source-drain resistance (Rd1a, etc.) and each gate resistance (Rg1a, etc.) shown in FIG.
- Rd1a, etc. each source-drain resistance
- Rg1a, etc. each gate resistance
- FIG. an example of the structure of a double gate transistor provided with two gate electrodes G1 and G2 between the source and drain (OE1 and OE2) is shown, but in the triple gate transistor, n + is further provided between G2 and OE2.
- the structure is such that the electrode and the gate electrode are
- Such a HEMT device uses a well-type potential formed at a hetero-bond interface between a GaAs layer (EP) and an AlGaAs layer (LY2), and uses a two-dimensional electron gas formed in the well-type potential as a carrier.
- the width of the well-type potential existing at the heterojunction interface is only as wide as the wavelength of the electrons, and the electrons can only move two-dimensionally along the interface, so that a large electron mobility can be obtained. . Therefore, because of the high mobility characteristics of the two-dimensional electron gas, the high frequency characteristics and high speed characteristics are excellent, and the noise is very low. It is beneficial to apply.
- the gate width of each of the switching transistors described above is roughly the length in the depth direction of the gate electrode (G1 or G2) in FIG.
- the gate width of the common transistor Q_RXcom for the reception switch is preferably the total value of the gate widths of the transistors Q_RX1 and Q_RX2 for the reception switch (for example, twice the Q_RX1).
- the apparent ratio of the gate width (for example, twice) can have a predetermined fluctuation width according to the layout structure or the like.
- Patent Document 1 when a meander structure layout in which the gate extends while meandering in the depth direction of FIG. 4 is used, a portion extending in the direction of the gate on the layout plane is orthogonal to the portion.
- the ratio of contribution to the source-drain current of the entire transistor (that is, the effective gate width) may be different from the portion extending in the direction in which the transistor extends.
- the effective gate width may vary depending on the number of multi-gates. Therefore, the ratio of the apparent gate width (simply equivalent to the physical length in the extending direction of the gate) is not always set to double or the like. However, the ratio of the effective gate width in consideration of such variation factors is set to double or the like.
- the set value of the gate width can actually have a fluctuation range of about ⁇ 20% depending on manufacturing variations and the like.
- the gate width of Q_RXcom is set to 1.5 mm, but may have a fluctuation range of about ⁇ 0.3 mm depending on manufacturing variations and the like.
- FIG. 5 is a block diagram showing an example of the overall configuration of the high-frequency module according to Embodiment 1 of the present invention.
- the high-frequency module RFMD shown in FIG. 5 is used in, for example, a mobile phone that is one of wireless communication systems, and is configured by, for example, one wiring board (ceramic board or the like) on which a plurality of components are mounted.
- the RFMD includes a high-frequency power amplification module HPAMD, a high-frequency signal processing chip RFIC, SAW (Surface Acoustic Wave) filters SAW1 and SAW2, W-CDMA power amplifier circuits PA_W1 to PA_W3, duplexers DPX1 to DPX3, and the like. Has been.
- the high frequency signal processing chip RFIC is composed of, for example, one semiconductor chip and includes low noise amplifier circuits LNA1 to LNA5 and the like.
- the HPAMD is composed of, for example, a single wiring board (ceramic board or the like), and power amplifier circuits HPA1 and HPA2, low-pass filters LPF1 and LPF2, a control chip CTLIC, an antenna switch device ANTSW, and the like are provided on the wiring board.
- HPA1 and HPA2 are constituted by one semiconductor chip, for example.
- HPA1 and HPA2 are realized by LDMOS (Laterally Diffused ⁇ MOS) or the like
- HPA1, HPA2 and CTLIC can be integrated in one semiconductor chip.
- the LPF 1 and LPF 2 are configured by a wiring pattern on the wiring board, various SMD (Surface Mount Device) components, and the like.
- the antenna switch device ANTSW is realized by, for example, one compound semiconductor chip (GaAs chip or the like), and here, from an antenna connection terminal PNant, transmission terminals TX1 and TX2, reception terminals RX1 and RX2, and transmission / reception terminals TRX1 to TRX3. Eight external terminals are provided.
- the ANTSW has a so-called SP7T configuration in which one of seven signal terminals (TX1, TX2, RX1, RX2, TRX1 to TRX3) is selectively connected to a PNant to which an antenna ANT is connected.
- the control chip CTLIC selects a connection destination of this PNant based on a control signal (BB control) from a baseband circuit (not shown).
- HPA1 amplifies the GSM low-band transmission signal GSM_LB_TX and outputs it to the transmission terminal TX1 via LPF1.
- GSM_LB_TX corresponds to, for example, GSM850 having a transmission frequency band of 824 MHz to 849 MHz and GSM900 having a transmission frequency band of 880 MHz to 915 MHz.
- the HPA 2 amplifies the GSM high-band transmission signal GSM_HB_TX and outputs it to the transmission terminal TX 2 via the LPF 2.
- GSM_HB_TX corresponds to, for example, DCS1800 having a transmission frequency band of 1710 MHz to 1780 MHz and PCS1900 having a transmission frequency band of 1850 MHz to 1910 MHz.
- processing for up-converting the transmission baseband signal to a predetermined transmission frequency band is performed.
- Such processing is performed by, for example, an RFIC using a mixer circuit or the like.
- CTLIC amplifies HPA1 and HPA2 according to a control signal (BB control) from a baseband circuit and a detection signal from a power detection circuit (coupler) (not shown) provided at the output of HPA1 and HPA2. The rate is also controlled.
- Is output as GSM_LB_RX corresponds to, for example, GSM850 having a reception frequency band of 869 MHz to 894 MHz and GSM900 having a reception frequency band of 925 MHz to 960 MHz.
- Such reception frequency band selection is performed by SAW1.
- the reception signal input from the ANT to the reception terminal RX2 according to the selection of CTLIC is selected as a specific reception frequency band via the SAW2, amplified by the RFNA LNA5, and then output as a reception signal GSM_HB_RX for GSM.
- GSM_HB_RX corresponds to, for example, DCS1800 having a reception frequency band of 1805 MHz to 1880 MHz and PCS1900 having a reception frequency band of 1930 MHz to 1990 MHz.
- Such reception frequency band selection is performed by SAW2.
- a process of down-converting the received high-frequency signal into a received baseband signal is performed.
- Such processing is performed by, for example, an RFIC using a mixer circuit or the like.
- PA_W1 amplifies a transmission signal W-CDMA_TX (1900) in the 1.9 GHz band of W-CDMA (corresponding to, for example, band 2 of the W-CDMA standard), and the amplified signal is classified into a transmission / reception frequency band by DPX1. And then output to the transmission / reception terminal TRX1.
- the received signal input from ANT to TRX1 is subjected to transmission / reception frequency band separation by DPX1, then amplified by LNA2, and output as received signal W-CDMA_RX (1900).
- PA_W2 amplifies the transmission signal W-CDMA_TX (2100) of the W-CDMA 2.1 GHz band (corresponding to, for example, band 1 of the W-CDMA standard), and the amplified signal is classified into the transmission / reception frequency band by DPX2. And then output to the transmission / reception terminal TRX2.
- the received signal input from ANT to TRX2 is subjected to transmission / reception frequency band separation by DPX2, then amplified by LNA3, and output as received signal W-CDMA_RX (2100).
- PA_W3 amplifies the transmission signal W-CDMA_TX (900) in the 900 MHz band of W-CDMA (corresponding to, for example, band 8 of the W-CDMA standard), and the amplified signal undergoes transmission / reception frequency band separation by DPX3.
- the signal is output to the transmission / reception terminal TRX3.
- the received signal input from ANT to TRX3 is subjected to transmission / reception frequency band separation by DPX3, then amplified by LNA4, and output as received signal W-CDMA_RX (900).
- PA_W1 to PA_W3 are configured by, for example, heterojunction bipolar transistors (HBT).
- the DPX1 to DPX3 are configured by SMD parts, for example.
- up-conversion is performed before PA_W1 to PA_W3, and down-conversion is performed after LNA2 to LNA4.
- Such processing is performed by, for example, an RFIC using a mixer circuit or the like.
- the high-frequency module RFMD corresponding to a plurality of communication systems (multimode) and a plurality of frequency bands (multiband)
- a large number of switching transistors are connected to the antenna ANT.
- the semiconductor integrated circuit device as described in FIG.
- FIG. 6 is a circuit diagram showing a detailed configuration example of the antenna switch device in the high-frequency module of FIG.
- the antenna switch device ANTSW shown in FIG. 6 controls on / off of each switch transistor in addition to the eight signal terminals (PNant, TX1, TX2, RX1, RX2, TRX1 to TRX3) described in FIG. ON / OFF control terminals TX1c, TX2c, RX1c, RX2c, TRX1c to TRX3c, RXcomc and a plurality of ground power supply voltage terminals (ground power supply voltage) GND are provided.
- the on / off control terminal is omitted in FIG. 5, but is actually provided in the ANTSW of FIG.
- a source / drain path of a transmission switch transistor Q_TX1 including double-stage transistors Q_TX11 and Q_TX12 connected in two stages is coupled between a transmission terminal TX1 for GSM low band and an antenna connection terminal PNant. Further, a source / drain path of a shunt switch transistor Q_TX1s including two-stage triple gate transistors Q_TX1s1 and Q_TX1s2 is coupled between TX1 and GND. Similarly, the source / drain path of the transmission switch transistor Q_TX2 including the double-gate transistors Q_TX21 and Q_TX22 connected in two stages is coupled between the transmission terminal TX2 for high band of GSM and PNant. A source / drain path of a shunt switch transistor Q_TX2s composed of two-stage triple gate transistors Q_TX2s1 and Q_TX2s2 is coupled between TX2 and GND.
- a source / drain path of a transmission / reception switch transistor Q_TRX1 including two-stage connected double gate transistors Q_TRX11 and Q_TRX12 is coupled between a transmission / reception terminal TRX1 and PNant for W-CDMA 1.9 GHz band.
- a source / drain path of a shunt switch transistor Q_TRX1s composed of a single-stage triple gate transistor is coupled between TRX1 and GND.
- a source / drain path of a transmission / reception switching transistor Q_TRX2 including two-stage connected double gate transistors Q_TRX21 and Q_TRX22 is coupled between a transmission / reception terminal TRX2 and a PNant for the 2.1 GHz band of W-CDMA. .
- a source / drain path of a shunt switch transistor Q_TRX2s composed of a single-stage triple gate transistor is coupled between TRX2 and GND. Further, a source / drain path of a transmission / reception switching transistor Q_TRX3 including two-stage connected double gate transistors Q_TRX31 and Q_TRX32 is coupled between a transmission / reception terminal TRX3 and a PNant for 900 MHz band of W-CDMA. Further, a source / drain path of a shunt switch transistor Q_TRX3s composed of a single-stage triple gate transistor is coupled between TRX3 and GND.
- a source / drain path of the reception switch common transistor Q_RXcom composed of a single-stage triple gate transistor is coupled.
- a source / drain path of a receiving switch transistor Q_RX2 made of a single gate transistor is coupled between the receiving terminals RX2 and Ncom for GSM high band, and a shunt switch made of a single gate transistor is connected between RX2 and GND.
- the source / drain path of the transistor for transistor Q_RX2s is coupled.
- the source / drain path of the receiving switch transistor Q_RX1 made of a single gate transistor is coupled between the receiving terminals RX1 and Ncom for the GSM low band, and a single gate transistor is made between RX1 and GND.
- the source / drain paths of the shunt switch transistor Q_RX1s are coupled.
- the bias voltage from TX1c is applied to the gate of switch transistor (through switch transistor) Q_TX1 and the source (TX1 side) of shunt switch transistor Q_TX1s corresponding thereto.
- the bias voltage from TX2c is applied to the gate of the through switch transistor Q_TX2 and the source (TX2 side) of the corresponding shunt switch transistor Q_TX2s.
- the gates of the other through-switch transistors Q_TRX1 to Q_TRX3, Q_RX1 and Q_RX2 and the sources (signal terminal side) of the shunt switch transistors Q_TRX1s to Q_TRX3s, Q_RX1s and Q_RX2s are also biased by TRX1c to TRX3c, RX1c and RX2c, respectively.
- a voltage is applied.
- the gate of each shunt switch transistor is coupled to GND through a predetermined gate resistance, and the drain of each shunt switch transistor is connected to GND in an AC manner via a capacitor.
- the through switch transistor and the shunt switch transistor corresponding to the through switch transistor are complementarily controlled on and off.
- V_TX1c a high voltage
- the gate-source voltage of the shunt switch transistor Q_TX1s is controlled to be off because it is biased to ⁇ V_TX1c.
- each switch transistor mainly takes into account the relative balance between passing power, insertion loss when turned on, isolation and distortion characteristics when turned off, and the number of multi-gate gates and transistor stages. Is adjusted accordingly. For example, since the GSM transmission power (for example, 35 dBm) is larger than the W-CDMA transmission power (for example, 24 dBm), the TX1 shunt switch transistor Q_TX1s is connected in two stages of triple gate transistors, and the TRX1 shunt switch transistor Q_TRX1s is a one-stage connection of triple gate transistors.
- FIG. 7 is an explanatory diagram showing an example of the dependency of the insertion loss and isolation characteristics of each switch transistor in FIG. 6 on the gate width. As shown in FIG. 7, when the gate width is increased, the insertion loss can be reduced. On the other hand, the off-capacitance is increased (impedance is reduced at the time of off), and the isolation characteristics are deteriorated. Therefore, the gate width of each switch transistor is set to an optimum value considering such a trade-off relationship.
- Q_TX1 As described above, the number of multi-gate gates, the number of transistor stages, and the gate width may be different depending on the corresponding signal terminal, but the basic configuration is almost the same as each switching transistor. Therefore, Q_TX1 As a representative example, the detailed configuration will be described. First, Q_TX11 which is a part of Q_TX1 and is disposed on the PNant side is coupled to the source and drain via resistors Rd1 and Rd2, and Q_TX12 which is a part of Q_TX1 and is disposed on the TX1 side is a source and drain. The two are coupled through resistors Rd3 and Rd4. The resistance values of Rd1 to Rd4 are, for example, 15 k ⁇ .
- the coupling node of Rd1 and Rd2 is coupled to the inter-gate node of the double gate of Q_TX11, and the coupling node of Rd3 and Rd4 is coupled to the inter-gate node of the double gate of Q_TX12.
- the distortion characteristics can be improved by feeding the inter-gate node.
- a capacitor C11 is coupled between the drain of Q_TX11 (a coupling node with PNant) and a gate near the drain side of Q_TX11, and a source of Q_TX12 (coupling node with TX1) and a gate near the source side of Q_TX12, A capacitor C12 is coupled in between.
- the capacitance values of C11 and C12 are, for example, 0.8 pF.
- the drain side (PNant side) gate is connected to TX1c via resistors Rg12, Rg11, Rg15
- the source side (Q_TX12 side) gate is connected to TX1c via Rg11, Rg15. Is done.
- the source side (TX1 side) gate is connected to TX1c via resistors Rg14, Rg13, and Rg15
- the drain side (Q_TX11 side) gate is connected to TX1c via Rg13, Rg15. Is done.
- the resistance values of Rg11 to Rg14 are, for example, 10 k ⁇
- the resistance value of Rg15 is, for example, 20 k ⁇ .
- the relationship of the gate width according to the system of the present embodiment described above is applied to the receiving switch common transistor Q_RXcom and the receiving switch transistors Q_RX1 and Q_RX2.
- the detailed circuit configuration of this part is the same as that in FIG. This makes it possible to reduce high-order harmonic distortion (2HD, 3HD, etc.) with respect to the transmission signal during a GSM transmission operation from TX2 or the like, for example. Further, for example, during a W-CDMA transmission operation from TRX1 or the like, it is possible to reduce intermodulation distortion (IMD) with respect to a transmission signal.
- IMD intermodulation distortion
- the method of the present embodiment is applied to the GSM reception system, but in principle, it can be applied to the transmission system as well as the reception system.
- the transmission system the insertion loss characteristic and the like at the time of on are particularly important, and therefore it is not always beneficial to provide a common transistor as in the reception system. Therefore, although not necessarily limited, in particular, in the case of having a plurality of transmission terminals and a plurality of reception terminals individually as in the GSM system (that is, in the case of having a TDD (Time Division Division Duplex) system), It is beneficial to apply the system of this embodiment to the reception system.
- TDD Time Division Division Duplex
- FIG. 8 is an explanatory diagram showing an example of a result of verifying various effects in the antenna switch device of FIG.
- 2HD / 3HD ⁇ 77.1 dBc / ⁇ 71.6 dBc.
- 2HD / 3HD ⁇ 80.9 dBc / ⁇ 81.6 dBc, and for example, an improvement effect of about 10 dB is obtained in 3HD.
- the semiconductor integrated circuit device and the high-frequency module according to the first embodiment it is possible to improve the distortion characteristics in the high-frequency signal.
- FIG. 9 is a circuit diagram showing a configuration example of the antenna switch device included in the high-frequency module according to Embodiment 2 of the present invention.
- the part (TRX3c, Q_TRX3, Q_TRX3s) associated with the W-CDMA transmission / reception terminal TRX3 is deleted as compared to the ANTSW of FIG. , RX4 and on / off control terminals RX3c, RX4c and associated switching transistors are added. Since the configuration other than this is the same as that in FIG. ANTSW2 in FIG. 9 has an SP8T type configuration.
- a source / drain path of a receiving switch transistor Q_RX3 made up of a single gate transistor is coupled between the receiving terminal RX3 and the receiving common node Ncom, and a shunt switch transistor made up of a single gate transistor between RX3 and GND.
- the source / drain paths of Q_RX3s are coupled.
- a source / drain path of a reception switch transistor Q_RX4 made of a single gate transistor is coupled between the reception terminals RX4 and Ncom, and a shunt switch transistor Q_RX4s made of a single gate transistor is connected between RX4 and GND.
- Source / drain paths are coupled. That is, unlike the case of FIG. 6, four reception switch transistors Q_RX1 to Q_RX4 are connected to Ncom.
- the reception terminal RX1 is for GSM850, for example, in the GSM lowband
- the newly added RX3 is for GSM900, for example, in the GSM lowband.
- the transmission terminal TX2 is for GSM high band
- the reception terminal RX2 is for DCS1800 in the GSM high band, for example
- the newly added RX4 is PCS1900 in the GSM high band, for example. It is used.
- the voltage applied to each off-capacitance is made uniform, and the distortion characteristics (HD, IMD) can be improved.
- the value of Wg_RXcom may actually have a fluctuation range of about ⁇ 20% depending on manufacturing variations and the like.
- a HEMT element is used as a switching transistor, but of course, the present invention is not limited to this.
- a MOSFET Metal Oxide Semiconductor
- SOI Silicon On On Insulator
- SOS Silicon On On Sapphire
- the communication method is not limited to GSM or W-CDMA, and it is considered that the communication method can be applied to, for example, a high frequency module compatible with LTE (Long Term Term Evolution).
- LTE Long Term Term Evolution
- the present invention is not necessarily limited to a mobile phone, and can be similarly applied to various wireless communication systems including, for example, a wireless LAN antenna switch corresponding to a plurality of bands (for example, 2.4 GHz band, 5 GHz band). is there.
- the semiconductor integrated circuit device and the high-frequency module according to the present embodiment are particularly useful when applied to a mobile phone including a multiband-compatible antenna switch. Applicable.
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Abstract
Description
《半導体集積回路装置の主要部の構成》
図1は、本発明の実施の形態1による半導体集積回路装置において、その主要部の構成例を示す回路図である。図1に示す半導体集積回路装置(アンテナスイッチ用デバイス)は、アンテナ接続端子PNantと、送信端子TX2と、受信端子RX1,RX2と、オン・オフ制御端子RXcomc,RX2c,RX1cを備えている。更に、当該アンテナスイッチ用デバイスは、送信スイッチ用のトランジスタQ_TX2と、受信スイッチ用の共通トランジスタQ_RXcomと、受信スイッチ用のトランジスタQ_RX1,Q_RX2を備えている。各トランジスタは、特に限定はされないが、高周波数帯で低挿入損失、高アイソレーション、低雑音等を実現可能な例えばHEMT素子等で構成される。なお、ここでは、付加的に送信スイッチ用のトランジスタQ_TX1と、送受信スイッチ用のトランジスタQ_TRX1~Q_TRX3も示されているが、これらは必ずしも必要という訳ではない。 (Embodiment 1)
<Configuration of main part of semiconductor integrated circuit device>
FIG. 1 is a circuit diagram showing a configuration example of a main part of a semiconductor integrated circuit device according to
本実施の形態による半導体集積回路装置は、図1で述べたような各種工夫によって、歪み特性の向上が図られている。ただし、前述したQ_RX2(又はQ_RX1)が支配的となって生じる歪み特性の劣化を改善するためには更なる工夫が必要とされ、この工夫が当該半導体集積回路装置の特に重要な特徴となっている。以下、この特徴について詳細に説明する。 << Main features and effects of this embodiment >>
In the semiconductor integrated circuit device according to the present embodiment, the distortion characteristics are improved by various devices as described in FIG. However, in order to improve the deterioration of the distortion characteristics caused by the above-described Q_RX2 (or Q_RX1) being dominant, further contrivance is required, and this contrivance becomes a particularly important feature of the semiconductor integrated circuit device. Yes. Hereinafter, this feature will be described in detail.
図4は、図1の半導体集積回路装置において、その各スイッチ用トランジスタのデバイス構造例を示す断面図である。図1に示した各スイッチ用トランジスタは、例えば図4に示すような高電子移動度トランジスタ(HEMT)素子で構成される。図4に示すHEMT素子では、まず、半絶縁性基板SUB上にエピタキシャル層EPが形成されている。半絶縁性基板SUBとは、化合物半導体であるガリウムヒ素(GaAs)基板等から構成される以下に示すような基板である。つまり、禁制帯幅の大きい化合物半導体では、ある種の不純物を添加すると、禁制帯の内部に深い準位が形成される。そして、この深い準位の電子および正孔が固定され、伝導帯の電子密度あるいは価電子帯の正孔密度が非常に小さくなり絶縁体に近くなる。このような基板を半絶縁性基板と呼ぶ。GaAs基板では、Cr、In、酸素などを添加したり、過剰に砒素を導入することにより深い準位が形成され、半絶縁性基板となる。 <Device structure of switch transistor>
FIG. 4 is a cross-sectional view showing a device structure example of each switch transistor in the semiconductor integrated circuit device of FIG. Each switching transistor shown in FIG. 1 is composed of, for example, a high electron mobility transistor (HEMT) element as shown in FIG. In the HEMT device shown in FIG. 4, first, an epitaxial layer EP is formed on a semi-insulating substrate SUB. The semi-insulating substrate SUB is a substrate as shown below composed of a gallium arsenide (GaAs) substrate which is a compound semiconductor. That is, in a compound semiconductor having a large forbidden band, when a certain type of impurity is added, a deep level is formed inside the forbidden band. The deep level electrons and holes are fixed, and the electron density in the conduction band or the hole density in the valence band becomes very small, becoming closer to an insulator. Such a substrate is called a semi-insulating substrate. In a GaAs substrate, deep levels are formed by adding Cr, In, oxygen or the like, or introducing arsenic excessively, thereby forming a semi-insulating substrate.
図5は、本発明の実施の形態1の高周波モジュールにおいて、その全体構成の一例を示すブロック図である。図5に示す高周波モジュールRFMDは、例えば、無線通信システムの一つである携帯電話機で用いられ、例えば複数の部品が実装された1個の配線基板(セラミック基板等)によって構成される。当該RFMDには、高周波電力増幅モジュールHPAMDと、高周波信号処理チップRFICと、SAW(Surface Acoustic Wave)フィルタSAW1,SAW2と、W-CDMA用パワーアンプ回路PA_W1~PA_W3と、デュプレクサDPX1~DPX3等が搭載されている。 <Configuration of high-frequency module>
FIG. 5 is a block diagram showing an example of the overall configuration of the high-frequency module according to
図6は、図5の高周波モジュールにおいて、そのアンテナスイッチ用デバイスの詳細な構成例を示す回路図である。図6に示すアンテナスイッチ用デバイスANTSWは、図5で述べた8個の信号端子(PNant,TX1,TX2,RX1,RX2,TRX1~TRX3)に加えて、各スイッチ用トランジスタのオン・オフを制御するオン・オフ制御端子TX1c,TX2c,RX1c,RX2c,TRX1c~TRX3c,RXcomcおよび複数の接地電源電圧端子(接地電源電圧)GNDを備えている。当該オン・オフ制御端子は、図5では省略しているが、実際には、図5のANTSWに備わっている。 <Details of antenna switch device>
FIG. 6 is a circuit diagram showing a detailed configuration example of the antenna switch device in the high-frequency module of FIG. The antenna switch device ANTSW shown in FIG. 6 controls on / off of each switch transistor in addition to the eight signal terminals (PNant, TX1, TX2, RX1, RX2, TRX1 to TRX3) described in FIG. ON / OFF control terminals TX1c, TX2c, RX1c, RX2c, TRX1c to TRX3c, RXcomc and a plurality of ground power supply voltage terminals (ground power supply voltage) GND are provided. The on / off control terminal is omitted in FIG. 5, but is actually provided in the ANTSW of FIG.
図8は、図6のアンテナスイッチ用デバイスにおいて、その各種効果を検証した結果の一例を示す説明図である。図8に示すように、本発明の前提として検討したアンテナスイッチ用デバイス(比較例)では、Q_RXcomのゲート幅(Wg_RXcom)がQ_RX1のゲート幅(Wg_RX1)(ここではQ_RX2のゲート幅(Wg_RX2)も同一とする)の3倍(Wg_RXcom/Wg_RX1=1.8mm/0.6mm)に設定されていた。この場合、TX2からの送信動作を行った際に、2HD/3HD=-77.1dBc/-71.6dBcとなった。一方、本実施の形態の方式を適用した場合、Wg_RXcom=Wg_RX1+Wg_RX2に設定され、ここでは、Wg_RX1=Wg_RX2であるため、Wg_RXcomがWg_RX1の2倍(Wg_RXcom/Wg_RX1=1.5mm/0.75mm)に設定される。この場合、TX2からの送信動作を行った際に、2HD/3HD=-80.9dBc/-81.6dBcとなり、例えば3HDにおいて約10dBの改善効果が得られた。なお評価条件は、送信パワー(Pin)=35dBm、送信周波数=1880MHz、ゲートバイアス電圧V_TX2c=4.6Vである。 << Verification results of antenna switch device >>
FIG. 8 is an explanatory diagram showing an example of a result of verifying various effects in the antenna switch device of FIG. As shown in FIG. 8, in the antenna switch device (comparative example) studied as a premise of the present invention, the gate width (Wg_RXcom) of Q_RXcom is Q_RX1 (Wg_RX1) (here, the gate width (Wg_RX2) of Q_RX2) is also 3 times (Wg_RXcom / Wg_RX1 = 1.8 mm / 0.6 mm). In this case, when a transmission operation from TX2 was performed, 2HD / 3HD = −77.1 dBc / −71.6 dBc. On the other hand, when the method of the present embodiment is applied, Wg_RXcom = Wg_RX1 + Wg_RX2 is set, and here Wg_RX1 = Wg_RX2, and therefore Wg_RXcom is twice Wg_RX1 (Wg_RXcom / Wg_RX1 = 1.5 mm / 0.75 mm). Is set. In this case, when a transmission operation from TX2 is performed, 2HD / 3HD = −80.9 dBc / −81.6 dBc, and for example, an improvement effect of about 10 dB is obtained in 3HD. The evaluation conditions are transmission power (Pin) = 35 dBm, transmission frequency = 1880 MHz, and gate bias voltage V_TX2c = 4.6V.
本実施の形態2では、図6に示したアンテナスイッチ用デバイスの変形例について説明する。図9は、本発明の実施の形態2による高周波モジュールにおいて、それに含まれるアンテナスイッチ用デバイスの構成例を示す回路図である。図9に示すアンテナスイッチ用デバイスANTSW2は、図6のANTSWと比較して、W-CDMA用の送受信端子TRX3に伴う箇所(TRX3c,Q_TRX3,Q_TRX3s)が削除され、代わりに2個の受信端子RX3,RX4およびオン・オフ制御端子RX3c,RX4cとこれに伴う各スイッチ用トランジスタが追加された構成となっている。これ以外の構成に関しては図6と同様であるため詳細な説明は省略する。図9のANTSW2は、SP8T型の構成となる。 (Embodiment 2)
In the second embodiment, a modification of the antenna switch device shown in FIG. 6 will be described. FIG. 9 is a circuit diagram showing a configuration example of the antenna switch device included in the high-frequency module according to
BF バッファ層
C 容量
CTLIC 制御チップ
DPX デュプレクサ
EP エピタキシャル層
G ゲート電極
GND 接地電源電圧
HPAMD 高周波電力増幅モジュール
ISL 絶縁膜
LNA ロウノイズアンプ回路
LPF ロウパスフィルタ
LY 半導体層
OE オーミック電極
PA,HPA パワーアンプ回路
PNant アンテナ接続端子
Q トランジスタ
R 抵抗
RFIC 高周波信号処理チップ
RFMD 高周波モジュール
RX1~RX4 受信端子
RXcomc,RX1c~RX4c,TX1c,TX2c オン・オフ制御端子
SAW SAWフィルタ
SH n+電極
SUB 半絶縁性基板
TRX1~TRX3 送受信端子
TX1,TX2 送信端子 ANTSW Antenna switch device BF Buffer layer C Capacitance CTLIC Control chip DPX Duplexer EP Epitaxial layer G Gate electrode GND Ground power supply voltage HPAMD High frequency power amplification module ISL Insulating film LNA Low noise amplifier circuit LPF Low pass filter LY Semiconductor layer OE Ohmic electrode PA, HPA power amplifier circuit PNant antenna connection terminal Q transistor R resistance RFIC high frequency signal processing chip RFMD high frequency module RX1 to RX4 reception terminal RXcomc, RX1c to RX4c, TX1c, TX2c ON / OFF control terminal SAW SAW filter SH n + electrode SUB Semi-insulating substrate TRX1 to TRX3 Transmission / reception terminals TX1, TX2 Transmission terminals
Claims (17)
- アンテナ接続用であり、アンテナに向けた第1送信信号が伝送されるアンテナ端子と、
第1~第N(Nは2以上の整数)端子と、
前記アンテナ端子と共通ノードの間にソース・ドレイン経路が結合され、前記アンテナ端子に前記第1送信信号が伝送される際にオフに制御される共通トランジスタと、
前記共通ノードと前記第1~第N端子の間にそれぞれソース・ドレイン経路が結合され、前記共通トランジスタがオフに制御される際に共にオフに制御される第1~第Nトランジスタとを備え、
前記共通トランジスタのゲート幅は、前記第1~第Nトランジスタにおける各ゲート幅の合計値の±20%の範囲であることを特徴とする半導体集積回路装置。 An antenna terminal for antenna connection, through which a first transmission signal directed to the antenna is transmitted;
First to Nth (N is an integer of 2 or more) terminals;
A common transistor having a source / drain path coupled between the antenna terminal and a common node and controlled to be turned off when the first transmission signal is transmitted to the antenna terminal;
Source-drain paths are coupled between the common node and the first to Nth terminals, respectively, and the first to Nth transistors are controlled to be turned off when the common transistor is controlled to be turned off.
The semiconductor integrated circuit device, wherein a gate width of the common transistor is in a range of ± 20% of a total value of gate widths in the first to Nth transistors. - 請求項1記載の半導体集積回路装置において、
前記第1~第N端子は、受信端子であることを特徴とする半導体集積回路装置。 The semiconductor integrated circuit device according to claim 1.
The semiconductor integrated circuit device, wherein the first to Nth terminals are reception terminals. - 請求項2記載の半導体集積回路装置において、
前記共通トランジスタは、マルチゲートトランジスタであり、
前記第1~第Nトランジスタのそれぞれは、シングルゲートトランジスタであり、
前記共通トランジスタとなる前記マルチゲートトランジスタを等価的に構成する各シングルゲートトランジスタのゲート幅は、前記第1~第Nトランジスタにおける各ゲート幅の合計値の±20%の範囲であることを特徴とする半導体集積回路装置。 The semiconductor integrated circuit device according to claim 2.
The common transistor is a multi-gate transistor;
Each of the first to Nth transistors is a single gate transistor,
A gate width of each single gate transistor that equivalently constitutes the multi-gate transistor serving as the common transistor is in a range of ± 20% of a total value of gate widths in the first to Nth transistors. A semiconductor integrated circuit device. - 請求項2記載の半導体集積回路装置において、
さらに、前記共通トランジスタのゲート電圧を制御する共通制御端子を備え、
前記共通トランジスタは、HEMT素子からなるトリプルゲートトランジスタであり、
前記共通トランジスタとなる前記トリプルゲートトランジスタに含まれる両端のゲートは、第1抵抗値を介して前記共通制御端子に結合され、
前記共通トランジスタとなる前記トリプルゲートトランジスタに含まれる真ん中のゲートは、前記第1抵抗値よりも小さい第2抵抗値を介して前記共通制御端子に結合されることを特徴とする半導体集積回路装置。 The semiconductor integrated circuit device according to claim 2.
And a common control terminal for controlling a gate voltage of the common transistor,
The common transistor is a triple gate transistor composed of a HEMT element,
Gates at both ends included in the triple gate transistor serving as the common transistor are coupled to the common control terminal via a first resistance value,
A semiconductor integrated circuit device, wherein a middle gate included in the triple gate transistor serving as the common transistor is coupled to the common control terminal via a second resistance value smaller than the first resistance value. - 請求項2記載の半導体集積回路装置において、さらに、
第1送信端子と、
前記第1送信端子と前記アンテナ端子の間にソース・ドレイン経路が結合される第1送信用トランジスタとを備え、
前記第1送信信号は、オンに制御される前記第1送信用トランジスタを介して前記第1送信端子から前記アンテナ端子に伝送されることを特徴とする半導体集積回路装置。 3. The semiconductor integrated circuit device according to claim 2, further comprising:
A first transmission terminal;
A first transmission transistor having a source / drain path coupled between the first transmission terminal and the antenna terminal;
The semiconductor integrated circuit device, wherein the first transmission signal is transmitted from the first transmission terminal to the antenna terminal through the first transmission transistor controlled to be turned on. - 請求項5記載の半導体集積回路装置において、
前記共通トランジスタ、前記第1~第Nトランジスタ、および前記第1送信用トランジスタのそれぞれは、HEMT素子であることを特徴とする半導体集積回路装置。 The semiconductor integrated circuit device according to claim 5.
Each of the common transistor, the first to Nth transistors, and the first transmission transistor is a HEMT element. - 請求項5記載の半導体集積回路装置において、
さらに、前記第1~第N端子と接地電源電圧の間にそれぞれソース・ドレイン経路が結合され、前記第1~第Nトランジスタと相補の関係でオン・オフが制御される第1~第Nシャント用トランジスタを有することを特徴とする半導体集積回路装置。 The semiconductor integrated circuit device according to claim 5.
Further, source-drain paths are coupled between the first to N-th terminals and the ground power supply voltage, respectively, and first to N-th shunts controlled on and off in a complementary relationship with the first to N-th transistors. A semiconductor integrated circuit device comprising a transistor for use. - 請求項5記載の半導体集積回路装置において、
前記第1送信信号は、GSM方式の周波数帯を持つことを特徴とする半導体集積回路装置。 The semiconductor integrated circuit device according to claim 5.
The semiconductor integrated circuit device, wherein the first transmission signal has a GSM frequency band. - 請求項5記載の半導体集積回路装置において、
前記第1送信信号は、W-CDMA方式の周波数帯を持つことを特徴とする半導体集積回路装置。 The semiconductor integrated circuit device according to claim 5.
The semiconductor integrated circuit device, wherein the first transmission signal has a W-CDMA frequency band. - 1個の配線基板によって実現され、
前記配線基板上に実装された第1半導体チップを備え、
前記第1半導体チップは、
アンテナ接続用であるアンテナ端子と、
第1送信信号が入力される第1送信端子と、
第1~第N(Nは2以上の整数)受信端子と、
前記第1送信端子と前記アンテナ端子の間にソース・ドレイン経路が結合され、前記第1送信信号を前記アンテナ端子に伝送する際にオンに制御される第1送信用トランジスタと、
前記アンテナ端子と共通ノードの間にソース・ドレイン経路が結合され、前記第1送信用トランジスタがオンに制御される際にオフに制御され、前記アンテナからの受信信号を前記第1~第N受信端子のいずれか1個に向けて伝送する際にオンに制御される受信用共通トランジスタと、
前記共通ノードと前記第1~第N受信端子の間にそれぞれソース・ドレイン経路が結合され、前記受信用共通トランジスタがオフに制御される際に共にオフに制御され、前記受信用共通トランジスタがオンに制御される際にいずれか1個がオンに制御される第1~第N受信用トランジスタとを備え、
前記受信用共通トランジスタのゲート幅は、前記第1~第N受信用トランジスタにおける各ゲート幅の合計値の±20%の範囲であることを特徴とする高周波モジュール。 Realized by one wiring board,
A first semiconductor chip mounted on the wiring board;
The first semiconductor chip is
An antenna terminal for antenna connection;
A first transmission terminal to which a first transmission signal is input;
First to Nth (N is an integer of 2 or more) receiving terminals;
A first transmission transistor having a source / drain path coupled between the first transmission terminal and the antenna terminal and controlled to be turned on when transmitting the first transmission signal to the antenna terminal;
A source / drain path is coupled between the antenna terminal and the common node, and is controlled to be turned off when the first transmission transistor is controlled to be turned on, and a reception signal from the antenna is received in the first to Nth reception. A receiving common transistor that is turned on when transmitting toward any one of the terminals; and
A source / drain path is coupled between the common node and the first to Nth receiving terminals, respectively. When the receiving common transistor is controlled to be turned off, both are controlled to be off, and the receiving common transistor is turned on. 1st to Nth receiving transistors, any one of which is controlled to be turned on when controlled by
The high frequency module according to claim 1, wherein a gate width of the common receiving transistor is in a range of ± 20% of a total value of gate widths of the first to Nth receiving transistors. - 請求項10記載の高周波モジュールにおいて、
前記受信用共通トランジスタは、マルチゲートトランジスタであり、
前記第1~第N受信用トランジスタのそれぞれは、シングルゲートトランジスタであり、
前記受信用共通トランジスタとなる前記マルチゲートトランジスタを等価的に構成する各シングルゲートトランジスタのゲート幅は、前記第1~第N受信用トランジスタにおける各ゲート幅の合計値の±20%の範囲であることを特徴とする高周波モジュール。 The high-frequency module according to claim 10,
The reception common transistor is a multi-gate transistor,
Each of the first to Nth receiving transistors is a single gate transistor,
The gate width of each single gate transistor equivalently constituting the multi-gate transistor serving as the reception common transistor is in a range of ± 20% of the total value of the gate widths in the first to Nth reception transistors. A high-frequency module characterized by that. - 請求項11記載の高周波モジュールにおいて、
さらに、前記受信用共通トランジスタのゲート電圧を制御する共通制御端子を備え、
前記受信用共通トランジスタは、HEMT素子からなるトリプルゲートトランジスタであり、
前記受信用共通トランジスタとなる前記トリプルゲートトランジスタに含まれる両端のゲートは、第1抵抗値を介して前記共通制御端子に結合され、
前記受信用共通トランジスタとなる前記トリプルゲートトランジスタに含まれる真ん中のゲートは、前記第1抵抗値よりも小さい第2抵抗値を介して前記共通制御端子に結合されることを特徴とする高周波モジュール。 The high frequency module according to claim 11, wherein
And a common control terminal for controlling a gate voltage of the common transistor for reception.
The reception common transistor is a triple gate transistor made of a HEMT element,
Gates at both ends included in the triple gate transistor serving as the reception common transistor are coupled to the common control terminal via a first resistance value,
A high-frequency module, wherein a middle gate included in the triple gate transistor serving as the reception common transistor is coupled to the common control terminal through a second resistance value smaller than the first resistance value. - 請求項11記載の高周波モジュールにおいて、
前記受信用共通トランジスタ、前記第1~第N受信用トランジスタ、および前記第1送信用トランジスタのそれぞれは、HEMT素子であることを特徴とする高周波モジュール。 The high frequency module according to claim 11, wherein
Each of the reception common transistor, the first to Nth reception transistors, and the first transmission transistor is a HEMT element. - 請求項10記載の高周波モジュールにおいて、さらに、
前記第1~第N受信端子と接地電源電圧の間にそれぞれソース・ドレイン経路が結合され、前記第1~第N受信用トランジスタと相補の関係でオン・オフが制御される第1~第N受信シャント用トランジスタと、
前記第1送信端子と前記接地電源電圧の間にソース・ドレイン経路が結合され、前記第1送信用トランジスタと相補の関係でオン・オフが制御される第1送信シャント用トランジスタとを有することを特徴とする高周波モジュール。 The high-frequency module according to claim 10, further comprising:
Source / drain paths are coupled between the first to Nth receiving terminals and the ground power supply voltage, respectively, and are turned on / off in a complementary relationship with the first to Nth receiving transistors. A receiving shunt transistor;
A source / drain path is coupled between the first transmission terminal and the ground power supply voltage, and a first transmission shunt transistor whose ON / OFF is controlled in a complementary relationship with the first transmission transistor is provided. High-frequency module featuring - 請求項10記載の高周波モジュールにおいて、
前記第1送信信号は、GSM方式の周波数帯を持つことを特徴とする高周波モジュール。 The high-frequency module according to claim 10,
The first transmission signal has a GSM frequency band. - 請求項15記載の高周波モジュールにおいて、さらに、
第2送信信号および第1受信信号を伝送する第1送受信端子と、
前記第1送受信端子と前記アンテナ端子の間にソース・ドレイン経路が結合され、前記第2送信信号を前記アンテナ端子に伝送する際と前記アンテナ端子からの受信信号を前記第1受信信号として前記第1送受信端子に伝送する際にオンに制御される第1送受信用トランジスタとを備え、
前記受信用共通トランジスタは、前記第1送受信用トランジスタがオンに制御される際にオフに制御され、
前記第2送信信号および前記第1受信信号は、W-CDMA方式の周波数帯を持つことを特徴とする高周波モジュール。 The high-frequency module according to claim 15, further comprising:
A first transmission / reception terminal for transmitting the second transmission signal and the first reception signal;
A source / drain path is coupled between the first transmission / reception terminal and the antenna terminal, and the second transmission signal is transmitted to the antenna terminal and a reception signal from the antenna terminal is used as the first reception signal. A first transmission / reception transistor that is turned on when transmitting to one transmission / reception terminal;
The reception common transistor is controlled to be off when the first transmission / reception transistor is controlled to be on,
The high-frequency module, wherein the second transmission signal and the first reception signal have a frequency band of W-CDMA system. - 請求項15記載の高周波モジュールにおいて、
前記配線基板上には、さらに、前記第1送信端子に向けて前記第1送信信号を出力するパワーアンプ回路が実装されることを特徴とする高周波モジュール。 The high frequency module according to claim 15,
A high-frequency module, wherein a power amplifier circuit that outputs the first transmission signal toward the first transmission terminal is further mounted on the wiring board.
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