WO2012157650A1 - Appareil de traitement d'image - Google Patents

Appareil de traitement d'image Download PDF

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Publication number
WO2012157650A1
WO2012157650A1 PCT/JP2012/062433 JP2012062433W WO2012157650A1 WO 2012157650 A1 WO2012157650 A1 WO 2012157650A1 JP 2012062433 W JP2012062433 W JP 2012062433W WO 2012157650 A1 WO2012157650 A1 WO 2012157650A1
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Prior art keywords
data
enable signal
effective period
signal
image data
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PCT/JP2012/062433
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English (en)
Japanese (ja)
Inventor
▲高▼橋　昌之
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シャープ株式会社
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Publication of WO2012157650A1 publication Critical patent/WO2012157650A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/12—Use of DVI or HDMI protocol in interfaces along the display data pipeline
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
    • H04N21/4363—Adapting the video stream to a specific local network, e.g. a Bluetooth® network
    • H04N21/43632—Adapting the video stream to a specific local network, e.g. a Bluetooth® network involving a wired protocol, e.g. IEEE 1394
    • H04N21/43635—HDMI

Definitions

  • the present invention relates to an image processing apparatus that can appropriately process image data even when an HDMI signal of the HDMI (registered trademark) standard is deteriorated.
  • High Definition television: HDTV High Definition television
  • the resolution of the current high-definition television broadcast is 1920 horizontal pixels ⁇ 1080 vertical pixels (so-called 2K1K, hereinafter this resolution is referred to as full HD resolution).
  • 2K1K the resolution of the full HD resolution
  • 8K4K the resolution of the full HD resolution
  • 4K2K 4K2K
  • 8K4K 16 times the resolution
  • HDMI High-Definition Multimedia Interface
  • the HDMI standard adopts a specification that allows video signals, audio signals, and control signals to be transmitted through a single cable without compression, and can simplify wiring and circuit configuration.
  • a TMDS (Transition / Minimized / Differential / Signal) signal used in the HDMI standard is composed of three pairs of differential data signals and one pair of clock differential signals.
  • the TMDS signal corresponding to the 8K4K resolution has a 12-bit format, and has a higher frequency than the TMDS signal corresponding to the current full HD resolution, which is the 8-bit format, and is likely to cause a reception error due to a deterioration in quality.
  • the conversion circuit outputs a clock signal CLK, a data enable signal DE, and image data DATA as shown in FIG.
  • the data enable signal DE is a signal that defines a period during which the image data DATA is output.
  • the image processing unit in the receiving apparatus recognizes the image data DATA during a period in which the data enable signal DE is at the H level in order to process the image data DATA.
  • the image processing unit tries to recognize the image data DATA one clock earlier than usual, but the image data DATA has not yet been output from the conversion circuit, and therefore 0 data, that is, black data is captured.
  • 0 data that is, black data is captured.
  • Patent Document 1 discloses an improvement for reducing an error rate with respect to a reception error that occurs when a poor HDMI cable is used. Specifically, the following two processes are performed as this improvement. (1) The receiving apparatus controls the transmitting apparatus so that the voltage amplitude of the TMDS signal from the transmitting apparatus is increased in advance. (2) The receiving apparatus controls the transmitting apparatus so that a skew is previously added to the TMDS signal from the transmitting apparatus.
  • JP 2008-199175 A Japanese Patent Publication “JP 2008-199175 A” (published September 28, 2008)
  • Patent Document 1 requires that the receiving device can control the transmitting device. For this reason, the receiving apparatus must have a function of controlling the transmitting apparatus.
  • the transmission device needs to include a reception-side control unit that transmits error rate information to the transmission device. Further, since it is necessary to add a signal line for transmitting the control signal to the HDMI cable, it is necessary to change the interface for that purpose. In addition, it is necessary for the transmission device to have a function of performing the above processing under the control of the reception device.
  • the present invention has been made in view of the above problems, and an object thereof is to provide an image processing apparatus capable of correcting an error for a deteriorated received signal (TMDS signal) without controlling the transmitting apparatus. There is to do.
  • TMDS signal deteriorated received signal
  • the image processing apparatus recognizes image data obtained from a TMDS signal based on a valid signal indicating a valid period during which the image data is valid, and displays the recognized image data on the recognized image data Image processing means for performing, phase shift detection means for detecting a phase shift at the start point of the effective period in the effective signal, and phase correction means for correcting the phase of the start point so as to eliminate the detected phase shift It is characterized by having.
  • the phase shift of the start point is detected by the phase shift detection means. Then, the phase of the starting point is corrected by the phase correction means so as to eliminate the phase shift.
  • the image processing means can properly recognize the image data based on the valid signal having an appropriate starting point. Therefore, it is possible to display image data normally.
  • the image processing apparatus which is configured as described above, can correct an error for a deteriorated TMDS signal (received signal) without controlling the transmitting apparatus that transmits the TMDS signal. There is an effect.
  • FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention. It is a block diagram which shows the structure which concerns on Embodiment 1 of the data enable signal correction
  • 3 is a flowchart showing an operation procedure of a data enable signal correction unit in FIG. 2.
  • 2A is a timing chart showing the operation of the data enable signal correction unit in FIG. 2 when the data enable signal is normally output from the HDMI conversion unit in the image processing apparatus, and FIG. It is a timing chart which shows operation
  • FIG. 3 is a diagram illustrating a state of an image displayed when the phase of the data enable signal is corrected by the data enable signal correction unit of FIG. 2.
  • FIG. 6A is a timing chart showing the operation of the data enable signal correction unit in FIG. 6 when the data enable signal is normally output from the HDMI conversion unit in the image processing apparatus, and FIG. It is a timing chart which shows operation
  • FIG. 10 is a flowchart illustrating an operation procedure of a data enable signal correction unit in FIG. 9.
  • FIG. 9A is a timing chart showing the operation of the data enable signal correction unit in FIG. 9 when the data enable signal is normally output from the HDMI conversion unit in the image processing apparatus
  • FIG. 6 is a timing chart showing the operation of the data enable signal correction unit when it falls later than the normal timing
  • FIG. 5C shows the operation of the data enable signal correction unit when the first image data of one line is 0. It is a timing chart which shows. It is a figure which shows the image which a black line appears in the right end by the error which arises in the said HDMI conversion part.
  • (A) is a timing chart showing the relationship between a clock, a data enable signal and data obtained as a result of converting a TMDS signal into a CMOS level signal in a conventional device, and (b) shows a large amount of jitter generated in the conventional device. It is a timing chart which shows said relationship at the time. It is a figure which shows the image displayed in the case shown in (b) of FIG.
  • FIG. 1 is a block diagram showing an overall configuration of an image processing apparatus 1 according to the present embodiment.
  • the image processing device 1 includes an HDMI conversion unit 2, a data enable signal correction unit 3, an image processing unit 4, and a liquid crystal display device 5.
  • the HDMI conversion unit 2 is a circuit that converts the TMDS signal output from the signal source 7 and transmitted via the HDMI cable 8 into a CMOS level signal.
  • the HDMI conversion unit 2 is configured by an IC in order to perform a specified conversion process. As a result of the conversion, the HDMI conversion unit 2 outputs a clock signal CLK, image data DATA, and a data enable signal DE (see (a) of FIG. 4).
  • the HDMI conversion unit 2 also outputs a horizontal synchronization signal for defining the start of the line and a vertical synchronization signal for defining the start of the frame.
  • the data enable signal DE is generated by the signal source 7 and is transmitted to the image processing apparatus 1 by being included in the TMDS signal.
  • the data enable signal DE (valid signal) is a signal that determines a period during which the image processing unit 4 recognizes the image data DATA for processing the image data DATA.
  • This data enable signal DE is a signal that normally becomes active (H level) so as to enable recognition of the image data DATA during the period when the image data DATA is output, and rises in synchronization with the rise of the clock signal CLK. And fall down.
  • the period during which the data enable signal DE is active may not coincide with the period in which the image data DATA is output due to an error or other error that has occurred in the HDMI conversion unit 2, as will be described later. .
  • the data enable signal correction unit 3 detects a shift (phase shift) with respect to the normal phase of the phase of the data enable signal DE output from the HDMI conversion unit 2 (the start point of the effective period). .
  • the data enable signal correction unit 3 (phase correction means) outputs the data enable signal DE as it is when no rising phase shift is detected.
  • the data enable signal correction unit 3 appropriately corrects the rising phase and outputs a data enable signal DE.
  • the data enable signal correction unit 3 outputs the clock signal CLK and the image data DATA input from the HDMI conversion unit 2. Further, the data enable signal correction unit 3 outputs the horizontal synchronization signal and the vertical synchronization signal input from the HDMI conversion unit 2 as they are.
  • the image processing unit 4 performs predetermined processing on the image data DATA output from the data enable signal correction unit 3. Specifically, the image processing unit 4 performs processing such as noise removal, color conversion, edge enhancement, and resolution conversion. In these processes, the image processing unit 4 recognizes the image data DATA in synchronization with the clock signal CLK during the valid period of the data enable signal DE from the data enable signal correction unit 3. Further, the image processing unit 4 outputs the clock signal CLK, the horizontal synchronization signal, and the vertical synchronization signal received from the data enable signal correction unit 3 to the liquid crystal display device 5.
  • the liquid crystal display device 5 has a drive unit (a timing controller, a source driver and a gate driver described later) and a liquid crystal display panel.
  • the driving unit drives the liquid crystal display panel based on a vertical synchronization signal, a horizontal synchronization signal, a clock signal CLK, a data enable signal DE, and the like input via the image processing unit 4.
  • An image can be displayed with a gradation corresponding to the image data DATA.
  • FIG. 2 is a block diagram showing the configuration of the data enable signal correction unit 11 according to the present embodiment of the data enable signal correction unit 3.
  • the data enable signal correction unit 11 includes a counter 12, a comparator 13, a selection output circuit 14, and a delay circuit 15.
  • the counter 12 counts the clock signal CLK during the valid period of the data enable signal DE, and outputs a count value CNT1 that is the value of the count number of the valid period.
  • the counter 12 (effective period width measuring means) can measure the effective period width of the data enable signal DE based on the number of clocks of the clock signal CLK (count value CNT1).
  • the comparator 13 compares the predetermined reference value R1 with the count value CNT1. As a result of comparison, the comparator 13 outputs an H level determination signal CMP1 when the count value CNT1 is larger than the reference value R1, and outputs an L level determination signal CMP1 when the count value CNT1 is equal to or less than the reference value R1. To do. Thereby, the comparator 13 (effective period width determination means) can determine whether or not the width of the data enable signal DE is larger than the reference value R1.
  • the reference value R1 is set to 1920 (one line of image data DATA), which is the number of effective pixels of one line, assuming that a full HD resolution image is displayed.
  • the selection output circuit 14 (selection output means) outputs the data enable signal DE to the delay circuit 15 when the determination signal CMP1 is at the H level, while the data enable signal DE is externally output as it is when the determination signal CMP1 is at the L level. Output.
  • the selection output circuit 14 can be configured to selectively output the data enable signal DE as described above by a combination of logic circuits.
  • the delay circuit 15 delays the rising edge of the data enable signal DE output from the selection output circuit 14 by one clock of the clock signal CLK and outputs the delayed data enable signal DDE.
  • the delay circuit 15 can be configured to delay the rising edge of the data enable signal DE by one clock, for example, by a flip-flop.
  • FIG. 3 is a flowchart showing an operation procedure of the data enable signal correction unit 11.
  • FIG. 4A is a timing chart showing the operation of the data enable signal correction unit 11 when the data enable signal DE is normally output.
  • FIG. 4B is a timing chart showing the operation of the data enable signal correction unit 11 when the data enable signal DE rises earlier than the normal timing.
  • the counter 12 counts the effective period clock signal CLK in the data enable signal DE, thereby measuring the effective period width (step S11).
  • step S12 when it is determined that the count value CNT1 is not larger than 1920 (NO) (the determination signal CMP1 is at L level), the selection output circuit 14 outputs the data enable signal DE as it is for the next line and thereafter (as is the case). Step S13). The selection output circuit 14 performs the operation on the output of the next line. At the same time as the output operation of the data enable signal DE by the selection output circuit 14 is performed on the next line, the process returns to step S11 in order to perform the operation on and after step S11 for the next line.
  • step S12 determines whether the count value CNT1 is greater than 1920 (YES) (the determination signal CMP1 is at H level) (the determination signal CMP1 is at H level) (the determination signal CMP1 is at H level) (the determination signal CMP1 is at H level)
  • the selection output circuit 14 sends the data enable signal DE to the delay circuit 15 in the next line and thereafter. Output to.
  • the delay circuit 15 delays the rising edge of the data enable signal DE input from the selection output circuit 14 by one clock of the clock signal CLK and outputs it (step S14).
  • the delay circuit 15 performs the operation of step S14 on the output of the next line.
  • the process returns to step S11 in order to perform the operation after step S11 on the next line.
  • step S12 it is determined that the count value CNT1 is not greater than 1920 (NO). Therefore, the data enable signal DE is output from the selection output circuit 14 as it is.
  • the data enable signal correction unit 11 measures the width of the data enable signal DE, so that the delayed data enable signal DDE whose rising edge is delayed by one clock based on the determination result in the next line and thereafter. Is output from the delay circuit 15.
  • the data enable signal DE from the HDMI conversion unit 2 is output from the data enable signal correction unit 11 as it is.
  • the data enable signal DE is output simultaneously with the measurement of the width of the data enable signal DE. For this reason, the data enable signal DE is output as it is through the selection output circuit 14 regardless of whether the width of the valid period is larger than the reference value R1.
  • FIG. 5 is a diagram illustrating a state of an image displayed when the phase of the data enable signal DE is corrected by the data enable signal correction unit 11.
  • the data enable signal correction unit 11 changes the data enable signal DE to 1 of the clock signal CLK. Output with delay by clock. As a result, the data enable signal DE is changed to an appropriate width equal to the reference value R1. Therefore, the image processor 4 does not recognize 0 (black) data by recognizing the image data DATA one clock earlier based on the data enable signal DE. As a result, the image displayed on the liquid crystal display device 5 is normally displayed without including the black line LBL as shown in FIG. 14, as shown in FIG.
  • the TMDS signal corresponding to the above-mentioned 8K4K resolution has a very high frequency, and reception errors are likely to occur due to the quality degradation of the TMDS signal. Therefore, when an image is displayed based on the TMDS signal, it is preferable to correct the data enable signal DE as described above.
  • the data enable signal correction unit 11 detects the rising phase shift of the data enable signal DE and corrects the rising phase based on the detected phase shift. Thereby, the error of the data enable signal DE generated in the HDMI conversion unit 2 can be corrected without controlling the signal source 7. For this reason, the image processing apparatus 1 does not require a configuration for controlling the signal source 7 for error correction, and the signal source 7 performs processing for error correction under the control of the image processing apparatus 1. Does not require configuration.
  • the data enable signal correction unit 11 can be configured on a relatively small scale by a digital circuit. Therefore, the enlargement of the image processing apparatus 1 can be suppressed.
  • FIG. 6 is a block diagram showing a configuration of the data enable signal correction unit 21 according to the present embodiment of the data enable signal correction unit 3.
  • the data enable signal correction unit 21 includes a D flip-flop (D-FF in the figure) 22, a comparator 23, a selection output circuit 24, and a shift circuit 25.
  • D-FF D flip-flop
  • the D flip-flop 22 takes in the image data DATA (image data DATA at the start of the valid period) from the HDMI conversion unit 2 in synchronization with the rise of the data enable signal DE from the HDMI conversion unit 2.
  • the comparator 23 compares the image data DATA fetched by the D flip-flop 22 with the zero data D0 which is a value of 0.
  • the comparator 23 (data value determination means) outputs an L level determination signal CMP2 when the two data match as a result of comparison, and outputs an H level determination signal CMP1 when the two data are different.
  • the selection output circuit 24 (selection output means) outputs the data enable signal DE to the shift circuit 25 when the determination signal CMP2 is at the H level, while the data enable signal DE is externally output as it is when the determination signal CMP1 is at the L level. Output.
  • the selection output circuit 25 may be configured in the same manner as the selection output circuit 14 described above.
  • the shift circuit 25 shifts the data enable signal DE output from the selection output circuit 24 by one clock of the clock signal CLK and outputs it as a shift data enable signal SDE.
  • the shift circuit 25 can be configured to shift the data enable signal DE by one clock using, for example, a shift register.
  • FIG. 7 is a flowchart showing an operation procedure of the data enable signal correction unit 21.
  • FIG. 8A is a timing chart showing the operation of the data enable signal correction unit 21 when the data enable signal DE is normally output.
  • FIG. 8B is a timing chart showing the operation of the data enable signal correction unit 21 when the data enable signal DE rises earlier than the normal timing.
  • the D flip-flop 22 takes in the image data DATA in synchronization with the rising edge of the data enable signal DE (step S21).
  • the comparator 23 compares the captured image data DATA with the zero data D0, and determines whether or not the image data DATA is 0 (step S22).
  • Step S22 when it is determined that the image data DATA is not 0 (NO) (the determination signal CMP2 is L level), the selection output circuit 24 outputs the data enable signal DE as it is (Step S23). Thereafter, the processing returns to step S21 in order to perform the operations after step S21 for the next line.
  • step S22 if it is determined in step S22 that the image data DATA is 0 (YES) (the determination signal CMP2 is at H level), the selection output circuit 24 outputs the data enable signal DE to the shift circuit 25.
  • the shift circuit 25 shifts the input data enable signal DE by one clock of the clock signal CLK and outputs it (step S24). Then, the process returns to step S21 in order to perform the operation after step S21 for the next line.
  • step S22 it is determined that the image data DATA is not 0 (NO). Therefore, the data enable signal DE is output from the selection output circuit 24 as it is.
  • the state is fixed, so that the data enable signal DE rises earlier by one clock as shown in FIG.
  • the D flip-flop 22 captures data in a period before the first image data DATA actually has no image data DATA.
  • 0 data is taken into the D flip-flop 22, and it is determined in step S 22 that the image data DATA is 0 (YES).
  • the shift data enable signal SDE delayed by one clock is output from the first line.
  • the quality of the TMDS signal becomes high, an error does not occur in the HDMI conversion unit 2, so that the jitter of the clock signal CLK is also eliminated.
  • the normal data enable signal DE is output from the HDMI conversion unit 2
  • the image data DATA captured in synchronization with the rising edge of the data enable signal DE is not zero data D0. Therefore, the data enable signal DE from the HDMI conversion unit 2 is output from the data enable signal correction unit 21 as it is.
  • the data enable signal correction unit 21 outputs the data enable signal DE after shifting the data enable signal DE by one shift by the shift circuit 25, but is not limited thereto.
  • the data enable signal correction unit 21 includes a delay circuit similar to the delay circuit 15 in the data enable signal correction unit 11 described above instead of the shift circuit 25, thereby delaying the rising edge of the data enable signal DE by one clock. May be.
  • the data enable signal correction unit 21 shifts the data enable signal DE by one clock of the clock signal CLK when the image data DATA captured in synchronization with the rising edge of the data enable signal DE is 0. Output. Thereby, the data enable signal DE rises during a period in which the image data DATA actually exists. Therefore, the image processing unit 4 does not recognize 0 (black) data by recognizing the video signal one clock earlier based on the data enable signal DE. As a result, as shown in FIG. 5, the image displayed on the liquid crystal display device 5 is normally displayed without including the black line BL as shown in FIG.
  • the data enable signal correction unit 11 similarly to the data enable signal correction unit 11 described above, it is possible to avoid the influence of reception errors caused by the quality degradation of the TMDS signal. Therefore, the image can be displayed favorably. Therefore, similarly to the data enable signal correction unit 11, the error of the data enable signal DE generated in the HDMI conversion unit 2 can be corrected without controlling the signal source 7. Moreover, the data enable signal correction unit 21 can be configured on a relatively small scale by a digital circuit as described above. Therefore, the enlargement of the image processing apparatus 1 can be suppressed.
  • the data enable signal correction unit 21 is superior to the data enable signal correction unit 11 as follows.
  • the data enable signal correction unit 11 determines the width of the data enable signal DE at the end of the line and, based on the determination result, raises the data enable signal DE on the next line or later if necessary. Delayed.
  • the data enable signal correction unit 21 takes in the image data DATA at the head of the line, determines whether or not the image data DATA is zero data D0, and is necessary based on the determination result. If there is, the data enable signal DE is shifted from the line. Thus, the data enable signal correction unit 21 can correct the data enable signal DE from the line.
  • FIG. 9 is a block diagram illustrating a configuration of the data enable signal correction unit 31 according to the present embodiment of the data enable signal correction unit 3.
  • the data enable signal correction unit 31 includes a D flip-flop (D-FF in the figure) 32, a comparator 33, a selection output circuit 34, a counter 35, a comparator 36, a selection output circuit 37, and a delay circuit 38. have.
  • the D flip-flop 32 takes in the image data DATA from the HDMI conversion unit 2 in synchronization with the rising edge of the data enable signal DE from the HDMI conversion unit 2.
  • the comparator 33 compares the image data DATA fetched by the D flip-flop 32 with the zero data D0 which is a value of 0.
  • the comparator 33 (data value determination means) outputs an L level determination signal CMP3 when the two data match as a result of comparison, and outputs an H level determination signal CMP3 when the two data are different.
  • the selection output circuit 34 (first selection output means) outputs the data enable signal DE to the counter 35 when the determination signal CMP3 is at the H level.
  • the selection output circuit 34 outputs the data enable signal DE as it is when the determination signal CMP3 is at L level.
  • the counter 35 counts the clock signal CLK during the valid period of the data enable signal DE, and outputs a count value CNT2 that is the value of the count number of the valid period.
  • the counter 35 (effective period width measuring means) can measure the width of the effective period of the data enable signal DE based on the number of clocks of the clock signal CLK (count value CNT2).
  • the comparator 36 compares the predetermined reference value R2 with the count value CNT2.
  • This comparator 36 (effective period width determination means) outputs a determination signal CMP4 of H level when the count value CNT2 is larger than the reference value R2 as a result of comparison, and L when the count value CNT2 is less than or equal to the reference value R2.
  • a level determination signal CMP4 is output.
  • the reference value R2 is set to 1920, which is the number of effective pixels in one line, assuming that a full HD resolution image is displayed.
  • the selection output circuit 37 (second selection output means) outputs the data enable signal DE to the delay circuit 38 when the determination signal CMP4 is at the H level, while the data enable signal DE remains unchanged when the determination signal CMP4 is at the L level. Output to the outside.
  • the selection output circuit 37 can be configured to selectively output the data enable signal DE as described above by a combination of logic circuits.
  • the delay circuit 38 delays the rising edge of the data enable signal DE output from the selection output circuit 37 by one clock of the clock signal CLK and outputs the delayed data enable signal DDE.
  • the delay circuit 38 can be configured to delay the rising edge of the data enable signal DE by one clock, for example, by a flip-flop.
  • FIG. 10 is a flowchart showing an operation procedure of the data enable signal correction unit 31.
  • FIG. 11A is a timing chart showing the operation of the data enable signal correction unit 31 when the data enable signal DE is normally output.
  • FIG. 11B is a timing chart showing the operation of the data enable signal correction unit 21 when the data enable signal DE falls later than the normal timing.
  • FIG. 11C is a timing chart showing the operation of the data enable signal correction unit 31 when the head image data DATA of one line is zero.
  • the D flip-flop 32 takes in the image data DATA in synchronization with the rising edge of the data enable signal DE (step S31).
  • the comparator 33 compares the captured image data DATA with the zero data D0, and determines whether or not the image data DATA is 0 (step S32).
  • step S32 when it is determined that the image data DATA is not 0 (NO) (the determination signal CMP3 is L level), the selection output circuit 34 outputs the data enable signal DE as it is from the line (step S33). And in order to perform operation
  • step S32 if it is determined in step S32 that the image data DATA is 0 (YES) (the determination signal CMP3 is at H level), the selection output circuit 34 outputs the data enable signal DE to the counter 35.
  • the counter 35 measures the width of the valid period by counting the clock signal CLK of the valid period in the data enable signal DE of the first line of one screen (step S34).
  • step S35 when it is determined that the count value CNT2 is not greater than 1920 (NO) (the determination signal CMP4 is at L level), the selection output circuit 37 outputs the data enable signal DE as it is for the next and subsequent lines ( Step S33). And in order to perform operation
  • step S35 determines whether the count value CNT2 is greater than 1920 (YES) (determination signal CMP4 is H level)
  • the selection output circuit 37 sends the data enable signal DE to the delay circuit 38 in the next line and thereafter. Output to.
  • the delay circuit 38 delays the rising edge of the input data enable signal DE by one clock of the clock signal CLK and outputs it (step S36). And in order to perform operation
  • step S32 it is determined that the image data DATA is not 0 (NO). Therefore, the data enable signal DE is output from the selection output circuit 34 as it is.
  • the data enable signal DE rises normally but is delayed by one clock compared to the case where the fall is normal. Sometimes. In this case, it is assumed that the leading image data DATA is not zero. In this case, in step S32, it is determined that the image data DATA is not 0 (NO). Therefore, as in the case described above, the data enable signal DE is output from the selection output circuit 34 as it is.
  • the image processing unit 4 does not recognize the image data DATA in this portion by ignoring the falling portion delayed by one clock of the data enable signal DE. Therefore, only regular image data DATA is provided for display.
  • step S32 it is determined that the image data DATA is 0 (YES). Since the count value CNT2 is 1920, it is determined in step S36 that the count value CNT2 is not greater than 1920 (NO). Therefore, in this case, the data enable signal DE is output from the selection output circuit 37 as it is.
  • step S36 it is determined that the count value CNT2 is larger than 1920 (YES). . Therefore, in this case, the delay circuit 38 delays the rising edge of the data enable signal DE by one clock and outputs the delayed data enable signal DDE.
  • FIG. 12 is a diagram illustrating an image in which a black line appears at the right end due to an error generated in the HDMI conversion unit 2.
  • the data enable signal correction unit 31 can avoid the influence of the reception error caused by the quality degradation of the TMDS signal, like the data enable signal correction units 11 and 21 described above. Therefore, the image can be displayed favorably. Therefore, similarly to the data enable signal correction unit 11, the error of the data enable signal DE generated in the HDMI conversion unit 2 can be corrected without controlling the signal source 7. Moreover, as described above, the data enable signal correction unit 31 can be configured on a relatively small scale by a digital circuit. Therefore, the enlargement of the image processing apparatus 1 can be suppressed.
  • the data enable signal correction unit 31 is superior to the data enable signal correction units 11 and 21 as follows.
  • the data enable signal correction unit 11 when the falling edge of the data enable signal DE is delayed by one clock compared with the normal case, the data enable signal correction unit 11 described above malfunctions. Specifically, since the width of the valid period of the data enable signal DE becomes larger than the reference value R1, the data enable signal correction unit 11 sets the rise of the data enable signal DE to 1 even though the rise of the data enable signal DE is normal. Delay by clock. For this reason, the first image data DATA is not recognized in the image processing unit 4, and the period of one clock (data non-existing period) following the last image data DATA is recognized as 0 (black) image data DATA. End up. As a result, as shown in FIG. 12, the liquid crystal display device 5 displays an image including a black line RBL extending in the vertical direction at the right end because it is shifted to the left by one dot.
  • the data enable signal correction unit 31 outputs the data enable signal DE shown in FIG. 11B as it is as described above.
  • the image processing unit 4 correctly recognizes all the image data DATA, so that a normal image not including the black line RBL is displayed on the liquid crystal display device 5 as shown in FIG. .
  • the data enable signal correction unit 21 malfunctions. Specifically, since the image data DATA captured at the rising edge of the data enable signal DE is zero data D0, the data enable signal correction unit 21 shifts and outputs the data enable signal DE by one clock. For this reason, the top image data DATA is not recognized in the image processing unit 4, and the above data non-existing period is recognized as the image data DATA. As a result, the image including the black line RBL is displayed on the liquid crystal display device 5 as shown in FIG.
  • the data enable signal correction unit 31 outputs the data enable signal DE shown in FIG. 11C as it is as described above.
  • the image processing unit 4 correctly recognizes all the image data DATA, so that a normal image not including the black line RBL is displayed on the liquid crystal display device 5 as shown in FIG. .
  • the data enable signal correction unit 31 measures the width of the effective period for the data enable signal DE that rises earlier by one clock shown in FIG. 4B as in the data enable signal correction unit 11. Based on the above, the rising edge is delayed by one clock.
  • the data enable signal correction unit 31 determines whether or not the data enable signal DE can be output based on the value of the head image data DATA by the data enable signal correction unit 21. In addition to this, the data enable signal correction unit 31 determines whether the data enable signal DE needs to be delayed by the data enable signal correction unit 11 based on the width of the valid period. Accordingly, the data enable signal DE shown in (b) and (c) of FIG. 11 can be properly output without causing malfunction.
  • the image processing apparatus 1 receives a data signal (image data DATA) and a valid signal (data enable DE) indicating a valid period of the data signal via an input interface (for example, the HDMI cable 8).
  • the image processing apparatus 1 includes an active period (valid period) of the valid signal and a detection unit (comparator 13, which detects at least one of the contents of the data signal (first image data DATA) obtained based on the valid signal. 23, 33, 36) and a correction unit (delay circuit 15, 38 and shift circuit 25) for correcting the phase shift of the effective signal in accordance with the detection result of the detection unit.
  • the liquid crystal display device 5 is used as a device for displaying an image, but a display device such as an organic EL display device other than the liquid crystal display device 5 may be used.
  • the data enable signal DE is a signal that activates the H level, but is not limited thereto, and may be a signal that activates the L level.
  • the data enable signal correction unit 11 delays the falling edge of the data enable signal DE by one clock of the clock signal CLK.
  • steps S11 and S12 (FIG. 3), steps S21 and S22 (FIG. 7), and steps S31 and S32 (FIG. 10) are performed on all lines in the frame.
  • the above processing may be performed only for the first line of the frame, and the output processing of the data enable signal DE may be performed for the second and subsequent lines based on the result.
  • the image processing apparatus 1 according to the present embodiment can also be expressed as follows.
  • the image processing apparatus 1 recognizes the image data obtained from the TMDS signal based on a valid signal indicating a valid period during which the image data is valid, and performs an image processing for displaying the recognized image data A processing unit; a phase shift detection unit that detects a phase shift of the start point of the effective period in the effective signal; and a phase correction unit that corrects the phase of the start point so as to eliminate the detected phase shift. ing.
  • the phase shift detection unit includes an effective period width measurement unit that measures the width of the effective period, and the effective period width is larger than a reference value corresponding to one line of the image data.
  • An effective period width determination unit that determines whether or not the phase correction unit includes a delay unit that delays the start point when it is determined that the width of the effective period is greater than the reference value. It is preferable to have.
  • the effective period width determination unit determines whether the width is larger than the reference value. If it is determined that the width of the effective period is larger than the reference value, the start point has a phase shift, so that the phase of the start point is delayed by the delay unit. Thereby, the phase of the starting point is corrected so as to eliminate the phase shift.
  • the image processing apparatus 1 When it is determined that the effective period width is larger than the reference value, the image processing apparatus 1 outputs the effective signal to the delay unit, while the effective period width is equal to or less than the reference value. It is preferable to include a selection output unit that outputs the valid signal as it is.
  • the valid signal when it is determined that the width of the valid period is larger than the reference value, the valid signal is output to the delay unit by the selection output unit. At this time, the starting point of the valid signal is delayed by the delay unit. On the other hand, when it is determined that the width of the valid period is equal to or less than the reference value, the valid signal is output as it is by the selection output unit. Thereby, when the start point has a phase shift, the phase of the start point of the effective signal is corrected, and when the start point has no phase shift, the effective signal is output as it is.
  • the phase shift detection unit includes a data value determination unit that determines whether or not the value of the image data at the start of the effective period is 0, and the phase correction unit includes: It is preferable to have a delay unit that delays the start point when it is determined that the value of the image data at the start of the effective period is zero.
  • the start point when the data value determination unit determines that the value of the image data at the start of the effective period is 0, the start point has a phase shift up to a period in which no image data exists. In this case, the starting point is delayed by the delay unit. Thereby, the phase of the starting point is corrected so as to eliminate the phase shift.
  • the image processing apparatus 1 outputs the valid signal to the delay unit when it is determined that the value of the image data at the start of the valid period is 0, while the image processing apparatus 1 outputs the valid signal at the start of the valid period. It is preferable to include a selection output unit that outputs the valid signal as it is when it is determined that the value of the image data is not zero.
  • the selection output unit when it is determined that the value of the image data at the start of the effective period is 0, the selection output unit outputs an effective signal to the delay unit. At this time, the starting point of the valid signal is delayed by the delay unit. On the other hand, when it is determined that the value of the image data at the start of the effective period is not 0, the effective signal is output as it is by the selection output unit. Thereby, when the start point has a phase shift, the phase of the start point of the effective signal is corrected, and when the start point has no phase shift, the effective signal is output as it is.
  • the phase shift detection unit includes a data value determination unit that determines whether the value of the image data at the start of the effective period is 0, and the image at the start of the effective period. When it is determined that the value of the data is 0, an effective period width measurement unit that measures the width of the effective period, and the effective period width is greater than a reference value corresponding to one line of the image data An effective period width determination unit that determines whether or not the phase correction unit includes a delay unit that delays the start point when it is determined that the width of the effective period is greater than the reference value. It is preferable to have.
  • the start point when the data value determination unit determines that the value of the image data at the start of the effective period is 0, the start point has a phase shift until a period in which no image data exists.
  • the effective period width measuring unit measures the width of the effective period of the effective signal, and the effective period width determining unit determines whether or not the width is larger than the reference value.
  • the start point is delayed by the delay unit because the start point has a phase shift. Thereby, the phase of the starting point is corrected so as to eliminate the phase shift.
  • the phase of the end point is not the phase of the start point of the effective period (see FIG. 11B), it is not necessary to correct the phase of the start point.
  • the effective period width measuring unit measures the width of the effective period of the effective signal, it is determined that the width is larger than the reference value. If the start point is delayed by the delay unit based on the determination, the image processing unit does not recognize the head of the image data, so that the image is not displayed normally. Therefore, in such a case, since the value of the image data at the start of the effective period is not determined to be 0 by performing the determination by the data value determination unit, the start point is not delayed. Therefore, it is possible to prevent a malfunction that the start point is delayed although the phase of the start point is appropriate.
  • the start point is delayed by the delay unit. Then, since the head of the image data is not recognized by the image processing unit, the image is not displayed normally. Therefore, in such a case, the effective period width of the effective signal is measured by the effective period width measurement unit, and it is further determined whether or not the effective period width is larger than the reference value. Thereby, since it is determined that the width of the effective period is equal to or less than the reference value, the start point is not delayed. Therefore, it is possible to prevent a malfunction that the start point is delayed although the phase of the start point is appropriate.
  • the image processing apparatus 1 When it is determined that the value of the image data at the start of the effective period is 0, the image processing apparatus 1 outputs the effective signal to the effective period width measurement unit, while starting the effective period When it is determined that the value of the image data at time is not 0, the first selection output unit that outputs the effective signal as it is, and when it is determined that the width of the effective period is larger than the reference value, A second selection output unit that outputs the valid signal as it is when the valid signal is output to the delay unit and the width of the valid period is determined to be equal to or less than the reference value. preferable.
  • the first selection output unit when it is determined that the value of the image data at the start of the effective period is 0, the first selection output unit outputs an effective signal to the delay unit. At this time, the starting point of the valid signal is delayed by the delay unit. On the other hand, when it is determined that the value of the image data at the start of the effective period is not 0, the effective signal is output as it is by the first selection output unit. For example, as described above, when not the start point of the valid period but the end point has a phase shift, the delay of the start point is unnecessary, and the valid signal is output as it is.
  • the valid signal is output to the delay unit by the second selection output unit. At this time, the starting point of the valid signal is delayed by the delay unit.
  • the valid signal is output as it is by the second selection output unit. For example, as described above, when the value of the image data at the start of the effective period is intentionally set to 0, and the start point does not have a phase shift, the start point is not required to be delayed. Is output as is.
  • the phase of the start point is corrected, and when the start point has no phase shift, the valid signal is output as it is.
  • Any one of the image processing apparatuses 1 described above preferably includes a display device that displays the image data output from the image processing unit.
  • the display device is preferably a liquid crystal display device.
  • the display device and the liquid crystal display device are based on the image data processed by the image processing unit.
  • the image can be displayed normally.
  • the image processing apparatus can be suitably used in combination with a liquid crystal display device or the like for displaying high-definition video.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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Abstract

La présente invention se rapporte à un appareil de traitement d'image comprenant un convertisseur HDMI (2) : qui convertit un signal TMDS provenant d'une source de signal (7) au niveau d'un CMOS ; qui délivre en sortie des données d'image ; et qui délivre également en sortie un signal d'horloge ainsi qu'un signal d'activation de données représentatif d'une période où des données d'image pour un traitement d'image sont valides (une période efficace). L'appareil de traitement d'image selon la présente invention comprend d'autre part un module de correction de signal d'activation de données (3) qui détecte un décalage (décalage de phase) dans la phase, lors de la montée du signal d'activation de données délivré en sortie par le convertisseur HDMI (2) (le point de début de la période efficace), par rapport à la phase normale. Le module de correction de signal d'activation de données (3) délivre en sortie le signal d'activation de données, sans le modifier, quand aucun décalage de phase n'est détecté lors de la montée du signal d'activation de données. Par contre, il corrige la phase de montée de la façon appropriée, avant de délivrer en sortie le signal d'activation de données, quand un décalage de phase est détecté lors de la montée du signal d'activation de données.
PCT/JP2012/062433 2011-05-18 2012-05-15 Appareil de traitement d'image WO2012157650A1 (fr)

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WO2004107750A1 (fr) * 2003-05-28 2004-12-09 Matsushita Electric Industrial Co., Ltd. Appareil recepteur d'interface numerique
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JP2004056373A (ja) * 2002-07-18 2004-02-19 Matsushita Electric Ind Co Ltd 信号遅延調節方法および装置
WO2004107750A1 (fr) * 2003-05-28 2004-12-09 Matsushita Electric Industrial Co., Ltd. Appareil recepteur d'interface numerique
JP2005260462A (ja) * 2004-03-10 2005-09-22 Sharp Corp 遅延検出装置および遅延調整装置
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JP2015204513A (ja) * 2014-04-14 2015-11-16 ザインエレクトロニクス株式会社 送信装置、受信装置および送受信システム
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