WO2012152364A1 - Substrat doté d'une zone électriquement neutre - Google Patents

Substrat doté d'une zone électriquement neutre Download PDF

Info

Publication number
WO2012152364A1
WO2012152364A1 PCT/EP2012/001665 EP2012001665W WO2012152364A1 WO 2012152364 A1 WO2012152364 A1 WO 2012152364A1 EP 2012001665 W EP2012001665 W EP 2012001665W WO 2012152364 A1 WO2012152364 A1 WO 2012152364A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
substrate according
electrically
semiconductor element
Prior art date
Application number
PCT/EP2012/001665
Other languages
German (de)
English (en)
Inventor
Albert Heilmann
Roland Reul
Andreas Klein
Michael Schäfer
Stefan Malkmus
Frank Krüger
Eckhard Ditzel
Wolfgang Schmitt
Tanja Eckardt
Albert Kastner
Thomas Scholl
Original Assignee
Heraeus Materials Technology Gmbh & Co. Kg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Heraeus Materials Technology Gmbh & Co. Kg filed Critical Heraeus Materials Technology Gmbh & Co. Kg
Publication of WO2012152364A1 publication Critical patent/WO2012152364A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/641—Heat extraction or cooling elements characterized by the materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0075—Processes relating to semiconductor body packages relating to heat extraction or cooling elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/642—Heat extraction or cooling elements characterized by the shape
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10106—Light emitting diode [LED]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10969—Metallic case or integral heatsink of component electrically connected to a pad on PCB

Definitions

  • the invention relates to a substrate for receiving at least one electronic element, in particular at least one semiconductor element.
  • the invention also relates to an electronic component, in particular a semiconductor component, comprising at least one semiconductor element and such a substrate as well as a method for producing such a substrate.
  • Components such as integrated circuits are often applied in layers to substrates in order to achieve a compact design. Due to the compact design, different interconnections and components, such as chips and LEDs can be realized in a small space.
  • the semiconductor elements must be contacted in a small space to supply the semiconductor element with a voltage.
  • a semiconductor component in which a contact is arranged on both sides in order to supply the integrated semiconductor element with a voltage.
  • the semiconductor element comprises a plurality of layers, here a plurality of differently doped semiconductor layers.
  • the structure is supported by two electrical terminals that are electrically separated from each other by a distance.
  • One of the contacts is connected to an electrically conductive adhesive or a solder directly to one of the electrical connections.
  • the other contact is connected via a bonding wire to the other electrical connection.
  • a disadvantage of this is that at a high power consumption of the semiconductor element, the electrical power converted by the semiconductor element must be dissipated as heat in order to create stable working conditions for the semiconductor element or to prevent it being destroyed.
  • a cooling device must be attached to the semiconductor device, but this reduces the advantage of the small size of the semiconductor element.
  • a substrate for receiving an electronic element in which an electrically conductive layer is provided for electrical contacting of the element.
  • an electrically insulating connection layer is arranged, which connects a substrate body made of metal with the electrically conductive layer.
  • the bonding layer is composed of a matrix formed of a preceramic polymer.
  • the disadvantage of this is that the structure of the matrix is complicated and the matrix formed is not homogeneous. This can cause the formed substrate to be mechanically unstable and the heat conduction through the substrate to be uneven and thereby limited. For many applications, the cooling by the substrate is not enough.
  • a further disadvantage is that the matrix ages too rapidly in blue and ultraviolet light, so that use of the substrate with many, in particular white LEDs as elements is unfavorable or at least leads to a short lifetime of the manufactured components.
  • the preceramic material for building the ceramic matrix must be processed at high temperatures, whereby the substrate is thermally stressed and the choice of materials for the substrate is limited. Namely, the reaction pyrolysis for converting the preceramic material into a ceramic matrix is usually carried out at temperatures between 800 ° C and 1600 ° C.
  • any interlayer is a thermal resistance and therefore undesirable. If the materials are matched, they are severely limited in their choice, especially as they must also be temperature-stable. Many materials, especially the metals used, very particularly thin layers thereof, are not stable under oxidizing atmosphere at high temperatures, so that either these materials can not be used, or the structure of the substrate has to be carried out under protective gas.
  • the object of the invention is therefore to overcome the disadvantages of the prior art.
  • a stable substrate is to be provided which has an effective cooling effect. an element attached to it.
  • safer process management for fabricating the substrate is also desirable, as is lesser waste in fabricating the substrate.
  • a lower necessary temperature in building the substrate would also be advantageous.
  • the substrate or the semiconductor device is easy to install.
  • the application of the semiconductor devices on boards or the installation in electrical circuits on a circuit board or circuit board should be particularly easy to perform. Improving the cooling performance through the substrate would also allow for further miniaturization of power devices. It is also intended to provide a substrate for electronic elements having an electrically neutral region.
  • the materials used do not age too fast by blue light or ultraviolet light.
  • a substrate for accommodating at least one electronic element, in particular at least one semiconductor element comprising an electrically conductive first layer for contacting the element, a thermally conductive second layer for dissipating heat from the element and an electrically insulating third layer between the first layer and the second layer is arranged such that the third layer electrically isolates the first layer from the second layer, wherein the third layer is a thin layer.
  • a thin film is a layer of a solid in the micrometer or even nanometer range.
  • the separation of the first and second layers by a thin layer allows a variety of new technical possibilities.
  • the thermal resistance is significantly reduced and on the other hand, other materials can be used, which would be out of the question as thick film.
  • the material of the third layer can be matched to the materials of the first and second layer, thus achieving a further improvement in the thermal conductivity and / or the mechanical stability of the substrate.
  • An element is a chip and / or partially differently doped semiconductor, which are contacted as electronic functional elements by the substrate.
  • the electronic element incorporated in the substrate together form a component according to the invention ready for use in circuits on boards or printed circuit boards can be installed.
  • a component thus differs from an element in the sense of the present invention in that the component comprises the substrate and an element contacted with the substrate, such as an integrated circuit on a chip.
  • a built-in element is to be understood as an element applied to the first layer of the substrate, that is to say adhesively bonded, soldered or similarly mechanically fastened and contacted. The installation takes place in such a way that the electronic element can fulfill its function.
  • the thickness of the third layer is less than 10 ⁇ m, preferably less than 5 ⁇ m, particularly preferably less than 2 ⁇ m.
  • electrical insulators with average or even low heat conduction may also be used as materials for the third layer.
  • the third layer is applied to the first layer by sputtering, vapor deposition, physical vapor deposition (PVD) or chemical vapor deposition (CVD).
  • These coating methods are particularly suitable for applying the third layer to the first layer as a thin layer.
  • the coupling to the first layer is particularly good in these methods and thus the thermal resistance of the interface is particularly low.
  • the third layer of AIN or Al 2 0 3 consists.
  • these two materials have a particularly good thermal conductivity and good electrical insulation properties for an insulator and are therefore particularly preferred.
  • aluminum alloys and aluminum (Al) are particularly suitable as the first and / or second layer, especially due to their electrical and mechanical properties and machinability and availability, with a particularly good, mechanically stable compound with AIN or Al 2 0 3 produced on such layers leaves. Due to the interface properties of these materials and on AI or Al alloys anyway always present Oxide layer, the interfaces of these materials lead to a particularly low thermal resistance.
  • a substrate for receiving at least one electronic element comprising an electrically conductive first layer for contacting the element, a thermally conductive second layer for dissipating heat from the element and an electrically insulating third layer, disposed between the first layer and the second layer, such that the third layer electrically isolates the first layer from the second layer, wherein the third layer is a glass-ceramic.
  • the use of a glass ceramic is especially preferred because of its homogeneity and the resulting uniform heat conduction.
  • the glass ceramic can be done for example by lamination of a glass-ceramic inlay.
  • the glass ceramic or the inlay can be, for example, a low-temperature cofired ceramic (LTCC), a high-temperature cofired ceramic (HTCC) or an AIN ceramic.
  • the third layer is applied to the first layer by a printing process, in particular a screen printing process, and baked in the substrate, preferably melted onto the first layer.
  • the glass-ceramic layer can be applied particularly easily and quickly.
  • the firing or melting improves the homogeneity of the third layer, in particular with respect to the uniformity of the thickness of the glass-ceramic layer, and produces a stable connection to the first and / or second layer.
  • the object of the invention is further achieved by a substrate for receiving at least one electronic element, in particular at least one semiconductor element, comprising an electrically conductive first layer for contacting the element, a heat-conducting second layer for dissipating heat from the element and an electrically insulating third layer, disposed between the first layer and the second layer so that the third layer electrically isolates the first layer from the second layer, wherein the third layer is a ceramic powder-filled polymer matrix.
  • the third layer is a ceramic powder-filled polymer matrix.
  • the polymer of the polymer matrix is a silicone or a resin, preferably an epoxy resin, acrylic resin, silicone resin, particularly preferably silicone solid ® or a silicone-polyester resin and / or the ceramic powder is an Al 2 0 3 powder, an AIN powder and / or a BN (boron nitride) powder.
  • the third layer may further be provided that in the polymer matrix, a plurality of spacers are provided, so that the third layer has a defined and uniform thickness, which is determined by the thickness of the Spacer is given, wherein the spacers are in particular spherical and preferably made of glass, Si0 2 glass, Al 2 0 3 , AIN, BN and / or SiN.
  • spacers which are preferably formed as ceramic and / or glass beads
  • a uniform thickness of the third layer can be ensured even in difficult production conditions. For example, uneven pressure on the second layer, which can easily occur in mass production, does not affect the third layer to become unevenly thick.
  • a sufficient number of spacers must be provided in the polymer matrix. A sufficient number may for example be three to one hundred spacers, preferably three to eight spacers per substrate. If the spacers are mixed into the raw material (polymer, possibly also already mixed with the ceramic powder) prior to the application of the third layer, the density should be selected such that statistically at least three spacers are contained in every third layer.
  • the second layer is metallic or comprises a metal core.
  • Metals have a particularly good heat conduction, therefore, the use of a metal is particularly preferred.
  • aluminum (AI) or copper (Cu) or aluminum or copper alloys are particularly preferred as metal for the second layer due to their particularly high thermal conductivity.
  • the third layer and the second layer are arranged in a depression of the first layer and the third layer covers the first layer and the second layer at least partially covers the third layer in the depression.
  • the thickness of the third layer and the second layer together corresponds to the depth of the depression, so that the surface of the second layer lies in a, in particular planar plane with the first layer outside the depression.
  • the recess protects the second and especially the third layer.
  • a planar construction of the substrate on the bottom also leads to an easy installation of the substrate according to the invention or the substrate according to the invention with built-in element (of the manufactured component). As a result, a mass production of circuits with such substrates or components is greatly simplified.
  • a further embodiment of the invention provides substrates in which the second layer is bonded to the third layer by PVD, sputtering, lamination, gluing, soldering, low-temperature silver sintering or a printing process, in particular a screen printing process.
  • the second layers produced by these methods meet different requirements for use in mass production, the mechanical stability of the substrate and the thermal conductivity of the substrate, that is, the achievable with the substrate cooling performance for an applied to the substrate element.
  • the third layer only partially covers the first layer and / or the second layer only partially covers the third layer. This construction can ensure that no electrically conductive connection between the first and second layer is formed. The electrically neutral region created by the third layer is necessary to prevent or degrade the electronic circuitry of the device.
  • the first layer is subdivided into two regions which are electrically insulated from one another, so that the element can be contacted with the two regions.
  • the regions of the first layer are electrically insulated from each other by a recess in the first layer.
  • an electrical voltage can be applied to the element over the regions.
  • the third layer has a thermal conductivity of more than 5 W / m K, preferably more than 30 W / m K, more preferably more than 100 W / m K.
  • Such high thermal conductivities enable a strong cooling performance of the elements used in the substrate according to the invention and thus a high possible power consumption of the elements.
  • the third layer is homogeneous, in particular consists of only one solid material.
  • the homogeneity simplifies the manufacturability of the third layer and leads to an improvement in the thermal conductivity of the transition into the second layer for cooling the element.
  • the handling of the substrate is improved if it is provided that a carrier film, in particular a plastic film, is arranged on the first layer.
  • the carrier film is arranged on the, the third layer opposite side.
  • the carrier film comprises openings for each element. It can also be provided that the carrier film comprises one or two additional openings for each element.
  • the additional openings are arranged in a different area of the first layer than the area of the opening for the element. This can be realized in a partially divided first layer.
  • the carrier film facilitates the construction and thus the production of the substrate, provides additional stabilization and protection of the substrate.
  • the openings also mark the positions where elements can be inserted and to which bonding wires can be applied and thus facilitate the usability of a substrate according to the invention.
  • the object of the invention is also achieved by an electronic component, in particular semiconductor component comprising at least one semiconductor element and a substrate according to the invention, wherein the semiconductor element is electrically conductively connected on a first side with the first layer, preferably via a solder, a conductive adhesive or a silver sintered compound.
  • Semiconductor elements in particular power semiconductor elements, can be used particularly well together with substrates according to the invention.
  • the surface contact facilitates the transfer of heat from the element into the first layer and then into the third and second layer.
  • the at least one semiconductor element is contacted on a second side via a bonding wire with the first layer, so that an electrical voltage between the first and second sides of the semiconductor element can be applied, wherein the first layer is divided into at least two areas and the two sides of the semiconductor element are connected to different regions of the first layer.
  • the electronic component and the semiconductor element of the component are then particularly easy contacted by the substrate.
  • Electronic components according to the invention can be distinguished by the fact that the at least one semiconductor element is a chip or an LED.
  • Chips and LEDs often convert a lot of electrical power and are therefore particularly well suited as semiconductor elements for electronic components according to the invention.
  • Stability of inventive third layers against blue or ultraviolet light particularly suitable when using LEDs, especially white LEDs as semiconductor elements.
  • a heat sink is arranged on the second layer, preferably a metallic heat sink, particularly preferably an aluminum substrate.
  • the first layer is connected to a metallization of a printed circuit board on a dielectric and preferably the second layer is connected in a recess of the dielectric with an underlying metallic substrate.
  • the object of the invention is also achieved by a method for producing a substrate according to the invention, wherein on a first electrically conductive layer a third electrically insulating layer by sputtering, vapor deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), laminating, gluing, soldering or a printing method, in particular a screen printing method, is applied and that a second heat-conducting layer by PVD, sputtering, lamination, gluing, soldering, low-temperature silver sintering or a printing method, in particular a screen printing method, is applied to the third layer such that the second layer with the first layer has no electrical contact.
  • a third electrically insulating layer by sputtering, vapor deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), laminating, gluing, soldering or a printing method, in particular a screen printing method, is applied and that a second heat-conducting
  • At least one recess is produced in the first layer, preferably by embossing, profile rolling or milling, wherein the third layer is applied to the first layer in the region of the depression.
  • the invention is based on the surprising finding that it is possible by the use of a thin film or a glass ceramic as an insulating layer, a homogeneous provide electrically insulating separation layer, which allows a uniform heat conduction into the second layer and thus allows a uniform and efficient cooling of the electronic element.
  • thermal conduction causes scattering of the lattice vibrations (phonons) at the interfaces of the various materials of the composite.
  • the use of thin layers or glass ceramics according to the invention provides a homogeneous third layer, through which the lattice vibrations or the phonons can propagate without scattering at interfaces within the electrical insulator.
  • the thermal resistance of the insulator is reduced.
  • the reduction of the thermal resistance leads to a greater cooling of the built-in substrate electronic element.
  • elements with a larger electrical power can be installed in a smaller space.
  • the invention is based on the surprising finding that, when using a polymer matrix with ceramic powder as the third layer, a lower temperature can be selected in the construction of the third layer than in the production of a ceramic matrix from a preceramic material.
  • a lower temperature can be selected in the construction of the third layer than in the production of a ceramic matrix from a preceramic material.
  • the production of the substrate can be carried out at lower temperatures, which brings advantages with respect to the devices for machining the substrate.
  • the production rate in mass production is significantly increased.
  • the substrate is exposed to a lower thermal stress, whereby the third layer can be thinner and the durability of the substrate is improved or the rejects during production is reduced.
  • the thinner such a third layer according to the invention the lower its thermal resistance and the greater the cooling power can be achieved by such a third layer.
  • a thin-film technique requires the use of a homogeneous material, since the structure of a matrix requires a certain volume and thus a minimum thickness of at least 10 ⁇ , usually well above 10 m. Therefore, the use of a thin film was surprising. Since the thermal resistance of such a layer is also determined by its thickness, the reduction of the layer thickness per se already leads to an improvement of the prior art according to the invention.
  • the homogeneity of the glass ceramic layer is particularly high when the glass ceramic is melted or slightly melted during the firing on the first layer. By the melting process a uniform flat layer thickness is achieved and thus a uniform heat dissipation from the element.
  • Another inventive advantage of a glass ceramic plain and also certain thin layers, for example of AIN, can be seen in their light resistance.
  • various materials, such as the organic materials used in the prior art are not stable to light in the visible blue spectrum and in the ultraviolet (UV) range. This limits the use in daylight and makes the use of the substrate in the use of LEDs as elements, in particular white LEDs impossible or at least leads to the fact that the use of such substrates draws considerable disadvantages.
  • the blue and the UV light lead to embrittlement or discoloration of the third layer.
  • the substrates according to the invention are thus particularly suitable for use with LEDs as elements.
  • the glass-ceramic layer also causes a corrosion protection for the surfaces of the first and / or second layer. This is especially true when the third layer is briefly melted or slightly melted, as then can create a particularly dense connection without inclusions.
  • substrates according to the invention are the low material costs, since the low cost of expensive materials such as AIN, the costs can be reduced.
  • the modules / components produced can be separated more easily from a manufactured carrier tape. The lifetime of the manufactured components is improved by a better balance of the thermal expansion coefficients of the layers.
  • FIG. 1 shows a schematic cross-sectional view of a first component according to the invention with a first substrate according to the invention
  • FIG. 2 shows a schematic cross-sectional view of a second component according to the invention with a second substrate according to the invention
  • FIG. 3 shows a schematic cross-sectional view of a third component according to the invention with a third substrate according to the invention
  • FIG. 4 shows a schematic cross-sectional view of a fourth component according to the invention with a substrate according to the invention, connected to a printed circuit board;
  • FIG. 5 shows a perspective true-to-scale view of a component according to the invention on a substrate according to the invention.
  • FIG. 6 shows a perspective view of a component according to the invention on another substrate according to the invention.
  • FIG. 1 shows a schematic cross-sectional view of an electronic component 1 according to the invention with a substrate according to the invention.
  • the substrate comprises a first layer 2 of a base metal foil, a second layer 3 which is a metallization and a third layer 4 of a dielectric arranged between the first layer 2 and the second layer 3.
  • a recess 5 for the electrical separation of two regions of the first layer 2 is provided in the first layer 2.
  • the substrate also comprises a carrier film 6 made of plastic.
  • a first recess 7 is provided, in which a semiconductor element 8 is contacted with a solder 9, a conductive adhesive 9 or a silver sintered compound 9 with a first region of the first layer 2 of the substrate.
  • the semiconductor element 8 can be supplied with current by applying a voltage.
  • the electrical power consumed in the semiconductor element 8 is converted to a large extent into heat energy. In order that the performance of the semiconductor element 8 is maintained and the semiconductor element 8 is not destroyed or can operate under uniform conditions, it is necessary to remove the heat from the semiconductor element 8.
  • the second layer 3 which is separated from the first region of the first layer 2 by the dielectric of the third layer 4, there is a metallic, ie good heat-conducting, electrical neutral range available over which the device 1 and the semiconductor element 8 can be cooled.
  • the thin dielectric layer 4 causes only a low thermal resistance during the transition from the first metallic layer 2 to the second metallic layer 3.
  • FIG. 2 shows a schematic view of a second electronic component 11 according to the invention with a slightly modified construction compared to that shown in FIG.
  • the modification relates to the substrate according to the invention, more precisely the first layer 2 of the substrate.
  • this first layer 2 which consists for example of an aluminum alloy
  • a recess 12 is provided which receives the second layer 3, which consists for example of a glass ceramic, and the third layer 4, which consists for example of aluminum.
  • the depression 12 is produced by embossing, profile rolling and / or milling in the first layer 2.
  • the first layer is laminated with a carrier film 6 made of plastic.
  • the third layer 4 is applied by gluing and then the second layer 3 by soldering.
  • the recess 5 is produced in the first layer 2 and thus two mutually electrically insulated regions of the first layer 2 are formed.
  • the lamination of the plastic carrier film 6 with the first layer 2, the production of the recesses 7 in the plastic carrier film 6 and the production of the recess 12 in the first layer 2 can be carried out in one step by a punch-laminating technique.
  • the substrate produced in this way can be heated in a further step in order to produce a uniform connection of the glass ceramic 4 with the metal layers 2, 3. If the temperature is too high for the plastic carrier film 6, it is expedient to apply this to the first metal layer 2 only after this temperature treatment.
  • the underside of the semiconductor element 8 is contacted with the first region of the first metal layer 2.
  • the upper side of the semiconductor element 8 is contacted via a bonding wire 10 with the second region of the first metal layer 2.
  • the substrate or the component 11 has a bottom, which lies at a height or in a plane.
  • the substrate can be easily applied to flat circuit boards or printed circuit boards.
  • the two regions of the first layer 2 form the electrodes of the electronic component 11.
  • the second layer 3 forms an electrically neutral region, which is directly below of the semiconductor element 8 is arranged and via which the heat can be dissipated from the semiconductor element 8.
  • FIG. 3 shows a schematic view of a third electronic component 21 according to the invention with a modified construction compared to FIG.
  • a first layer 2 is here divided by recesses 5 in three areas which are electrically isolated from each other.
  • the two outer regions of the first layer 2 could also be connected to one another electronically.
  • a single recess 5 would be suitable if it is shaped correspondingly in the third dimension (in the image depth of FIG. 3).
  • the middle region of the first layer 2 is thinner than the two outer regions.
  • the third layer 4 and below the second layer 3 are arranged on the underside thereof.
  • the thickness of the second and third layers 3, 4 together with the first layer 2 in the middle region is the same as the thickness of the first layer 2 in the outer regions.
  • the third layer 4 can be, for example, a polymer matrix such as an epoxy resin, in which a ceramic powder, such as, for example, aluminum nitride (AIN) is embedded.
  • the grain size of the ceramic powder may, according to the invention, be between 0.1 ⁇ m and 10 ⁇ m, preferably between 0.5 ⁇ m and 5 ⁇ m.
  • the third layer 4 is applied to the first layer 2 by a printing process.
  • a carrier film 6 is arranged, which connects the regions of the first layer 2 to one another and carries the entire substrate structure together with the first layer 2.
  • recesses 7 are provided in the carrier film 6 .
  • an electronic element 8 such as a semiconductor transistor is arranged in the middle recess 7.
  • the electronic element 8 is soldered on its underside to the middle region of the first layer 2 with a solder 9.
  • this is connected with two bonding wires 10 to the two outer regions of the first layer 2.
  • the bonding wires 10 extend through the outer recesses 7 in the carrier film 6.
  • FIG. 4 shows, in a schematic cross-sectional view, a component according to the invention, as in FIG. 1, which is constructed on a printed circuit board.
  • the electronic component according to FIG. 4 is provided with its first layer 2 on the outside via a solder 33 with conductor tracks 34, ie with connected to the metallizations 34 of a printed circuit board.
  • the metallizations 34 are arranged on a dielectric 35 on the upper side of the printed circuit board.
  • the interior of the circuit board is a metallic heat sink 36, which consists for example of copper or aluminum.
  • the underside of the circuit board is also covered by a dielectric 35.
  • a recess is provided, through which the second layer 3 is connected to the heat sink 36.
  • the second layer 3 and the heat sink 36 are soldered together with a solder 33.
  • the arrows in FIG. 4 show the heat flow from an electronic element 8 of the electronic component, for example from a high-power LED, through a conductive adhesive 9, through the first layer 2, the third layer 4, the second layer 3 and the metallic solder 33 in the heat sink 36, where the heat is dissipated to all sides.
  • the heat sink 36 is generally designed substantially thicker than the component, or the first layer 2. Figure 4 is therefore not to be regarded as a true to scale drawing.
  • FIG. 5 shows a perspective, true-to-scale view of a component 41 according to the invention on a substrate according to the invention.
  • the substrate comprises a metallic first layer 42, 42 'on the underside of which is arranged in a recess 52 a second metallic layer 43, which is electrically separated from the first metallic layer 42, 42' by a dielectric thin film 44.
  • the first layer 42, 42 ' is separated by a recess 45 into a first region 42 and a second region 42'.
  • the two areas 42, 42 ' are electrically isolated from each other.
  • a carrier film 46 made of PET is glued on.
  • a thickening of the first layer 42 in the first region 42 is sufficient due to a larger recess in the carrier film 46.
  • a further recess 47 in the carrier film 46 is provided above the second region 42 '.
  • an electronic element 48 is arranged, which is connected over a large area electrically and thermally conductive with the first region 42 of the first layer 42, 42'.
  • On the top of the electronic element 48 is a contact 57, via which the electronic element 48 can be supplied with electrical energy.
  • a bonding wire 50 connects the contact 57 with the second region 42 'of the first layer 42, 42'.
  • the electronic element 48 is supplied with electrical energy.
  • the electronic element 48 converts the electrical energy, for example, by generating light, wherein also heat is created.
  • the component 41 can be fastened to a printed circuit board (not shown) which, in addition to the two metal terminals (metallizations) for supplying voltage, also comprises a metallic cooling connection, which is electrically insulated from the live parts.
  • the current-carrying conductor tracks are contacted with the two areas 42, 42 'of the first metallic layer 42, 42', while the cooling connection is connected to the second metallic layer 43.
  • the latter compound should be large and continuous in order to achieve good heat conduction between the second metallic layer 43 and the heat sink.
  • a good connection can be achieved for example by soldering, welding or cold welding.
  • the heat from the electronic element 48 then flows through the first region 42 of the first layer 42, 42 ', through the dielectric thin film 44, and the second metallic layer 43 into the cooling port of the circuit board where the heat is dissipated.
  • FIG. 6 shows a perspective view of a component according to the invention on a further substrate according to the invention.
  • the substrate comprises an embossed first layer 42 42 'of aluminum.
  • a thin, insulating AIN layer 44 has been vapor-deposited, on which a thin metallic layer 43 has been vapor-deposited.
  • the vapor deposition can be carried out by a PVD process such as sputtering or a CVD process.
  • Recesses 45 are provided in the first layer 42, 42 ', subdividing the first layer 42, 42' into a first region 42 and a second region 42 ', which are electrically insulated from one another.
  • the recesses may also be filled with an electrically insulating material to increase the stability of the substrate.
  • the substrate comprises a carrier foil 46, which has a recess in the region of the extent of the first layer 42 or the second metallic thin layer 43, through which the expression with the AIN layer 44 and the metallic thin layer 43 extends.
  • the material of the metallic thin film 43 can be matched to the material of the heat sink (not shown) which is used for cooling the component shown.
  • an electronic element 48 such as a chip or an LED.
  • a contact 57 is provided, which by means of a bonding wire 50 the top of the electronic element 48 connects to the second region 42 'of the first layer 42, 42'.
  • the structure of the substrate continues, so that a multiplicity of electronic elements 48 are thereby connected in series.
  • the series connection of the electronic elements 48 succeeds only if they can be effectively cooled, as is possible in the present case by the electrically neutral connection with the metallic thin film 43.
  • the illustrated first layers 2, 42, 42 ' can be produced with a stamped circuit board technology (SCB technology).
  • a dielectric 4, 44 is then applied to or below it, onto which in turn a conductive layer (metallization) 3, 43 for further contact is applied to a heat sink 36 or to a metal core circuit board 34, 35, 36.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Led Device Packages (AREA)

Abstract

L'invention concerne un substrat pour recevoir au moins un élément électronique, notamment au moins un élément semi-conducteur, comprenant une première couche électro-conductrice pour la mise en contact de l'élément, une deuxième couche thermo-conductrice pour dissiper la chaleur de l'élément et une troisième couche électriquement isolante qui est disposée entre la première couche et la deuxième couche, de telle façon que la troisième couche assure l'isolement électrique entre la première couche et la deuxième couche, la troisième couche étant une mince couche ou une vitrocéramique ou une matrice polymère remplie d'une poudre céramique. L'invention concerne également un composant électronique, notamment un composant semi-conducteur, comprenant au moins un élément semi-conducteur et un tel substrat, le composant semi-conducteur étant relié, sur toute la surface d'une première face, de manière électro-conductrice avec la première couche, de préférence par l'intermédiaire d'un métal d'apport de soudage, d'une colle conductrice ou d'une liaison de frittage d'argent, ainsi qu'un procédé de production d'un tel substrat, une troisième couche électriquement isolante étant appliquée sur une première couche électro-conductrice par pulvérisation cathodique, évaporation sous vide, dépôt physique en phase vapeur (PVD), dépôt chimique en phase vapeur (CVD), laminage, collage, brasage ou un procédé d'impression, notamment un procédé de sérigraphie; et une deuxième couche thermo-conductrice étant appliquée sur la troisième couche par PVD, pulvérisation cathodique, laminage, collage, brasage, un procédé de frittage d'argent basse température ou un procédé d'impression, notamment un procédé de sérigraphie, de telle façon que la deuxième couche n'a aucun contact électrique avec la première couche.
PCT/EP2012/001665 2011-05-09 2012-04-18 Substrat doté d'une zone électriquement neutre WO2012152364A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE201110101052 DE102011101052A1 (de) 2011-05-09 2011-05-09 Substrat mit elektrisch neutralem Bereich
DE102011101052.5 2011-05-09

Publications (1)

Publication Number Publication Date
WO2012152364A1 true WO2012152364A1 (fr) 2012-11-15

Family

ID=46046092

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2012/001665 WO2012152364A1 (fr) 2011-05-09 2012-04-18 Substrat doté d'une zone électriquement neutre

Country Status (2)

Country Link
DE (1) DE102011101052A1 (fr)
WO (1) WO2012152364A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016102588A1 (de) * 2016-02-15 2017-08-17 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines Anschlussträgers, Anschlussträger, optoelektronisches Bauelement mit einem Anschlussträger und Verfahren zur Herstellung eines optoelektronischen Bauelements
US10939563B2 (en) 2016-09-27 2021-03-02 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Flame retardant structure for component carrier

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102013202542A1 (de) * 2013-02-18 2014-09-18 Heraeus Materials Technology Gmbh & Co. Kg Substrat zur Herstellung einer LED und Verfahren zu dessen Herstellung
EP2979783A1 (fr) * 2014-07-28 2016-02-03 Heraeus Deutschland GmbH & Co. KG Procédé de liaison de composants par frittage sous pression
DE102016100320A1 (de) 2016-01-11 2017-07-13 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement, optoelektronisches Modul und Verfahren zur Herstellung eines optoelektronischen Bauelements
DE102016121510A1 (de) * 2016-11-10 2018-05-17 Osram Opto Semiconductors Gmbh Leiterrahmen, optoelektronisches Bauelement mit einem Leiterrahmen und Verfahren zur Herstellung eines optoelektronischen Bauelements
DE102020106521A1 (de) 2020-03-10 2021-09-16 Rogers Germany Gmbh Elektronikmodul und Verfahren zur Herstellung eines Elektronikmoduls

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19625622A1 (de) 1996-06-26 1998-01-02 Siemens Ag Lichtabstrahlendes Halbleiterbauelement mit Lumineszenzkonversionselement
US5766740A (en) * 1995-05-26 1998-06-16 Sheldahl, Inc. Adherent film with low thermal impedance and high electrical impedance used in an electronic assembly with a heat sink
US5857767A (en) * 1996-09-23 1999-01-12 Relume Corporation Thermal management system for L.E.D. arrays
US20030057573A1 (en) * 2001-09-26 2003-03-27 Kabushiki Kaisha Toshiba Semiconductor device
US20040079957A1 (en) * 2002-09-04 2004-04-29 Andrews Peter Scott Power surface mount light emitting die package
US20040135156A1 (en) * 2003-01-06 2004-07-15 Sharp Kabushiki Kaisha Semiconductor light emitting device and fabrication method thereof
US20040222516A1 (en) * 2003-05-07 2004-11-11 Ting-Hao Lin Light emitting diode bulb having high heat dissipating efficiency
US20060011928A1 (en) * 2002-06-26 2006-01-19 Osram Opto Semiconductors Gmbh Surface-mountable light-emitting diode and/or photodiode and method for the production thereof
US20060124953A1 (en) * 2004-12-14 2006-06-15 Negley Gerald H Semiconductor light emitting device mounting substrates and packages including cavities and cover plates, and methods of packaging same
US20080048204A1 (en) * 2006-07-28 2008-02-28 Sharp Kabushiki Kaisha Semiconductor light-emitting element assembly
EP2109156A1 (fr) * 2007-01-30 2009-10-14 Denki Kagaku Kogyo Kabushiki Kaisha Unité de source lumineuse del
DE102008044847A1 (de) * 2008-08-28 2010-03-04 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement
DE102009000882A1 (de) 2009-02-16 2010-08-26 Semikron Elektronik Gmbh & Co. Kg Substrat zur Aufnahme mindestens eines Bauelements und Verfahren zur Herstellung eines Substrats

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5766740A (en) * 1995-05-26 1998-06-16 Sheldahl, Inc. Adherent film with low thermal impedance and high electrical impedance used in an electronic assembly with a heat sink
DE19625622A1 (de) 1996-06-26 1998-01-02 Siemens Ag Lichtabstrahlendes Halbleiterbauelement mit Lumineszenzkonversionselement
US5857767A (en) * 1996-09-23 1999-01-12 Relume Corporation Thermal management system for L.E.D. arrays
US20030057573A1 (en) * 2001-09-26 2003-03-27 Kabushiki Kaisha Toshiba Semiconductor device
US20060011928A1 (en) * 2002-06-26 2006-01-19 Osram Opto Semiconductors Gmbh Surface-mountable light-emitting diode and/or photodiode and method for the production thereof
US20040079957A1 (en) * 2002-09-04 2004-04-29 Andrews Peter Scott Power surface mount light emitting die package
US20040135156A1 (en) * 2003-01-06 2004-07-15 Sharp Kabushiki Kaisha Semiconductor light emitting device and fabrication method thereof
US20040222516A1 (en) * 2003-05-07 2004-11-11 Ting-Hao Lin Light emitting diode bulb having high heat dissipating efficiency
US20060124953A1 (en) * 2004-12-14 2006-06-15 Negley Gerald H Semiconductor light emitting device mounting substrates and packages including cavities and cover plates, and methods of packaging same
US20080048204A1 (en) * 2006-07-28 2008-02-28 Sharp Kabushiki Kaisha Semiconductor light-emitting element assembly
EP2109156A1 (fr) * 2007-01-30 2009-10-14 Denki Kagaku Kogyo Kabushiki Kaisha Unité de source lumineuse del
DE102008044847A1 (de) * 2008-08-28 2010-03-04 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement
DE102009000882A1 (de) 2009-02-16 2010-08-26 Semikron Elektronik Gmbh & Co. Kg Substrat zur Aufnahme mindestens eines Bauelements und Verfahren zur Herstellung eines Substrats

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016102588A1 (de) * 2016-02-15 2017-08-17 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines Anschlussträgers, Anschlussträger, optoelektronisches Bauelement mit einem Anschlussträger und Verfahren zur Herstellung eines optoelektronischen Bauelements
DE102016102588B4 (de) 2016-02-15 2021-12-16 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung eines Anschlussträgers, Anschlussträger, optoelektronisches Bauelement mit einem Anschlussträger und Verfahren zur Herstellung eines optoelektronischen Bauelements
US10939563B2 (en) 2016-09-27 2021-03-02 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Flame retardant structure for component carrier

Also Published As

Publication number Publication date
DE102011101052A1 (de) 2012-11-15

Similar Documents

Publication Publication Date Title
EP3008753B1 (fr) Module de puissance
EP2548419B1 (fr) Système de feuilles pour des applications del
DE102015118633B4 (de) Ein Leistungshalbleitermodul mit einem Direct Copper Bonded Substrat und einem integrierten passiven Bauelement und ein integriertes Leistungsmodul sowie ein Verfahren zur Herstellung des Leistungshalbleitermoduls
WO2012152364A1 (fr) Substrat doté d'une zone électriquement neutre
DE102016104844B4 (de) Verfahren zur Herstellung eines Chipverbunds
DE102014100309B4 (de) Chipanordnung und Verfahren zum Bilden einer Chipanordnung
DE102011088218B4 (de) Elektronisches Leistungsmodul mit thermischen Kopplungsschichten zu einem Entwärmungselement und Verfahren zur Herstellung
WO2017182159A1 (fr) Système de support multicouche, procédé de fabrication d'un système de support multicouche et utilisation d'un système de support multicouche
EP1620892A2 (fr) Materiau composite et circuit electrique ou module electrique
WO2009016039A1 (fr) Module électronique doté d'au moins un élément constitutif, en particulier un élément constitutif semi-conducteur, et son procédé de fabrication
DE102016214607B4 (de) Elektronisches Modul und Verfahren zu seiner Herstellung
EP3053192B1 (fr) Dispositif avec un circuit et procédé de fabrication du dispositif
EP2054947B1 (fr) Composant opto-électronique
EP1817945A1 (fr) Substrat
DE202015006897U1 (de) Halbleitermodul und Leistungsanordnung
DE102015100868B4 (de) Integrierte Schaltung und Verfahren zum Herstellen einer integrierten Schaltung
EP2219211A1 (fr) Substrat destiné à la réception d'au moins un composant et procédé de fabrication d'un substrat
DE102008031231B4 (de) Herstellungsverfahren für planare elektronsche Leistungselektronik-Module für Hochtemperatur-Anwendungen und entsprechendes Leistungselektronik-Modul
DE10217214B4 (de) Kühlanordnung für eine Schaltungsanordnung
DE102020209752A1 (de) Elektronisches Schaltungsmodul
WO2007080027A1 (fr) Dispositif de refroidissement de composants de puissance sur des cartes de circuit imprimé et son procédé de fabrication
DE102014109385A1 (de) Elektronische Bauteilanordnung
WO2017182157A1 (fr) Système de support
DE102004041417B4 (de) Elektrische Anordnung und Verfahren zum Herstellen einer elektrischen Anordnung
EP3595002A1 (fr) Substrat métal-céramique pourvu d'un film formé pour un refroidissement direct comme côté inférieur du substrat

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12719571

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 12719571

Country of ref document: EP

Kind code of ref document: A1