WO2012152331A1 - Boucle à asservissement de phase avec phase ajustable - Google Patents

Boucle à asservissement de phase avec phase ajustable Download PDF

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Publication number
WO2012152331A1
WO2012152331A1 PCT/EP2011/057669 EP2011057669W WO2012152331A1 WO 2012152331 A1 WO2012152331 A1 WO 2012152331A1 EP 2011057669 W EP2011057669 W EP 2011057669W WO 2012152331 A1 WO2012152331 A1 WO 2012152331A1
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WO
WIPO (PCT)
Prior art keywords
phase
phase detector
locked loop
detector
signal
Prior art date
Application number
PCT/EP2011/057669
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English (en)
Inventor
Mingquan Bao
Original Assignee
Telefonaktiebolaget Lm Ericsson (Publ)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget Lm Ericsson (Publ) filed Critical Telefonaktiebolaget Lm Ericsson (Publ)
Priority to PCT/EP2011/057669 priority Critical patent/WO2012152331A1/fr
Publication of WO2012152331A1 publication Critical patent/WO2012152331A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations

Definitions

  • the present invention discloses a phase locked loop with tunable phase.
  • Signal sources with tunable phase are used in many applications, for example in providing multiphase local oscillator, LO, signals for up-/down- conversion mixers in RF or microwave transceivers, for driving electric beam steering antenna array in radar systems, etc.
  • the tuneability of the phase of a signal from a signal source with tunable phase is often achieved by means of a phase shifter.
  • phase shifters There are many known kinds of phase shifters, and these can be divided into two groups, passive and active phase shifters.
  • the first group i.e. the passive phase shifters, often exhibit losses
  • the second group i.e. the active phase shifters, inherently have a consumption of DC power, in addition to which they generate noise and nonlinear inter-modulation.
  • Phase locked loops, PLLs are a common component in, for example, transceivers and radar systems, where they are used for "locking" the phase of the output signal from the PLL to the phase of an input signal to the PLL.
  • a traditional PLL comprises a phase detector which produces an output signal which is proportional in amplitude to the phase difference between two input signals to the phase detector.
  • the output signal from the phase detector is used as tuning signal to a VCO, and the output from the VCO is used as one of the input signals to the phase detector, as well as being the output signal from the PLL.
  • a low-pass filter is arranged between the phase detector and the VCO.
  • phase locked loop which comprises a phase detector with a first and a second input port for a first and a second input signal, respectively.
  • the phase detector also comprises an output port, and the phase detector is arranged to deliver a signal at its output port which is proportional to the phase difference between the first and the second input signals and which varies between maximum and minimum points with variations in the phase difference between the first and the second input signals.
  • the phase locked loop also comprises a Voltage Controlled Oscillator, a VCO, which receives the output signal from the phase detector as a tuning signal.
  • a first part of the output signal of the VCO is arranged to be one of the input signals to the phase detector and a second part of output signal of the VCO is arranged to be the output signal of the phase locked loop.
  • the phase locked loop also comprises a DC voltage shifter which is arranged between the phase detector and the VCO.
  • the DC voltage shifter is arranged to shift the DC voltage level of the output signal from the phase detector so that a point at a predefined distance from a centre point between said maximum and minimum points is shifted to zero volts DC.
  • phase detector is tunable with respect to the phase of its output signal.
  • the phase locked loop of the invention can be used as a signal source which can be tuned in phase by means of the tunable phase detector.
  • the predefined distance from a centre point between the maximum and minimum points which is shifted to zero volts DC is zero, i.e. in embodiments, the "moved" point is the centre point.
  • the phase locked loop additionally comprises a frequency divider which is arranged between the VCO and the phase detector.
  • the phase detector comprises a T- network with a first and a second capacitance, each of which has a first and a second connection port and which are serially connected to each other via their second connection ports. At least one of the capacitances is tunable, and an inductance connects a point between the capacitances, i.e. between their second connection ports, to ground.
  • the first connection port of the first and second capacitance, respectively, are arranged to be used as the first and second input port of the phase locked loop.
  • the first of the capacitances also has its first connection point connected to the input port of a power detector.
  • the output port of the power detector is arranged to be output port of the phase detector.
  • the phase detector comprises a ⁇ - network with a first and a second capacitance, each of which capacitance has a first and a second connection port. At least one of the capacitances is variable, and the capacitances are connected via an inductance at their first connection ports and have their second connection port connected to ground.
  • the first connection port of the first and second capacitance, respectively, are arranged to be used as the first and second input port of the phase locked loop.
  • the first of the capacitances also has its first connection port connected to the input port of a power detector.
  • the output port of the power detector is arranged to be output port of the phase detector.
  • the inductors can be exchanged for capacitors if the capacitors are exchanged for inductors.
  • Fig 1 shows a prior art Phase Locked Loop
  • Fig 2 shows a basic embodiment of a signal source of the invention
  • Fig 3 shows a characteristic of a phase detector
  • Fig 4 shows a first tunable phase detector
  • Fig 5 shows a second tunable phase detector
  • Fig 6 shows a characteristic of the phase detector of fig 5
  • Figs 7 and 8 show further embodiments of signal sources.
  • fig 1 shows a block diagram of a prior art Phase Locked Loop 1 10, commonly abbreviated as PLL.
  • the PLL 1 10 has as a first input signal a reference signal which has a certain phase cp-i .
  • the first input signal with the phase ⁇ is received by a phase detector in the PLL 1 10, and the phase detector also receives a second input signal which has the phase cp 2 .
  • the phase detector produces an output signal, an "error signal”, denoted as ⁇ , which is proportional in amplitude to the difference between the phases of the input signals, i.e. ⁇ and ⁇ 2.
  • the error signal from the phase detector is passed through a low pass filter, LPF, and is then used as the tuning signal to a VCO, thereby "driving" the VCO, and creating an output signal from the VCO with a certain phase.
  • the output signal from the VCO is either used “straight off as the second input signal to the phase detector, or, as shown in fig 1 , the output signal from the VCO is passed through a frequency divider before being used as input signal to the phase detector. If a frequency divider is used, the phase of the signal from the VCO will be divided by the division factor n of the divider, i.e. if the phase from the VCO is cp, then the phase 1 ⁇ 2 from the frequency divider will be cp/n.
  • the output signal from the VCO is also used as the output signal from the PLL 1 10 and from the signal source 100.
  • this design serves to create a control loop in which the phase of the output signal from the signal source 100 is ""locked" to the phase of the reference signal, i.e. locked to cp-i .
  • Fig 2 shows an embodiment of a phase locked loop 200 of the invention, and also shows a source 205 for a reference signal: the phase locked loop 200 has a first input port 206 for a first input signal and a second input port 207 for a second input signal. The first and second input ports are used as input ports to a phase detector 21 0. As described above in connection with the PLL 1 10, the phase detector 210 produces an output signal P d iff at an output port 208, which is proportional in amplitude to the phase difference between the input signals at the first and second input ports 206, 207.
  • the reference signal from the source 205 is used as the first input signal at the first input port 206.
  • the phase detector 21 0 is tunable, i.e. the amplitude of the output signal from the phase detector 210 for one and the same phase difference between the input signals to the phase detector 210 is tunable by means of a tuning signal shown as V T UNE in fig 2.
  • the tuning signal V T UNE is used to tune the capacitance of the varactors in the T or ⁇ network, consequently, to tune the phase of the output signal from the PLL 200 in a manner which will be described in more detail later in this text.
  • the phase locked loop 200 also comprises a DC voltage shifter 21 5 connected to the output of the tunable phase detector 215.
  • the output signal from the phase detector 210 is used as input signal to a DC voltage shifter 21 5.
  • the role of the DC voltage shifter 215 will be described in more detail later in this text, but, as the name implies, a basic function of the DC voltage shifter 215 is to shift the DC level of the output signal from the phase detector 210 and to deliver the "DC-shifted" signal as its out signal.
  • the output signal from the DC voltage shifter 215 is used as the input signal or tuning signal to a Voltage Controlled Oscillator, a VCO 220.
  • the tuning signal to the VCO 220 controls the frequency of the VCO's 220 output signal. Since frequency is the derivative of phase, the tuning signal to the VCO can also be seen as controlling the phase of the output signal from the VCO 220.
  • the output signal from the VCO 220 is used in one part as the output signal from the entire PLL 200, and in another part as the second input signal to the phase detector 210 at the second input port 207.
  • the PLL 200 is shown as comprising a frequency divider 225 between the output of the VCO 220 and the phase detector 210.
  • the frequency divider is however optional, i.e. it is used in some embodiments and not in some other embodiments, depending on the frequency of VCO and the frequency of reference source.
  • Fig 3 shows the amplitude of the output signal from the tunable phase detector 210 as a function of the phase difference ⁇ between the input signals to the tunable phase detector 210.
  • Three different curves are shown, numbered as 1 , 2 and 3, one for each of three different values of the tuning signal V T UNE, i.e., different capacitances of the varactors of the tunable phase detector 210.
  • the curves numbered 1 , 2 and 3 correspond, respectively, to the varactors 315, 320 being tuned to a capacitance of 3, 4 and 5 pF.
  • the amplitude shown in fig 3 varies between maximum and minimum values, in this example as a sine/cosine-function.
  • the role of the DC voltage shifter 215 is to shift the DC-level of the output of the tunable phase detector so that a certain point on the amplitude curve is shifted to zero V DC.
  • the point which is moved to zero V DC is a point between the maximum and the minimum point on the curve, i.e. a point on the "downward" (negative) slop of the curve; it should be stressed that such a point is not to be confused with a point between the minimum and the maximum point on the curve, i.e. a point on the "upward" slope of the curve.
  • the point which is moved to zero V DC is a point in the middle of the maximum and minimum points of the curve, i.e. a centre point between the maximum and minimum points of the curve, although other points at a certain distance from the centre point can also be used, in order to create other effects.
  • the point which is moved to zero V DC is here referred to as the "zero gain point", and is the point whose output phase the PLL will be "locked” to.
  • the phase detector 210 is tunable, the phase of the output signal from the VCO 220 can also be altered, thereby altering the phase difference ⁇ between the two input signals to the tunable phase detector 210.
  • phase of the reference signal i.e. the input signal at the input port 206
  • ⁇ the phase difference between the VCO 220 and the signal from the frequency divider 225
  • the frequency of the signal from the frequency divider 225 will be fo/8, i.e. 875 MHz. If, as is preferable, the reference signal is at the same frequency as the signal from the frequency divider 225, the frequency of the reference signal will also be 875 MHz.
  • Fig 4 shows an embodiment of a tunable phase detector 410 for use in the PLL 200 in fig 2: as shown in fig 4, the tunable phase detector 410 comprises a so called "T-network" 310 with an inductor 325 connect to ground at one end, and at its other end connected to a point in between two capacitors 320, 315, which are serially connected to each other. At least one of the capacitors, and suitably both of them, are varactors, i.e. tunable capacitances, which are tuned by means of a tuning voltage shown in fig 4, and which is the tuning voltage V T UNE from fig 2. The two capacitors 320, 315, are connected to each other at one of their respective ends.
  • the capacitor 320 has its other end connected to the input port of a power detector 305, where the output port of the power detector 305 is arranged to be output port of the phase detector, shown as 208 in figs 2 and 4.
  • the same end of the capacitor 320 that is connected to the input port of the power detector 305 is also arranged to be one of the input ports to the phase detector 410, in this case the input port which is numbered as 206 in fig 2 as well as in fig 4.
  • the other input port of the phase detector i.e. the input port shown as 207 in fig 2 is the end of the capacitor 315 which is not connected to the capacitor 320. This end is also shown as 207 in fig 4.
  • fig 4 also shows the reference signal source 205, connected to the input port 206 via a resistor 335, and the frequency divider 225, connected to the input port 207 via a resistor 330.
  • the resistor 335 represents the output impedance of the reference signal source 205
  • the resistor 330 represents the output impedance of the frequency divider.
  • both of the capacitors 315, 320 are tunable, i.e. they are so called varactors.
  • Fig 5 shows a second embodiment 510 of a tunable phase detector for use as the tunable phase detector 210 of fig 2.
  • the tunable phase detector comprises a ⁇ -network 51 1 with a first 520 and a second 515 capacitor, connected an inductor 525 between them at one a first connection point or input port, the inductors 520, 525, being grounded at their second connection point or input port.
  • at least one of the capacitors 515, 520 is a varactor, and suitably, this is the case for both of the capacitors 520, 515.
  • the first connection port 206, 207 of the first 520 and second 515 capacitor, respectively, are arranged to be used as the first and second input ports, shown as 206 and 207 in fig 2, of the tunable phase detector, and the first capacitor also has its first connection port connected to the input port of a power detector 505.
  • the output port 205 of the power detector 505 is arranged to be output port of the tunable phase detector 510.
  • Fig 6 shows three curves similar to those shown in fig 3, numbered 1 ', 2' and 3', respectively. It can be seen that the amplitude of the output signal from the tunable phase detector 510 varies from 0.48 to 0.04 V DC along curve 1 ', which represents a setting of the varactors 520, 515 to a capacitance of 3 pF.
  • the curve 2' represents a setting of the varactors 520, 515 to a capacitance of 4.5 pF
  • the curve 3' represents a setting of the varactors 520, 515 to a capacitance of 6 pF.
  • the shift from the DC voltage shifter 215 is here chosen to be 0.27 V, or rather -0.27 V, since the shift is negative. It can be seen that the zero gain points vary from 70° to 120°, which, in this example will lead to a phase variation in the output signal from the VCO 220 of 400°.
  • Fig 7 shows a further embodiment 700, which is a so called two-tunable phase signal source, and which comprises two PLLs 701 and 702, where the PLL 701 is a PLL which comprises a tunable phase detector 771 with a T- network, as shown in fig 4 and explained in connection with that figure, and the PLL 702 is a PLL which comprises a tunable phase detector 730 with a TT-network, as shown in fig 5 and explained in connection with that figure.
  • the PLL 701 is a PLL which comprises a tunable phase detector 771 with a T- network, as shown in fig 4 and explained in connection with that figure
  • the PLL 702 is a PLL which comprises a tunable phase detector 730 with a TT-network, as shown in fig 5 and explained in connection with that figure.
  • One and the same tuning signal VTUNE is used for both of the phase detectors 710, 730, which leads to a phase difference between the output signals from the two PLLs 701 , 702, of approximately ⁇ radians, since stable zero gain points for a T-network is in the region of between 3 ⁇ /2 and 2 ⁇ radians, and for a ⁇ -network is between 0 and ⁇ radians.
  • different tuning signals VTUNE are used for the two phase detectors 710, 730, and also, it is possible to use similar T or ⁇ networks, depending on the desired range of phase differences for the PLLs 701 , 702.
  • the PLLs 701 , 702 do not comprise a frequency divider between the VCO 720, 740, and the tunable phased detector 710, 730.
  • Fig 8 shows an embodiment 800 which illustrates how a Phase Locked Loop of the invention can be used to generate multi-phase signals, in a manner which is similar to the embodiment which is shown in fig 7:
  • N PLL of the invention which all share the same reference signal source 805.
  • Three PLLs 801 -803 are shown explicitly in fig 8, with respective output signals Out-i , Out 2 and Out 3 , and the use of N PLLs is indicated by means of a dotted line and an output signal shown as OutN.
  • the output signals from the PLLs in the embodiment 800 can be given different phases by means of applying a different tuning signal, show as VTUNE-I , V T UNE2 and V T UNE3, to the tuneable phase detector in each of the PLLs 801 -803.

Abstract

L'invention concerne une boucle à asservissement de phase (200, 700, 800) comprenant un détecteur de phase (210, 710, 730) dont le signal de sortie varie entre des points maximum et minimum en fonction de la différence de phase entre les signaux d'entrée. Un OCT (220, 720, 740) reçoit le signal de sortie du détecteur de phase (210, 710, 730) en qualité de signal d'ajustement. Une première partie du signal de sortie de l'OCT (220, 720, 740) est un signal d'entrée vers le détecteur de phase (210, 710, 730) et une seconde partie est le signal de sortie de la boucle à asservissement de phase. Un décaleur de tension CC (215, 715, 735) est disposé entre le détecteur de phase et l'OCT, et décale le niveau de tension CC du signal de sortie venant du détecteur de phase (210, 710, 730) de sorte qu'un point à une certaine distance d'un point central entre lesdits points maximum et minimum est décalé vers zéro volt (CC). Le détecteur de phase (210, 710, 730) est ajustable.
PCT/EP2011/057669 2011-05-12 2011-05-12 Boucle à asservissement de phase avec phase ajustable WO2012152331A1 (fr)

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PCT/EP2011/057669 WO2012152331A1 (fr) 2011-05-12 2011-05-12 Boucle à asservissement de phase avec phase ajustable

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4570130A (en) * 1982-10-20 1986-02-11 International Business Machines Corporation Input controller circuit apparatus for phase lock loop voltage controlled oscillator
US5917352A (en) * 1994-06-03 1999-06-29 Sierra Semiconductor Three-state phase-detector/charge pump with no dead-band offering tunable phase in phase-locked loop circuits
US6424212B1 (en) * 1999-11-25 2002-07-23 Telefonaktiebolaget Lm Ericsson (Publ) Power amplifiers
US20090261873A1 (en) * 2008-04-21 2009-10-22 Kuo-Kai Lin Signal generating circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4570130A (en) * 1982-10-20 1986-02-11 International Business Machines Corporation Input controller circuit apparatus for phase lock loop voltage controlled oscillator
US5917352A (en) * 1994-06-03 1999-06-29 Sierra Semiconductor Three-state phase-detector/charge pump with no dead-band offering tunable phase in phase-locked loop circuits
US6424212B1 (en) * 1999-11-25 2002-07-23 Telefonaktiebolaget Lm Ericsson (Publ) Power amplifiers
US20090261873A1 (en) * 2008-04-21 2009-10-22 Kuo-Kai Lin Signal generating circuit

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