WO2012138868A2 - Exposed die package for direct surface mounting - Google Patents
Exposed die package for direct surface mounting Download PDFInfo
- Publication number
- WO2012138868A2 WO2012138868A2 PCT/US2012/032334 US2012032334W WO2012138868A2 WO 2012138868 A2 WO2012138868 A2 WO 2012138868A2 US 2012032334 W US2012032334 W US 2012032334W WO 2012138868 A2 WO2012138868 A2 WO 2012138868A2
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- WO
- WIPO (PCT)
- Prior art keywords
- metal layer
- back side
- package
- leads
- semiconductor die
- Prior art date
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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Definitions
- Disclosed embodiments relate to packaged semiconductor devices including die with exposed substrates (e.g., silicon) and electronic assemblies including such packaged semiconductor devices.
- exposed substrates e.g., silicon
- One known power package that includes enhanced cooling is an exposed heat slug package that comprises a heat slug (e.g., copper slug) that is exposed on the bottom side of the package.
- the die is bonded face (active top side) up on top of the heat slug with a thermally conductive die attach material.
- Another known power package is an exposed silicon package that flip chip mounts the semiconductor die on a die pad and exposes the bottom side of the semiconductor die. A heat sink is then thermally coupled to the bottom side of the semiconductor die using a thermal grease.
- the exposed heat slug package includes the semiconductor substrate (e.g., silicon), the die attach material, the heat slug and solder in the cooling path from the top side of the semiconductor to an underlying workpiece, such as a printed circuit board (PCB).
- the exposed silicon package includes the substrate, thermal grease and the heat sink in the cooling path from the top side of the semiconductor die to the atmosphere.
- Disclosed embodiments recognize conventional packaged semiconductor devices, particularly high power semiconductor devices, can reach high junction temperatures during their operation due to high thermal resistance resulting from a large thermal resistance drop across multiple interfaces that interferes with heat dissipation from the packaged device to its heat sink during its operation.
- a workpiece such as a printed circuit board (PCB)
- PCB printed circuit board
- One disclosed embodiment comprises a packaged semiconductor device that includes a semiconductor die comprising a substrate having a top side including active circuitry and a bottom side, and at least one back side metal layer that is directly attached to the bottom side.
- a package including a molding material comprising a die pad and a plurality of leads is encapsulated within the molding material, wherein the leads include an exposed portion that includes a bonding portion.
- the top side of the semiconductor die is attached to the die pad, and the package includes a gap that exposes the back side metal layer along a bottom surface of the package. Bond wires couple pads on the top side of the semiconductor die to the leads.
- the bonding portions, the bottom surface of the package, and the back side metal layer are all substantially planar to one another.
- Another disclosed embodiment comprises an electronic assembly comprising a disclosed packaged semiconductor device and a PCB including a plurality of surface pads.
- Direct solder connections are provided from the back side metal layer and the bonding portions of the leads to the surface pads on the PCB.
- Direct solderability provided by disclosed packaged semiconductor device reduces assembly cost as compared to conventional assembly, such as by eliminating the need for thermal grease and heat sinks, and added processing such to attach a heat sink.
- direct soldering reduces board space for PCB assemblies, and eases PCB layout by enabling use of surface mount device (SMD) rules.
- SMD surface mount device
- FIG. 1A is a cross-sectional depiction of an example packaged semiconductor device comprising a leaded package, with back side metal of the semiconductor die exposed along a bottom surface of the package for direct surface mounting, according to an example embodiment.
- FIG. IB is a cross-sectional depiction of an example packaged semiconductor device comprising a leadless package, with back side metal of the semiconductor die exposed at along a bottom surface of the surface of the package, according to an example embodiment.
- FIG. 2 is a cross-sectional depiction of an example electronic assembly comprising the packaged semiconductor device shown in FIG. 1 A surface mounted using a direct solder connection to a multi-layer PCB, according to an example embodiment.
- FIG. 1A illustrates an example packaged semiconductor device 100 comprising a leaded package, with back side metal of the semiconductor die 110 exposed along a bottom surface of the package for direct surface mounting, according to an example embodiment.
- the semiconductor die 110 comprises a substrate (e.g., silicon or silicon/germanium) 112 having a top side 113 including active circuitry 114 and a bottom side 116, and at least one back side metal layer 118 on the bottom side 116 of the substrate 112.
- the active circuitry 114 on top side surface 1 13 of semiconductor die 110 is configured to provide an IC circuit function.
- the back side metal layer 118 is directly attached to the bottom side 116 of the semiconductor die 110.
- the back side metal layer 1 18 is a single metal layer, such as a copper layer.
- the thickness of the copper layer is typically 3 ⁇ to 6 ⁇ , but can be thinner or thicker than this range.
- One example process involves forming a thin seed layer before forming the copper layer.
- the back side metal layer comprises a first metal layer on the bottom side 116 of the semiconductor die 110 and a multi-layer metal stack comprising at least a second metal layer different from the first metal layer on the first metal layer.
- the first metal layer can comprise titanium. Titanium is known to provide good adhesion with silicon and other semiconductors and thereby to create an effective "adhesion layer".
- Other embodiments may comprise tantalum, palladium, vanadium or molybdenum as the first layer in contact with the bottom side 116 of the semiconductor die 110.
- these metals provide good adhesion to silicon because they can form intermediate metal-silicides with silicon at relatively low temperatures.
- Some examples of specific multi-layer back side metal stacks include Cu on Ti, Ag on Ti, Cu on Ti, and stacks including first, second and third metal layers, such as Au on Ni on Ti, and Ag on Ni on Ti.
- a nickel layer can provide protection for underlying metal layers from mechanical scratching and corrosion.
- the first metal layer or second metal layer can comprises nickel.
- nickel For example, Ag on Cr on Ni, or Pd on Ni on Au.
- Chromium can act as a barrier layer to stop metal diffusion into the substrate, provides a stress buffer layer, and also act to prevent fracturing inside the metal stack due to its high fracture strength.
- Typical thicknesses for the multi-layer metal stack can comprise 1 to 2 kA for the first metal layer, 2 to 4 kA for the second metal layer and 10 to 20 kA for the third metal layer.
- the Au thickness can be significantly thicker than 20 kA.
- the respective metal layer thicknesses can be thinner or thicker than these ranges.
- An area of the back side metal layer 118 matches an area of the bottom side 116 of the semiconductor die 110.
- directly attached refers to a connection that does not include any intervening layers.
- Back side metal layer 118 matching an area of the bottom side 116 of the semiconductor die 110 is provided by the back side metal layer 118 being on the bottom side 116 of the semiconductor die 110 before singulation (e.g., back side metal layer 118 is deposited on the bottom side 116 of the substrate 112 while the semiconductor die 110 are in wafer form), so that the singulation process cuts the wafer into a plurality of semiconductor die each having an area that is constant during the cutting process through both the back side metal 118 and the substrate 112.
- the package 130 in FIG. 1A is shown as a leaded package including a molding material 132, such as a standard epoxy-resin package material having a die pad 125 and a plurality of leads 127 that include a portion encapsulated within the molding material 132 and exposed portions 127(a) on which the leads shown are bent including a bonding portion 127(a)(1) shown as feet 127(a)(1).
- a molding material 132 such as a standard epoxy-resin package material having a die pad 125 and a plurality of leads 127 that include a portion encapsulated within the molding material 132 and exposed portions 127(a) on which the leads shown are bent including a bonding portion 127(a)(1) shown as feet 127(a)(1).
- the top side 113 of the semiconductor die 110 is attached to the die pad 125 by a die attach material 126, such as an epoxy.
- the back side metal layer 118 is exposed by a gap in the molding material 132 along a portion of the bottom surface 130(a) of the package 130.
- the package can be molded with a gap in the molding material so that the back side metal layer 118 is exposed.
- Back side metal layer 118 allows packaged semiconductor device 100 to be directly soldered to a package substrate, such as a PCB.
- a package substrate e.g., a PCB
- the thermal dissipation path has a minimum number of interfaces, including from the active devices 114 on the top side 113 of the semiconductor die 110 through the thickness of the substrate 112 and a tiny contribution across the back side metal 118, so that thermal dissipation for packaged semiconductor device 100 to the underlying workpiece is generally set by the thermal conductivity the substrate 112 for the semiconductor die 110, or about 140 W/m-K for a silicon substrate.
- the semiconductor die 110 is a thinned die, such as 40 to 100 ⁇ in thickness, to further enhance thermal transfer from the packaged semiconductor device to the workpiece.
- direct solderability provided by packaged semiconductor device 100 reduces assembly cost as compared to conventional assembly, such as by eliminating the need for thermal grease and heat sinks, and added processing such to attach a heat sink. Moreover, direct soldering reduces board space for PCB assemblies, and eases PCB layout by enabling use of surface mount device (SMD) rules.
- SMD surface mount device
- Bond wires 136 are shown for coupling bond pads 119 on the top side 113 of the semiconductor die 110 to the plurality of leads 127.
- the feet 127(a)(1), the bottom surface 130(a) of the package 130, and the back side metal layer 118 are all substantially planar to one another.
- substantially planar refers to a maximum range between the lower edges of bonding portion of the leads for bonding to the workpiece (e.g., PCB) such as the feet 127(a)(1) shown in FIG. 1A, the bottom surface 130(a) of the package 130, and the back side metal layer 118 all being within a range of +/- 0.25 mm (i.e. a maximum 0.5 mm tilt).
- substantially planar arrangement facilitates direct surface mounting, such as for the example case where the soldering process comprises a solder paste onto a screen (mask) having a thickness of 0.3 to 0.5 mm on a workpiece such as a PCB.
- the molding material 132 along the full length of the bottom surface 130(a) of the package 130 can also be substantially planar throughout (i.e. no indentation regions).
- FIG. IB illustrates an example packaged semiconductor device 150 comprising a leadless package 180, with back side metal 118 of the semiconductor die 110 exposed along a bottom surface 180(a) of the package for direct surface mounting, according to an example embodiment.
- Package 180 includes a die pad 125 and plurality of exposed portions shown as perimeter terminating leads 181 (also sometimes referred to as perimeter lands) that do not extend beyond the molding material 132. Perimeter terminating leads 181 are substantially planar to the bottom surface 180(a) of the leadless package 180, and the back side metal 118.
- Leadless package 180 can comprise a variety of Flat No leads packages such as QFN (Quad Flat No leads) and DFN (Dual Flat No leads).
- Packaged semiconductor device 150 provides the directly solderability, high level of thermal, reduced assembly cost, reduced board space for PCB assemblies, and the same ease of board layout provided by packaged semiconductor device 100 described above.
- FIG. 2 illustrates an example electronic assembly 200, comprising the packaged semiconductor device 100 shown in FIG. 1A surface mounted using a direct solder connection to a multi-layer PCB 210 comprising at least one internal metal (e.g., copper) plane 211 and a plurality of surface pads 215.
- Direct solder connections 216 are shown for coupling the back side metal layer 118 and the feet 127(a)(1) of the packaged semiconductor device 100 to ones of the surface pads 215 on the PCB 210, such as copper surface pads.
- a disclosed packaged semiconductor device such as packaged semiconductor devices 100 or 150 described, is directly solder to a workpiece such as a PCB including a plurality of surface pads.
- the back side metal layer and the bonding portions of the plurality of leads are directly soldered to substrate pads on the PCB.
- the active circuitry formed on the semiconductor wafers and the semiconductor die therefrom comprise circuit elements that may generally include transistors, diodes, capacitors, and resistors, as well as signal lines and other electrical conductors that interconnect the various circuit elements to provide an IC circuit function.
- provide an IC circuit function refers to circuit functions from ICs, that for example may include an application specific integrated circuit (ASIC), a digital signal processor, a radio frequency chip, a memory, a microcontroller and a system-on-a-chip or a combination thereof.
- ASIC application specific integrated circuit
- the IC assembly can comprise single semiconductor die or multiple die, such as PoP configurations comprising a plurality of stacked semiconductor die.
- a variety of package substrates may be used.
- the semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc.
- the semiconductor die can formed from a variety of processes including bipolar, CMOS, BiCMOS and MEMS.
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Abstract
A packaged semiconductor device (100) includes a semiconductor die (110) including a substrate (112) having a top side (113) including active circuitry (114) and a bottom side (116) with at least one back side metal layer (118) directly attached. A package (130) including a molding material (132) having a die pad (125) and a plurality of leads (127) is encapsulated within the molding material, wherein the leads include an exposed portion 127(a) that includes a bonding portion 127(a)(1). The top side of the semiconductor die is attached to the die pad, and the package includes a gap that exposes the back side metal layer along a bottom surface of the package. Bond wires couple pads on the top side of the semiconductor die to the leads. The bonding portions, the molding material along the bottom surface of the package, and the back side metal layer are all substantially planar to one another.
Description
EXPOSED DIE PACKAGE FOR DIRECT SURFACE MOUNTING
[0001] Disclosed embodiments relate to packaged semiconductor devices including die with exposed substrates (e.g., silicon) and electronic assemblies including such packaged semiconductor devices.
BACKGROUND
[0002] For a semiconductor package that includes at least one semiconductor die therein, particularly for power integrated circuits (ICs), the problem of heat dissipation is an important issue. A semiconductor package with poor heat dissipation may not just produce errors, but may also reduce product reliability and greatly increase manufacturing cost.
[0003] One known power package that includes enhanced cooling is an exposed heat slug package that comprises a heat slug (e.g., copper slug) that is exposed on the bottom side of the package. The die is bonded face (active top side) up on top of the heat slug with a thermally conductive die attach material. Another known power package is an exposed silicon package that flip chip mounts the semiconductor die on a die pad and exposes the bottom side of the semiconductor die. A heat sink is then thermally coupled to the bottom side of the semiconductor die using a thermal grease.
[0004] Both of these known power packages have significant thermal resistance that reduces cooling performance due to multiple interfaces in the cooling path that increases the thermal resistance of the package. For example, the exposed heat slug package includes the semiconductor substrate (e.g., silicon), the die attach material, the heat slug and solder in the cooling path from the top side of the semiconductor to an underlying workpiece, such as a printed circuit board (PCB). Similarly, the exposed silicon package includes the substrate, thermal grease and the heat sink in the cooling path from the top side of the semiconductor die to the atmosphere.
SUMMARY
[0005] Disclosed embodiments recognize conventional packaged semiconductor devices, particularly high power semiconductor devices, can reach high junction temperatures during their operation due to high thermal resistance resulting from a large thermal resistance drop across multiple interfaces that interferes with heat dissipation from the packaged device to its heat sink during its operation. By having the bonding portion of the leads, the bottom surface of the package, and the back side metal of the semiconductor die all be substantially planar to one another allows direct soldering of the packaged semiconductor device to a workpiece such as a printed circuit board (PCB), and as a result improved heat dissipation to the workpiece (e.g., PCB) due to a reduction in interfaces in the thermal cooling path to the workpiece.
[0006] One disclosed embodiment comprises a packaged semiconductor device that includes a semiconductor die comprising a substrate having a top side including active circuitry and a bottom side, and at least one back side metal layer that is directly attached to the bottom side. A package including a molding material comprising a die pad and a plurality of leads is encapsulated within the molding material, wherein the leads include an exposed portion that includes a bonding portion. The top side of the semiconductor die is attached to the die pad, and the package includes a gap that exposes the back side metal layer along a bottom surface of the package. Bond wires couple pads on the top side of the semiconductor die to the leads. The bonding portions, the bottom surface of the package, and the back side metal layer are all substantially planar to one another.
[0007] Another disclosed embodiment comprises an electronic assembly comprising a disclosed packaged semiconductor device and a PCB including a plurality of surface pads. Direct solder connections are provided from the back side metal layer and the bonding portions of the leads to the surface pads on the PCB. Direct solderability provided by disclosed packaged semiconductor device reduces assembly cost as compared to conventional assembly, such as by eliminating the need for thermal grease and heat sinks, and added processing such to attach a heat sink. Moreover, direct soldering reduces board space for PCB assemblies, and eases PCB layout by enabling use of surface mount device (SMD) rules.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1A is a cross-sectional depiction of an example packaged semiconductor device comprising a leaded package, with back side metal of the semiconductor die exposed
along a bottom surface of the package for direct surface mounting, according to an example embodiment.
[0009] FIG. IB is a cross-sectional depiction of an example packaged semiconductor device comprising a leadless package, with back side metal of the semiconductor die exposed at along a bottom surface of the surface of the package, according to an example embodiment.
[0010] FIG. 2 is a cross-sectional depiction of an example electronic assembly comprising the packaged semiconductor device shown in FIG. 1 A surface mounted using a direct solder connection to a multi-layer PCB, according to an example embodiment.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0011] FIG. 1A illustrates an example packaged semiconductor device 100 comprising a leaded package, with back side metal of the semiconductor die 110 exposed along a bottom surface of the package for direct surface mounting, according to an example embodiment. The semiconductor die 110 comprises a substrate (e.g., silicon or silicon/germanium) 112 having a top side 113 including active circuitry 114 and a bottom side 116, and at least one back side metal layer 118 on the bottom side 116 of the substrate 112. The active circuitry 114 on top side surface 1 13 of semiconductor die 110 is configured to provide an IC circuit function. The back side metal layer 118 is directly attached to the bottom side 116 of the semiconductor die 110.
[0012] A variety of back side metal layers 118 can be used. In one embodiment, the back side metal layer 1 18 is a single metal layer, such as a copper layer. The thickness of the copper layer is typically 3 μιη to 6 μιη, but can be thinner or thicker than this range. One example process involves forming a thin seed layer before forming the copper layer. In another embodiment, the back side metal layer comprises a first metal layer on the bottom side 116 of the semiconductor die 110 and a multi-layer metal stack comprising at least a second metal layer different from the first metal layer on the first metal layer. For example, the first metal layer can comprise titanium. Titanium is known to provide good adhesion with silicon and other semiconductors and thereby to create an effective "adhesion layer". Other embodiments may comprise tantalum, palladium, vanadium or molybdenum as the first layer in contact with the bottom side 116 of the semiconductor die 110. Like titanium, these metals provide good adhesion to silicon because they can form intermediate metal-silicides with silicon at relatively low temperatures. Some examples of specific multi-layer back side metal stacks include Cu on Ti, Ag on Ti, Cu on Ti, and stacks including first, second and third metal layers, such as Au on
Ni on Ti, and Ag on Ni on Ti. A nickel layer can provide protection for underlying metal layers from mechanical scratching and corrosion.
[0013] In other example embodiments the first metal layer or second metal layer can comprises nickel. For example, Ag on Cr on Ni, or Pd on Ni on Au. Chromium can act as a barrier layer to stop metal diffusion into the substrate, provides a stress buffer layer, and also act to prevent fracturing inside the metal stack due to its high fracture strength. Typical thicknesses for the multi-layer metal stack can comprise 1 to 2 kA for the first metal layer, 2 to 4 kA for the second metal layer and 10 to 20 kA for the third metal layer. In the case of Au for the third metal layer, the Au thickness can be significantly thicker than 20 kA. However, the respective metal layer thicknesses can be thinner or thicker than these ranges.
[0014] An area of the back side metal layer 118 matches an area of the bottom side 116 of the semiconductor die 110. As used herein "directly attached" refers to a connection that does not include any intervening layers. Back side metal layer 118 matching an area of the bottom side 116 of the semiconductor die 110 is provided by the back side metal layer 118 being on the bottom side 116 of the semiconductor die 110 before singulation (e.g., back side metal layer 118 is deposited on the bottom side 116 of the substrate 112 while the semiconductor die 110 are in wafer form), so that the singulation process cuts the wafer into a plurality of semiconductor die each having an area that is constant during the cutting process through both the back side metal 118 and the substrate 112.
[0015] The package 130 in FIG. 1A is shown as a leaded package including a molding material 132, such as a standard epoxy-resin package material having a die pad 125 and a plurality of leads 127 that include a portion encapsulated within the molding material 132 and exposed portions 127(a) on which the leads shown are bent including a bonding portion 127(a)(1) shown as feet 127(a)(1).
[0016] The top side 113 of the semiconductor die 110 is attached to the die pad 125 by a die attach material 126, such as an epoxy. The back side metal layer 118 is exposed by a gap in the molding material 132 along a portion of the bottom surface 130(a) of the package 130. The package can be molded with a gap in the molding material so that the back side metal layer 118 is exposed. Back side metal layer 118 allows packaged semiconductor device 100 to be directly soldered to a package substrate, such as a PCB.
[0017] Directly soldering the back side metal layer 118 of packaged semiconductor device 100 to a package substrate (e.g., a PCB) provides good thermal transfer from the semiconductor die 110 to the package substrate. In this directly soldered arrangement, the thermal dissipation path has a minimum number of interfaces, including from the active devices 114 on the top side 113 of the semiconductor die 110 through the thickness of the substrate 112 and a tiny contribution across the back side metal 118, so that thermal dissipation for packaged semiconductor device 100 to the underlying workpiece is generally set by the thermal conductivity the substrate 112 for the semiconductor die 110, or about 140 W/m-K for a silicon substrate. In one embodiment, the semiconductor die 110 is a thinned die, such as 40 to 100 μιη in thickness, to further enhance thermal transfer from the packaged semiconductor device to the workpiece.
[0018] In addition, direct solderability provided by packaged semiconductor device 100 reduces assembly cost as compared to conventional assembly, such as by eliminating the need for thermal grease and heat sinks, and added processing such to attach a heat sink. Moreover, direct soldering reduces board space for PCB assemblies, and eases PCB layout by enabling use of surface mount device (SMD) rules.
[0019] Bond wires 136 are shown for coupling bond pads 119 on the top side 113 of the semiconductor die 110 to the plurality of leads 127. The feet 127(a)(1), the bottom surface 130(a) of the package 130, and the back side metal layer 118 are all substantially planar to one another. As used herein, "substantially planar" refers to a maximum range between the lower edges of bonding portion of the leads for bonding to the workpiece (e.g., PCB) such as the feet 127(a)(1) shown in FIG. 1A, the bottom surface 130(a) of the package 130, and the back side metal layer 118 all being within a range of +/- 0.25 mm (i.e. a maximum 0.5 mm tilt). This disclosed "substantially planar" arrangement facilitates direct surface mounting, such as for the example case where the soldering process comprises a solder paste onto a screen (mask) having a thickness of 0.3 to 0.5 mm on a workpiece such as a PCB. Moreover, as shown in FIG. 1A, the molding material 132 along the full length of the bottom surface 130(a) of the package 130 can also be substantially planar throughout (i.e. no indentation regions).
[0020] FIG. IB illustrates an example packaged semiconductor device 150 comprising a leadless package 180, with back side metal 118 of the semiconductor die 110 exposed along a bottom surface 180(a) of the package for direct surface mounting, according to an example
embodiment. Package 180 includes a die pad 125 and plurality of exposed portions shown as perimeter terminating leads 181 (also sometimes referred to as perimeter lands) that do not extend beyond the molding material 132. Perimeter terminating leads 181 are substantially planar to the bottom surface 180(a) of the leadless package 180, and the back side metal 118. Leadless package 180 can comprise a variety of Flat No leads packages such as QFN (Quad Flat No leads) and DFN (Dual Flat No leads). Packaged semiconductor device 150 provides the directly solderability, high level of thermal, reduced assembly cost, reduced board space for PCB assemblies, and the same ease of board layout provided by packaged semiconductor device 100 described above.
[0021] FIG. 2 illustrates an example electronic assembly 200, comprising the packaged semiconductor device 100 shown in FIG. 1A surface mounted using a direct solder connection to a multi-layer PCB 210 comprising at least one internal metal (e.g., copper) plane 211 and a plurality of surface pads 215. Direct solder connections 216 are shown for coupling the back side metal layer 118 and the feet 127(a)(1) of the packaged semiconductor device 100 to ones of the surface pads 215 on the PCB 210, such as copper surface pads.
[0022] Another disclosed embodiment is a method of forming an electronic assembly. A disclosed packaged semiconductor device, such as packaged semiconductor devices 100 or 150 described, is directly solder to a workpiece such as a PCB including a plurality of surface pads. The back side metal layer and the bonding portions of the plurality of leads are directly soldered to substrate pads on the PCB.
[0023] The active circuitry formed on the semiconductor wafers and the semiconductor die therefrom comprise circuit elements that may generally include transistors, diodes, capacitors, and resistors, as well as signal lines and other electrical conductors that interconnect the various circuit elements to provide an IC circuit function. As used herein "provide an IC circuit function" refers to circuit functions from ICs, that for example may include an application specific integrated circuit (ASIC), a digital signal processor, a radio frequency chip, a memory, a microcontroller and a system-on-a-chip or a combination thereof.
[0024] Disclosed embodiments can be integrated into a variety of assembly flows to form a variety of different IC devices and related products. The IC assembly can comprise single semiconductor die or multiple die, such as PoP configurations comprising a plurality of stacked semiconductor die. A variety of package substrates may be used. The semiconductor die may
include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can formed from a variety of processes including bipolar, CMOS, BiCMOS and MEMS.
[0025] Those skilled in the art to which this disclosure relates will appreciate that modifications of the described embodiments and many other embodiments are possible within the scope of the claimed invention.
Claims
1. A packaged semiconductor device, comprising:
a semiconductor die comprising a substrate having a top side including active circuitry and a bottom side, and at least one back side metal layer on said bottom side of said substrate, wherein said back side metal layer is directly attached to said bottom side of said semiconductor die and an area of said back side metal layer matches an area of said bottom side of said semiconductor die;
a package including a molding material having a die pad and a plurality of leads encapsulated within said molding material, wherein said plurality of leads include an exposed portion that includes a bonding portion;
wherein said top side of said semiconductor die is attached to said die pad, and wherein said package includes a gap that exposes said back side metal layer along a bottom surface of said package; and
bond wires coupling pads on said top side of said semiconductor die to said plurality of leads;
wherein said bonding portions, said molding material along said bottom surface of said package, and said back side metal layer are all substantially planar to one another.
2. The device of claim 1, wherein said exposed portions extend laterally beyond said molding material and are bent beyond said molding material; and said bonding portions comprise distal feet.
3. The device of claim 1, wherein said plurality of leads comprises a plurality of perimeter terminating leads that do not extend beyond said molding material; and wherein said plurality of perimeter terminating leads provide said bonding portions.
4. The packaged semiconductor device of claim 1, wherein said back side metal layer comprises copper.
5. The packaged semiconductor device of claim 1, wherein said back side metal layer comprises a first metal layer on said bottom side of said semiconductor die and at least a second metal layer different from said first metal layer on said first metal layer.
6. The packaged semiconductor device of claim 5, wherein said first metal layer comprises titanium.
7. The packaged semiconductor device of claim 5, wherein said first metal layer or said second metal layer comprises nickel.
8. The packaged semiconductor device of claim 5, wherein said first metal layer comprises titanium, said second metal layer comprises nickel, and further comprising a third metal layer on said second metal layer comprising gold or silver.
9. The packaged semiconductor device of claim 1, wherein said molding material along said bottom surface of said package is planar throughout.
10. An electronic assembly, comprising:
a packaged semiconductor device, comprising:
a semiconductor die comprising a substrate having a top side including active circuitry and a bottom side, and at least one back side metal layer on said bottom side of said substrate, wherein said back side metal layer is directly attached to said bottom side of said semiconductor die and an area of said back side metal layer matches an area of said bottom side of said semiconductor die;
a package including a molding material having a die pad and a plurality of leads encapsulated within said molding material, wherein said plurality of leads include an exposed portion that includes a bonding portion;
wherein said top side of said semiconductor die is attached to said die pad, and wherein said package includes a gap that exposes said back side metal layer along a bottom surface of said package; and
bond wires coupling pads on said top side of said semiconductor die to said plurality of leads; and wherein said bonding portions, said molding material along said bottom surface of said package, and said back side metal layer are all substantially planar to one another;
a printed circuit board (PCB) including a plurality of surface pads; and
direct solder connections from said back side metal layer and said bonding portions of said plurality of leads to ones of said plurality of surface pads on said PCB.
11. The electronic assembly of claim 10, wherein said PCB comprises a multi-layer PCB.
12. A method of forming an electronic assembly, comprising:
providing a packaged semiconductor device comprising a semiconductor die including a substrate having a top side including active circuitry and a bottom side, and at least one back side metal layer on said bottom side of said substrate, wherein said back side metal layer is directly attached to said bottom side of said semiconductor die and an area of said back side metal layer matches an area of said bottom side of said semiconductor die; a package including a molding material having a die pad and a plurality of leads encapsulated within said molding material, wherein said plurality of leads include an exposed portion that includes a bonding portion; wherein said bottom side of said semiconductor die is attached to said die pad, wherein said package includes a gap that exposes said back side metal layer along a bottom surface of said package, and bond wires coupling pads on said top side of said semiconductor die to said plurality of leads, and wherein said bonding portions, said molding material along said bottom surface of said package, and said back side metal layer are all substantially planar to one another; and
directly soldering said packaged semiconductor device to a printed circuit board (PCB) including a plurality of surface pads, wherein said back side metal layer and said bonding portions of said plurality of leads are soldered to ones of said plurality of substrate pads on said PCB.
13. The method of claim 12, wherein said exposed portions extend laterally beyond said molding material and are bent beyond said molding material, and said bonding portions comprise distal feet.
14. The method of claim 12, wherein said plurality of leads comprises a plurality of perimeter terminating leads that do not extend beyond said molding material, and wherein said plurality of perimeter terminating leads provide said bonding portions.
15. The method of claim 12, wherein said back side metal layer comprises a first metal layer on said bottom side of said semiconductor die and at least a second metal layer different from said first metal layer on said first metal layer.
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JP2014503986A JP2014515187A (en) | 2011-04-05 | 2012-04-05 | Exposed die package for direct surface mount |
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US13/080,320 | 2011-04-05 |
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Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5714916B2 (en) * | 2011-01-12 | 2015-05-07 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
WO2013175714A1 (en) * | 2012-05-22 | 2013-11-28 | パナソニック株式会社 | Semiconductor device and method for manufacturing same |
DE102013010843A1 (en) * | 2013-06-28 | 2014-12-31 | Wabco Gmbh | Electric control unit |
US9490173B2 (en) * | 2013-10-30 | 2016-11-08 | Infineon Technologies Ag | Method for processing wafer |
US9287227B2 (en) | 2013-11-29 | 2016-03-15 | STMicroelectronics (Shenzhen) R&D Co. Ltd | Electronic device with first and second contact pads and related methods |
US9431319B2 (en) * | 2014-08-01 | 2016-08-30 | Linear Technology Corporation | Exposed, solderable heat spreader for integrated circuit packages |
CN104600047B (en) * | 2014-12-26 | 2017-11-14 | 珠海格力电器股份有限公司 | Power module and packaging method thereof |
US9461005B2 (en) * | 2015-02-12 | 2016-10-04 | Ampleon Netherlands B.V. | RF package with non-gaseous dielectric material |
DE102016117826B4 (en) * | 2016-09-21 | 2023-10-19 | Infineon Technologies Ag | ELECTRONIC MODULE AND PRODUCTION METHOD THEREOF |
US10262926B2 (en) * | 2016-10-05 | 2019-04-16 | Nexperia B.V. | Reversible semiconductor die |
IT201700055921A1 (en) * | 2017-05-23 | 2018-11-23 | St Microelectronics Srl | SEMICONDUCTOR, CIRCUIT AND CORRESPONDENT PROCEDURE |
DE102017120747B4 (en) * | 2017-09-08 | 2020-07-30 | Infineon Technologies Austria Ag | Top cooling SMD package and method of providing it |
KR102468765B1 (en) | 2017-11-29 | 2022-11-22 | 삼성전자주식회사 | Semiconductor package structure and semiconductor Module including the same |
JP2019161105A (en) * | 2018-03-15 | 2019-09-19 | 東芝メモリ株式会社 | Semiconductor device |
CN110752191B (en) * | 2019-10-29 | 2022-02-01 | 维沃移动通信有限公司 | Device packaging module, preparation method of device packaging module and electronic equipment |
US11302615B2 (en) | 2019-12-30 | 2022-04-12 | Texas Instruments Incorporated | Semiconductor package with isolated heat spreader |
US11562949B2 (en) | 2020-06-17 | 2023-01-24 | Texas Instruments Incorporated | Semiconductor package including undermounted die with exposed backside metal |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58101432A (en) | 1981-12-11 | 1983-06-16 | Hitachi Ltd | Back surface electrode structure for semiconductor pellet |
JPS6064457A (en) | 1983-09-19 | 1985-04-13 | Hitachi Ltd | Semiconductor device |
JPH05315526A (en) | 1992-05-08 | 1993-11-26 | Hitachi Ltd | Semiconductor device |
US20060033185A1 (en) | 2004-08-12 | 2006-02-16 | Kummerl Steven A | Integrated circuit chip packaging assembly |
US20080290482A1 (en) | 2007-05-25 | 2008-11-27 | National Semiconductor Corporation | Method of packaging integrated circuits |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5293301A (en) * | 1990-11-30 | 1994-03-08 | Shinko Electric Industries Co., Ltd. | Semiconductor device and lead frame used therein |
US5177669A (en) * | 1992-03-02 | 1993-01-05 | Motorola, Inc. | Molded ring integrated circuit package |
JPH0677358A (en) * | 1992-08-28 | 1994-03-18 | Mitsubishi Electric Corp | Ultrathin surface mounting type package |
JP2551349B2 (en) * | 1993-08-25 | 1996-11-06 | 日本電気株式会社 | Resin-sealed semiconductor device |
JP2556294B2 (en) * | 1994-05-19 | 1996-11-20 | 日本電気株式会社 | Resin-sealed semiconductor device |
US5604376A (en) | 1994-06-30 | 1997-02-18 | Digital Equipment Corporation | Paddleless molded plastic semiconductor chip package |
US5625226A (en) * | 1994-09-19 | 1997-04-29 | International Rectifier Corporation | Surface mount package with improved heat transfer |
US6208513B1 (en) * | 1995-01-17 | 2001-03-27 | Compaq Computer Corporation | Independently mounted cooling fins for a low-stress semiconductor package |
US5869883A (en) * | 1997-09-26 | 1999-02-09 | Stanley Wang, President Pantronix Corp. | Packaging of semiconductor circuit in pre-molded plastic package |
JP3871486B2 (en) * | 1999-02-17 | 2007-01-24 | 株式会社ルネサステクノロジ | Semiconductor device |
US6256200B1 (en) * | 1999-05-27 | 2001-07-03 | Allen K. Lam | Symmetrical package for semiconductor die |
US6208519B1 (en) * | 1999-08-31 | 2001-03-27 | Micron Technology, Inc. | Thermally enhanced semiconductor package |
US6198171B1 (en) * | 1999-12-30 | 2001-03-06 | Siliconware Precision Industries Co., Ltd. | Thermally enhanced quad flat non-lead package of semiconductor |
US6559525B2 (en) * | 2000-01-13 | 2003-05-06 | Siliconware Precision Industries Co., Ltd. | Semiconductor package having heat sink at the outer surface |
TW523887B (en) * | 2001-11-15 | 2003-03-11 | Siliconware Precision Industries Co Ltd | Semiconductor packaged device and its manufacturing method |
US6835592B2 (en) * | 2002-05-24 | 2004-12-28 | Micron Technology, Inc. | Methods for molding a semiconductor die package with enhanced thermal conductivity |
TW556469B (en) * | 2002-08-20 | 2003-10-01 | Via Tech Inc | IC package with an implanted heat-dissipation fin |
US6841858B2 (en) * | 2002-09-27 | 2005-01-11 | St Assembly Test Services Pte Ltd. | Leadframe for die stacking applications and related die stacking concepts |
JP3740116B2 (en) * | 2002-11-11 | 2006-02-01 | 三菱電機株式会社 | Molded resin encapsulated power semiconductor device and manufacturing method thereof |
US7315077B2 (en) * | 2003-11-13 | 2008-01-01 | Fairchild Korea Semiconductor, Ltd. | Molded leadless package having a partially exposed lead frame pad |
US7745927B2 (en) | 2004-06-29 | 2010-06-29 | Agere Systems Inc. | Heat sink formed of multiple metal layers on backside of integrated circuit die |
TWI244185B (en) * | 2004-06-30 | 2005-11-21 | Advanced Semiconductor Eng | Quad flat non leaded package |
US7554179B2 (en) * | 2005-02-08 | 2009-06-30 | Stats Chippac Ltd. | Multi-leadframe semiconductor package and method of manufacture |
US7468548B2 (en) * | 2005-12-09 | 2008-12-23 | Fairchild Semiconductor Corporation | Thermal enhanced upper and dual heat sink exposed molded leadless package |
US7598603B2 (en) * | 2006-03-15 | 2009-10-06 | Infineon Technologies Ag | Electronic component having a power switch with an anode thereof mounted on a die attach region of a heat sink |
US7851908B2 (en) * | 2007-06-27 | 2010-12-14 | Infineon Technologies Ag | Semiconductor device |
US20090026619A1 (en) | 2007-07-24 | 2009-01-29 | Northrop Grumman Space & Mission Systems Corp. | Method for Backside Metallization for Semiconductor Substrate |
US8018050B2 (en) * | 2007-11-01 | 2011-09-13 | National Semiconductor Corporation | Integrated circuit package with integrated heat sink |
US8354740B2 (en) * | 2008-12-01 | 2013-01-15 | Alpha & Omega Semiconductor, Inc. | Top-side cooled semiconductor package with stacked interconnection plates and method |
-
2011
- 2011-04-05 US US13/080,320 patent/US8304871B2/en active Active
-
2012
- 2012-04-05 WO PCT/US2012/032334 patent/WO2012138868A2/en active Application Filing
- 2012-04-05 EP EP12767538.7A patent/EP2727135A4/en not_active Withdrawn
- 2012-04-05 CN CN201280027904.2A patent/CN103703549A/en active Pending
- 2012-04-05 JP JP2014503986A patent/JP2014515187A/en active Pending
- 2012-10-05 US US13/646,199 patent/US8470644B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58101432A (en) | 1981-12-11 | 1983-06-16 | Hitachi Ltd | Back surface electrode structure for semiconductor pellet |
JPS6064457A (en) | 1983-09-19 | 1985-04-13 | Hitachi Ltd | Semiconductor device |
JPH05315526A (en) | 1992-05-08 | 1993-11-26 | Hitachi Ltd | Semiconductor device |
US20060033185A1 (en) | 2004-08-12 | 2006-02-16 | Kummerl Steven A | Integrated circuit chip packaging assembly |
US20080290482A1 (en) | 2007-05-25 | 2008-11-27 | National Semiconductor Corporation | Method of packaging integrated circuits |
Non-Patent Citations (1)
Title |
---|
See also references of EP2727135A4 |
Also Published As
Publication number | Publication date |
---|---|
WO2012138868A3 (en) | 2013-02-21 |
CN103703549A (en) | 2014-04-02 |
US8470644B2 (en) | 2013-06-25 |
US20130034937A1 (en) | 2013-02-07 |
EP2727135A4 (en) | 2015-10-21 |
US8304871B2 (en) | 2012-11-06 |
EP2727135A2 (en) | 2014-05-07 |
JP2014515187A (en) | 2014-06-26 |
US20120256306A1 (en) | 2012-10-11 |
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