WO2012137407A1

WO2012137407A1 - Image display apparatus and method of controlling the same

Info

Publication number: WO2012137407A1
Application number: PCT/JP2012/001518
Authority: WO
Inventors: Koji Kobayashi
Original assignee: Canon Kabushiki Kaisha
Priority date: 2011-04-05
Filing date: 2012-03-06
Publication date: 2012-10-11
Also published as: JP2012220565A

Abstract

Each of pixel circuits includes: a capacitor; a write switch for charging the capacitor with an electric charge corresponding to an image signal; a driving transistor configured to drive an electro-optic device in accordance with a gate voltage based on the electric charge held in the capacitor; and a stop switch configured to stop light emission of the electro-optic device by causing the capacitor to discharge. The stop switches of the pixel circuits in at least two rows are connected to a common stop control line, to stop light emissions of the respective electro-optic devices according to a stop control signal fed thereto through the common stop control line.

Description

IMAGE DISPLAY APPARATUS AND METHOD OF CONTROLLING THE SAME

The present invention relates to an active-matrix type image display apparatus.

Flat panel displays (FPDs) include a liquid crystal display (LCD), a plasma display panel (PDP), an electroluminescent display (ELD), a field emission display (FED), and the like. Among them, the ELD is superior in moving image quality because the ELD is of the self-emitting type which has a low view angle dependence, and has a fast-response property. Further, the ELD of the active-matrix drive type can easily make the definition higher and enjoys a long lifetime because a peak current passing through its display devices can be lowered.

On the other hand, a hold-type image display apparatus using an active-matrix drive system causes a phenomenon so-called "hold blur" by which an image is seen blurred in moving image display. PTL 1 (Japanese Patent Application Laid-Open No. 2001-060076) discloses an image display apparatus which is configured to suppress the hold blur by adjusting a light emitting period (i.e., hold time).

[PTL 1] Japanese Patent Application Laid-Open No. 2001-060076

PTL 1 discloses the following three configurations for adjusting the hold time. Configuration (1) is designed to stop light emission by controlling the potential of a power supply line supplying a power supply potential Vdd to a pixel circuit. Configuration (2) is designed to write a zero luminance (black) signal after having written an image signal. Configuration (3) is provided with a stop control line row by row for stopping light emission. These configurations (1) to (3), however, have the problems described below.

In the case of configuration (1), the power supply lines are electrically separated from each other row by row. For this reason, currents for light emission corresponding to one row of pixels (1920 x 3 = 5760 pixels in the case of full high definition) connected to a power supply line are concentrated on the single power supply line and, hence, a voltage drop attributable to wiring resistance takes place. When the amount of such a voltage drop differs row by row, the light emission luminance fluctuates, which sometimes causes luminance unevenness (so-called "crosstalk") to occur on an image displayed. This problem is known to be relieved by making driving transistors to operate like constant current drive in a saturation region. It is, however, difficult to completely flatten the saturation region characteristics of the transistors and, therefore, this approach has a difficulty in solving the above-described problem satisfactorily. The crosstalk problem can be suppressed if the wiring resistance is reduced by increasing the wire width or thickness. However, another problem arises such that an increase in wire width makes a higher definition difficult because of wiring layout limitations while an increase in wire thickness leads to a higher cost.

In the case of configuration (2), a period for writing the zero luminance signal has to be secured and, therefore, the image signal writing period is reduced to about a half. This makes a higher definition difficult for the reason of occurrence of a writing failure and other reason.

In the case of configuration (3) provided with the dedicated stop control line, the above-described crosstalk problem does not occur because the power supply lines need not be separated from each other on a row-by-row basis, while there is no need to reduce the writing period because writing and light emission stop control can be achieved independently by using respective dedicated lines. However, the number of wiring lines to be provided in the row direction has to be doubled at least, which makes a higher definition difficult because of wiring layout limitations.

The present invention has been made with the foregoing in view. An object of the present invention is to provide a technique to be applied to an active-matrix type image display apparatus for realizing a satisfactory moving image quality and a higher definition while avoiding the problems with the shortage of the writing period and the wiring layout limitations.

The present invention in its first aspect provides an active-matrix type image display apparatus including: a plurality of electro-optic devices arranged in a matrix form; and a plurality of pixel circuits for driving the respective electro-optic devices, wherein each of the pixel circuits includes: a capacitor; a write switch for charging the capacitor with an electric charge corresponding to an image signal; a driving transistor configured to drive one of the electro-optic devices in accordance with a gate voltage based on the electric charge held in the capacitor; and a stop switch configured to stop light emission of the electro-optic device by causing the capacitor to discharge, and wherein the stop switches of the pixel circuits in at least two rows are connected to a common stop control line, to stop light emissions of the respective electro-optic devices according to a stop control signal fed thereto through the common stop control line.

The present invention in its second aspect provides a method of controlling an active-matrix type image display apparatus including a plurality of electro-optic devices arranged in a matrix form and a plurality of pixel circuits for driving the respective electro-optic devices, the pixel circuits each having a capacitor, a driving transistor configured to drive one of the electro-optic devices in accordance with a gate voltage based on an electric charge held in the capacitor, and a stop switch configured to stop light emission of the electro-optic device by causing the capacitor to discharge, at least the stop switches of the pixel circuits in a first row and the stop switches of the pixel circuits in a second row are connected to a common stop control line, the method comprising the steps of: causing the electro-optic device in the first row to start light emission by charging the capacitor of the pixel circuit in the first row with an electric charge corresponding to an image signal; causing the electro-optic device in the second row to start light emission by charging the capacitor of the pixel circuit in the second row with an electric charge corresponding to an image signal; and causing the electro-optic devices in the first and second rows to stop light emission by feeding a stop control signal through the common stop control line.

According to the present invention, an active-matrix type image display apparatus with a satisfactory moving image quality and a higher definition can be realized while avoiding the problems with the writing period shortage and the wiring layout limitations.
Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.

FIG. 1 is a view schematically illustrating the overall configuration of an image display apparatus according to a first embodiment. FIG. 2 is an equivalent circuit diagram of pixel circuits according to the first embodiment. FIG. 3 is a timing chart illustrating an operation of the image display apparatus according to the first embodiment. FIG. 4 is a view illustrating a light emitting state of an image display apparatus according to a third embodiment. FIG. 5 is an equivalent circuit diagram of pixel circuits according to a fourth embodiment. FIG. 6 is a view illustrating a light emitting state of an image display apparatus according to the fourth embodiment. FIG. 7 is a view schematically illustrating the overall configuration of an image display apparatus according to a fifth embodiment. FIG. 8 is an equivalent circuit diagram of pixel circuits according to the fifth embodiment. FIG. 9 is a view illustrating a light emitting state of the image display apparatus according to the fifth embodiment.

The present invention relates to an image display apparatus, and more specifically to a configuration for controlling the light emitting period (i.e., hold time) of each pixel. The present invention is preferably applicable to an active-matrix type image display apparatus having a plurality of electro-optic devices (i.e., display elements) arranged in a matrix form and a plurality of pixel circuits for driving the respective electro-optic devices. The "electro-optic device", as used herein, is meant by a self-emitting device of which the light emission intensity (luminance) is controlled by electric signals (current signals or voltage signals). Examples of such electro-optic devices include an organic light emitting diode (OLED), and a light emitting device comprising an electron emitting device (i.e., cold cathode device) and an electron beam excited fluorescent substance.
Hereinafter, embodiments of the present invention will be described by way of an exemplary ELD using OLEDs as light emitting devices.

(First Embodiment)
FIG. 2 is an equivalent circuit diagram of pixel circuits PXL associated with two pixels arranged on the upper and lower sides. In FIG. 2, reference characters "Vdd", "A", "K", "G", "D", and "S" represent a power supply voltage, an anode, a cathode, a gate, a drain, and a source, respectively.

A scanning line Y is a line which feeds a selection signal for selecting pixel circuits PXL on a row-by-row basis sequentially. A data line X is a line which feeds a data signal for instructing each pixel circuit PXL on a light emission luminance. The data signal is given as a voltage signal corresponding to the value of an image signal (i.e., gradation information). Each pixel circuit PXL is formed at the point of intersection of the scanning line Y and the data line X. The pixel circuit PXL is a circuit for driving an OLED and includes a write switch TFT1, a driving transistor TFT 2, a hold capacitor Cs, and a stop switch TFT3.

The OLED is an electro-optic device of which the luminance varies in accordance with the amount of current fed thereto. The write switch TFT1 is a transistor controlled by the selection signal fed thereto through the scanning line Y. When the write switch TFT1 is ON, the write switch TFT1 charges the hold capacitor Cs with an electric charge corresponding to the data signal fed from the data line X. By so doing, gradation information is written into the pixel circuit PXL. The driving transistor TFT2 controls an electric signal (the amount of current in the present embodiment) to be fed to the OLED in accordance with the gate voltage based on the electric charge held by the hold capacitor Cs. Because the gradation information written in the pixel circuit PXL is held in the hold capacitor Cs even after the scanning line Y has assumed an unselected state, the light emitting state of the OLED is maintained.

The stop switch TFT3 is a transistor for stopping the operation (i.e., light emission) of the OLED. The stop switch TFT3 is turned ON and OFF by a stop control signal fed to the gate G through a stop control line Z. When the stop switch TFT3 is turned ON, the hold capacitor Cs is caused to discharge. As a result, voltage Vgs across the gate-source of the driving transistor TFT2 assumes 0 V to cut off the drive current passing through the OLED, thereby turning OFF the OLED. In the present embodiment, the stop switches TFT3 of the pixel circuits PXL in two rows arranged on the upper and lower sides have the respective gates G connected to the common stop control line Z and, accordingly, light emission stop control is performed on every two rows.

FIG. 1 schematically illustrates the overall configuration of the image display apparatus. The above-described circuit diagram of FIG. 2 corresponds to a portion depicted by broken line of FIG. 1. Scanning lines Y1, Y2, ..., and YN are arranged to extend along rows, while data lines X arranged to extend along columns. The pixel circuits PXL are each formed at a respective one of the points of intersection of the scanning lines Y and the data lines X. Stop control lines Z1, Z2, ..., and ZN/2 are formed to extend parallel with the scanning lines Y1, Y2, ..., and YN. The stop control lines Z are arranged in such a manner that one stop control line Z is provided for one pair of scanning lines Y extending along an odd-numbered row (first row) and an even-numbered row (second row).

The scanning lines Y are connected to a scanning line drive circuit 21. The scanning line drive circuit 21 includes a shift register and selects the scanning lines Y1, Y2, ..., and YN sequentially by transferring vertical start pulses VSP1 sequentially in synchronization with vertical clocks VCK. In cases where the frame frequency is 60 Hz for example, one scanning cycle is 1/60 second, and each scanning line Y is selected once per scanning cycle. On the other hand, the stop control lines Z are connected to a light emission stop control circuit 23. The light emission stop control circuit 23 also includes a shift register and outputs stop control signals to the stop control lines Z1, Z2, ..., and ZN/2 sequentially by transferring vertical start pulses VSP2 sequentially in synchronization with the vertical clocks VCK. The pulses VSP2 are each delayed by a predetermined time from a respective one of the pulses VSP1 by a delay circuit 24.

The data lines X are connected to a data line drive circuit 22. The data line drive circuit 22 outputs data signals to the respective data lines X in synchronization with line sequential scanning by the scanning lines Y. In outputting the data signals, the data line drive circuit 22 performs the so-called line sequential driving by which the data signals are fed to all the pixels in a selected row at a time. An image processing circuit 20 is a circuit configured to perform necessary signal processing (e.g., IP conversion, color conversion, gradation conversion, frame frequency conversion, and the like) on an image signal inputted to the image display apparatus and then outputs the image signal thus converted to the data line drive circuit 22. The data line drive circuit 22, in turn, generates a data signal (voltage signal) corresponding to the value of the image signal fed from the image processing circuit 20.

FIG. 3 is a timing chart illustrating an operation of the image display apparatus. Initially, the vertical start pulse VSP1 is inputted to the scanning line drive circuit 21 and the delay circuit 24. After receipt of the pulse VSP1 inputted, the scanning line drive circuit 21 selects the scanning lines Y1, Y2, ..., and YN sequentially in synchronization with the vertical clocks VCK. In synchronization with this scanning operation, the data line drive circuit 22 feeds data signals to write gradation information into the pixel circuits PXL scanning line by scanning line. The OLED of each pixel circuit PXL starts emitting light at an intensity according to the gradation information thus written.

The pulse VSP1 is delayed by the delay circuit 24 and inputted as the pulse VSP2 to the light emission stop control circuit 23. After receipt of the pulse VSP2, the light emission stop control circuit 23 outputs stop control signals to the stop control lines Z1, Z2, ..., and ZN/2 sequentially in synchronization with the vertical clocks VCK. At that time, the shift register of the light emission stop control circuit 23 shifts the pulse VSP2 every two cycles of vertical clock VCK. As a result, light emission is stopped on the basis of every two rows such as scanning lines Y1 and Y2, scanning lines Y3 and Y4, ..., and scanning lines YN-1 and YN.

In this configuration, the light emitting period of each pixel is a period from the time when the gradation information is written into the pixel circuit PXL until light emission is stopped by the stop control signal. The length of the light emitting period is substantially equal to the length of a delay time set by the delay circuit 24. The ratio of light emission of each pixel in terms of time, namely, the duty is about t/T, where t represents the delay time and T represents one scanning cycle (one frame period). Strictly speaking, the light emitting period of a pixel in an odd-numbered row is slightly different from that of a pixel in an even-numbered row (as indicated a portion A in FIG. 3). In the present embodiment, however, the difference in luminance which reflects the difference A is considered allowable.

With the above-described configuration according to the present embodiment, it is possible to suppress the hold blur thereby to improve the moving image quality by appropriately adjusting the light emitting period based on the delay time t set by the delay circuit 24. Since the number of the stop control lines Z required by the present configuration can be reduced to a half of the number of stop control lines required by a conventional configuration in which a stop control line is provided for every row, the definition can be easily made higher. Since the number of output stages of the light emission stop control circuit 23 can also be reduced to a half of the number of the scanning lines, the circuit scale can be reduced, which leads to a reduced cost. Further, image quality degradation due to crosstalk can hardly occur because little current passes through the stop control lines Z except currents for charging and discharging parasitic capacitances.

(Second Embodiment)
According to the first embodiment, the light emitting period of a pixel in an odd-numbered row is longer than that of a pixel in an even-numbered row by a period of selection of one row, as indicated by the portion A in FIG. 3. This is because the two scanning lines sharing a stop control line Z share the same light emission stop timing, whereas the light emission start timing differs scanning line by scanning line. As a result, the pixel in the odd-numbered row is slightly brighter than the pixel in the even-numbered row when the same gradation information is written into these pixels.

The difference between the lengths of light emitting periods can be expressed as T/N and the luminance change ratio between an odd-numbered row and an even-numbered row into which the same gradation information is written can be expressed as T/(N x t), where N represents the total number of scanning lines, t represents the light emitting period of the odd-numbered row (corresponding to the delay time), and T represents one scanning cycle (i.e., one frame period). A luminance difference detection limit is generally said to be about 1%, though depending on the brightness of an image. Therefore, when T/(N x t) is more than about 0.01, that is, when the duty (t/T) is smaller than about 100/N, luminance unevenness is sometimes recognized visually.

To avoid such an inconvenience, the image display apparatus according to the present embodiment sets the light emission stop timing, i.e., the delay time of the delay circuit 24 such that the duty satisfies the following conditional expression:
duty > 100/N, where N is the number of scanning lines.
When the duty becomes too large, it is possible that the hold blur takes place and, hence, the moving image quality is lowered. For this reason, the upper limit of the duty is simply determined by the following conditional expression:
duty > Dmax.
In this expression, Dmax is a value of the duty at which the hold blur reaches an allowable limit. A specific Dmax value can be determined from experiments on subjects. Dmax may be a fixed value or may be altered depending on the frame frequency, the brightness of an image, the moving amount of the image, or the like.
The light emitting period control described above makes it possible to render luminance unevenness suppression and hold blur suppression compatible with each other thereby to realize high quality moving image display.

The above-described method according to the second embodiment cannot be utilized when 100/N is not smaller than Dmax. For this reason, each of the third and fourth embodiments described below is provided with separate means for suppressing luminance unevenness attributable to the difference between the lengths of light emitting periods of a plurality of rows connected to a common stop control line.

(Third Embodiment)
The third embodiment is configured to suppress luminance unevenness attributable to the difference between the lengths of light emitting periods by correcting the image signal (i.e., gradation value). Detailed description below is directed to those features of the third embodiment which are different from the first embodiment.

FIG. 4 illustrates a light emitting state of an odd-numbered row and that of an even-numbered row. The horizontal axis represents time and the vertical axis represents the light emission intensity. Light emission start timing and light emission stop timing are controlled in the same manner as in the first embodiment (see FIG. 3). The light emitting period of the odd-numbered row is longer than that of that even-numbered row, as indicated by the portion A. A brightness that can be sensed by human is equivalent to the time integral of a light emission intensity, specifically, each of the area defined by the graph of FIG. 4. Therefore, in order to eliminate the difference in brightness between the odd-numbered row and the even-numbered row, the light emission intensities of these rows are simply adjusted so as to make the areas defined by the graph of FIG. 4 equal to each other.

In the present embodiment, an image signal to be fed to the odd-numbered row (i.e., the light emission intensity of the odd-numbered row) is lowered so as to make the area of the portion A and the area of the portion B in FIG. 4 equal to each other. In cases where the light emitting period of the odd-numbered row is longer by 2% than that of the even-numbered row for example, it is sufficient that the image signal to be fed to the odd-numbered row is multiplied by a gain such as to lower the image signal by 2% (e.g., 0.98). In cases where the value of the image signal and the light emission intensity are not proportional to each other, it is sufficient to carry out a process in which the image signal is converted to a signal which is linear relative to the light emission intensity and then the signal is multiplied by the gain or a process using a gain value determined in view of the nonlinear relation between the image signal and the light emission intensity. These processes are carried out by the image processing circuit 20 of FIG. 1.

The configuration described above can suppress luminance unevenness attributable to the difference between the lengths of light emitting periods. Unlike the second embodiment, the third embodiment does not have a lower limit (limitation) of the duty and hence can set the duty to a value of not more than 1/N when necessary. Thus, the third embodiment can suppress the hold blur reliably.

While the present embodiment corrects the image signal to be fed to the odd-numbered row, the same effect will result when correction is made to the image signal to be fed to the even-numbered row or to the image signals to be fed to the odd-numbered row and the even-numbered row both. However, the subject to be corrected is preferably the image signal to be fed to the row which has a longer light emitting period. This is because in cases where correction is made to the image signal to be fed to the row which has a shorter light emitting period, the value of the image signal is increased (i.e., multiplied by a gain of more than 1 for example) and, hence, additional means (e.g., limiter circuit) is necessary for preventing the corrected value from overflowing.

(Fourth Embodiment)
When the odd-numbered row and the even-numbered row are different in light emitting period from each other as described above, it is possible that an edge of an object in a quickly moving image is seen jaggy when the viewer follows such a quick movement. This is because a picture provided by rows having a longer light emitting period is seen wider than that provided by rows having a shorter light emitting period because of after image. To prevent this inconvenience, the fourth embodiment is configured to vary an attenuation rate (for example, time constant) during stopping light emission to lessen the difference in light emitting period between rows. Detailed description below is directed to those features of the fourth embodiment which are different from the first embodiment.

FIG. 5 is an equivalent circuit diagram of pixel circuits according to the fourth embodiment. The fourth embodiment is different from the first embodiment (see FIG. 2) in that a resistance R is additionally provided on the source side of a stop switch TFT32 of each pixel circuit PXL in an even-numbered row.

FIG. 6 illustrates a light emitting state of an odd-numbered row and that of an even-numbered row. The horizontal axis represents time and the vertical axis represents the light emission intensity. Light emission start timing and light emission stop timing are controlled in the same manner as in the first embodiment (see FIG. 3). In stopping light emission, the gate G of a stop switch TFT31 in the odd-numbered row and the gate G of the stop switch TFT32 in the even-numbered row are both applied with a light emission stop signal simultaneously through the common stop control line Z. At that time, a hold capacitor Cs1 of each pixel circuit PXL in the odd-numbered row discharges electric charge quickly to stop light emission immediately. In each pixel circuit PXL in the even-numbered row, on the other hand, the resistance R functions to cause a hold capacitor Cs2 to discharge electric charge slowly and, therefore, the amount of drive current through a driving transistor TFT22 (i.e., the light emission intensity of the OLED) is attenuated with a predetermined time constant. As a result, the difference in light emitting period between the odd-numbered row and the even-numbered row is lessened.

The time constant mentioned above is determined from the hold capacitor Cs2, resistance R, parasitic capacitance and parasitic resistance around other discharge path, gate capacitance of the stop switch 32, and the like. Therefore, the size, structure, characteristics and other features of each element of the pixel circuit PXL are simply set so that a portion C of FIG. 6 has the same area as the portion A. For example, the resistance R can be practically adjusted because the ON-resistance of the stop switch TFT32 can be adjusted by varying the gate width and length. If the attenuation rate of the light emission intensity (i.e., drive current) is adjusted, any one of the factors including the hold capacitor Cs2, resistance R2, and parasitic capacitance and parasitic resistance around other discharge path may be varied.

With the configuration described above, it is possible to lessen the difference in light emitting period between rows, thereby to suppress jaggy which is seen when the viewer follows a quickly moving image. Further, luminance unevenness can be suppressed by making the area of the portion A and that of the portion C equal to each other as shown in FIG. 6. In addition, unlike the third embodiment, the present embodiment has an advantage that little increase is incurred in production cost because the present embodiment does not need any special circuit for correcting the image signal and hence can be practiced by merely changing the exposure mask pattern for the fabrication of a display panel substrate.

(Fifth Embodiment)
Detailed description below is directed to those features of the fifth embodiment which are different from the first embodiment.

FIG. 7 is a view schematically illustrating the overall configuration of an image display apparatus according to the fifth embodiment. FIG. 8 is an equivalent circuit diagram of pixel circuits in four rows which corresponds to a portion indicated by broken line of FIG. 7. The present embodiment is different from the first embodiment in that two stop control lines Z are connected to the same output stage of the light emission stop control circuit 23 to control the pixel circuits in four rows by means of the same stop control signal and that the pixel circuits in the four rows have different attenuation rates of drive current.

Specifically, as shown in FIG. 7, one stop control line Z is provided for every two scanning lines Y extending along two rows, and lead portions of two stop control lines Z are tied together and connected to a single output stage of the light emission stop control circuit 23. Accordingly, the number of output stages of the light emission stop control circuit 23 according to the present embodiment is a half of the number of output stages of the light emission stop control circuit 23 according to the first embodiment.

As shown in FIG. 8, the stop switches TFT32, TFT33 and TFT34 of the pixel circuits PXL in the second to fourth rows of a group of four rows are provided with resistances R2, R3 and R4, respectively. In stopping light emission, the drive current attenuation rate can be lowered in the order of the first to fourth pixel circuits by setting the resistance value ratio of R2:R3:R4 to 1:2:3. A specific method of forming each of the resistances is the same as in the fourth embodiment.

FIG. 9 illustrates light emitting states of respective of the first to fourth pixel circuits. The horizontal axis represents time and the vertical axis represents the light emission intensity. Light emission start timing and light emission stop timing are controlled in the same manner as in the first embodiment (see FIG. 3). The resistances R2 to R4 function to make a light emission intensity drop of a row slower than that of the immediately preceding row. As a result, the differences in light emission period between the four rows are lessened.

The configuration described above can exercise, in addition to the effects of the preceding embodiments, the effect that the circuit scale and the cost can be reduced by further reducing the number of output stages of the light emission stop control circuit 23.

While two stop control lines Z are connected to the same output stage according to the present embodiment, the number of output stages of the light emission stop control circuit 23 can be further reduced by connecting a larger number of stop control lines Z to the same output stage. The present embodiment suppresses luminance unevenness attributable to the difference between light emitting periods by means of the resistances R2 and R3. However, the same effect can be obtained by adjusting the hold capacitor, gate capacitance and the like as described in the fourth embodiment or correcting the image signal as described in the third embodiment. In cases where the luminance unevenness problem does not arise as in the first and second embodiments, any arrangement for suppressing luminance unevenness is not necessary.

The forgoing embodiments are merely specific examples of the present invention which are not limitative of the present invention. For example, any one of the foregoing embodiments has the feature that pixel circuits in two rows are connected to a single stop control line, but the present invention may have a feature that pixel circuits in three or more rows are connected to a common stop control line. The present invention is applicable to ELDs as well as any other image display apparatus of the active-matrix drive type which includes a plurality of electro-optic devices and pixel circuits each configured to output an electric signal for driving a respective one of the electro-optic devices. For example, the present invention is applicable to an FED using as an electro-optic device a light emitting device comprising an electron emitting device and a fluorescent substance. A pixel circuit of such an FED preferably uses a source follower for driving the electron emitting device by voltage signals. The present invention is also applicable to an image display apparatus having other pixel circuits (such as various pixel circuits for compensating for characteristic fluctuations of TFTs). In the foregoing embodiments, the switches and driving transistors are each simply constructed of a field effect transistor, which is preferably a thin film transistor.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
This application claims the benefit of Japanese Patent Application No. 2011-083684, filed on April 5, 2011, which is hereby incorporated by reference herein in its entirety.

Claims

An active-matrix type image display apparatus comprising: a plurality of electro-optic devices arranged in a matrix form; and
a plurality of pixel circuits for driving the respective electro-optic devices,
wherein each of the pixel circuits includes:
a capacitor;
a write switch for charging the capacitor with an electric charge corresponding to an image signal;
a driving transistor configured to drive one of the electro-optic devices in accordance with a gate voltage based on the electric charge held in the capacitor; and
a stop switch configured to stop light emission of the electro-optic device by causing the capacitor to discharge, and
wherein the stop switches of the pixel circuits in at least two rows are connected to a common stop control line, to stop light emissions of the respective electro-optic devices according to a stop control signal fed thereto through the common stop control line.
The image display apparatus according to claim 1, wherein timing for stopping the light emissions of the electro-optic devices by the stop control signal is determined such that a duty which is a ratio of a light emitting period of each of the electro-optic devices to one scanning cycle satisfies duty > 100/N, where N represents the number of scanning lines.
The image display apparatus according to claim 1 or 2, further comprising means for suppressing luminance unevenness attributable to a difference between lengths of light emitting periods of a plurality of rows connected to the common stop control line.
The image display apparatus according to claim 3, wherein the means for suppressing luminance unevenness is a circuit configured to make an image signal correction by decreasing the image signal to be fed to the row which has a longer light emitting period or increasing the image signal to be fed to the row which has a shorter light emitting period.
The image display apparatus according to claim 3, wherein the means for suppressing luminance unevenness is a circuit configured to make a light emission intensity attenuation rate of the electro-optic devices in the row which has a shorter light emitting period slower than a light emission intensity attenuation rate of the electro-optic devices in the row which has a longer light emitting period when the light emission is stopped by the stop switch.
The image display apparatus according to any one of claims 1 to 5, further comprising a light emission stop control circuit having a plurality of output stages for outputting the stop control signal,
wherein two or more stop control lines are connected to a same output stage of the light emission stop control circuit.
A method of controlling an active-matrix type image display apparatus including a plurality of electro-optic devices arranged in a matrix form and a plurality of pixel circuits for driving the respective electro-optic devices,
the pixel circuits each having a capacitor, a driving transistor configured to drive one of the electro-optic devices in accordance with a gate voltage based on an electric charge held in the capacitor, and a stop switch configured to stop light emission of the electro-optic device by causing the capacitor to discharge,
at least the stop switches of the pixel circuits in a first row and the stop switches of the pixel circuits in a second row are connected to a common stop control line,
the method comprising the steps of:
causing the electro-optic device in the first row to start light emission by charging the capacitor of the pixel circuit in the first row with an electric charge corresponding to an image signal;
causing the electro-optic device in the second row to start light emission by charging the capacitor of the pixel circuit in the second row with an electric charge corresponding to an image signal; and
causing the electro-optic devices in the first and second rows to stop light emission by feeding a stop control signal through the common stop control line.