WO2012133277A1 - Dispositif de traitement de signal, programme de contrôle et circuit intégré - Google Patents

Dispositif de traitement de signal, programme de contrôle et circuit intégré Download PDF

Info

Publication number
WO2012133277A1
WO2012133277A1 PCT/JP2012/057706 JP2012057706W WO2012133277A1 WO 2012133277 A1 WO2012133277 A1 WO 2012133277A1 JP 2012057706 W JP2012057706 W JP 2012057706W WO 2012133277 A1 WO2012133277 A1 WO 2012133277A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
frequency
vertical
input
time
Prior art date
Application number
PCT/JP2012/057706
Other languages
English (en)
Japanese (ja)
Inventor
清一 合志
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to CN201280010961.XA priority Critical patent/CN103404131B/zh
Publication of WO2012133277A1 publication Critical patent/WO2012133277A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
    • H04N7/012—Conversion between an interlaced and a progressive signal

Definitions

  • the present invention relates to a signal processing device, a control program, and an integrated circuit that perform signal processing on a video signal after interlace-progressive conversion.
  • interlaced scanning method also referred to as interlaced scanning
  • progressive scanning method also referred to as sequential scanning
  • the interlace scanning method is a method of scanning the screen every other line.
  • one frame is composed of two fields. That is, one frame includes a first field that scans odd-numbered lines and a second field that scans even-numbered lines. These lines are called scanning lines.
  • one frame is acquired at 1/30 second intervals. Then, the first field and the second field are scanned at 1/60 second intervals. That is, one field is displayed at 60 Hz. In Europe and other regions, there is a place where one field is displayed at 50 Hz.
  • the progressive scanning method is a method of scanning line by line from the top to the bottom of the screen. That is, in the progressive scanning method, one frame is acquired by one sequential scanning.
  • an interlace signal scanned by an interlace scanning method is transmitted in order to efficiently transmit a video within a limited transmission band.
  • an interlace scanning method is also used for a recording method such as a DVD (Digital Versatile Disk).
  • liquid crystal displays that display content such as TV broadcasts and DVDs, and PDPs (plasma display panels) display images by a progressive scanning method.
  • FIG. 11A is a graph showing the position of the scanning line in interlaced scanning in the time-vertical direction.
  • FIG. 11B is a graph showing the position of the scanning line in the progressive scanning in the time-vertical direction.
  • Circles shown in (a) and (b) of FIG. 11 shows the scanning lines P 100. Further, in the time direction (frame direction) of the graph shown in FIG. 11A, the interval Ti between the first field Fld1 and the second field Fld2 is 1/60 ms. Further, the scanning line of the first field Fld1 and the scanning line of the second field Fld2 appear at positions shifted by an interval L. The interval L is 1125 TV lines.
  • the interframe Tp is 1/60 ms.
  • the interval L is 1125 TV lines.
  • IP conversion interlace-progressive conversion
  • Non-Patent Document 1 As an example of a technique for realizing IP conversion, a technique for performing inter-field interpolation, a technique for performing intra-field interpolation, and the like can be cited (see Non-Patent Document 1).
  • the inter-field interpolation method is a method in which the value of the scanning line of the previous field is delayed as it is for 1/60 second and used as the value of the scanning line of the current field.
  • An arrow A1 in FIG. 12 shows a state of inter-field interpolation. That is, the scanning line P ′ 100 indicated by a black circle in FIG. 12 is a point to be interpolated, and the value of the scanning line P ′ 100 is acquired from the scanning line P 103 of the immediately preceding field.
  • the progressive part of the image will be doubled or the interlace structure will be visible in the progressive video. It has been known.
  • the method of performing intra-field interpolation is a method of supplementing the average value of the adjacent scanning lines as the value of the scanning line between the adjacent scanning lines in the same field.
  • An arrow A2 in FIG. 12 shows the state of intra-field interpolation. That is, the value of the scanning line P ′ 100 in FIG. 12 is an average value of the scanning lines P 101 and P 102 above and below the scanning line P ′ 100 in the same field.
  • the vertical resolution is halved, but the image deterioration as described above can be suppressed.
  • Non-Patent Document 1 also proposes a technique that adaptively combines the inter-field interpolation and the intra-field interpolation.
  • Non-Patent Document 1 discloses that motion detection is performed in units of pixels, intra-field interpolation is applied to the motion portion, and inter-field interpolation is applied to the stationary portion.
  • a weighted sum of values obtained by the inter-field interpolation and the intra-field interpolation is adaptively determined according to the degree of motion.
  • motion detection is accompanied by erroneous detection, and a part that does not actually move may be detected as a moving part, or a part that actually moves may be detected as a stationary part.
  • interline flicker when a video is played back based on an IP converted progressive signal, for example, when the caption super is scrolled in the vertical direction, a phenomenon that the periphery of the character outline flickers remarkably appears. Such flicker is called interline flicker.
  • Patent Document 1 discloses a technique for reducing interline flicker in interlace-interlace conversion, but reduces interline flicker that occurs when video is reproduced based on an IP-converted progressive signal. It does not solve the problem of making it happen.
  • the present invention has been made in view of the above problems, and its purpose is to provide a signal processing device that can reduce interline flicker that occurs when video is reproduced based on an IP-converted progressive signal, It is to realize a control program and an integrated circuit.
  • a signal processing apparatus uses a progressive signal by a progressive scanning method converted from an interlace signal obtained by interlace scanning an image as an input signal.
  • a signal processing apparatus that outputs a progressive signal subjected to signal processing as an output signal, the point at which a DC signal folds in a time-vertical frequency region of an interlace signal (a DC component of a two-dimensional sampling frequency in discretization by scanning)
  • the output signal is generated by removing, from the input signal, a frequency band excluding the frequency band in which the carrier appears in the time-vertical frequency region of the progressive signal from the frequency band in which the carrier that is a repeated point) appears. Having frequency component removing means And butterflies.
  • an integrated circuit uses a progressive scanning system converted from an interlace signal obtained by interlace scanning an image as an input signal, 1 or a plurality of line delay elements that output a line delay signal obtained by delaying the input video signal by one line in the vertical direction, and which are connected in cascade.
  • the line delay circuit in which the input signal is input to the line delay element in the foremost stage, and the output signal is obtained by adding each of the input signal and the line delay signal multiplied by a weighting factor. And an adding circuit to be generated.
  • an integrated circuit uses a progressive scanning system converted from an interlace signal obtained by interlace scanning an image as an input signal, A time-frequency component removal circuit that generates a time-low frequency removal signal by removing a low-frequency component of the time frequency in the input signal, and an integrated circuit that outputs a progressive signal subjected to signal processing as an output signal; A vertical frequency component removing circuit for generating a vertical low frequency removal signal by removing a low frequency component of a vertical frequency in the time low frequency removal signal, and the output signal by subtracting the vertical low frequency removal signal from the input signal. And a subtracting circuit for generating.
  • interlace signal an interlace signal carrier (hereinafter referred to as interlace signal) is detected in an IP converted progressive signal. May appear).
  • an interlace carrier that is a carrier in the time-vertical frequency domain of an interlaced signal and not a carrier in the time-vertical frequency domain of a progressive signal may appear.
  • an interlace signal is 2/60 seconds and 1 frame (1 field in 1/30 seconds), and a progressive signal is 1 frame in 1/60 seconds
  • the time-vertical frequency region of the progressive signal is around 30 Hz.
  • an interlace carrier of an interlace signal appears.
  • the interlace is near 1 / (2 * 1125 TV lines) in the time-vertical frequency domain of the IP converted progressive signal. A career may appear.
  • the interlace carrier is removed from the progressive signal.
  • the processing for removing the frequency band can be realized by, for example, a time direction low-pass filter, a vertical direction low-pass filter, or a combination thereof.
  • the signal processing apparatus uses the progressive signal converted from the interlace signal obtained by interlaced scanning the image as the input signal, and performs signal processing on the input signal.
  • a signal processing apparatus that outputs a progressive signal as an output signal, and a point at which a DC signal is folded back in the time-vertical frequency domain of an interlaced signal (a point at which a DC component of a two-dimensional sampling frequency repeatedly appears in discretization by scanning)
  • the integrated circuit according to the present invention uses a progressive signal by a progressive scanning method converted from an interlaced signal obtained by interlaced scanning an image as an input signal, and a progressive signal obtained by performing signal processing on the input signal.
  • An integrated circuit that outputs as an output signal, and is formed by connecting one or a plurality of line delay elements that output a line delay signal obtained by delaying an input video signal by one line in the vertical direction.
  • a line delay circuit in which the input signal is input to an element; and an adder circuit that generates the output signal by adding each of the input signal and the line delay signal multiplied by a weighting factor. is there.
  • the integrated circuit according to the present invention uses a progressive signal by a progressive scanning method converted from an interlaced signal obtained by interlaced scanning an image as an input signal, and a progressive signal obtained by performing signal processing on the input signal.
  • An integrated circuit that outputs as an output signal, a time frequency component removal circuit that generates a time low frequency removal signal by removing a low frequency component of the time frequency in the input signal, and a vertical frequency in the time low frequency removal signal
  • a vertical frequency component removal circuit that generates a vertical low frequency removal signal by removing the low frequency component of the signal, and a subtraction circuit that generates the output signal by subtracting the vertical low frequency removal signal from the input signal It is.
  • the interlace carrier and the spectrum due to the interlace carrier can be removed.
  • FIG. 1 It is a block diagram which illustrates about a schematic structure of a display apparatus provided with the interlace carrier removal part which concerns on one Embodiment of this invention. It is a figure which illustrates about the circuit structure of the vertical direction low-pass filter circuit which implement
  • (A) shows one configuration example, and (b) shows an equivalent circuit of the configuration example. It is a figure explaining the characteristic in the frequency band of an interlace signal and a progressive signal.
  • (A) is a schematic diagram showing carriers in a time-vertical frequency domain of an interlace signal.
  • (B) and (c) are schematic diagrams showing carriers in a time-vertical region in a progressive signal.
  • FIG. 6 is a diagram showing the position of a scanning line by progressive scanning in a time direction (frame direction) t-vertical direction y region.
  • 10 shows an example of the configuration of a time direction-vertical direction filter processing circuit that realizes an interlace carrier removal unit according to another embodiment of the present invention. It is a figure which shows the specific structure of the time direction high-pass filter with which the said time direction-vertical direction filter processing circuit is provided. It is a figure which shows the specific structure of the vertical direction high-pass filter with which the said time direction-vertical direction filter processing circuit is provided.
  • FIG. 6 is a graph showing the position of the scanning line in the time-vertical direction, where (a) shows an interlaced scan and (b) shows a progressive scan.
  • FIG. 4 is a diagram illustrating inter-field interpolation and intra-field interpolation in interlace-progressive conversion.
  • FIG. 1 is a block diagram illustrating a schematic configuration of the display device 1.
  • the display device 1 includes an MPEG (Moving Picture Experts Group) decoder 11, an IP (Interlace-Progressive) conversion unit 12, an interlace carrier removal unit 13, and a display unit 14.
  • MPEG Motion Picture Experts Group
  • IP Interlace-Progressive
  • An MPEG (Moving Picture Experts Group) decoder 11 has an antenna for receiving a television broadcast wave, and demodulates and decodes the received television broadcast wave to generate an interlace signal. Then, the MPEG decoder 11 supplies the generated interlace signal to the IP conversion unit 12.
  • MPEG Motion Picture Experts Group
  • the IP conversion unit 12 progressively converts the interlace signal supplied from the MPEG decoder 11 by interlace-progressive conversion. Then, the IP conversion unit 12 supplies the progressive signal # 12 obtained by the progressive process to the interlace carrier removal unit 13.
  • the interlace carrier removing unit 13 performs a filtering process on the progressive signal # 12 in order to reduce interline flicker during video reproduction.
  • the interlace carrier removing unit 13 is realized by the vertical direction low-pass filter circuit (frequency component removing means) 130 (see FIG. 2)
  • the interlace carrier removal unit 13 supplies the display unit 14 with an interlace carrier removed signal # 13 that is a progressive signal after the filter processing.
  • the display unit 14 displays an image on the screen according to the interlace carrier removed signal # 13 supplied from the interlace carrier removal unit 13.
  • the display unit 14 displays an image by a progressive scanning method, such as a liquid crystal display or a PDP (plasma display panel).
  • interlace carrier removing processing (About the principle of the interlace carrier removal processing by the interlace carrier removal unit) Before describing the specific configuration of the interlace carrier removing unit 13, the following describes the principle of filter processing (hereinafter referred to as interlace carrier removing processing) performed in the interlace carrier removing unit 13, with reference to FIG. To do.
  • FIG. 3 is a diagram for explaining the characteristics of the interlaced signal and the progressive signal in the frequency domain.
  • FIG. 3A is a schematic diagram showing a carrier that is a point at which a DC signal turns back in a time-vertical frequency region of an interlace signal (a point at which a DC component of a two-dimensional sampling frequency repeatedly appears in discretization by scanning). is there.
  • (B) and (c) of FIG. 3 are schematic diagrams showing carriers of spectral intensity in the time-vertical region in the progressive signal.
  • the horizontal axis is the frequency (Hz) and the vertical axis is the vertical component.
  • the carrier C is indicated by a black dot.
  • the intensity of the frequency spectrum of the carrier C is stronger than the frequency spectrum near the carrier C, and is about 1000 times stronger than the weakest position.
  • interlace-to-progressive conversion converts the interlaced signal having the carrier arrangement shown in FIG. 3A into a progressive signal having the carrier arrangement shown in FIG. 3B. Is done.
  • motion detection is accompanied by false detection.
  • the frequency spectrum characteristic of the interlace signal affects the frequency spectrum of the progressive signal after the interlace-progressive conversion.
  • a carrier that is a carrier in the time-vertical frequency domain of the interlace signal and is not a carrier in the time-vertical frequency domain of the progressive signal (hereinafter referred to as an interlace carrier) may appear in the progressive signal.
  • edge portion degradation that is, interline flicker becomes conspicuous in the reproduced video.
  • the interlace carrier removal unit 13 performs an interlace carrier removal process by removing the interlace carrier F from the progressive signal.
  • the interlace carrier removing unit 13 can be realized by, for example, the configuration described below.
  • FIG. 2A shows a configuration example when the interlace carrier removing unit 13 is realized by the vertical low-pass filter circuit 130
  • FIG. 2B shows the vertical low-pass filter circuit 130 shown in FIG.
  • the equivalent circuit which has a function equivalent to is shown.
  • the vertical low-pass filter circuit 130 outputs an interlace carrier removed signal # 13 subjected to an interlace carrier removal process by removing a high frequency component of a vertical frequency in the progressive signal # 12 input from the outside.
  • the progressive signal # 12 is obtained by IP conversion of the interlace signal by the IP conversion unit 12 as described above.
  • the vertical low-pass filter circuit 130 includes one-line delay circuits (line delay elements, line delay means) 131 and 132, coefficient units (addition means) 134, 135A and 135B, and adders. (Adding means) 136 and a weighting coefficient setting unit (weighting coefficient setting means) 137.
  • the progressive signal # 12 is first supplied to the one-line delay circuit 131, the coefficient unit 135A, and the weighting coefficient setting unit 137.
  • the 1-line delay circuit 131 generates a 1-line delay signal # 131 obtained by delaying the progressive signal # 12 by one line.
  • the 1-line delay circuit 131 supplies the 1-line delay signal # 131 to the 1-line delay circuit 132 and the coefficient unit 134.
  • the 1-line delay circuit 132 further delays the 1-line delay signal # 131 supplied from the 1-line delay circuit 131 by one line, that is, two lines compared to the original progressive signal # 12. 132 is generated.
  • the 1-line delay circuit 132 supplies the generated 2-line delay signal # 132 to the coefficient unit 135B.
  • Coefficient unit 134 generates a 1-line delay signal # weighted signal # 134 is multiplied by the coefficient alpha 0 against 131 supplied from the one-line delay circuit 131.
  • the coefficient unit 134 supplies the generated weighted signal # 134 to the adder 136.
  • Coefficient unit 135A multiplies the coefficient alpha 1 relative to a progressive signal # 12 inputted from the outside to generate a weighted signal # 135A.
  • the coefficient unit 135A supplies the generated weighted signal # 135A to the adder 136.
  • Coefficient multiplier 135B is multiplied by the coefficient alpha 1 generates a weighted signal # 135B for two-line delay signal # 132 supplied Karakara 1-line delay circuit 132.
  • the coefficient unit 135B supplies the generated weighted signal # 135B to the adder 136.
  • the adder 136 adds the weighted signal # 134 supplied from the coefficient unit 134, the weighted signal # 135A supplied from the coefficient unit 135A, and the weighted signal # 135B supplied from the coefficient unit 135B.
  • the interlace carrier removed signal # 13 is generated and output to the outside.
  • the weighting coefficient setting unit 137 sets coefficients used by the coefficient units 134, 135A, and 135B.
  • the coefficient ⁇ 0 used by the coefficient unit 134 and the coefficient ⁇ 1 used by the coefficient units 135A and 135B are coefficients for taking a weighted average.
  • the weighting coefficient setting unit 137 sets the coefficient ⁇ 0 to “1/2” and sets the coefficient ⁇ 1 to “1/4”.
  • the vertical low-pass filter circuit 130 includes one-line delay circuits 131 and 132, adders (adding means) 133 and 136, and coefficient multipliers (adding means) 134 and 135C. It is good also as a structure. However, in FIG. 2B, the description of the weighting coefficient setting unit 137 is omitted. Since the vertical low-pass filter circuits 130 in FIGS. 2A and 2B are equivalent, the same interlace carrier removed signal # 13 can be obtained in both cases.
  • the vertical low-pass filter circuit 130 shown in FIG. 2 (b), the progressive signal # 12, after adding the two-line delayed signal # 132, is that it is multiplied by the coefficient alpha 1 differs.
  • the carrier-removed signal # 13 is the same as the signal output from the vertical low-pass filter circuit 130 shown in FIG.
  • FIG. 5 shows the position of the scanning line by progressive scanning in the time direction (frame direction) t-vertical direction y region.
  • the value of the scanning line P 0 shown in FIG. 5 is filtered by the vertical low-pass filter circuit 130 as follows. That is, one of the value obtained by multiplying 1/2 to the value of the scan line P 0, and a value obtained by multiplying 1/4 to the one on the value of the scan line P 1 of the scanning lines P 0, the scanning lines P 0 is a value obtained by multiplying 1/4 to the value of the scan line P 2 below is calculated.
  • the interpolation process shown in FIG. 5 has more sample points from which interpolation is performed. That is, in the conventional interpolation process shown in FIG. 12, the number of sample points is one or two, whereas in the interpolation process shown in FIG. 5, the number of sample points is three.
  • FIG. 4 shows the frequency characteristics of the interlace carrier removed signal # 13 output from the vertical direction low-pass filter circuit.
  • the vertical low-pass filter circuit 130 removes the frequency band indicated by the removal region R10 including the interlace carrier F, and passes the other frequency bands.
  • the removal region R10 is a band having a predetermined width in the vertical direction centered on the position of the interlace carrier F in the case of 0 to 1/1125 TV lines. The same applies to 1/1125 TV lines to 2/1125 TV lines.
  • the removal region R10 includes a frequency band that is higher by a predetermined frequency than k / 1125 TV lines (k is an integer of 0 or more), and a frequency band that is lower than the k / 1125 TV lines by a predetermined frequency. It can be said that this is a combined area.
  • the removal region R10 is a frequency band in which the carrier of the interlace signal is generated and is not a frequency band in which the carrier of the progressive signal is generated, that is, a frequency band having a predetermined width including the interlace carrier F.
  • the frequency band indicated by the removal region R10 including the interlace carrier F is removed from the input progressive signal, so that the high frequency component due to the interlace carrier F can be removed. it can.
  • the interlace carrier removing unit 13 uses the progressive signal # 12 converted from the interlace signal obtained by interlace scanning the image as an input signal, and uses the DC signal in the time-vertical frequency region of the interlace signal.
  • the frequency band where the carrier appears in the time-vertical frequency domain in the progressive signal is excluded from the frequency band where the carrier is the signal folding point (the DC component of the two-dimensional sampling frequency appears repeatedly in the discretization by scanning).
  • Vertical direction low pass filter that generates an interlace carrier removed signal # 13 as an output signal by removing the frequency band in which the interlace carrier F appears from the progressive signal # 12.
  • the interlace carrier can be removed.
  • the vertical low-pass filter circuit 130 generates the interlace carrier removed signal # 13 signal # 13 by removing the high-frequency component in the vertical direction in the progressive signal # 12.
  • the area removed by the vertical low-pass filter circuit 130 is a band area having a predetermined width in the vertical direction from the position of the interlace carrier. Furthermore, this band region is a region extending in the time direction.
  • the frequency spectrum of a moving image tends to extend in the time direction.
  • the coefficient of the coefficient unit 135A and the coefficient of the coefficient unit 135B set by the weighting coefficient setting unit 137 are “ ⁇ 1 ” and the same.
  • the present invention is not limited to this, and the weighting coefficient setting unit 137 can set different coefficients for the coefficient unit 135A and the coefficient unit 135B.
  • the vertical low-pass filter circuit 130 is a 3-tap (stage number) filter having filter coefficients of (1/4, 1/2, 1/4). That is, the coefficient unit 134 applies the coefficient 1/2 to the video signal delayed by one line, and the coefficient unit 135 applies the coefficient 1/4 to the progressive signal # 12 and the two-line delayed signal # 132. .
  • the present invention is not limited to this configuration, and a filter having a tap number other than 3 can be used for the vertical low-pass filter circuit 130.
  • a filter having a tap number larger than 3 can be used for the vertical low-pass filter circuit 130.
  • a filter with the number of taps of 5, 7, 9 and the like can be used.
  • the weighting coefficient setting unit 137 may set the sum of 5, 7, and 9 coefficients to be “1” according to the number of taps.
  • the vertical width of the removal region R10 can be reduced.
  • the weight coefficient setting unit 137 in the vertical low-pass filter circuit 130 may be configured to adaptively change the filter according to the video characteristics of the progressive signal # 12 input.
  • changing the filter means that the weighting coefficient setting unit 137 changes the number of taps of the filter and sets a coefficient corresponding to the changed number of taps. Note that the present invention is not limited to this, and only a coefficient may be set.
  • the weighting coefficient setting unit 137 adaptively converts the progressive signal # 12 and the signal output from each 1-line delay circuit according to the video characteristics of the progressive signal # 12. Set the coefficient to apply to. Note that the sum of the coefficients is set to be “1”. In addition, setting the coefficient includes setting the coefficient value to “0”.
  • An example of changing the filter according to the video characteristics of progressive signal # 12 is as follows.
  • the filter may be changed according to the steepness of the signal corresponding to the contour portion (edge) included in the image represented by the progressive signal # 12. That is, an edge included in the image indicated by the input progressive signal # 12 may be detected, and the filter may be changed according to the rising or falling steepness of the signal corresponding to the detected edge.
  • the filter may be changed when the vertical edge is gentle or the vertical edge is steep.
  • edge is gentle, a filter with a small number of taps may be used. If the edge is steep, a filter with a large number of taps may be used. As an example where the edge is steep, for example, a boundary where an image changes from white to black can be cited.
  • the filter may be changed according to the spread of the spectrum due to the interlace carrier F in the frequency domain.
  • the spread of the spectrum means, for example, the extent that the spectrum spreads in the vertical direction, the time direction, or both in the frequency domain.
  • a filter with a small number of taps may be used. This is because when the number of taps of the filter is small, a gentle filter characteristic can be obtained compared to the case of a filter with a large number of taps.
  • a filter with a large number of taps may be used. This is because when the number of taps of the filter is large, steep filter characteristics can be obtained compared to the case of a filter with a small number of taps.
  • FIGS. 6 to 9 Another embodiment of the present invention will be described with reference to FIGS. 6 to 9 as follows.
  • members having the same functions as those in the drawings described in the first embodiment are denoted by the same reference numerals and description thereof is omitted.
  • FIG. 6 shows a configuration example when the interlace carrier removal unit 13 is realized by the time direction-vertical direction filter processing circuit 20.
  • the time direction-vertical direction filter processing circuit 20 includes a high-pass filter circuit frequency component removing unit 230, a two-line delay circuit 240, and a subtracter (subtracting unit) 250.
  • the time direction-vertical direction filter processing circuit 20 externally outputs the interlace carrier removed signal # 13 that has been subjected to the interlace carrier removal processing by performing filtering using the high-pass filter circuit 230 on the input progressive signal # 12. Output.
  • the high-pass filter circuit 230 includes a time-direction high-pass filter (time-frequency component removing unit) 210 and a vertical-direction high-pass filter (vertical frequency component removing unit) 220.
  • the time direction high-pass filter 210 performs high-pass processing in the time direction on the input signal.
  • FIG. 7 shows a specific configuration of the time direction high-pass filter 210.
  • the time-direction high-pass filter 210 includes a one-frame delay circuit (frequency component removing means) 211 and a subtracter (frequency component removing means) 212.
  • the 1-frame delay circuit 211 delays the progressive signal # 12 by one frame.
  • the one-frame delay circuit 211 functions as a low-pass filter in the time direction (frame direction).
  • the 1-frame delay circuit 211 generates a video signal # 211 obtained by performing a low-pass process in the time direction on the progressive signal # 12 and supplies the video signal # 211 to the subtractor 212.
  • the subtractor 212 generates a first filtered signal (temporal low frequency removal signal) # 210 obtained by subtracting the video signal # 211 subjected to the low-pass processing from the progressive signal # 12 that is an input signal.
  • the time-direction high-pass filter 210 is indirectly realized by using a time-direction low-pass filter.
  • the time-direction high-pass filter 210 generates the first filtered signal # 210 that has been subjected to the time-direction high-pass processing in this way, and outputs it to the outside.
  • the vertical high-pass filter 220 performs vertical high-pass processing on the input signal.
  • FIG. 8 shows a specific configuration of the vertical high-pass filter 220.
  • the vertical high-pass filter 220 includes a vertical low-pass filter 221 and a subtractor 222.
  • the vertical low-pass filter 221 can be the same as the vertical low-pass filter circuit 130, detailed description thereof is omitted.
  • the vertical low-pass filter 221 generates a video signal # 221 obtained by performing vertical low-pass processing on the first filtered signal # 210 output from the time-direction high-pass filter 210, and supplies the video signal # 221 to the subtractor 222. To do.
  • the subtracter 222 generates a second filtered signal (vertical low frequency removal signal) # 230 obtained by subtracting the video signal # 221 that has been subjected to the low-pass processing in the vertical direction from the first filtered signal # 210. .
  • the vertical high-pass filter 220 is indirectly realized by using a vertical high-pass filter.
  • the vertical high-pass filter 220 generates the second filtered signal # 230 subjected to the high-pass processing in the vertical direction in this way.
  • the high-pass filter circuit 230 outputs the second filtered signal # 230 that has been subjected to the filter processing by the vertical low-pass filter 221 and the vertical high-pass filter 220 as described above.
  • the two-line delay circuit 240 is synchronized with the second filtered signal # 230 by delaying the progressive signal # 12 by an amount delayed when the progressive signal # 12 passes through the high-pass filter circuit 230.
  • 2-line delay signal # 240 is output.
  • the subtractor 250 generates an interlace carrier removed signal # 13 obtained by subtracting the second filtered signal # 230 output from the high-pass filter circuit 230 from the 2-line delay signal # 240 output from the 2-line delay circuit 240. And output.
  • FIG. 9 shows frequency characteristics of signals output from the respective units included in the time direction-vertical direction filter processing circuit 20.
  • (A), (b), (c), and (d) of FIG. 9 are output from the 1-frame delay circuit 211, the time direction high-pass filter 210, the vertical direction low-pass filter 221, and the vertical direction high-pass filter 220, respectively.
  • the frequency characteristics of each video signal are shown.
  • the one-frame delay circuit 211 removes the frequency band indicated by the mask region R′21 and passes the other frequency band.
  • the time-direction high-pass filter 210 removes the frequency band indicated by the mask region R′21 shown in FIG. 9A from the progressive signal # 12 that is an input signal, and as a result, shown in FIG. 9B.
  • the frequency band indicated by the removal region R21 is obtained.
  • the removal region R21 includes a frequency band on the right side by a predetermined frequency from 30 * m (Hz) (m is an integer of 1 or more) and a frequency band on the left side by a predetermined frequency from 30 * m (Hz). It can be said that this is a combined area.
  • This frequency characteristic is also the frequency characteristic of the first filtered signal # 210.
  • the vertical low-pass filter 221 has the frequency characteristics shown in FIG. 4 as already described. Therefore, the vertical low-pass filter 221 removes the frequency band indicated by the removal region R10 shown in FIG. 4 from the frequency band indicated by the removal region R21. As a result, the frequency band indicated by the mask region R′22 shown in FIG. 9C is obtained. Therefore, the video signal # 221 output from the vertical low-pass filter 221 includes a frequency band indicated by the mask region R′22.
  • the vertical high-pass filter 220 subtracts the frequency band indicated by the mask area R′22 of the video signal # 221 from the frequency band indicated by the removal area R21 of the first filtered signal # 210.
  • the frequency band indicated by the removal region R22 shown in 9 (d) is obtained.
  • the removal region R22 is a rectangular region including the interlace carrier F.
  • the time direction-vertical direction filter processing circuit 20 generates an interlace carrier removed signal # 13 from which the removal region R22 including the interlace carrier F is removed from the video signal # 230.
  • the time direction-vertical direction filter processing circuit 20 includes the time direction high-pass filter 210 that generates the first filtered signal # 210 by removing the low frequency component of the time frequency in the progressive signal # 12.
  • the vertical high-pass filter 220 that generates the second filtered signal # 230 by removing the low frequency component of the vertical frequency in the first filtered signal # 210, and the second filtered signal # 12 from the progressive signal # 12
  • the subtractor 250 generates the interlace carrier removed signal # 13 by subtracting 230.
  • the frequency spectrum of a still image tends to spread in the time direction around the carrier.
  • the removal region R22 can be a rectangular region including the interlace carrier F, the interlace carrier and the spectrum due to the interlace carrier included in the rectangular region can be selectively removed. For this reason, it can prevent removing the frequency component of a time direction excessively. Thereby, there is an effect that blur of a still image can be reduced.
  • the filter processing of the time direction high pass filter 210 and the vertical direction high pass filter 220 of the high pass filter circuit 230 has linearity, the positions of the time direction high pass filter 210 and the vertical direction high pass filter 220 can be interchanged. .
  • the vertical high-pass filter 220 may be omitted, and only the filtering process by the time-direction high-pass filter 210 may be performed.
  • the time direction-vertical direction filter processing circuit 20 can function as a low pass filter in the time direction.
  • the time-direction high-pass filter 300 includes one-frame delay circuits (frame delay elements, frame delay means) 301 and 302, coefficient units (first addition means) 303, 304, and 305, adders (first An addition unit) 306 and a subtracter (first subtraction unit) 307 are provided.
  • the input progressive signal # 12 is supplied to the 1-frame delay circuit 301 and the coefficient unit 303.
  • the time direction high pass filter 300 is different in that the number of taps is three.
  • the 1-frame delay circuit 301 delays the input video signal by one frame, similarly to the 1-frame delay circuit 211 already described. Specifically, the 1-frame delay circuit 301 generates a 1-frame delay signal # 301 obtained by delaying the progressive signal # 12 by one frame. The 1-frame delay circuit 301 supplies the generated 1-frame delay signal # 301 to the 1-frame delay circuit 302, the coefficient unit 304, and the subtracter 307.
  • the 1-frame delay circuit 302 delays the input video signal by one frame, similarly to the 1-frame delay circuit 301. Specifically, the 1-frame delay circuit 302 generates a 2-frame delay signal # 302 obtained by delaying the 1-frame delay signal # 301 by one frame (that is, by delaying the progressive signal # 12 by two frames). The 1-frame delay circuit 301 supplies the generated 2-frame delay signal # 302 to the coefficient unit 305.
  • Coefficient multiplier 303 multiplies the coefficient alpha 11 generates a weighted signal # 303 against progressive signal # 12.
  • the coefficient unit 134 supplies the generated weighted signal # 303 to the adder 306.
  • the coefficient ⁇ 11 is illustratively “1 ⁇ 4”.
  • Coefficient unit 304 generates a weighted signal # 304 is multiplied by a coefficient alpha 12 for one-frame delayed signal # 301.
  • the coefficient unit 304 supplies the generated weighted signal # 304 to the adder 306.
  • the coefficient alpha 12 illustratively a "1/2".
  • the present invention is not limited to this, and the coefficient ⁇ 12 can be set arbitrarily as with the coefficient ⁇ 11 described above.
  • Coefficient unit 305 generates the weighted signal # 305 is multiplied by a coefficient alpha 13 with respect to the two-frame delayed video signal # 302.
  • the coefficient unit 305 supplies the generated weighted signal # 305 to the adder 306.
  • the coefficient alpha 13 illustratively a "1/4".
  • the adder 306 adds the weighted signal # 303 supplied from the coefficient unit 303, the weighted signal # 304 supplied from the coefficient unit 304, and the weighted signal # 305 supplied from the coefficient unit 305. An addition signal # 306 is generated, and the generated addition signal # 306 is supplied to the subtractor 307.
  • the subtracter 307 subtracts the addition signal # 306 supplied from the adder 306 from the 1-frame delay signal # 301 supplied from the 1-frame delay circuit 301 to generate a first filtered signal # 210.
  • the configuration of the time direction high-pass filter 300 is not limited to the configuration described above.
  • the filter can be changed.
  • the coefficient ⁇ 11 applied to the progressive signal # 12 in the immediately preceding frame of the 1-frame delayed signal # 301 and the 2-frame delayed signal # 302 in the immediately following frame of the 1-frame delayed signal # 301 the coefficient alpha 13 to be applied together, in contrast, "1/4" is set.
  • the first filtered signal # 210 output from the time direction high-pass filter 300 does not unnaturally blur when an object moves. That is, so-called tailing can be reduced.
  • each block of the above-described interlace carrier removal unit 13 may be realized by hardware by a logic circuit formed on an integrated circuit (IC chip), or software using a CPU (Central Processing Unit). May be realized.
  • IC chip integrated circuit
  • CPU Central Processing Unit
  • the display device 1 executes a CPU that executes instructions of a program that realizes each function, a ROM (Read Only Memory) that stores the program, a RAM (Random Access Memory) that expands the program, and the program
  • a storage device such as a memory for storing various data may be provided.
  • the function of the interlace carrier removal part 13 mentioned above may be implement
  • a recording medium in which the program code (execution format program, intermediate code program, source program) of the program is recorded so as to be readable by a computer is supplied to the display device 1, and the computer (or CPU or MPU) is supplied.
  • the computer or CPU or MPU
  • Examples of the recording medium include tapes such as magnetic tape and cassette tape, magnetic disks such as floppy (registered trademark) disks / hard disks, and CD-ROM / MO / MD / DVD / CD-R / Blu-ray disks (registered trademarks). ) And other optical disks, IC cards (including memory cards) / optical cards, semiconductor memories such as mask ROM / EPROM / EEPROM / flash ROM, PLD (Programmable logic device) and FPGA ( Logic circuits such as Field Programmable Gate Array can be used.
  • tapes such as magnetic tape and cassette tape
  • magnetic disks such as floppy (registered trademark) disks / hard disks
  • CD-ROM / MO / MD / DVD / CD-R / Blu-ray disks registered trademarks
  • IC cards including memory cards
  • semiconductor memories such as mask ROM / EPROM / EEPROM / flash ROM, PLD (Programmable logic device) and FPGA ( Logic circuits
  • the display device 1 may be configured to be connectable to a communication network, and the program code may be supplied via the communication network.
  • the communication network is not particularly limited as long as it can transmit the program code.
  • the Internet intranet, extranet, LAN, ISDN, VAN, CATV communication network, virtual private network (Virtual Private Network), telephone line network, mobile communication network, satellite communication network, etc. can be used.
  • the transmission medium constituting the communication network may be any medium that can transmit the program code, and is not limited to a specific configuration or type.
  • wired lines such as IEEE 1394, USB, power line carrier, cable TV line, telephone line, ADSL (Asymmetric Digital Subscriber Line) line, infrared rays such as IrDA and remote control, Bluetooth (registered trademark), IEEE 802.11 wireless, HDR ( It can also be used by wireless such as High Data Rate, NFC (Near Field Communication), DLNA (Digital Living Network Alliance), mobile phone network, satellite line, and terrestrial digital network.
  • the present invention can also be realized in the form of a computer data signal embedded in a carrier wave in which the program code is embodied by electronic transmission.
  • means does not necessarily mean physical means, but includes cases where the functions of each means are realized by software. Further, the function of one means may be realized by two or more physical means, or the functions of two or more means may be realized by one physical means.
  • the interlace carrier removing unit 13 included in the display device uses the progressive signal # 12 converted from the interlace signal obtained by interlace scanning the image as an input signal, and the time of the interlace signal ⁇ Progressive signal time-carrier appears in the vertical frequency domain from the frequency band where the carrier appears, which is the point where the DC signal turns around in the vertical frequency domain (the DC component of the two-dimensional sampling frequency appears repeatedly in discretization by scanning)
  • the interlace carrier removed signal # 13, which is the output signal, is generated by removing the frequency band excluding the frequency band to be processed from the progressive signal # 12.
  • the signal processing apparatus uses a progressive signal by a progressive scanning method converted from an interlace signal obtained by interlace scanning an image as an input signal, and a progressive signal obtained by performing signal processing on the input signal.
  • a signal processing device that outputs a signal as an output signal, which is a point at which a DC signal folds in a time-vertical frequency domain of an interlace signal (a DC component of a two-dimensional sampling frequency repeatedly appears in discretization by scanning)
  • the integrated circuit according to the present invention uses a progressive signal by a progressive scanning method converted from an interlaced signal obtained by interlaced scanning an image as an input signal, and a progressive signal obtained by performing signal processing on the input signal.
  • An integrated circuit that outputs as an output signal, and is formed by connecting one or a plurality of line delay elements that output a line delay signal obtained by delaying an input video signal by one line in the vertical direction.
  • a line delay circuit in which the input signal is input to an element; and an adder circuit that generates the output signal by adding each of the input signal and the line delay signal multiplied by a weighting factor. is there.
  • the integrated circuit according to the present invention uses a progressive signal by a progressive scanning method converted from an interlaced signal obtained by interlaced scanning an image as an input signal, and a progressive signal obtained by performing signal processing on the input signal.
  • An integrated circuit that outputs as an output signal, a time frequency component removal circuit that generates a time low frequency removal signal by removing a low frequency component of the time frequency in the input signal, and a vertical frequency in the time low frequency removal signal
  • a vertical frequency component removal circuit that generates a vertical low frequency removal signal by removing the low frequency component of the signal, and a subtraction circuit that generates the output signal by subtracting the vertical low frequency removal signal from the input signal It is.
  • interlaced carrier As already described, according to the knowledge obtained by the inventor of the present invention regarding the above-described problem, when a motion region is erroneously detected in motion detection performed at the time of IP conversion, an interlace signal is detected in an IP converted progressive signal. May appear (hereinafter referred to as interlaced carrier).
  • an interlace carrier that is a carrier in the time-vertical frequency domain of an interlaced signal and not a carrier in the time-vertical frequency domain of a progressive signal may appear.
  • an interlace signal is 2/60 seconds and 1 frame (1 field in 1/30 seconds), and a progressive signal is 1 frame in 1/60 seconds
  • the time-vertical frequency region of the progressive signal is around 30 Hz.
  • an interlace carrier of an interlace signal appears.
  • the interlace is near 1 / (2 * 1125 TV lines) in the time-vertical frequency domain of the IP converted progressive signal. A career may appear.
  • the interlace carrier is removed from the progressive signal.
  • the processing for removing the frequency band can be realized by, for example, a time direction low-pass filter, a vertical direction low-pass filter, or a combination thereof.
  • the frequency component removing unit may generate the output signal by removing a high-frequency component in a vertical direction from the input signal.
  • the frequency component removing unit removes a high-frequency component in the vertical direction from the input signal. That is, the frequency component removing unit functions as a vertical low-pass filter.
  • the frequency band removed by the vertical low-pass filter that is, the high frequency component band in the vertical direction is a band region having a predetermined width in the vertical direction with the interlace carrier as the center. Furthermore, this band region is a region extending in the time direction.
  • the interlace carrier can be removed by a band region having a predetermined width in the vertical direction and extending in the time direction.
  • the frequency spectrum of a moving image tends to extend in the time direction.
  • the frequency component removing unit further connects one or a plurality of line delay elements that output a line delay signal obtained by delaying the input video signal by one line in the vertical direction.
  • the line delay means for inputting the input signal to the line delay element at the front stage, and adding the output signal by multiplying each of the input signal and the line delay signal after multiplying by a weighting factor.
  • generate may be sufficient.
  • the vertical low-pass filter can be realized with a simple configuration, so that the cost of the apparatus can be reduced.
  • the signal processing apparatus further includes weight coefficient setting means for setting the weight coefficient in accordance with the steepness of the signal corresponding to the contour portion included in the image represented by the input signal. May be.
  • the weighting factor can be set adaptively according to the steepness of the signal corresponding to the contour portion (edge) included in the image represented by the progressive signal. Thereby, the frequency characteristic of the output signal can be adjusted. Note that the sum of the weight coefficients is set to be “1”.
  • setting the weighting factor includes setting the value of the coefficient to “0”.
  • the number of weighting factors may be increased as the steepness of the signal corresponding to the contour portion included in the image represented by the progressive signal is higher.
  • the number of weighting factors may be reduced as the steepness is lower.
  • the line delay means may be configured by cascading two line delay elements.
  • the frequency component removing means is a so-called vertical low-pass filter with 3 taps. Therefore, the design of the frequency component removing means is simplified. Therefore, it is possible to reduce the size and cost of the apparatus and reduce the processing load.
  • the frequency component removing unit further generates a time low frequency removal signal by removing a low frequency component of the time frequency in the input signal, Vertical frequency component removal means for generating a vertical low frequency removal signal by removing a low frequency component of a vertical frequency in the time low frequency removal signal, and the output signal by subtracting the vertical low frequency removal signal from the input signal. And a subtracting means for generating.
  • the temporal low frequency removal signal is generated by removing the low frequency component of the temporal frequency in the input signal. That is, a time direction high-pass filter is applied to the input signal.
  • the above-mentioned time direction high-pass filter passes a frequency band of a predetermined width in the time direction with the interlace carrier as the center.
  • the time-direction high-pass filter can be realized by, for example, a circuit that subtracts a video signal obtained by delaying the video signal by one frame from the input video signal.
  • a vertical low frequency removal signal is generated by removing the low frequency component of the vertical frequency in the time low frequency removal signal. That is, a vertical high-pass filter is applied to the temporal low frequency removal signal.
  • the above-mentioned vertical high-pass filter passes a frequency band of a predetermined width in the vertical direction around the interlace carrier.
  • the vertical high-pass filter can be realized by, for example, a circuit that subtracts a video signal obtained by passing a low-frequency component in the vertical direction from the input video signal.
  • the band region having the predetermined width in the time direction and the band region having the predetermined width in the vertical direction are overlapped from the input signal.
  • An area (hereinafter referred to as an overlapping area) is extracted.
  • the overlapping area includes an interlace carrier.
  • the frequency band including the interlace carrier is removed.
  • the overlapping region is a region narrower than both the band region having a predetermined width in the time direction and the belt region having a predetermined width in the vertical direction.
  • the time frequency component removal means generates the time low frequency removal signal by calculating a difference between two consecutive frames constituting the image represented by the input signal. It may be configured to.
  • the temporal low frequency removal signal is generated by calculating the difference between the input signal and the video signal obtained by delaying the input signal by one frame.
  • This configuration can be realized by, for example, one frame memory.
  • the apparatus can be reduced in size, cost, and processing load can be reduced.
  • the time-frequency component removing unit further includes a frame delay element that outputs a frame delay signal obtained by delaying an input video signal by one frame (n is an arbitrary positive number).
  • a frame delay element that outputs a frame delay signal obtained by delaying an input video signal by one frame (n is an arbitrary positive number).
  • An integer) number of cascaded connections frame delay means for inputting the input signal to the frame delay element at the front stage, and adding each of the input signal and the frame delay signal multiplied by a weighting factor
  • First addition means for generating an addition signal
  • subtraction means for generating the output signal by subtracting the addition signal from the frame delay signal output from the frame delay element at the nth stage from the front. It may be a configuration.
  • the temporal low-frequency removal signal is generated using a plurality of continuous frames, there is an effect that blur appearing in the video can be made natural.
  • each frame delay signal when a weighting factor to be multiplied by each frame delay signal is set according to the degree of delay from the frame delay signal output from the n-th frame delay element from the forefront of each frame delay signal, the frame to be added Since there is no bias in the delayed signal, so-called tail flickering can be reduced.
  • the vertical frequency component removing means further comprises a plurality of line delay elements that output a line delay signal obtained by delaying the input video signal by one line in the vertical direction in cascade.
  • a line delay means for inputting the time low frequency removal signal to the line delay element at the front stage, and adding each of the time low frequency removal signal and the line delay signal after multiplying by a weighting factor.
  • a configuration may be provided that includes second adding means for generating the output signal.
  • the vertical frequency component removing means is a so-called n-tap vertical low-pass filter.
  • the apparatus can be reduced in size, cost, and processing load can be reduced.
  • the signal processing apparatus further includes weight coefficient setting means for setting the weight coefficient according to the steepness of the signal corresponding to the contour portion included in the image represented by the input signal. There may be.
  • the weighting factor can be adaptively set according to the steepness of the signal corresponding to the contour portion included in the image represented by the input signal. Thereby, the frequency characteristic of the output signal can be adjusted. Note that the sum of the weight coefficients is set to be “1”.
  • setting the weighting factor includes setting the value of the coefficient to “0”.
  • the number of weighting factors may be increased as the steepness of the signal corresponding to the contour portion included in the image represented by the progressive signal is higher.
  • the number of weighting factors may be reduced as the steepness is lower.
  • the frequency component removing unit further generates a time low frequency removal signal by removing a low frequency component of the time frequency in the input signal
  • a configuration may be provided that includes subtracting means for generating the output signal by subtracting the vertical low frequency removal signal from the temporal low frequency removal signal.
  • the time frequency component removing means removes the low frequency component of the time frequency in the input signal. That is, the time frequency component removing unit functions as a time direction high-pass filter.
  • the frequency band removed by the frequency component removing means is a band region having a predetermined width in the time direction with the interlace carrier as the center. Furthermore, this band region is a region extending in the vertical direction.
  • the interlace carrier can be removed by a band region having a predetermined width in the time direction and extending in the vertical direction.
  • the frequency spectrum of a still image tends to extend in the vertical direction.
  • the signal processing device may be realized by a computer.
  • a control program for the signal processing device that causes the signal processing device to be realized by the computer by causing the computer to operate as each of the means, and A computer-readable recording medium on which it is recorded also falls within the scope of the present invention.
  • the interlace carrier removal unit according to the present invention can be applied to an apparatus that displays an interlace-scanned signal in a progressive manner.
  • the present invention can be suitably applied to a receiver for digital terrestrial broadcasting such as a liquid crystal television set and a portable terminal.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)

Abstract

Selon la présente invention, en utilisant un signal progressif (#12) converti à partir d'un signal entrelacé en tant qu'un signal d'entrée, un module d'élimination de porteuse entrelacée (13) génère un signal de porteuse entrelacée éliminée (#13) en éliminant, du signal progressif (#12), une bande de fréquences à laquelle la bande de fréquences porteuses d'un domaine de fréquences orthogonales par rapport au temps du signal progressif est éliminée de la bande de fréquences porteuses du domaine de fréquences orthogonales par rapport au temps du signal entrelacé.
PCT/JP2012/057706 2011-03-31 2012-03-26 Dispositif de traitement de signal, programme de contrôle et circuit intégré WO2012133277A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201280010961.XA CN103404131B (zh) 2011-03-31 2012-03-26 信号处理装置、控制程序以及集成电路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011-081174 2011-03-31
JP2011081174 2011-03-31

Publications (1)

Publication Number Publication Date
WO2012133277A1 true WO2012133277A1 (fr) 2012-10-04

Family

ID=46930995

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/057706 WO2012133277A1 (fr) 2011-03-31 2012-03-26 Dispositif de traitement de signal, programme de contrôle et circuit intégré

Country Status (2)

Country Link
CN (1) CN103404131B (fr)
WO (1) WO2012133277A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0391387A (ja) * 1989-09-04 1991-04-16 Hitachi Ltd 走査変換回路
JPH0730821A (ja) * 1993-07-14 1995-01-31 Matsushita Electric Ind Co Ltd 順次走査方式対応撮像装置
JP3850071B2 (ja) * 1995-06-07 2006-11-29 三菱電機株式会社 変換装置及び変換方法
JP2010251880A (ja) * 2009-04-13 2010-11-04 Canon Inc 映像処理装置およびその制御方法
JP2011023843A (ja) * 2009-07-14 2011-02-03 Sony Corp 画像処理装置および画像処理方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910585A (en) * 1988-06-29 1990-03-20 General Electric Company Frequency selective video signal intraframe processor
KR100563866B1 (ko) * 2003-05-19 2006-03-23 매크로영상기술(주) 영상 신호의 디인터레이스 방법 및 장치
CN100518243C (zh) * 2007-01-31 2009-07-22 天津大学 采用运动检测和自适应加权滤波的去隔行装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0391387A (ja) * 1989-09-04 1991-04-16 Hitachi Ltd 走査変換回路
JPH0730821A (ja) * 1993-07-14 1995-01-31 Matsushita Electric Ind Co Ltd 順次走査方式対応撮像装置
JP3850071B2 (ja) * 1995-06-07 2006-11-29 三菱電機株式会社 変換装置及び変換方法
JP2010251880A (ja) * 2009-04-13 2010-11-04 Canon Inc 映像処理装置およびその制御方法
JP2011023843A (ja) * 2009-07-14 2011-02-03 Sony Corp 画像処理装置および画像処理方法

Also Published As

Publication number Publication date
CN103404131A (zh) 2013-11-20
CN103404131B (zh) 2017-02-22

Similar Documents

Publication Publication Date Title
JP5062968B2 (ja) 画像処理装置および方法、記録媒体、並びにプログラム
US9185431B2 (en) Motion detection device and method, video signal processing device and method and video display device
EP0629083A1 (fr) Convertisseur de balayage entrelacé en non-entrelacé à fonction de lissage double et procédé associé
KR100403364B1 (ko) 영상 신호의 디인터레이스 방법 및 장치
US20060285010A1 (en) Systems and methods for deinterlacing video signals
JP2006304352A (ja) 画像処理装置
CN100518288C (zh) 自适应垂直/时态滤波的解交错方法
JP5249166B2 (ja) 画像処理装置、画像処理方法
EP1616300A1 (fr) Conversion spatiale d'images
WO2012133277A1 (fr) Dispositif de traitement de signal, programme de contrôle et circuit intégré
US8139153B2 (en) Method for generating distances representative of the edge orientations in a video picture, corresponding device and use of the method for deinterlacing or format conversion
JP5147655B2 (ja) 映像信号処理装置および映像表示装置
JP4292853B2 (ja) デジタル放送受信装置
TWI510076B (zh) 影像處理方法及相關的影像處理裝置
WO2008038442A1 (fr) Procédé de conversion ip de signal de différence de couleur
US20040012334A1 (en) Video signal processing
JP2011078136A (ja) 映像ノイズ削減処理装置及び映像処理装置
WO2012073865A1 (fr) Dispositif de traitement d'image, procédé de traitement d'image, programme de traitement d'image et dispositif d'affichage
JP5057964B2 (ja) 映像信号処理装置、映像信号処理方法、及び映像信号表示装置
WO2012124516A1 (fr) Dispositif de traitement de réduction de bruit et dispositif d'affichage
JPS58177078A (ja) テレビジヨン信号処理回路
JP3746441B2 (ja) 映像信号処理装置
JP2009267753A (ja) 画像フォーマット変換装置
US8508662B1 (en) Post de-interlacer motion adaptive filter for smoother moving edges
JP2003199055A (ja) 順次走査変換装置と順次走査変換方法及びテレビジョン装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12763407

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12763407

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP