WO2012132216A1 - Signal processing circuit and signal processing method - Google Patents

Signal processing circuit and signal processing method Download PDF

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Publication number
WO2012132216A1
WO2012132216A1 PCT/JP2012/001278 JP2012001278W WO2012132216A1 WO 2012132216 A1 WO2012132216 A1 WO 2012132216A1 JP 2012001278 W JP2012001278 W JP 2012001278W WO 2012132216 A1 WO2012132216 A1 WO 2012132216A1
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signal
error signal
output
subtractor
processing circuit
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PCT/JP2012/001278
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French (fr)
Japanese (ja)
Inventor
元紀 水田
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ルネサスエレクトロニクス株式会社
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Publication of WO2012132216A1 publication Critical patent/WO2012132216A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals

Definitions

  • the present invention relates to a signal processing circuit and a signal processing method, and more particularly to a signal processing circuit and a signal processing method for removing an error signal.
  • FIG. 22 is a block diagram showing a configuration of a filter circuit 600 according to Patent Document 1. As shown in FIG. The filter circuit 600 is a filter circuit for the purpose of equalizing the signal delays of the two paths and accurately removing the error signal.
  • the sampler 610 when a signal including an error signal is input from the frequency converter 601, the sampler 610 generates an analog discrete time signal.
  • the analog discrete time signal is converted into a digital signal by an A / D converter (ADC) 621.
  • ADC A / D converter
  • the digital signal passes through a digital filter 622 that extracts signals outside the desired band.
  • the digital signal is then converted to an analog signal by a D / A converter (DAC) 630.
  • the subtracter 650 subtracts the analog signal generated by the DAC 630 from the analog discrete time signal that has passed through the delay unit 640.
  • the subtraction result of the subtracter 650 is converted into a digital signal by an A / D converter (ADC) 602 and output.
  • ADC A / D converter
  • FIG. 23 is a block diagram showing a configuration of a noise cancellation circuit 700 according to Patent Document 3.
  • a signal including a noise signal in a desired wave signal is input from the antenna 701.
  • the filter 702 attenuates the desired wave signal included in the input signal and extracts only the noise signal.
  • the phase inverting unit 703 inverts the phase of the noise signal.
  • the oscillation unit 706 oscillates a noise signal at a predetermined frequency.
  • the level adjustment unit 705 adjusts the level of the oscillated noise signal.
  • the phase synchronization unit 704 synchronizes the phase of the noise signal whose phase is inverted and the noise signal subjected to level adjustment.
  • Adder 707 adds the input signal and the output of phase synchronization section 704.
  • the output of the phase synchronization unit 704 is output to a reception circuit or the like through the LNA 708.
  • the filter 702, the phase inversion unit 703, the phase synchronization unit 704, the level adjustment unit 705, and the oscillation unit 706 constitute an interference wave countermeasure unit 750.
  • the inventors have studied the above-described technique and found that, depending on the above-described circuit, the error signal cannot be removed when the frequency of the error signal is the same as or close to the frequency of the desired wave signal. This problem occurs because when the error signal is extracted, if the frequency band of the desired wave signal is attenuated, an error signal having the same frequency as or close to that of the desired wave signal is attenuated.
  • the signal processing circuit which is one embodiment of the present invention is the same as the signal output by the signal source output from the sensor circuit when the sensor circuit connected to the signal source does not detect the signal to be detected.
  • a storage device for storing a signal waveform of a frequency error signal for a predetermined period, and a reproduction error signal for repeatedly outputting a reproduction error signal obtained by reproducing the error signal from the signal waveform stored in the storage device for each predetermined period
  • a signal processing circuit which is one embodiment of the present invention extracts an error signal having a frequency that is the same as or close to that of a desired wave signal. Then, the error signal is subtracted by the extracted error signal. Thereby, an error signal can be removed.
  • the signal processing method is the same as the signal output from the signal source that is output from the sensor circuit when the sensor circuit connected to the signal source does not detect the signal to be detected.
  • a signal waveform of a frequency error signal for a predetermined period is stored in a storage device, and a reproduction error signal obtained by reproducing the error signal from the signal waveform stored in the storage device is repeatedly output for each predetermined period.
  • the first subtracter outputs a signal obtained by subtracting the reproduction error signal from the error signal to an output terminal, and the output of the first subtracter is not detected by the sensor circuit.
  • the supply timing of the reproduction error signal to the first subtracter is adjusted so that the signal level of the signal is minimized.
  • the signal processing method extracts an error signal having a frequency that is the same as or close to that of the desired wave signal. Then, the error signal is subtracted by the extracted error signal. Thereby, an error signal can be removed.
  • the present invention it is possible to provide a signal processing circuit and a signal processing method capable of removing an error signal that is the same as or close to that of a desired wave signal.
  • FIG. 1 is a block diagram schematically showing a configuration of a signal processing circuit 100 according to a first exemplary embodiment.
  • 3 is a flowchart showing an error signal removal operation of the signal processing circuit 100 according to the first exemplary embodiment;
  • FIG. 3 is a block diagram showing ON / OFF of first to third switches of the signal processing circuit 100 according to the first exemplary embodiment;
  • FIG. 3 is a block diagram showing ON / OFF of first to third switches of the signal processing circuit 100 according to the first exemplary embodiment;
  • FIG. 3 is a block diagram showing ON / OFF of first to third switches of the signal processing circuit 100 according to the first exemplary embodiment;
  • 6 is a timing chart illustrating an operation of the signal processing circuit 200 according to the second exemplary embodiment;
  • FIG. 3 is a block diagram schematically showing a configuration of a signal processing circuit 200 according to a second exemplary embodiment.
  • 6 is a flowchart showing an error signal removal operation of the signal processing circuit 200 according to the second exemplary embodiment;
  • FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 200 according to a second exemplary embodiment.
  • FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 200 according to a second exemplary embodiment.
  • FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 200 according to a second exemplary embodiment.
  • 6 is a timing chart illustrating an operation of the signal processing circuit 200 according to the second exemplary embodiment;
  • FIG. 6 is a block diagram schematically showing a configuration of a signal processing circuit 300 according to a third exemplary embodiment.
  • 10 is a flowchart showing an error signal removal operation of the signal processing circuit 300 according to the third exemplary embodiment.
  • FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 300 according to a third exemplary embodiment.
  • FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 300 according to a third exemplary embodiment.
  • FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 300 according to a third exemplary embodiment.
  • 10 is a timing chart illustrating an operation of the signal processing circuit 300 according to the third exemplary embodiment.
  • FIG. 6 is a block diagram schematically showing a configuration of a signal processing circuit 400 according to a fourth exemplary embodiment.
  • 10 is a flowchart illustrating an error signal removal operation of the signal processing circuit 400 according to the fourth embodiment.
  • FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 400 according to a fourth exemplary embodiment.
  • FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 400 according to a fourth exemplary embodiment.
  • FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 400 according to a fourth exemplary embodiment.
  • 10 is a timing chart illustrating an operation of the signal processing circuit 400 according to the fourth embodiment.
  • FIG. 10 is a timing chart illustrating an operation of the signal processing circuit 400 according to the fourth embodiment.
  • FIG. 10 is a block diagram schematically showing a configuration of a signal processing circuit 500 according to a fifth embodiment. 10 is a flowchart showing an error signal removal operation of the signal processing circuit 500 according to the fifth exemplary embodiment.
  • FIG. 10 is a block diagram showing on / off of first to third switches of a signal processing circuit 500 according to a fifth exemplary embodiment;
  • FIG. 10 is a block diagram showing on / off of first to third switches of a signal processing circuit 500 according to a fifth exemplary embodiment;
  • FIG. 10 is a block diagram showing on / off of first to third switches of a signal processing circuit 500 according to a fifth exemplary embodiment;
  • 10 is a timing chart illustrating an operation of the signal processing circuit 500 according to the fifth embodiment;
  • FIG. 10 is a block diagram schematically showing a configuration of a signal processing circuit 500 according to a fifth embodiment. 10 is a flowchart showing an error signal removal operation of the signal processing circuit 500 according to the fifth exemplary embodiment.
  • FIG. 10 is a block diagram
  • 10 is a block diagram schematically showing a configuration of a signal processing system 1000 according to a sixth exemplary embodiment.
  • 10 is a block diagram illustrating a configuration of a filter circuit 600 according to Patent Document 1.
  • FIG. 10 is a block diagram showing a configuration of a noise cancellation circuit 700 according to Patent Document 3.
  • FIG. 10 is a block diagram schematically showing a configuration of a signal processing system 1000 according to a sixth exemplary embodiment.
  • 10 is a block diagram illustrating a configuration of a filter circuit 600 according to Patent Document 1.
  • FIG. 10 is a block diagram showing a configuration of a noise cancellation circuit 700 according to Patent Document 3.
  • FIG. 1 is a block diagram schematically illustrating the configuration of the signal processing circuit 100 according to the first embodiment.
  • the signal processing circuit 100 is connected to the signal source 101 via the sensor circuit 102a.
  • the signal source 101 outputs a desired wave signal Sd.
  • the sensor circuit 102a detects a detected signal generated by an operation of a user of an apparatus in which the signal processing circuit 100 is incorporated.
  • the sensor circuit 102a is an ideal circuit whose output is zero when there is no user operation, that is, when no detected signal is detected.
  • the signal processing circuit 100 includes a first subtractor 11, a second subtractor 12, an analog / digital converter (hereinafter referred to as ADC) 13, a multi-input OR circuit 14, a storage device 15, a digital / digital converter It has an analog converter (Digital-to-Analog Converter: hereinafter referred to as DAC) 16, a filter 17, a control circuit 18, first to third switches SW11 to SW13, an output terminal Tout, and signal terminals Ten and Tend.
  • ADC analog / digital converter
  • DAC Digital-to-Analog Converter
  • the first subtractor 11 has a non-inverting input terminal connected to the output of the sensor circuit 102a, and an inverting input terminal connected to the output of the filter 17 via the second switch SW12.
  • the output of the first subtractor 11 is connected to the output terminal Tout and outputs an output signal Vout.
  • the output of the first subtractor 11 is connected to the input of the ADC 13 via the third switch SW13.
  • the second subtracter 12 has a non-inverting input terminal connected to the output of the sensor circuit 102a and an inverting input terminal connected to the ground.
  • the output of the second subtractor 12 is connected to the input of the ADC 13 via the first switch SW11.
  • the output of the ADC 13 is connected to the inputs of the multi-input OR circuit 14 and the storage device 15.
  • the number of outputs of the ADC 13 is set according to the number of bits of the output of the ADC 13.
  • An output OR_out of the multi-input OR circuit 14 is connected to a corresponding input of the control circuit 18.
  • the output of the storage device 15 is connected to the input of the DAC 16.
  • the output of the DAC 16 is connected to the input of the filter 17.
  • the control circuit 18 receives the enable signal en from the outside of the signal processing circuit 100 via the signal terminal Ten.
  • the control circuit 18 outputs control signals SIG11 to SIG13 to the first to third switches SW11 to SW13 and a control signal SIGm to the storage device 15.
  • the control circuit 18 outputs a completion signal end to the outside of the signal processing circuit 100 via the signal terminal Tend.
  • FIG. 2 is a flowchart showing the error signal removal operation of the signal processing circuit 100.
  • 3A to 3C are block diagrams showing ON / OFF of the first to third switches SW11 to SW13 of the signal processing circuit 100.
  • FIG. 4 is a timing chart showing the operation of the signal processing circuit 100.
  • the sensor circuit 102a is a circuit in which the output is ideally 0 when the detected signal is not detected (when not detected), but actually, even when the detected signal is detected.
  • An error signal is output.
  • This error signal is a signal that depends on the circuit configuration such as between the signal source and the sensor circuit, and has the same frequency as the desired wave signal output from the signal source. As shown in FIG. 4, in the initial state, the error signal err1 having the same frequency as the desired wave signal is output from the sensor circuit 102a.
  • the control circuit 18 determines whether or not the enable signal en is High (Step S101 in FIG. 2). If the enable signal is High, the control circuit 18 shifts to the error signal extraction mode (Step S102 in FIG. 2, timing T11 in FIG. 4). The control circuit 18 switches the storage device 15 to the write mode by the control signal SIGm (step S103 in FIG. 2).
  • the control circuit 18 turns on the first switch SW11 by the control signal SIG11 as shown in FIG. 3A. Further, the control circuit 18 turns off the second switch SW12 and the third switch SW13 by the control signals SIG12 and SIG13 (step S104 in FIG. 2).
  • the ADC 13 outputs a digital error signal err1_D obtained by A / D converting the error signal err1 output from the first subtractor 11 to the storage device 15 (step S105 in FIG. 2).
  • the storage device 15 stores the value of each bit of the digital error signal err1_D.
  • the storage device 15 stores a digital error signal err1_D for a period of at least one cycle of the desired wave signal Sd.
  • a period in which the storage device 15 stores the digital error signal err1_D is at least one period of the desired wave signal Sd is referred to as an error signal extraction period.
  • the storage device 15 stores the digital error signal err1_D according to the storage timing determined by dividing the error signal extraction period into a predetermined time (step S106 in FIG. 2).
  • the storage device 15 stores the digital error signal err1_D multiple times during the cycle T, for example.
  • the number of times the digital error signal err1_D is stored during the period T it is possible to reflect the fluctuation of the digital error signal err1_D during the period T.
  • a plurality of storage operations can be performed at regular intervals, for example. In this case, for example, the storage operation can be performed based on the clock signal CLK from the control circuit 18. Thereby, the waveform of the digital error signal err1_D during one cycle can be stored as a digital value.
  • control circuit 18 can also control the number of set repetitions by a control signal SIGm.
  • the control circuit 18 determines whether a predetermined time has elapsed since the storage device 15 started the storage operation (step S107 in FIG. 2). In this determination, it is determined whether a predetermined error signal extraction period has elapsed or a storage operation has been performed for a predetermined number of sets.
  • control circuit 18 shifts to the timing adjustment mode (step S108 in FIG. 2).
  • the control circuit 18 switches the storage device 15 to the read mode by the control signal SIGm (step S109 in FIG. 2).
  • the control circuit 18 turns off the first switch SW11 by the control signal SIG11.
  • the control circuit 18 turns on the second switch SW12 and the third switch SW13 by the control signals SIG12 and SIG13 (step S110 in FIG. 2, timing T12 in FIG. 4).
  • the control circuit 18 outputs the digital error signal err1_D stored in the storage device 15 by the control signal SIGm.
  • the DAC 16 outputs a reproduction error signal err1_R obtained by D / A converting the digital error signal err1_D to the filter 17. That is, the reproduction error signal err1_R output from the DAC 16 is an analog signal reproduced from the digital error signal err1_D stored in the storage device 15.
  • the filter 17 outputs the reproduction error signal err1_F obtained by removing the high frequency component from the reproduction error signal err1_R to the inverting input terminal of the first subtractor 11 via the second switch SW12 (step S111 in FIG. 2). .
  • the error signal err1 from the sensor circuit 102a is supplied to the non-inverting input terminal of the first subtractor 11. Therefore, the first subtractor 11 subtracts the reproduction error signal err1_RD from the error signal err1 (step S112 in FIG. 2).
  • the reproduction error signal err1_F is a reproduction of the digital error signal err1_D stored in the storage device 15. Therefore, even if a certain amount of waveform change occurs due to D / A conversion, A / D conversion, and filtering, the waveforms of the reproduction error signal err1_F and the error signal err1 are approximate or match. Therefore, if the timings of the error signal err1 and the reproduction error signal err1_F coincide with each other, the output of the first subtractor 11 is minimized and can be ideally zero. Therefore, in order to minimize the output of the first subtractor 11, it is necessary to match the timings of the error signal err1 and the reproduction error signal err1_F. Therefore, the output signal Vout of the first subtractor 11 is supplied to the ADC 13 via the third switch SW13. The ADC 13 outputs a digital signal Vout_D obtained by A / D converting the output signal Vout to the multi-input OR circuit 14.
  • the output signal Vout is 0 level. Therefore, when any bit of the digital signal Vout_D is “1”, it means that the timing of the error signal err1 and the reproduction error signal err1_F is shifted.
  • the output OR_out of the multi-input OR circuit 14 is “1” when any bit of the digital signal Vout_D is “1”, and “0” when all the bits of the digital signal Vout_D are “0”. " That is, the multi-input OR circuit 14 can detect whether or not there is a timing shift between the error signal err1 and the reproduction error signal err1_F (step S113 in FIG. 2).
  • the control circuit 18 delays the output timing of the storage device 15 by one step by the control signal SIGm (step S114 in FIG. 2, timing T13 in FIG. 4).
  • the delay amount (step) of the output timing may be specified by the control circuit 18 or may be one cycle or half cycle of the clock signal input to the storage device 15. Step S114 is repeated until the output OR_out of the multi-input OR circuit 14 becomes “0”.
  • the control circuit 18 turns on the second switch SW12 by the control signal SIG12 as shown in FIG. 3C. Further, the control circuit 18 turns off the first switch SW11 and the third switch SW13 by the control signals SIG11 and SIG13 (step S115 in FIG. 2). Then, the control circuit 18 outputs a completion signal end indicating that the timing adjustment has been completed, and ends the error signal removal process (step S116 in FIG. 2, timing T14 in FIG. 4).
  • the signal processing circuit 100 performs a normal operation. As described above, the signal processing circuit 100 removes the error signal of the output signal Vout by subtracting the reproduction error signal err1_F from the error signal err1 at an appropriate timing. Therefore, only the detected signal is reflected in the output signal Vout. Therefore, according to this configuration, it is possible to remove an error signal having a frequency that is the same as or close to that of the desired wave signal.
  • FIG. 5 is a block diagram schematically illustrating a configuration of the signal processing circuit 200 according to the second embodiment.
  • the signal processing circuit 200 has a configuration in which the second subtracter 12 and the first switch SW11 of the signal processing circuit 100 are deleted, and the first switch SW21 is added.
  • the first switch SW21 is connected between the inverting input terminal of the first subtractor 11 and the ground.
  • the first switch SW21 is turned on / off by a control signal SIG21 from the control circuit 18. Since the other configuration of the signal processing circuit 200 is the same as that of the signal processing circuit 100, description thereof is omitted.
  • FIG. 6 is a flowchart showing the error signal removal operation of the signal processing circuit 200.
  • 7A to 7C are block diagrams showing on / off of the first to third switches SW21, SW12, and SW13 of the signal processing circuit 200.
  • FIG. FIG. 8 is a timing chart showing the operation of the signal processing circuit 200. Timings T21 to T24 in FIG. 8 correspond to timings T11 to T14 in FIG. 4, respectively.
  • Steps S201 to S203 are the same as steps S101 to S103 in FIG.
  • the control circuit 18 turns on the first switch SW21 and the third switch SW13 by the control signals SIG21 and SIG13. Further, the control circuit 18 turns off the second switch SW12 by the control signal SIG12 (step S204 in FIG. 6).
  • steps S205 to S209 are the same as steps S105 to S109 in FIG.
  • the control circuit 18 After switching the storage device 15 to the write mode, as shown in FIG. 7B, the control circuit 18 turns off the first switch SW21 by the control signal SIG21. Further, the control circuit 18 turns on the second switch SW12 and the third switch SW13 by the control signals SIG12 and SIG13 (step S210 in FIG. 6). Subsequent steps S211 to S214 are the same as steps S111 to S114 in FIG.
  • step S216 is the same as step S116 of FIG.
  • the signal processing circuit 200 performs a normal operation in the same manner as the signal processing circuit 100.
  • the signal processing circuit 200 removes the error signal of the output signal Vout by subtracting the reproduction error signal err1_F from the error signal err1 at an appropriate timing. Therefore, only the detected signal is reflected in the output signal Vout. Therefore, according to this configuration, similarly to the first embodiment, it is possible to remove an error signal having a frequency that is the same as or close to that of the desired wave signal.
  • FIG. 9 is a block diagram schematically illustrating the configuration of the signal processing circuit 300 according to the third embodiment.
  • the signal processing circuit 300 has a configuration in which the filter 17 of the signal processing circuit 200 is removed and another filter 27 is added.
  • the filter 27 is inserted between the output of the first subtractor 11 and the output terminal Tout. Since the other configuration of the signal processing circuit 300 is the same as that of the signal processing circuit 200, description thereof is omitted.
  • the signal processing circuit 300 is a modification of the signal processing circuit 200 according to the second embodiment.
  • FIG. 10 is a flowchart showing the error signal removal operation of the signal processing circuit 300.
  • 11A to 11C are block diagrams showing on / off of the first to third switches SW21, SW12, and SW13 of the signal processing circuit 300.
  • FIG. FIG. 12 is a timing chart showing the operation of the signal processing circuit 300. Timings T31 to T34 in FIG. 12 correspond to timings T11 to T14 in FIG. 4, respectively.
  • Steps S301 to S303 are the same as steps S101 to S103 in FIG.
  • the control circuit 18 turns on the first switch SW21 and the third switch SW13 by the control signals SIG21 and SIG13. Further, the control circuit 18 turns off the second switch SW12 by the control signal SIG12 (step S304 in FIG. 10).
  • the first subtractor 11 outputs an error signal err1 to the filter 27.
  • the filter 27 is a filter that passes a signal having a frequency that is the same as or close to that of the desired wave signal Sd. Therefore, the error signal err1 passes through the filter 27 and is input to the ADC 13 via the third switch SW13.
  • the ADC 13 outputs a digital error signal err1_D obtained by A / D converting the error signal err1 to the storage device 15 (step S305 in FIG. 10).
  • Subsequent steps S306 to S309 are the same as steps S106 to S109 in FIG.
  • control circuit 18 After switching the storage device 15 to the read mode, the control circuit 18 turns off the first switch SW21 by the control signal SIG21 as shown in FIG. 11B. Further, the control circuit 18 turns on the second switch SW12 and the third switch SW13 by the control signals SIG12 and SIG13 (step S310 in FIG. 10).
  • control circuit 18 outputs the digital error signal err1_D stored in the storage device 15 by the control signal SIGm.
  • the DAC 16 outputs the reproduction error signal err1_R obtained by D / A converting the digital error signal err1_D to the inverting input terminal of the first subtractor 11 via the second switch SW12 (step S311 in FIG. 10).
  • the error signal err1 from the sensor circuit 102a is supplied to the non-inverting input terminal of the first subtractor 11. Therefore, the first subtracter 11 subtracts the reproduction error signal err1_R from the error signal err1 (step S312 in FIG. 10).
  • the filter 27 outputs a signal obtained by removing the high frequency component from the output of the first subtracter 11 as the output signal Vout.
  • the reproduction error signal err1_R is a reproduction of the digital error signal err1_D stored in the storage device 15. Therefore, even if the waveform changes to some extent by D / A conversion and A / D conversion, the waveforms of the reproduction error signal err1_R and the error signal err1 are approximated.
  • the signal processing circuit 300 does not filter the reproduction error signal err1_R, a high frequency component remains in the reproduction error signal err1_R.
  • the filter 27 is connected between the output of the first subtractor 11 and the output terminal Tout, the high frequency component resulting from the D / A conversion is removed from the output of the first subtractor 11. The Therefore, in this case, the output signal Vout of the signal processing circuit 300 is equivalent to that of the signal processing circuit 200.
  • the output of the first subtractor 11 is minimized and can be ideally zero. Therefore, in order to minimize the output of the first subtractor 11, it is necessary to match the timings of the error signal err1 and the reproduction error signal err1_R.
  • step S316 is the same as step S116 of FIG.
  • the signal processing circuit 300 After completion of the timing adjustment, the signal processing circuit 300 performs a normal operation in the same manner as the signal processing circuit 200. As described above, the signal processing circuit 300 removes the error signal of the output signal Vout by subtracting the reproduction error signal err1_R from the error signal err1 at an appropriate timing. Therefore, only the detected signal is reflected in the output signal Vout. Therefore, according to this configuration, similarly to the signal processing circuits 100 and 200, an error signal having a frequency that is the same as or close to that of the desired wave signal can be removed.
  • FIG. 13 is a block diagram schematically illustrating a configuration of the signal processing circuit 400 according to the fourth embodiment.
  • the signal processing circuit 400 has a configuration in which a delay line 40 is added to the signal processing circuit 300.
  • the delay line 40 is connected between the DAC 16 and the third switch SW13. Since the other configuration of the signal processing circuit 400 is the same as that of the signal processing circuit 300, description thereof is omitted.
  • FIG. 14 is a flowchart showing the error signal removal operation of the signal processing circuit 400.
  • 15A to 15C are block diagrams showing on / off of the first to third switches SW21, SW12, and SW13 of the signal processing circuit 400.
  • FIG. FIG. 16 is a timing chart showing the operation of the signal processing circuit 400. Timings T41 to T44 in FIG. 16 correspond to timings T11 to T14 in FIG. 4, respectively.
  • Steps S401 to S410 are the same as steps S101 to S110 in FIG.
  • the control circuit 18 outputs the digital error signal err1_D stored in the storage device 15 by the control signal SIGm.
  • the DAC 16 outputs a reproduction error signal err1_R obtained by D / A converting the digital error signal err1_D to the delay line 40.
  • the delay line 40 receives the reproduction error signal err1_RD, the output timing of the reproduction error signal err1_R having been adjusted by the control signal SIG40 from the control circuit 18, via the second switch SW12, and the inverting input terminal of the first subtractor 11. Output to.
  • the reproduction error signal err1_RD is an analog signal reproduced from the digital error signal err1_D stored in the storage device 15 (step S411 in FIG. 14).
  • the error signal err1 from the sensor circuit 102a is supplied to the non-inverting input terminal of the first subtractor 11. Therefore, the first subtracter 11 subtracts the reproduction error signal err1_RD from the error signal err1 (step S412 in FIG. 14).
  • the reproduction error signal err1_RD is a reproduction of the digital error signal err1_D stored in the storage device 15. Therefore, even if the waveform changes to some extent by D / A conversion and A / D conversion, the waveforms of the reproduction error signal err1_RD and the error signal err1 are approximated. Since the signal processing circuit 400 does not filter the reproduction error signal err1_RD, a high frequency component remains in the reproduction error signal err1_RD. However, since the filter 27 is connected between the output of the first subtractor 11 and the output terminal Tout, the high-frequency component due to D / A conversion is removed from the output signal Vout. Therefore, in this case, the output signal Vout of the signal processing circuit 400 is equivalent to that of the signal processing circuit 300.
  • the output of the first subtracter 11 is minimized and can be ideally zero. Therefore, in order to minimize the output of the first subtractor 11, it is necessary to match the timings of the error signal err1 and the reproduction error signal err1_RD.
  • step S413 is the same as step S113 in FIG.
  • the control circuit 18 delays the output timing of the delay line 40 by one step by the control signal SIG40 (step S414 in FIG. 14, timing T43 in FIG. 16).
  • the control circuit 18 may specify the output timing delay amount (step). Step S414 is repeated until the output OR_out of the multi-input OR circuit 14 becomes “0”.
  • step S416 is the same as step S116 of FIG.
  • the signal processing circuit 400 After the timing adjustment, the signal processing circuit 400 performs a normal operation in the same manner as the signal processing circuit 300. As described above, the signal processing circuit 400 removes the error signal of the output signal Vout by subtracting the reproduction error signal err1_RD from the error signal err1 at an appropriate timing. Therefore, only the detected signal is reflected in the output signal Vout. Therefore, according to this configuration, similarly to the signal processing circuits 100, 200, and 300, an error signal having a frequency that is the same as or close to that of the desired wave signal can be removed.
  • the delay line 40 adjusts the output timing of the reproduction error signal err1 which is an analog signal. Therefore, it is possible to finely adjust the output timing by using the delay line.
  • Embodiment 5 a signal processing circuit 500 according to a fifth embodiment of the present invention will be described.
  • a touch panel is used as a sensor circuit
  • the size of touch panels may be increased.
  • a capacitive touch panel for example, a uniform electric field is generated on the entire touch panel, so that power consumption increases as the size of the touch panel increases.
  • the area is 25 times and the power consumption is 25 times. Therefore, the performance of the IC corresponding to the 50-inch touch panel is also required 25 times.
  • the power consumption is not limited to a simple area doubled, and the power consumption can be further increased.
  • FIG. 17 is a block diagram schematically showing the configuration of the signal processing circuit 500 according to the fifth embodiment.
  • the signal processing circuit 500 is a modification of the signal processing circuit 300.
  • the signal processing circuit 500 has a configuration in which a third subtracter 50 and a fourth switch SW54 are added to the signal processing circuit 300.
  • the signal processing circuit 500 has a configuration in which the first switch SW21 of the signal processing circuit 300 is replaced with a first switch SW51.
  • a capacitive touch panel 102b is displayed as a sensor circuit.
  • the signal processing circuits 500 and 501 to 503 correspond to signal processing circuits that detect touch positions of the touch panel from four corners.
  • Each of the signal processing circuits 501 to 503 is a circuit equivalent to the signal processing circuit 500.
  • the inverting input terminal of the third subtracter 50 is connected to the output of the DAC 16, and the non-inverting input terminal is connected to the output terminal Tout.
  • the fourth switch SW54 is connected between the output of the third subtracter 50 and the input of the ADC 13.
  • the first switch SW51 is connected between the inverting input terminal of the first subtractor 11 and the signal source 101.
  • the first switch SW51 and the fourth switch SW54 are turned on / off by control signals SIG51 and SIG54 from the control circuit 18, respectively. Since the other configuration of the signal processing circuit 500 is the same as that of the signal processing circuit 300, the description thereof is omitted.
  • FIG. 18 is a flowchart showing the error signal removal operation of the signal processing circuit 500.
  • 19A to 19C are block diagrams showing on / off of the first to fourth switches SW51, SW12, SW13, and SW54 of the signal processing circuit 500.
  • FIG. FIG. 20 is a timing chart showing the operation of the signal processing circuit 500. Note that timings T51 to T54 in FIG. 20 correspond to timings T11 to T14 in FIG. 4, respectively.
  • the touch panel 102b which is the sensor circuit in this embodiment is ON
  • the touch panel 102b when the touch is not detected, that is, when the detected signal is not detected, ideally the same signal as the input is output. That is, the touch panel 102b when not detected ideally outputs the desired wave signal Sd as it is.
  • Steps S501 to S503 are the same as steps S301 to S303 in FIG.
  • the control circuit 18 turns on the first switch SW51 and the third switch SW13 by the control signals SIG51 and SIG13 as shown in FIG. 19A. Further, the control circuit 18 turns off the second switch SW12 and the fourth switch SW54 by the control signals SIG12 and SIG54 (step S504 in FIG. 18).
  • the first subtracter 11 subtracts the desired wave signal Sd from the output signal S_out of the sensor circuit including the error signal. As a result, the first subtractor 11 extracts the error signal err5. The extracted error signal err5 is supplied to the ADC 13 via the filter 27 and the third switch SW13.
  • the ADC 13 outputs a digital error signal err5_D obtained by A / D converting the error signal err5 to the storage device 15 (step S505 in FIG. 18).
  • the storage device 15 stores the value of each bit of the digital error signal err5_D (step S506 in FIG. 8). Note that the specific storage operation of the storage device 15 is the same as that of the first embodiment, and thus the description thereof is omitted. Subsequent steps S507 to S509 are the same as steps S307 to 309 in FIG.
  • control circuit 18 turns on the first switch SW51 and the fourth switch SW54 by the control signals SIG51 and SIG54 as shown in FIG. 19B. Further, the control circuit 18 turns off the second switch SW12 and the third switch SW13 by the control signals SIG12 and SIG13 (step S510 in FIG. 18).
  • control circuit 18 outputs the digital error signal err5_D stored in the storage device 15 by the control signal SIGm.
  • the DAC 16 outputs a reproduction error signal err5_R obtained by D / A converting the digital error signal err5_D to the inverting input terminal of the third subtracter 50 (step S511 in FIG. 18).
  • the third subtracter 50 outputs the output signal AMP_out obtained by subtracting the reproduction error signal err5_R from the error signal err5 to the ADC 13 via the fourth switch SW54 (step S512 in FIG. 18).
  • the reproduction error signal err5_R is a reproduction of the digital error signal err5_D stored in the storage device 15. Therefore, even if the waveform changes to some extent by D / A conversion and A / D conversion, the waveforms of the reproduction error signal err5_R and the error signal err5 are approximated.
  • the error signal component included in the output signal Vout can be minimized, and can be ideally zero. Therefore, in order to minimize the error signal component included in the output signal Vout, it is necessary to match the timings of the error signal err5 and the reproduction error signal err5_R.
  • the output signal Vout is 0 level. Therefore, when any bit of the digital signal AMP_out_D generated by the ADC 13 is “1”, it means that the timing of the error signal err5 and the reproduction error signal err5_R is shifted.
  • the output OR_out of the multi-input OR circuit 14 is “1” when any bit of the digital signal AMP_out_D is “1”, and “0” when all the bits of the digital signal AMP_out_D are “0”.
  • the multi-input OR circuit 14 can detect the presence / absence of a timing shift between the error signal err5 and the reproduction error signal err5_R (step S513 in FIG. 18).
  • step S514 is the same as step S214 in FIG.
  • step S516 is the same as step S216 in FIG.
  • the signal processing circuit 500 does not filter the reproduction error signal err5_R, a high frequency component remains in the reproduction error signal err5_R.
  • the filter 27 is connected between the output of the first subtractor 11 and the output terminal Tout, the D / A conversion is performed from the output of the first subtractor 11 in the same manner as the signal processing circuit 300.
  • the high-frequency component resulting from is removed. Therefore, in this case, the output signal Vout of the signal processing circuit 500 is equivalent to that of the signal processing circuit 300.
  • the signal processing circuit 500 After completion of timing adjustment, the signal processing circuit 500 performs a normal operation in the same manner as the signal processing circuit 300. As described above, the signal processing circuit 500 removes the error signal of the output signal Vout by subtracting the reproduction error signal err5_R from the error signal err5 at an appropriate timing. Thereby, even when the output of the sensor circuit when the detected signal is not detected is not 0, the error signal component included in the output signal Vout can be removed. Therefore, only the detected signal is reflected in the output signal Vout. Therefore, according to this configuration, similarly to the signal processing circuit 300, it is possible to remove an error signal having a frequency that is the same as or close to that of the desired wave signal.
  • the third subtracter 50 performs the subtraction operation only at the time of timing adjustment. That is, the third subtracter 50 does not function except during timing adjustment. Therefore, the circuit configuration of the signal processing circuit 500 other than the timing adjustment is substantially the same as that of the signal processing circuit 300. Therefore, the output signal Vout can be obtained even when the output of the sensor circuit is not 0 by simply adding the third subtractor 50 and the fourth switch SW54 to the signal processing circuit 300 and the detected signal is not easily detected. It is possible to realize a signal processing circuit that can remove the error signal component included in the.
  • the detected signal can be easily detected simply by adding the third subtractor 50 and the fourth switch SW54 between the third switch SW13 of the signal processing circuits 100, 200 and 400 and the input of the ADC 13. Even when the output of the sensor circuit when it is not performed is not 0, it is possible to realize a signal processing circuit that can remove the error signal component included in the output signal Vout.
  • the first switch SW 21 of the signal processing circuit 100 corresponds to the first switch SW 51 of the signal processing circuit 500. Further, the inverting input of the second subtractor 12 of the signal processing circuit 100 is connected to the signal source 101.
  • FIG. 21 is a block diagram schematically illustrating a configuration of a signal processing system 1000 according to the sixth embodiment.
  • the signal processing system 1000 has a configuration in which a CPU 1001 is connected to the signal processing circuit 300 according to the third embodiment.
  • the CPU 1001 supplies an enable signal en to the signal terminal Ten of the signal processing circuit 300. Further, the CPU 1001 receives a completion signal end from the signal terminal Tend of the signal processing circuit 300.
  • the CPU 1001 can instruct the signal processing circuit 300 to start the error signal removal operation by the enable signal en.
  • This start command can be issued by the CPU 1001 in response to an instruction from the user of the system. Further, the CPU 1001 monitors the environmental temperature, and can issue a start command when there is a certain temperature fluctuation.
  • the CPU 1001 recognizes the completion of the error signal removal operation by receiving the completion signal end from the signal processing circuit 300. Then, the CPU 1001 can transition the level of the enable signal en, and cause the signal processing circuit 300 to end the error signal removal operation.
  • the signal processing circuit 300 is used, but it goes without saying that the signal processing circuit 100, 200, 300, or 500 can be used.
  • the CPU is connected to the signal processing circuit.
  • the signal processing circuit it is connected to another computer or a microcomputer to construct a system. It is also possible to do.
  • the present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit of the present invention.
  • the filter 27 according to the third embodiment can be applied.
  • the delay line 40 according to the fourth embodiment can be applied to the signal processing circuits 100 and 200.
  • the signal processing circuit 500 is a signal processing in which the first switch SW51, the fourth switch SW54, and the third subtracter 50 are appropriately applied to the signal processing circuits 100, 200, 300, 400, and the above configuration change examples. It can also be replaced by a circuit.
  • the signal processing circuit 300 according to the sixth embodiment can be replaced not only with the signal processing circuits 100, 200, 400, and 500 but also with the signal processing circuit according to the above-described configuration change example.
  • a touch panel is used as a sensor circuit, but this is only an example. Therefore, the above-described signal processing circuit can be applied to any sensor circuit other than the touch panel.
  • the storage device 15 may be any storage device capable of writing / reading, and for example, a storage element such as a flash memory or other storage device capable of writing / reading may be used.
  • Second subtractor 13 ADC 14 Multi-input OR circuit 15 Storage device 16 DAC 17, 27 Filter 18 Control circuit 40 Delay line 50 Third subtractor 100, 200, 300, 400, 500 to 503 Signal processing circuit 101 Signal source 102a Sensor circuit 102b Touch panel 600 Filter circuit 601 Frequency converter 602, 621 A / D converter 610 Sampler 622 Digital filter 630 D / A converter 640 Delay unit 650 Subtractor 700 Noise cancellation circuit 701 Antenna 702 Filter 703 Phase inversion unit 704 Phase synchronization unit 705 Level adjustment unit 706 Oscillation unit 707 Adder 708 LNA 750 Interference wave countermeasure unit 1000 Signal processing system OR_out Output of multi-input OR circuit S_out Output signal of sensor circuit SIG11 to 13, SIG21, SIG40, SIG51, SIG54, SIGm Control signal SW11 to SW13, SW21, SW51, SW54 Switch Sd Desired wave Signal Ten, Tend signal terminal Tout output terminal Vout output signal Vout_

Abstract

When a sensor circuit (102a) which is connected to a signal source (101) does not detect a signal which is an object of detection, a storage device (15) stores a signal waveform of a prescribed interval of an error signal having the same frequency as that of a desired signal (Sd), which is outputted from the sensor circuit (102a). A D/A converter (16) repeatedly outputs a play error signal, which plays the error signal from a digital error signal which is stored in the storage unit (15), at prescribed intervals. A first subtraction device (11) outputs an output signal (Vout), wherein the play error signal is subtracted from the error signal, to an output terminal (Tout). In the state wherein the sensor circuit (102a) does not detect the signal which is the object of detection, a control circuit (18) adjusts the timing of the supply of the play error signal to the first subtraction device (11) such that the signal level of the output signal (Vout) of the first subtraction device (11) is minimized.

Description

信号処理回路及び信号処理方法Signal processing circuit and signal processing method
　本発明は信号処理回路及び信号処理方法に関し、特に誤差信号を除去する信号処理回路及び信号処理方法に関する。 The present invention relates to a signal processing circuit and a signal processing method, and more particularly to a signal processing circuit and a signal processing method for removing an error signal.
　電化製品での信号検出のため、センサ回路が広く用いられている。近年、センサ回路の高精度化が進展しており、希望波信号に乗った誤差信号の影響が問題となっている。そのため、誤差信号を除去する技術の重要性が増している。 Sensor circuits are widely used for signal detection in electrical appliances. In recent years, the accuracy of sensor circuits has been improved, and the influence of an error signal on a desired wave signal has become a problem. For this reason, the importance of techniques for removing error signals is increasing.
　誤差信号除去のため、フィルタ回路により誤差信号を除去する構成が知られている（特許文献１及び２）。図２２は、特許文献１にかかるフィルタ回路６００の構成を示すブロック図である。フィルタ回路６００は、２つの経路の信号遅延を等しくし、誤差信号を精度よく除去することを目的としたフィルタ回路である。 A configuration is known in which an error signal is removed by a filter circuit in order to remove an error signal (Patent Documents 1 and 2). FIG. 22 is a block diagram showing a configuration of a filter circuit 600 according to Patent Document 1. As shown in FIG. The filter circuit 600 is a filter circuit for the purpose of equalizing the signal delays of the two paths and accurately removing the error signal.
　より具体的には、周波数変換器６０１から誤差信号を含む信号が入力された際、サンプラ６１０はアナログ離散時間信号を生成する。アナログ離散時間信号は、Ａ／Ｄコンバータ（ＡＤＣ）６２１でデジタル信号に変換される。デジタル信号は、所望帯域外の信号を抽出するデジタルフィルタ６２２を通過する。デジタル信号は、その後Ｄ／Ａコンバータ（ＤＡＣ）６３０でアナログ信号に変換される。そして、減算器６５０は、遅延器６４０を通過したアナログ離散時間信号から、ＤＡＣ６３０で生成されたアナログ信号を減算する。減算器６５０の減算結果は、Ａ／Ｄコンバータ（ＡＤＣ）６０２によりデジタル信号に変換され、出力される。サンプラ６１０で生成されるアナログ離散時間信号は所定クロック分保持されて出力される。そのため、遅延器６４０により正確な信号遅延が生成され、減算器６５０において精度よく誤差信が除去される。この他にも、サンプラによって信号遅延を発生させるだけでなく、デジタルフィルタも制御することにより、正確な信号遅延を発生させる構成が知られている（特許文献２）。 More specifically, when a signal including an error signal is input from the frequency converter 601, the sampler 610 generates an analog discrete time signal. The analog discrete time signal is converted into a digital signal by an A / D converter (ADC) 621. The digital signal passes through a digital filter 622 that extracts signals outside the desired band. The digital signal is then converted to an analog signal by a D / A converter (DAC) 630. Then, the subtracter 650 subtracts the analog signal generated by the DAC 630 from the analog discrete time signal that has passed through the delay unit 640. The subtraction result of the subtracter 650 is converted into a digital signal by an A / D converter (ADC) 602 and output. The analog discrete time signal generated by the sampler 610 is held for a predetermined clock and output. Therefore, an accurate signal delay is generated by the delay unit 640, and the error signal is accurately removed by the subtractor 650. In addition to this, there is known a configuration in which an accurate signal delay is generated by controlling not only a signal delay by a sampler but also a digital filter (Patent Document 2).
　また、希望波信号の周波数と近接する所定の周波数のノイズ信号の影響を少なくすることを目的とし、適正に希望波信号を受信可能にするノイズキャンセル回路が知られている（特許文献３)。以下、例としてノイズキャンセル回路７００について説明する。図２３は、特許文献３にかかるノイズキャンセル回路７００の構成を示すブロック図である。ノイズキャンセル回路７００では、希望波信号にノイズ信号を含む信号がアンテナ７０１から入力される。フィルタ７０２は、入力信号に含まれる希望波信号を減衰させ、ノイズ信号のみを取り出す。位相反転部７０３は、ノイズ信号の位相を反転させる。一方、発振部７０６では所定の周波数でノイズ信号を発振する。レベル調節部７０５は、発振されたノイズ信号のレベルを調節する。位相同期部７０４は、位相を反転したノイズ信号とレベル調節を受けたノイズ信号の位相の同期を行う。加算器７０７は、入力信号と位相同期部７０４の出力とを加算する。位相同期部７０４の出力は、ＬＮＡ７０８を通じて、受信回路等に出力される。上述のフィルタ７０２、位相反転部７０３、位相同期部７０４、レベル調節部７０５及び発振部７０６は、妨害波対策部７５０を構成している。 Also, a noise canceling circuit that makes it possible to appropriately receive a desired wave signal is known for the purpose of reducing the influence of a noise signal having a predetermined frequency close to the frequency of the desired wave signal (Patent Document 3). Hereinafter, the noise cancellation circuit 700 will be described as an example. FIG. 23 is a block diagram showing a configuration of a noise cancellation circuit 700 according to Patent Document 3. As shown in FIG. In the noise cancellation circuit 700, a signal including a noise signal in a desired wave signal is input from the antenna 701. The filter 702 attenuates the desired wave signal included in the input signal and extracts only the noise signal. The phase inverting unit 703 inverts the phase of the noise signal. On the other hand, the oscillation unit 706 oscillates a noise signal at a predetermined frequency. The level adjustment unit 705 adjusts the level of the oscillated noise signal. The phase synchronization unit 704 synchronizes the phase of the noise signal whose phase is inverted and the noise signal subjected to level adjustment. Adder 707 adds the input signal and the output of phase synchronization section 704. The output of the phase synchronization unit 704 is output to a reception circuit or the like through the LNA 708. The filter 702, the phase inversion unit 703, the phase synchronization unit 704, the level adjustment unit 705, and the oscillation unit 706 constitute an interference wave countermeasure unit 750.
特開２００９－６５２７８号公報JP 2009-65278 A 特開２００９－２１２５８７号公報JP 2009-212587 A 特開２００８－２０６１０３号公報JP 2008-206103 A
　しかし、発明者が上述の技術について検討を行ったところ、上述の回路によっては、誤差信号の周波数が希望波信号の周波数と同じ又は近接する場合に、誤差信号を除去できないことを見出した。この問題は、誤差信号を抽出する際に、希望波信号の周波数帯を減衰させると、希望波信号と同じ又は近接する周波数の誤差信号まで減衰させてしまうために発生する。 However, the inventors have studied the above-described technique and found that, depending on the above-described circuit, the error signal cannot be removed when the frequency of the error signal is the same as or close to the frequency of the desired wave signal. This problem occurs because when the error signal is extracted, if the frequency band of the desired wave signal is attenuated, an error signal having the same frequency as or close to that of the desired wave signal is attenuated.
　例えば、特許文献１及び２にかかる回路に希望波信号と同じ周波数の誤差信号を含む信号が入力された場合について検討する。この場合、誤差信号抽出のためにデジタルフィルタで希望波信号の周波数を除去すると、希望波信号と同じ又は近接する周波数の誤差信号まで除去されてしまう。そのため、減算器からは、入力された信号と同じ又は近接する周波数の誤差信号を含んだ信号が出力されてしまう。よって、例えば希望波信号と振幅が異なる信号が出力されることとなる。 For example, consider the case where a signal including an error signal having the same frequency as the desired wave signal is input to the circuits according to Patent Documents 1 and 2. In this case, if the frequency of the desired wave signal is removed by the digital filter for extracting the error signal, an error signal having the same frequency as or close to the desired wave signal is also removed. For this reason, the subtracter outputs a signal including an error signal having a frequency that is the same as or close to that of the input signal. Therefore, for example, a signal having an amplitude different from that of the desired wave signal is output.
　また、例えば、特許文献特３にかかる回路に希望波信号と同じ周波数の誤差信号を含む信号が入力された場合について検討する。この場合、上述と同様に、誤差信号抽出のためにデジタルフィルタで希望波信号の周波数を除去すると、希望波信号と同じ又は近接する周波数の誤差信号まで除去されてしまう。そのため、その後の位相同期部７０４で誤差信号の位相を同期することができない。よって、加算器からは、入力された信号と同じ又は近接する周波数の誤差信号を含んだ信号が出力されてしまう。よって、例えば希望波信号と振幅が異なる信号が出力されることとなる。 Also, for example, a case where a signal including an error signal having the same frequency as that of the desired wave signal is input to the circuit according to Patent Document No. 3 will be considered. In this case, as described above, when the frequency of the desired wave signal is removed by the digital filter for extracting the error signal, an error signal having the same frequency as or close to the desired wave signal is also removed. Therefore, the subsequent phase synchronization unit 704 cannot synchronize the phase of the error signal. Therefore, the adder outputs a signal including an error signal having a frequency that is the same as or close to that of the input signal. Therefore, for example, a signal having an amplitude different from that of the desired wave signal is output.
　本発明の一態様である信号処理回路は、信号源と接続されるセンサ回路が検出対象となる信号を検出していない場合において、前記センサ回路から出力される前記信号源が出力する信号と同じ周波数の誤差信号の所定期間の信号波形を記憶する記憶装置と、前記記憶装置に記憶された前記信号波形から前記誤差信号を再生した再生誤差信号を、前記所定期間ごとに繰り返し出力する再生誤差信号出力部と、前記誤差信号から前記再生誤差信号を減算した信号を、出力端子へ出力する第１の減算器と、前記センサ回路が検出対象となる信号を検出していない状態で、前記第１の減算器の出力信号の信号レベルが最小化するように、前記第１の減算器への前記再生誤差信号の供給タイミングを調整する制御回路と、を備えるものである。本発明の一態様である信号処理回路は、希望波信号と同じ又は近接する周波数の誤差信号を抽出する。そして、誤差信号を抽出した誤差信号で減算する。これにより、誤差信号を除去することができる。 The signal processing circuit which is one embodiment of the present invention is the same as the signal output by the signal source output from the sensor circuit when the sensor circuit connected to the signal source does not detect the signal to be detected. A storage device for storing a signal waveform of a frequency error signal for a predetermined period, and a reproduction error signal for repeatedly outputting a reproduction error signal obtained by reproducing the error signal from the signal waveform stored in the storage device for each predetermined period An output unit; a first subtracter that outputs a signal obtained by subtracting the reproduction error signal from the error signal to an output terminal; and the first detection circuit in a state where the sensor circuit does not detect a signal to be detected. And a control circuit that adjusts the supply timing of the reproduction error signal to the first subtractor so as to minimize the signal level of the output signal of the subtractor. A signal processing circuit which is one embodiment of the present invention extracts an error signal having a frequency that is the same as or close to that of a desired wave signal. Then, the error signal is subtracted by the extracted error signal. Thereby, an error signal can be removed.
　本発明の一態様である信号処理方法は、信号源と接続されるセンサ回路が検出対象となる信号を検出していない場合において、前記センサ回路から出力される前記信号源が出力する信号と同じ周波数の誤差信号の所定期間の信号波形を、記憶装置に記憶させ、前記記憶装置に記憶された前記信号波形から前記誤差信号を再生した再生誤差信号を、前記所定期間ごとに繰り返し出力し、第１の減算器が前記誤差信号から前記再生誤差信号を減算した信号を、出力端子へ出力し、前記センサ回路が検出対象となる信号を検出していない状態で、前記第１の減算器の出力信号の信号レベルが最小化するように、前記第１の減算器への前記再生誤差信号の供給タイミングを調整するものである。本発明の一態様である信号処理方法は、希望波信号と同じ又は近接する周波数の誤差信号を抽出する。そして、誤差信号を抽出した誤差信号で減算する。これにより、誤差信号を除去することができる。 The signal processing method according to one embodiment of the present invention is the same as the signal output from the signal source that is output from the sensor circuit when the sensor circuit connected to the signal source does not detect the signal to be detected. A signal waveform of a frequency error signal for a predetermined period is stored in a storage device, and a reproduction error signal obtained by reproducing the error signal from the signal waveform stored in the storage device is repeatedly output for each predetermined period. The first subtracter outputs a signal obtained by subtracting the reproduction error signal from the error signal to an output terminal, and the output of the first subtracter is not detected by the sensor circuit. The supply timing of the reproduction error signal to the first subtracter is adjusted so that the signal level of the signal is minimized. The signal processing method according to one embodiment of the present invention extracts an error signal having a frequency that is the same as or close to that of the desired wave signal. Then, the error signal is subtracted by the extracted error signal. Thereby, an error signal can be removed.
　本発明によれば、希望波信号と同じ又は近接する誤差信号を除去することができる信号処理回路及び信号処理方法を提供することができる。 According to the present invention, it is possible to provide a signal processing circuit and a signal processing method capable of removing an error signal that is the same as or close to that of a desired wave signal.
実施の形態１にかかる信号処理回路１００の構成を模式的に示すブロック図である。1 is a block diagram schematically showing a configuration of a signal processing circuit 100 according to a first exemplary embodiment. 実施の形態１にかかる信号処理回路１００の誤差信号除去動作を示すフローチャートである。3 is a flowchart showing an error signal removal operation of the signal processing circuit 100 according to the first exemplary embodiment; 実施の形態１にかかる信号処理回路１００の第１～第３のスイッチのオン／オフを示すブロック図である。FIG. 3 is a block diagram showing ON / OFF of first to third switches of the signal processing circuit 100 according to the first exemplary embodiment; 実施の形態１にかかる信号処理回路１００の第１～第３のスイッチのオン／オフを示すブロック図である。FIG. 3 is a block diagram showing ON / OFF of first to third switches of the signal processing circuit 100 according to the first exemplary embodiment; 実施の形態１にかかる信号処理回路１００の第１～第３のスイッチのオン／オフを示すブロック図である。FIG. 3 is a block diagram showing ON / OFF of first to third switches of the signal processing circuit 100 according to the first exemplary embodiment; 実施の形態２にかかる信号処理回路２００の動作を示すタイミングチャートである。6 is a timing chart illustrating an operation of the signal processing circuit 200 according to the second exemplary embodiment; 実施の形態２にかかる信号処理回路２００の構成を模式的に示すブロック図である。FIG. 3 is a block diagram schematically showing a configuration of a signal processing circuit 200 according to a second exemplary embodiment. 実施の形態２にかかる信号処理回路２００の誤差信号除去動作を示すフローチャートである。6 is a flowchart showing an error signal removal operation of the signal processing circuit 200 according to the second exemplary embodiment; 実施の形態２にかかる信号処理回路２００の第１～第３のスイッチのオン／オフを示すブロック図である。FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 200 according to a second exemplary embodiment. 実施の形態２にかかる信号処理回路２００の第１～第３のスイッチのオン／オフを示すブロック図である。FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 200 according to a second exemplary embodiment. 実施の形態２にかかる信号処理回路２００の第１～第３のスイッチのオン／オフを示すブロック図である。FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 200 according to a second exemplary embodiment. 実施の形態２にかかる信号処理回路２００の動作を示すタイミングチャートである。6 is a timing chart illustrating an operation of the signal processing circuit 200 according to the second exemplary embodiment; 実施の形態３にかかる信号処理回路３００の構成を模式的に示すブロック図である。FIG. 6 is a block diagram schematically showing a configuration of a signal processing circuit 300 according to a third exemplary embodiment. 実施の形態３にかかる信号処理回路３００の誤差信号除去動作を示すフローチャートである。10 is a flowchart showing an error signal removal operation of the signal processing circuit 300 according to the third exemplary embodiment. 実施の形態３にかかる信号処理回路３００の第１～第３のスイッチのオン／オフを示すブロック図である。FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 300 according to a third exemplary embodiment. 実施の形態３にかかる信号処理回路３００の第１～第３のスイッチのオン／オフを示すブロック図である。FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 300 according to a third exemplary embodiment. 実施の形態３にかかる信号処理回路３００の第１～第３のスイッチのオン／オフを示すブロック図である。FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 300 according to a third exemplary embodiment. 実施の形態３にかかる信号処理回路３００の動作を示すタイミングチャートである。10 is a timing chart illustrating an operation of the signal processing circuit 300 according to the third exemplary embodiment. 実施の形態４にかかる信号処理回路４００の構成を模式的に示すブロック図である。FIG. 6 is a block diagram schematically showing a configuration of a signal processing circuit 400 according to a fourth exemplary embodiment. 実施の形態４にかかる信号処理回路４００の誤差信号除去動作を示すフローチャートである。10 is a flowchart illustrating an error signal removal operation of the signal processing circuit 400 according to the fourth embodiment. 実施の形態４にかかる信号処理回路４００の第１～第３のスイッチのオン／オフを示すブロック図である。FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 400 according to a fourth exemplary embodiment. 実施の形態４にかかる信号処理回路４００の第１～第３のスイッチのオン／オフを示すブロック図である。FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 400 according to a fourth exemplary embodiment. 実施の形態４にかかる信号処理回路４００の第１～第３のスイッチのオン／オフを示すブロック図である。FIG. 6 is a block diagram showing ON / OFF of first to third switches of a signal processing circuit 400 according to a fourth exemplary embodiment. 実施の形態４にかかる信号処理回路４００の動作を示すタイミングチャートである。10 is a timing chart illustrating an operation of the signal processing circuit 400 according to the fourth embodiment. 実施の形態５にかかる信号処理回路５００の構成を模式的に示すブロック図である。FIG. 10 is a block diagram schematically showing a configuration of a signal processing circuit 500 according to a fifth embodiment. 実施の形態５にかかる信号処理回路５００の誤差信号除去動作を示すフローチャートである。10 is a flowchart showing an error signal removal operation of the signal processing circuit 500 according to the fifth exemplary embodiment. 実施の形態５にかかる信号処理回路５００の第１～第３のスイッチのオン／オフを示すブロック図である。FIG. 10 is a block diagram showing on / off of first to third switches of a signal processing circuit 500 according to a fifth exemplary embodiment; 実施の形態５にかかる信号処理回路５００の第１～第３のスイッチのオン／オフを示すブロック図である。FIG. 10 is a block diagram showing on / off of first to third switches of a signal processing circuit 500 according to a fifth exemplary embodiment; 実施の形態５にかかる信号処理回路５００の第１～第３のスイッチのオン／オフを示すブロック図である。FIG. 10 is a block diagram showing on / off of first to third switches of a signal processing circuit 500 according to a fifth exemplary embodiment; 実施の形態５にかかる信号処理回路５００の動作を示すタイミングチャートである。10 is a timing chart illustrating an operation of the signal processing circuit 500 according to the fifth embodiment; 実施の形態６にかかる信号処理システム１０００の構成を模式的に示すブロック図である。FIG. 10 is a block diagram schematically showing a configuration of a signal processing system 1000 according to a sixth exemplary embodiment. 特許文献１にかかるフィルタ回路６００の構成を示すブロック図である。10 is a block diagram illustrating a configuration of a filter circuit 600 according to Patent Document 1. FIG. 特許文献３にかかるノイズキャンセル回路７００の構成を示すブロック図である。10 is a block diagram showing a configuration of a noise cancellation circuit 700 according to Patent Document 3. FIG.
　以下、図面を参照して本発明の実施の形態について説明する。各図面においては、同一要素には同一の符号が付されており、必要に応じて重複説明は省略される。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted as necessary.
　実施の形態１
　まず、本発明の実施の形態１にかかる信号処理回路１００について説明する。図１は、実施の形態１にかかる信号処理回路１００の構成を模式的に示すブロック図である。信号処理回路１００は、センサ回路１０２ａを介して、信号源１０１と接続される。信号源１０１は、希望波信号Ｓｄを出力する。センサ回路１０２ａは、信号処理回路１００が組み込まれた装置の使用者の操作などにより生じた被検出信号を検出する。センサ回路１０２ａは、使用者の操作などが無い場合、すなわち被検出信号を検出していない場合には、理想的にはその出力が０となる回路である。 Embodiment 1
First, the signal processing circuit 100 according to the first exemplary embodiment of the present invention will be described. FIG. 1 is a block diagram schematically illustrating the configuration of the signal processing circuit 100 according to the first embodiment. The signal processing circuit 100 is connected to the signal source 101 via the sensor circuit 102a. The signal source 101 outputs a desired wave signal Sd. The sensor circuit 102a detects a detected signal generated by an operation of a user of an apparatus in which the signal processing circuit 100 is incorporated. The sensor circuit 102a is an ideal circuit whose output is zero when there is no user operation, that is, when no detected signal is detected.
　信号処理回路１００は、第１の減算器１１、第２の減算器１２、アナログ／デジタル変換器（Analog to Digital Converter：以下ＡＤＣと称する）１３、多入力ＯＲ回路１４、記憶装置１５、デジタル／アナログ変換器（Digital to Analog Converter：以下ＤＡＣと称する）１６、フィルタ１７、制御回路１８、第１～第３のスイッチＳＷ１１～ＳＷ１３、出力端子Ｔｏｕｔ及び信号端子Ｔｅｎ及びＴｅｎｄを有する。 The signal processing circuit 100 includes a first subtractor 11, a second subtractor 12, an analog / digital converter (hereinafter referred to as ADC) 13, a multi-input OR circuit 14, a storage device 15, a digital / digital converter It has an analog converter (Digital-to-Analog Converter: hereinafter referred to as DAC) 16, a filter 17, a control circuit 18, first to third switches SW11 to SW13, an output terminal Tout, and signal terminals Ten and Tend.
　第１の減算器１１は、非反転入力端子がセンサ回路１０２ａの出力と接続され、反転入力端子が第２のスイッチＳＷ１２を介してフィルタ１７の出力と接続される。第１の減算器１１の出力は、出力端子Ｔｏｕｔと接続され、出力信号Ｖｏｕｔを出力する。また、第１の減算器１１の出力は、第３のスイッチＳＷ１３を介してＡＤＣ１３の入力と接続される。 The first subtractor 11 has a non-inverting input terminal connected to the output of the sensor circuit 102a, and an inverting input terminal connected to the output of the filter 17 via the second switch SW12. The output of the first subtractor 11 is connected to the output terminal Tout and outputs an output signal Vout. The output of the first subtractor 11 is connected to the input of the ADC 13 via the third switch SW13.
　第２の減算器１２は、非反転入力端子がセンサ回路１０２ａの出力と接続され、反転入力端子がグランドと接続される。第２の減算器１２の出力は、第１のスイッチＳＷ１１を介して、ＡＤＣ１３の入力と接続される。 The second subtracter 12 has a non-inverting input terminal connected to the output of the sensor circuit 102a and an inverting input terminal connected to the ground. The output of the second subtractor 12 is connected to the input of the ADC 13 via the first switch SW11.
　ＡＤＣ１３の出力は、多入力ＯＲ回路１４及び記憶装置１５の入力と接続される。ＡＤＣ１３の出力は、ＡＤＣ１３の出力のビット数に応じた本数が設けられる。多入力ＯＲ回路１４の出力ＯＲ＿ｏｕｔは、制御回路１８の対応する入力と接続される。記憶装置１５の出力は、ＤＡＣ１６の入力と接続される。ＤＡＣ１６の出力はフィルタ１７の入力と接続される。 The output of the ADC 13 is connected to the inputs of the multi-input OR circuit 14 and the storage device 15. The number of outputs of the ADC 13 is set according to the number of bits of the output of the ADC 13. An output OR_out of the multi-input OR circuit 14 is connected to a corresponding input of the control circuit 18. The output of the storage device 15 is connected to the input of the DAC 16. The output of the DAC 16 is connected to the input of the filter 17.
　制御回路１８は、信号端子Ｔｅｎを介して、信号処理回路１００の外部からイネーブル信号ｅｎが入力される。制御回路１８は、第１～第３のスイッチＳＷ１１～ＳＷ１３への制御信号ＳＩＧ１１～ＳＩＧ１３、記憶装置１５への制御信号ＳＩＧｍを出力する。制御回路１８は、信号端子Ｔｅｎｄを介して、信号処理回路１００の外部へ完了信号ｅｎｄを出力する。 The control circuit 18 receives the enable signal en from the outside of the signal processing circuit 100 via the signal terminal Ten. The control circuit 18 outputs control signals SIG11 to SIG13 to the first to third switches SW11 to SW13 and a control signal SIGm to the storage device 15. The control circuit 18 outputs a completion signal end to the outside of the signal processing circuit 100 via the signal terminal Tend.
　続いて、信号処理回路１００の誤差信号除去動作について説明する。図２は、信号処理回路１００の誤差信号除去動作を示すフローチャートである。図３Ａ～図３Ｃは、信号処理回路１００の第１～第３のスイッチＳＷ１１～ＳＷ１３のオン／オフを示すブロック図である。図４は、信号処理回路１００の動作を示すタイミングチャートである。 Subsequently, the error signal removal operation of the signal processing circuit 100 will be described. FIG. 2 is a flowchart showing the error signal removal operation of the signal processing circuit 100. 3A to 3C are block diagrams showing ON / OFF of the first to third switches SW11 to SW13 of the signal processing circuit 100. FIG. FIG. 4 is a timing chart showing the operation of the signal processing circuit 100.
　上述のように、センサ回路１０２ａは、被検出信号を検出していない場合（非検出時）には、理想的にはその出力が０となる回路であるが、実際には、被検出時でも誤差信号を出力している。この誤差信号は、信号源及びセンサ回路間などの回路構成に依存する信号であり、信号源が出力する希望波信号と同じ周波数を有する。図４に示すように、初期状態において、センサ回路１０２ａからは、希望波信号と同じ周波数の誤差信号ｅｒｒ１が出力されている。 As described above, the sensor circuit 102a is a circuit in which the output is ideally 0 when the detected signal is not detected (when not detected), but actually, even when the detected signal is detected. An error signal is output. This error signal is a signal that depends on the circuit configuration such as between the signal source and the sensor circuit, and has the same frequency as the desired wave signal output from the signal source. As shown in FIG. 4, in the initial state, the error signal err1 having the same frequency as the desired wave signal is output from the sensor circuit 102a.
　まず、制御回路１８は、イネーブル信号ｅｎがＨｉｇｈであるか否かを判定する（図２のステップＳ１０１）。イネーブル信号がＨｉｇｈであるならば、制御回路１８は誤差信号抽出モードへ移行する（図２のステップＳ１０２、図４のタイミングＴ１１）。制御回路１８は、制御信号ＳＩＧｍにより、記憶装置１５を書き込みモードに切り替える（図２のステップＳ１０３）。 First, the control circuit 18 determines whether or not the enable signal en is High (Step S101 in FIG. 2). If the enable signal is High, the control circuit 18 shifts to the error signal extraction mode (Step S102 in FIG. 2, timing T11 in FIG. 4). The control circuit 18 switches the storage device 15 to the write mode by the control signal SIGm (step S103 in FIG. 2).
　制御回路１８は、図３Ａに示すように、制御信号ＳＩＧ１１により、第１のスイッチＳＷ１１をオンにする。また、制御回路１８は、制御信号ＳＩＧ１２及びＳＩＧ１３により、第２のスイッチＳＷ１２及び第３のスイッチＳＷ１３をオフにする（図２のステップＳ１０４）。 The control circuit 18 turns on the first switch SW11 by the control signal SIG11 as shown in FIG. 3A. Further, the control circuit 18 turns off the second switch SW12 and the third switch SW13 by the control signals SIG12 and SIG13 (step S104 in FIG. 2).
　ＡＤＣ１３は、第１の減算器１１から出力される誤差信号ｅｒｒ１をＡ／Ｄ変換したデジタル誤差信号ｅｒｒ１＿Ｄを、記憶装置１５に出力する（図２のステップＳ１０５）。記憶装置１５は、デジタル誤差信号ｅｒｒ１＿Ｄの各ビットの値を記憶する。なお、記憶装置１５は、少なくとも希望波信号Ｓｄの１周期以上の期間のデジタル誤差信号ｅｒｒ１＿Ｄを記憶する。記憶装置１５がデジタル誤差信号ｅｒｒ１＿Ｄを記憶する、少なくとも希望波信号Ｓｄの１周期以上の期間を、誤差信号抽出期間と称する。記憶装置１５は、誤差信号抽出期間を所定の時間に分割して定められた記憶タイミングに応じて、デジタル誤差信号ｅｒｒ１＿Ｄを記憶する（図２のステップＳ１０６）。 The ADC 13 outputs a digital error signal err1_D obtained by A / D converting the error signal err1 output from the first subtractor 11 to the storage device 15 (step S105 in FIG. 2). The storage device 15 stores the value of each bit of the digital error signal err1_D. The storage device 15 stores a digital error signal err1_D for a period of at least one cycle of the desired wave signal Sd. A period in which the storage device 15 stores the digital error signal err1_D is at least one period of the desired wave signal Sd is referred to as an error signal extraction period. The storage device 15 stores the digital error signal err1_D according to the storage timing determined by dividing the error signal extraction period into a predetermined time (step S106 in FIG. 2).
　記憶装置１５の動作について、具体例を説明する。希望波信号Ｓｄの周期をＴとすると、記憶装置１５は、例えば周期Ｔの間に、複数回のデジタル誤差信号ｅｒｒ１＿Ｄの記憶動作を行う。周期Ｔの間のデジタル誤差信号ｅｒｒ１＿Ｄの記憶回数を好適に設定することにより、周期Ｔの間のデジタル誤差信号ｅｒｒ１＿Ｄの変動を反映することが可能である。複数回の記憶動作は、例えば時間的に等間隔で行うことが可能である。この場合、例えば、制御回路１８からのクロック信号ＣＬＫに基づいて、記憶動作を行うことが可能である。これにより、１周期の間のデジタル誤差信号ｅｒｒ１＿Ｄの波形をデジタル値として記憶することができる。 A specific example of the operation of the storage device 15 will be described. Assuming that the cycle of the desired wave signal Sd is T, the storage device 15 stores the digital error signal err1_D multiple times during the cycle T, for example. By suitably setting the number of times the digital error signal err1_D is stored during the period T, it is possible to reflect the fluctuation of the digital error signal err1_D during the period T. A plurality of storage operations can be performed at regular intervals, for example. In this case, for example, the storage operation can be performed based on the clock signal CLK from the control circuit 18. Thereby, the waveform of the digital error signal err1_D during one cycle can be stored as a digital value.
　また、周期Ｔの間の記憶動作を１セットとして、複数回のセットを繰り返してデジタル誤差信号ｅｒｒ１＿Ｄの平均値を取ることにより、デジタル誤差信号ｅｒｒ１＿Ｄを記憶することも可能である。制御回路１８は、制御信号ＳＩＧｍにより、セットの繰り返し数を制御することも可能である。 It is also possible to store the digital error signal err1_D by taking the average value of the digital error signal err1_D by repeating a plurality of sets and setting the storage operation during the period T as one set. The control circuit 18 can also control the number of set repetitions by a control signal SIGm.
　制御回路１８は、記憶装置１５が記憶動作を開始してから所定の時間が経過したかを判断する（図２のステップＳ１０７）。この判断では、予め定められた誤差信号抽出期間が経過したか、あるいは予め定められたセット数だけ記憶動作を行ったかを判断する。 The control circuit 18 determines whether a predetermined time has elapsed since the storage device 15 started the storage operation (step S107 in FIG. 2). In this determination, it is determined whether a predetermined error signal extraction period has elapsed or a storage operation has been performed for a predetermined number of sets.
　所定期間が経過していたならば、制御回路１８はタイミング調整モードへ移行する（図２のステップＳ１０８）。制御回路１８は、制御信号ＳＩＧｍにより、記憶装置１５を読み出しモードに切り替える（図２のステップＳ１０９）。そして、制御回路１８は、図３Ｂに示すように、制御信号ＳＩＧ１１により、第１のスイッチＳＷ１１をオフにする。また、制御回路１８は、制御信号ＳＩＧ１２及びＳＩＧ１３により、第２のスイッチＳＷ１２及び第３のスイッチＳＷ１３をオンにする（図２のステップＳ１１０、図４のタイミングＴ１２）。 If the predetermined period has elapsed, the control circuit 18 shifts to the timing adjustment mode (step S108 in FIG. 2). The control circuit 18 switches the storage device 15 to the read mode by the control signal SIGm (step S109 in FIG. 2). Then, as shown in FIG. 3B, the control circuit 18 turns off the first switch SW11 by the control signal SIG11. Further, the control circuit 18 turns on the second switch SW12 and the third switch SW13 by the control signals SIG12 and SIG13 (step S110 in FIG. 2, timing T12 in FIG. 4).
　次いで、制御回路１８は、制御信号ＳＩＧｍにより、記憶装置１５に記憶されたデジタル誤差信号ｅｒｒ１＿Ｄを出力させる。ＤＡＣ１６は、デジタル誤差信号ｅｒｒ１＿ＤをＤ／Ａ変換した再生誤差信号ｅｒｒ１＿Ｒを、フィルタ１７へ出力する。すなわち、ＤＡＣ１６から出力された再生誤差信号ｅｒｒ１＿Ｒは、記憶装置１５に記憶されたデジタル誤差信号ｅｒｒ１＿Ｄから再生されたアナログ信号である。フィルタ１７は、再生誤差信号ｅｒｒ１＿Ｒから高周波成分を取りのぞいた再生誤差信号ｅｒｒ１＿Ｆを、第２のスイッチＳＷ１２を介して、第１の減算器１１の反転入力端子へ出力する（図２のステップＳ１１１）。 Next, the control circuit 18 outputs the digital error signal err1_D stored in the storage device 15 by the control signal SIGm. The DAC 16 outputs a reproduction error signal err1_R obtained by D / A converting the digital error signal err1_D to the filter 17. That is, the reproduction error signal err1_R output from the DAC 16 is an analog signal reproduced from the digital error signal err1_D stored in the storage device 15. The filter 17 outputs the reproduction error signal err1_F obtained by removing the high frequency component from the reproduction error signal err1_R to the inverting input terminal of the first subtractor 11 via the second switch SW12 (step S111 in FIG. 2). .
　第１の減算器１１の非反転入力端子には、センサ回路１０２ａからの誤差信号ｅｒｒ１が供給される。よって、第１の減算器１１は、誤差信号ｅｒｒ１から再生誤差信号ｅｒｒ１＿ＲＤを減算する（図２のステップＳ１１２）。 The error signal err1 from the sensor circuit 102a is supplied to the non-inverting input terminal of the first subtractor 11. Therefore, the first subtractor 11 subtracts the reproduction error signal err1_RD from the error signal err1 (step S112 in FIG. 2).
　上述のように、再生誤差信号ｅｒｒ１＿Ｆは記憶装置１５に記憶したデジタル誤差信号ｅｒｒ１＿Ｄを再生したものである。そのため、Ｄ／Ａ変換、Ａ／Ｄ変換及びフィルタリングにより、ある程度の波形の変化が生じるとしても、再生誤差信号ｅｒｒ１＿Ｆ及び誤差信号ｅｒｒ１の波形は近似ないしは一致する。従って、誤差信号ｅｒｒ１及び再生誤差信号ｅｒｒ１＿Ｆのタイミングが一致していれば、第１の減算器１１の出力は最小となり、理想的には０とすることができる。よって、第１の減算器１１の出力を最小化するためには、誤差信号ｅｒｒ１及び再生誤差信号ｅｒｒ１＿Ｆのタイミングを一致させる必要がある。そのため、第１の減算器１１の出力信号Ｖｏｕｔは、第３のスイッチＳＷ１３を介して、ＡＤＣ１３に供給される。ＡＤＣ１３は、出力信号ＶｏｕｔをＡ／Ｄ変換したデジタル信号Ｖｏｕｔ＿Ｄを多入力ＯＲ回路１４に出力する。 As described above, the reproduction error signal err1_F is a reproduction of the digital error signal err1_D stored in the storage device 15. Therefore, even if a certain amount of waveform change occurs due to D / A conversion, A / D conversion, and filtering, the waveforms of the reproduction error signal err1_F and the error signal err1 are approximate or match. Therefore, if the timings of the error signal err1 and the reproduction error signal err1_F coincide with each other, the output of the first subtractor 11 is minimized and can be ideally zero. Therefore, in order to minimize the output of the first subtractor 11, it is necessary to match the timings of the error signal err1 and the reproduction error signal err1_F. Therefore, the output signal Vout of the first subtractor 11 is supplied to the ADC 13 via the third switch SW13. The ADC 13 outputs a digital signal Vout_D obtained by A / D converting the output signal Vout to the multi-input OR circuit 14.
　誤差信号ｅｒｒ１及び再生誤差信号ｅｒｒ１＿Ｆのタイミングが一致している場合には出力信号Ｖｏｕｔは０レベルである。従って、デジタル信号Ｖｏｕｔ＿Ｄのいずれかのビットが「１」である場合には、誤差信号ｅｒｒ１及び再生誤差信号ｅｒｒ１＿Ｆのタイミングがずれていることを意味する。多入力ＯＲ回路１４の出力ＯＲ＿ｏｕｔは、デジタル信号Ｖｏｕｔ＿Ｄのいずれかのビットが「１」である場合には「１」となり、デジタル信号Ｖｏｕｔ＿Ｄの全てのビットが「０」である場合には「０」となる。すなわち、多入力ＯＲ回路１４は、誤差信号ｅｒｒ１及び再生誤差信号ｅｒｒ１＿Ｆのタイミングのずれの有無を検出することができる（図２のステップＳ１１３）。 When the timings of the error signal err1 and the reproduction error signal err1_F coincide with each other, the output signal Vout is 0 level. Therefore, when any bit of the digital signal Vout_D is “1”, it means that the timing of the error signal err1 and the reproduction error signal err1_F is shifted. The output OR_out of the multi-input OR circuit 14 is “1” when any bit of the digital signal Vout_D is “1”, and “0” when all the bits of the digital signal Vout_D are “0”. " That is, the multi-input OR circuit 14 can detect whether or not there is a timing shift between the error signal err1 and the reproduction error signal err1_F (step S113 in FIG. 2).
　多入力ＯＲ回路１４の出力が「１」であるならば、制御回路１８は、制御信号ＳＩＧｍにより、記憶装置１５の出力タイミングを１ステップ遅らせる（図２のステップＳ１１４、図４のタイミングＴ１３）。出力タイミングの遅れ量（ステップ）は、制御回路１８が指定してもよいし、記憶装置１５に入力されるクロック信号の１周期又は半周期分であってもよい。ステップＳ１１４は、多入力ＯＲ回路１４の出力ＯＲ＿ｏｕｔが「０」となるまで繰り返される。 If the output of the multi-input OR circuit 14 is “1”, the control circuit 18 delays the output timing of the storage device 15 by one step by the control signal SIGm (step S114 in FIG. 2, timing T13 in FIG. 4). The delay amount (step) of the output timing may be specified by the control circuit 18 or may be one cycle or half cycle of the clock signal input to the storage device 15. Step S114 is repeated until the output OR_out of the multi-input OR circuit 14 becomes “0”.
　多入力ＯＲ回路１４の出力ＯＲ＿ｏｕｔが「０」であるならば、誤差信号ｅｒｒ１及び再生誤差信号ｅｒｒ１＿Ｆのタイミングが一致している。この場合、制御回路１８は、図３Ｃに示すように、制御信号ＳＩＧ１２により、第２のスイッチＳＷ１２をオンにする。また、制御回路１８は、制御信号ＳＩＧ１１及びＳＩＧ１３により、第１のスイッチＳＷ１１及び第３のスイッチＳＷ１３をオフにする（図２のステップＳ１１５）。そして、制御回路１８は、タイミング調整が完了したことを知らせる完了信号ｅｎｄを出力して、誤差信号除去処理を終了する（図２のステップＳ１１６、図４のタイミングＴ１４）。 If the output OR_out of the multi-input OR circuit 14 is “0”, the timings of the error signal err1 and the reproduction error signal err1_F match. In this case, the control circuit 18 turns on the second switch SW12 by the control signal SIG12 as shown in FIG. 3C. Further, the control circuit 18 turns off the first switch SW11 and the third switch SW13 by the control signals SIG11 and SIG13 (step S115 in FIG. 2). Then, the control circuit 18 outputs a completion signal end indicating that the timing adjustment has been completed, and ends the error signal removal process (step S116 in FIG. 2, timing T14 in FIG. 4).
　その後、信号処理回路１００は、通常動作を行う。以上のように、信号処理回路１００は、誤差信号ｅｒｒ１から再生誤差信号ｅｒｒ１＿Ｆを適切なタイミングで減算することにより、出力信号Ｖｏｕｔの誤差信号を除去している。よって、出力信号Ｖｏｕｔには、被検出信号のみが反映される。従って、本構成によれば、希望波信号と同じ又は近接する周波数の誤差信号を除去することができる。 Thereafter, the signal processing circuit 100 performs a normal operation. As described above, the signal processing circuit 100 removes the error signal of the output signal Vout by subtracting the reproduction error signal err1_F from the error signal err1 at an appropriate timing. Therefore, only the detected signal is reflected in the output signal Vout. Therefore, according to this configuration, it is possible to remove an error signal having a frequency that is the same as or close to that of the desired wave signal.
　実施の形態２
　次に、本発明の実施の形態２にかかる信号処理回路２００について説明する。信号処理回路２００は、実施の形態１にかかる信号処理回路１００の変形例である。図５は、実施の形態２にかかる信号処理回路２００の構成を模式的に示すブロック図である。信号処理回路２００は、信号処理回路１００の第２の減算器１２及び第１のスイッチＳＷ１１が削除され、第１のスイッチＳＷ２１が追加された構成を有する。第１のスイッチＳＷ２１は、第１の減算器１１の反転入力端子とグランドとの間に接続される。第１のスイッチＳＷ２１は、制御回路１８からの制御信号ＳＩＧ２１によりオン／オフする。信号処理回路２００のその他の構成は信号処理回路１００と同様であるので、説明を省略する。 Embodiment 2
Next, the signal processing circuit 200 according to the second exemplary embodiment of the present invention will be described. The signal processing circuit 200 is a modification of the signal processing circuit 100 according to the first embodiment. FIG. 5 is a block diagram schematically illustrating a configuration of the signal processing circuit 200 according to the second embodiment. The signal processing circuit 200 has a configuration in which the second subtracter 12 and the first switch SW11 of the signal processing circuit 100 are deleted, and the first switch SW21 is added. The first switch SW21 is connected between the inverting input terminal of the first subtractor 11 and the ground. The first switch SW21 is turned on / off by a control signal SIG21 from the control circuit 18. Since the other configuration of the signal processing circuit 200 is the same as that of the signal processing circuit 100, description thereof is omitted.
　続いて、信号処理回路２００の誤差信号除去動作について説明する。図６は、信号処理回路２００の誤差信号除去動作を示すフローチャートである。図７Ａ～図７Ｃは、信号処理回路２００の第１～第３のスイッチＳＷ２１、ＳＷ１２及びＳＷ１３のオン／オフを示すブロック図である。図８は、信号処理回路２００の動作を示すタイミングチャートである。図８におけるタイミングＴ２１～Ｔ２４は、それぞれ図４のタイミングＴ１１～Ｔ１４に対応する。 Subsequently, the error signal removal operation of the signal processing circuit 200 will be described. FIG. 6 is a flowchart showing the error signal removal operation of the signal processing circuit 200. 7A to 7C are block diagrams showing on / off of the first to third switches SW21, SW12, and SW13 of the signal processing circuit 200. FIG. FIG. 8 is a timing chart showing the operation of the signal processing circuit 200. Timings T21 to T24 in FIG. 8 correspond to timings T11 to T14 in FIG. 4, respectively.
　ステップＳ２０１～Ｓ２０３は、図２のステップＳ１０１～Ｓ１０３と同様であるので、説明を省略する。記憶装置１５を書き込みモードへ切り替えた後、図７Ａに示すように、制御回路１８は、制御信号ＳＩＧ２１及びＳＩＧ１３により、第１のスイッチＳＷ２１及び第３のスイッチＳＷ１３をオンにする。また、制御回路１８は、制御信号ＳＩＧ１２により、第２のスイッチＳＷ１２をオフにする（図６のステップＳ２０４）。その後のステップＳ２０５～Ｓ２０９は、図２のステップＳ１０５～Ｓ１０９と同様であるので、説明を省略する。 Steps S201 to S203 are the same as steps S101 to S103 in FIG. After switching the storage device 15 to the write mode, as shown in FIG. 7A, the control circuit 18 turns on the first switch SW21 and the third switch SW13 by the control signals SIG21 and SIG13. Further, the control circuit 18 turns off the second switch SW12 by the control signal SIG12 (step S204 in FIG. 6). Subsequent steps S205 to S209 are the same as steps S105 to S109 in FIG.
　記憶装置１５を書き込みモードへ切り替えた後、図７Ｂに示すように、制御回路１８は、制御信号ＳＩＧ２１により、第１のスイッチＳＷ２１をオフにする。また、制御回路１８は、制御信号ＳＩＧ１２及びＳＩＧ１３により、第２のスイッチＳＷ１２及び第３のスイッチＳＷ１３をオンにする（図６のステップＳ２１０）。その後のステップＳ２１１～Ｓ２１４は、図２のステップＳ１１１～Ｓ１１４と同様であるので、説明を省略する。 After switching the storage device 15 to the write mode, as shown in FIG. 7B, the control circuit 18 turns off the first switch SW21 by the control signal SIG21. Further, the control circuit 18 turns on the second switch SW12 and the third switch SW13 by the control signals SIG12 and SIG13 (step S210 in FIG. 6). Subsequent steps S211 to S214 are the same as steps S111 to S114 in FIG.
　多入力ＯＲ回路１４の出力ＯＲ＿ｏｕｔが「０」である場合には、図７Ｃに示すように、制御回路１８は、制御信号ＳＩＧ２１及びＳＩＧ１３により、第１のスイッチＳＷ２１及び第３のスイッチＳＷ１３をオフにする。また、制御回路１８は、制御信号ＳＩＧ１２により、第２のスイッチＳＷ１２をオンにする（図６のステップＳ２１５）。その後のステップＳ２１６は、図２のステップＳ１１６と同様であるので、説明を省略する。 When the output OR_out of the multi-input OR circuit 14 is “0”, as shown in FIG. 7C, the control circuit 18 turns off the first switch SW21 and the third switch SW13 by the control signals SIG21 and SIG13. To. Further, the control circuit 18 turns on the second switch SW12 by the control signal SIG12 (step S215 in FIG. 6). Subsequent step S216 is the same as step S116 of FIG.
　その後、信号処理回路２００は、信号処理回路１００と同様に通常動作を行う。以上のように、信号処理回路２００は、誤差信号ｅｒｒ１から再生誤差信号ｅｒｒ１＿Ｆを適切なタイミングで減算することにより、出力信号Ｖｏｕｔの誤差信号を除去している。よって、出力信号Ｖｏｕｔには、被検出信号のみが反映される。従って、本構成によれば、実施の形態１と同様に、希望波信号と同じ又は近接する周波数の誤差信号を除去することができる。 Thereafter, the signal processing circuit 200 performs a normal operation in the same manner as the signal processing circuit 100. As described above, the signal processing circuit 200 removes the error signal of the output signal Vout by subtracting the reproduction error signal err1_F from the error signal err1 at an appropriate timing. Therefore, only the detected signal is reflected in the output signal Vout. Therefore, according to this configuration, similarly to the first embodiment, it is possible to remove an error signal having a frequency that is the same as or close to that of the desired wave signal.
　さらに、信号処理回路２００、信号処理回路１００と比べて、減算器が一つ削減されている。従って、本構成によれば、信号処理回路１００よりも回路面積を縮小することができるので、小型かつ低コストの信号処理回路を提供することができる。 Furthermore, compared with the signal processing circuit 200 and the signal processing circuit 100, one subtracter is reduced. Therefore, according to this configuration, since the circuit area can be reduced as compared with the signal processing circuit 100, a small and low-cost signal processing circuit can be provided.
　実施の形態３
　次に、本発明の実施の形態３にかかる信号処理回路３００について説明する。図９は、実施の形態３にかかる信号処理回路３００の構成を模式的に示すブロック図である。信号処理回路３００は、信号処理回路２００のフィルタ１７を除去し、別のフィルタ２７を追加した構成を有する。フィルタ２７は、第１の減算器１１の出力と、出力端子Ｔｏｕｔとの間に挿入される。信号処理回路３００のその他の構成は信号処理回路２００と同様であるので、説明を省略する。 Embodiment 3
Next, a signal processing circuit 300 according to the third embodiment of the present invention will be described. FIG. 9 is a block diagram schematically illustrating the configuration of the signal processing circuit 300 according to the third embodiment. The signal processing circuit 300 has a configuration in which the filter 17 of the signal processing circuit 200 is removed and another filter 27 is added. The filter 27 is inserted between the output of the first subtractor 11 and the output terminal Tout. Since the other configuration of the signal processing circuit 300 is the same as that of the signal processing circuit 200, description thereof is omitted.
　続いて、信号処理回路３００の誤差信号除去動作について説明する。信号処理回路３００は、実施の形態２にかかる信号処理回路２００の変形例である。図１０は、信号処理回路３００の誤差信号除去動作を示すフローチャートである。図１１Ａ～図１１Ｃは、信号処理回路３００の第１～第３のスイッチＳＷ２１、ＳＷ１２及びＳＷ１３のオン／オフを示すブロック図である。図１２は、信号処理回路３００の動作を示すタイミングチャートである。図１２におけるタイミングＴ３１～Ｔ３４は、それぞれ図４のタイミングＴ１１～Ｔ１４に対応する。 Subsequently, the error signal removal operation of the signal processing circuit 300 will be described. The signal processing circuit 300 is a modification of the signal processing circuit 200 according to the second embodiment. FIG. 10 is a flowchart showing the error signal removal operation of the signal processing circuit 300. 11A to 11C are block diagrams showing on / off of the first to third switches SW21, SW12, and SW13 of the signal processing circuit 300. FIG. FIG. 12 is a timing chart showing the operation of the signal processing circuit 300. Timings T31 to T34 in FIG. 12 correspond to timings T11 to T14 in FIG. 4, respectively.
　ステップＳ３０１～Ｓ３０３は、図２のステップＳ１０１～Ｓ１０３と同様であるので、説明を省略する。記憶装置１５を書き込みモードへ切り替えた後、図１１Ａに示すように、制御回路１８は、制御信号ＳＩＧ２１及びＳＩＧ１３により、第１のスイッチＳＷ２１及び第３のスイッチＳＷ１３をオンにする。また、制御回路１８は、制御信号ＳＩＧ１２により、第２のスイッチＳＷ１２をオフにする（図１０のステップＳ３０４）。 Steps S301 to S303 are the same as steps S101 to S103 in FIG. After switching the storage device 15 to the write mode, as shown in FIG. 11A, the control circuit 18 turns on the first switch SW21 and the third switch SW13 by the control signals SIG21 and SIG13. Further, the control circuit 18 turns off the second switch SW12 by the control signal SIG12 (step S304 in FIG. 10).
　第１の減算器１１は、フィルタ２７に誤差信号ｅｒｒ１を出力する。フィルタ２７は、希望波信号Ｓｄと同一又は近接する周波数の信号を通過させるフィルタである。従って、誤差信号ｅｒｒ１は、フィルタ２７を通過し、第３のスイッチＳＷ１３を介して、ＡＤＣ１３に入力される。ＡＤＣ１３は、誤差信号ｅｒｒ１をＡ／Ｄ変換したデジタル誤差信号ｅｒｒ１＿Ｄを、記憶装置１５に出力する（図１０のステップＳ３０５）。その後のステップＳ３０６～Ｓ３０９は、図２のステップＳ１０６～Ｓ１０９と同様であるので、説明を省略する。 The first subtractor 11 outputs an error signal err1 to the filter 27. The filter 27 is a filter that passes a signal having a frequency that is the same as or close to that of the desired wave signal Sd. Therefore, the error signal err1 passes through the filter 27 and is input to the ADC 13 via the third switch SW13. The ADC 13 outputs a digital error signal err1_D obtained by A / D converting the error signal err1 to the storage device 15 (step S305 in FIG. 10). Subsequent steps S306 to S309 are the same as steps S106 to S109 in FIG.
　記憶装置１５を読み出しモードへ切り換えた後、図１１Ｂに示すように、制御回路１８は、制御信号ＳＩＧ２１により、第１のスイッチＳＷ２１をオフにする。また、制御回路１８は、制御信号ＳＩＧ１２及びＳＩＧ１３により、第２のスイッチＳＷ１２及び第３のスイッチＳＷ１３をオンにする（図１０のステップＳ３１０）。 After switching the storage device 15 to the read mode, the control circuit 18 turns off the first switch SW21 by the control signal SIG21 as shown in FIG. 11B. Further, the control circuit 18 turns on the second switch SW12 and the third switch SW13 by the control signals SIG12 and SIG13 (step S310 in FIG. 10).
　次いで、制御回路１８は、制御信号ＳＩＧｍにより、記憶装置１５に記憶されたデジタル誤差信号ｅｒｒ１＿Ｄを出力させる。ＤＡＣ１６は、デジタル誤差信号ｅｒｒ１＿ＤをＤ／Ａ変換した再生誤差信号ｅｒｒ１＿Ｒを、第２のスイッチＳＷ１２を介して、第１の減算器１１の反転入力端子へ出力する（図１０のステップＳ３１１）。 Next, the control circuit 18 outputs the digital error signal err1_D stored in the storage device 15 by the control signal SIGm. The DAC 16 outputs the reproduction error signal err1_R obtained by D / A converting the digital error signal err1_D to the inverting input terminal of the first subtractor 11 via the second switch SW12 (step S311 in FIG. 10).
　第１の減算器１１の非反転入力端子には、センサ回路１０２ａからの誤差信号ｅｒｒ１が供給される。よって、第１の減算器１１は、誤差信号ｅｒｒ１から再生誤差信号ｅｒｒ１＿Ｒを減算する（図１０のステップＳ３１２）。フィルタ２７は、第１の減算器１１の出力から高周波成分を取り除いた信号を、出力信号Ｖｏｕｔとして出力する。 The error signal err1 from the sensor circuit 102a is supplied to the non-inverting input terminal of the first subtractor 11. Therefore, the first subtracter 11 subtracts the reproduction error signal err1_R from the error signal err1 (step S312 in FIG. 10). The filter 27 outputs a signal obtained by removing the high frequency component from the output of the first subtracter 11 as the output signal Vout.
　上述のように、再生誤差信号ｅｒｒ１＿Ｒは記憶装置１５に記憶したデジタル誤差信号ｅｒｒ１＿Ｄを再生したものである。そのため、Ｄ／Ａ変換、Ａ／Ｄ変換により、ある程度の波形の変化が生じるとしても、再生誤差信号ｅｒｒ１＿Ｒ及び誤差信号ｅｒｒ１の波形は近似する。しかし、信号処理回路３００では、再生誤差信号ｅｒｒ１＿Ｒをフィルタリングしないので、再生誤差信号ｅｒｒ１＿Ｒには高周波成分が残存している。しかし、フィルタ２７が第１の減算器１１の出力と出力端子Ｔｏｕｔとの間に接続されているので、第１の減算器１１の出力からは、Ｄ／Ａ変換に起因する高周波成分は除去される。従って、この場合、信号処理回路３００の出力信号Ｖｏｕｔは、信号処理回路２００と同等となる。 As described above, the reproduction error signal err1_R is a reproduction of the digital error signal err1_D stored in the storage device 15. Therefore, even if the waveform changes to some extent by D / A conversion and A / D conversion, the waveforms of the reproduction error signal err1_R and the error signal err1 are approximated. However, since the signal processing circuit 300 does not filter the reproduction error signal err1_R, a high frequency component remains in the reproduction error signal err1_R. However, since the filter 27 is connected between the output of the first subtractor 11 and the output terminal Tout, the high frequency component resulting from the D / A conversion is removed from the output of the first subtractor 11. The Therefore, in this case, the output signal Vout of the signal processing circuit 300 is equivalent to that of the signal processing circuit 200.
　従って、誤差信号ｅｒｒ１及び再生誤差信号ｅｒｒ１＿Ｒのタイミングが一致していれば、第１の減算器１１の出力は最小となり、理想的には０とすることができる。よって、第１の減算器１１の出力を最小化するためには、誤差信号ｅｒｒ１及び再生誤差信号ｅｒｒ１＿Ｒのタイミングを一致させる必要がある。 Therefore, if the timings of the error signal err1 and the reproduction error signal err1_R coincide with each other, the output of the first subtractor 11 is minimized and can be ideally zero. Therefore, in order to minimize the output of the first subtractor 11, it is necessary to match the timings of the error signal err1 and the reproduction error signal err1_R.
　そのため、第１の減算器１１の出力信号Ｖｏｕｔは、第３のスイッチＳＷ１３を介して、ＡＤＣ１３に供給される。その後のステップＳ３１３及びＳ３１４は、図２のステップＳ１１３及びＳ１１４と同様であるので、説明を省略する。 Therefore, the output signal Vout of the first subtractor 11 is supplied to the ADC 13 via the third switch SW13. Subsequent steps S313 and S314 are the same as steps S113 and S114 in FIG.
　多入力ＯＲ回路１４の出力ＯＲ＿ｏｕｔが「０」であるならば、誤差信号ｅｒｒ１及び再生誤差信号ｅｒｒ１＿Ｒのタイミングが一致している。この場合、制御回路１８は、制御信号ＳＩＧ２により、第２のスイッチＳＷ１２をオンにする。また、制御回路１８は、制御信号ＳＩＧ２１及びＳＩＧ１３により、第１のスイッチＳＷ２１及び第３のスイッチＳＷ１３をオフにする（図１０のステップＳ３１５）。その後のステップＳ３１６は、図２のステップＳ１１６と同様であるので、説明を省略する。 If the output OR_out of the multi-input OR circuit 14 is “0”, the timings of the error signal err1 and the reproduction error signal err1_R match. In this case, the control circuit 18 turns on the second switch SW12 by the control signal SIG2. Further, the control circuit 18 turns off the first switch SW21 and the third switch SW13 by the control signals SIG21 and SIG13 (step S315 in FIG. 10). Subsequent step S316 is the same as step S116 of FIG.
　タイミング調整の終了後、信号処理回路３００は、信号処理回路２００と同様に、通常動作を行う。以上のように、信号処理回路３００は、誤差信号ｅｒｒ１から再生誤差信号ｅｒｒ１＿Ｒを適切なタイミングで減算することにより、出力信号Ｖｏｕｔの誤差信号を除去している。よって、出力信号Ｖｏｕｔには、被検出信号のみが反映される。従って、本構成によれば、信号処理回路１００及び２００と同様に、希望波信号と同じ又は近接する周波数の誤差信号を除去することができる。 After completion of the timing adjustment, the signal processing circuit 300 performs a normal operation in the same manner as the signal processing circuit 200. As described above, the signal processing circuit 300 removes the error signal of the output signal Vout by subtracting the reproduction error signal err1_R from the error signal err1 at an appropriate timing. Therefore, only the detected signal is reflected in the output signal Vout. Therefore, according to this configuration, similarly to the signal processing circuits 100 and 200, an error signal having a frequency that is the same as or close to that of the desired wave signal can be removed.
　実施の形態４
　次に、本発明の実施の形態４にかかる信号処理回路４００について説明する。信号処理回路４００は、実施の形態３にかかる信号処理回路３００の変形例である。図１３は、実施の形態４にかかる信号処理回路４００の構成を模式的に示すブロック図である。信号処理回路４００は、信号処理回路３００にディレイライン４０を追加した構成を有する。ディレイライン４０は、ＤＡＣ１６と第３のスイッチＳＷ１３との間に接続される。信号処理回路４００のその他の構成は信号処理回路３００と同様であるので、説明を省略する。 Embodiment 4
Next, a signal processing circuit 400 according to the fourth embodiment of the present invention will be described. The signal processing circuit 400 is a modification of the signal processing circuit 300 according to the third embodiment. FIG. 13 is a block diagram schematically illustrating a configuration of the signal processing circuit 400 according to the fourth embodiment. The signal processing circuit 400 has a configuration in which a delay line 40 is added to the signal processing circuit 300. The delay line 40 is connected between the DAC 16 and the third switch SW13. Since the other configuration of the signal processing circuit 400 is the same as that of the signal processing circuit 300, description thereof is omitted.
　続いて、信号処理回路４００の誤差信号除去動作について説明する。図１４は、信号処理回路４００の誤差信号除去動作を示すフローチャートである。図１５Ａ～図１５Ｃは、信号処理回路４００の第１～第３のスイッチＳＷ２１、ＳＷ１２及びＳＷ１３のオン／オフを示すブロック図である。図１６は、信号処理回路４００の動作を示すタイミングチャートである。図１６におけるタイミングＴ４１～Ｔ４４は、それぞれ図４のタイミングＴ１１～Ｔ１４に対応する。 Subsequently, the error signal removal operation of the signal processing circuit 400 will be described. FIG. 14 is a flowchart showing the error signal removal operation of the signal processing circuit 400. 15A to 15C are block diagrams showing on / off of the first to third switches SW21, SW12, and SW13 of the signal processing circuit 400. FIG. FIG. 16 is a timing chart showing the operation of the signal processing circuit 400. Timings T41 to T44 in FIG. 16 correspond to timings T11 to T14 in FIG. 4, respectively.
　ステップＳ４０１～Ｓ４１０は、図２のステップＳ１０１～Ｓ１１０と同様であるので、説明を省略する。ステップＳ４１０の後、制御回路１８は、制御信号ＳＩＧｍにより、記憶装置１５に記憶されたデジタル誤差信号ｅｒｒ１＿Ｄを出力させる。ＤＡＣ１６は、デジタル誤差信号ｅｒｒ１＿ＤをＤ／Ａ変換した再生誤差信号ｅｒｒ１＿Ｒを、ディレイライン４０へ出力する。ディレイライン４０は、制御回路１８からの制御信号ＳＩＧ４０により、再生誤差信号ｅｒｒ１＿Ｒの出力タイミングを調整した再生誤差信号ｅｒｒ１＿ＲＤを、第２のスイッチＳＷ１２を介して、第１の減算器１１の反転入力端子に出力する。再生誤差信号ｅｒｒ１＿ＲＤは、記憶装置１５に記憶されたデジタル誤差信号ｅｒｒ１＿Ｄから再生されたアナログ信号である（図１４のステップＳ４１１）。 Steps S401 to S410 are the same as steps S101 to S110 in FIG. After step S410, the control circuit 18 outputs the digital error signal err1_D stored in the storage device 15 by the control signal SIGm. The DAC 16 outputs a reproduction error signal err1_R obtained by D / A converting the digital error signal err1_D to the delay line 40. The delay line 40 receives the reproduction error signal err1_RD, the output timing of the reproduction error signal err1_R having been adjusted by the control signal SIG40 from the control circuit 18, via the second switch SW12, and the inverting input terminal of the first subtractor 11. Output to. The reproduction error signal err1_RD is an analog signal reproduced from the digital error signal err1_D stored in the storage device 15 (step S411 in FIG. 14).
　第１の減算器１１の非反転入力端子には、センサ回路１０２ａからの誤差信号ｅｒｒ１が供給される。よって、第１の減算器１１は、誤差信号ｅｒｒ１から再生誤差信号ｅｒｒ１＿ＲＤを減算する（図１４のステップＳ４１２）。 The error signal err1 from the sensor circuit 102a is supplied to the non-inverting input terminal of the first subtractor 11. Therefore, the first subtracter 11 subtracts the reproduction error signal err1_RD from the error signal err1 (step S412 in FIG. 14).
　上述のように、再生誤差信号ｅｒｒ１＿ＲＤは記憶装置１５に記憶したデジタル誤差信号ｅｒｒ１＿Ｄを再生したものである。そのため、Ｄ／Ａ変換、Ａ／Ｄ変換により、ある程度の波形の変化が生じるとしても、再生誤差信号ｅｒｒ１＿ＲＤ及び誤差信号ｅｒｒ１の波形は近似する。信号処理回路４００では、再生誤差信号ｅｒｒ１＿ＲＤをフィルタリングしないので、再生誤差信号ｅｒｒ１＿ＲＤには高周波成分が残存している。しかし、フィルタ２７が第１の減算器１１の出力と出力端子Ｔｏｕｔとの間に接続されているので、出力信号Ｖｏｕｔからは、Ｄ／Ａ変換に起因する高周波成分は除去される。従って、この場合、信号処理回路４００の出力信号Ｖｏｕｔは、信号処理回路３００と同等となる。 As described above, the reproduction error signal err1_RD is a reproduction of the digital error signal err1_D stored in the storage device 15. Therefore, even if the waveform changes to some extent by D / A conversion and A / D conversion, the waveforms of the reproduction error signal err1_RD and the error signal err1 are approximated. Since the signal processing circuit 400 does not filter the reproduction error signal err1_RD, a high frequency component remains in the reproduction error signal err1_RD. However, since the filter 27 is connected between the output of the first subtractor 11 and the output terminal Tout, the high-frequency component due to D / A conversion is removed from the output signal Vout. Therefore, in this case, the output signal Vout of the signal processing circuit 400 is equivalent to that of the signal processing circuit 300.
　従って、誤差信号ｅｒｒ１及び再生誤差信号ｅｒｒ１＿ＲＤのタイミングが一致していれば、第１の減算器１１の出力は最小となり、理想的には０とすることができる。よって、第１の減算器１１の出力を最小化するためには、誤差信号ｅｒｒ１及び再生誤差信号ｅｒｒ１＿ＲＤのタイミングを一致させる必要がある。 Therefore, if the timings of the error signal err1 and the reproduction error signal err1_RD coincide with each other, the output of the first subtracter 11 is minimized and can be ideally zero. Therefore, in order to minimize the output of the first subtractor 11, it is necessary to match the timings of the error signal err1 and the reproduction error signal err1_RD.
　そのため、フィルタ２７からの出力信号Ｖｏｕｔは、第３のスイッチＳＷ１３を介して、ＡＤＣ１３に供給される。その後のステップＳ４１３は、図２のステップＳ１１３と同様であるので、説明を省略する。 Therefore, the output signal Vout from the filter 27 is supplied to the ADC 13 via the third switch SW13. Subsequent step S413 is the same as step S113 in FIG.
　多入力ＯＲ回路１４の出力が「１」であるならば、制御回路１８は、制御信号ＳＩＧ４０により、ディレイライン４０の出力タイミングを１ステップ遅らせる（図１４のステップＳ４１４、図１６のタイミングＴ４３）。出力タイミングの遅れ量（ステップ）は、制御回路１８が指定してもよい。ステップＳ４１４は、多入力ＯＲ回路１４の出力ＯＲ＿ｏｕｔが「０」となるまで繰り返される。 If the output of the multi-input OR circuit 14 is “1”, the control circuit 18 delays the output timing of the delay line 40 by one step by the control signal SIG40 (step S414 in FIG. 14, timing T43 in FIG. 16). The control circuit 18 may specify the output timing delay amount (step). Step S414 is repeated until the output OR_out of the multi-input OR circuit 14 becomes “0”.
　多入力ＯＲ回路１４の出力ＯＲ＿ｏｕｔが「０」であるならば、誤差信号ｅｒｒ１及び再生誤差信号ｅｒｒ１＿ＲＤのタイミングが一致している。この場合、制御回路１８は、制御信号ＳＩＧ２により、第２のスイッチＳＷ１２をオンにする。また、制御回路１８は、制御信号ＳＩＧ２１及びＳＩＧ１３により、第１のスイッチＳＷ２１及び第３のスイッチＳＷ１３をオフにする（図１４のステップＳ４１５）。その後のステップＳ４１６は、図２のステップＳ１１６と同様であるので、説明を省略する。 If the output OR_out of the multi-input OR circuit 14 is “0”, the timings of the error signal err1 and the reproduction error signal err1_RD match. In this case, the control circuit 18 turns on the second switch SW12 by the control signal SIG2. Further, the control circuit 18 turns off the first switch SW21 and the third switch SW13 by the control signals SIG21 and SIG13 (step S415 in FIG. 14). Subsequent step S416 is the same as step S116 of FIG.
　タイミング調整の終了後、信号処理回路４００は、信号処理回路３００と同様に、通常動作を行う。以上のように、信号処理回路４００は、誤差信号ｅｒｒ１から再生誤差信号ｅｒｒ１＿ＲＤを適切なタイミングで減算することにより、出力信号Ｖｏｕｔの誤差信号を除去している。よって、出力信号Ｖｏｕｔには、被検出信号のみが反映される。従って、本構成によれば、信号処理回路１００、２００及び３００と同様に、希望波信号と同じ又は近接する周波数の誤差信号を除去することができる。 After the timing adjustment, the signal processing circuit 400 performs a normal operation in the same manner as the signal processing circuit 300. As described above, the signal processing circuit 400 removes the error signal of the output signal Vout by subtracting the reproduction error signal err1_RD from the error signal err1 at an appropriate timing. Therefore, only the detected signal is reflected in the output signal Vout. Therefore, according to this configuration, similarly to the signal processing circuits 100, 200, and 300, an error signal having a frequency that is the same as or close to that of the desired wave signal can be removed.
　さらに、ディレイライン４０は、アナログ信号である再生誤差信号ｅｒｒ１の出力タイミングを調整するものである。従って、ディレイラインを使用することによって微細な出力タイミングの調整を行うことが可能である。 Furthermore, the delay line 40 adjusts the output timing of the reproduction error signal err1 which is an analog signal. Therefore, it is possible to finely adjust the output timing by using the delay line.
　実施の形態５
　次に、本発明の実施の形態５にかかる信号処理回路５００について説明する。本実施の形態では、センサ回路としてタッチパネルが用いられる例について述べる。近年、タッチパネルの普及が進展し、将来的にはタッチパネルの大型化が考えられる。しかし、例えば静電容量方式のタッチパネルでは、タッチパネル全体に一様な電界を発生させるため、タッチパネルのサイズが大型化すればするほど消費電力が増加してしまう。具体的には、１０インチのタッチパネルと５０インチのタッチパネルとを比較すると、面積は２５倍となるため消費電力が２５倍となる。そのため、５０インチのタッチパネルに対応するＩＣの性能も、同様に２５倍必要となる。また、実際には、タッチした位置から検出部までの距離も増加するため、単純な面積倍にとどまらず、更なる消費電力の増加も考えられる。 Embodiment 5
Next, a signal processing circuit 500 according to a fifth embodiment of the present invention will be described. In this embodiment, an example in which a touch panel is used as a sensor circuit will be described. In recent years, the spread of touch panels has progressed, and in the future, the size of touch panels may be increased. However, in a capacitive touch panel, for example, a uniform electric field is generated on the entire touch panel, so that power consumption increases as the size of the touch panel increases. Specifically, when a 10-inch touch panel and a 50-inch touch panel are compared, the area is 25 times and the power consumption is 25 times. Therefore, the performance of the IC corresponding to the 50-inch touch panel is also required 25 times. In practice, since the distance from the touched position to the detection unit also increases, the power consumption is not limited to a simple area doubled, and the power consumption can be further increased.
　タッチパネルの大型化による消費電力の増加を解決する方法として、タッチパネル全体に発生している電界の振幅を下げることが考えられる。しかし、振幅を下げると、希望波信号がノイズに埋もれてしまう。特に大きなタッチパネルの場合、影響はさらに大きなものになる。このようにノイズ耐性に対する要求がシビアになるほど、希望波信号と同じ周波数の誤差信号が問題となってくると思われる。 As a method for solving the increase in power consumption due to the enlargement of the touch panel, it is conceivable to reduce the amplitude of the electric field generated in the entire touch panel. However, when the amplitude is lowered, the desired wave signal is buried in noise. Especially in the case of a large touch panel, the influence is even greater. As the demand for noise immunity becomes more severe, an error signal having the same frequency as the desired wave signal seems to be a problem.
　また、この問題はタッチパネルの大型化だけではなく、液晶パネルの高解像度化においても同様に発生する。例えば、現在のフルハイビジョンに対し、その４倍の解像度でのテレビ放送への移行が予定されている。さらに将来的には１６倍の解像度になるなど、液晶パネルはより一層高解像度化される方向にある。そのため、タッチパネルの高精度化が必要となった際にも、希望波信号と同じ周波数の誤差信号が問題となってくると思われる。 This problem occurs not only when the touch panel is enlarged, but also when the resolution of the liquid crystal panel is increased. For example, the current full high-definition is scheduled to shift to television broadcasting at a resolution four times that of the current full high-definition. Furthermore, in the future, the resolution of liquid crystal panels is in the direction of higher resolution, such as 16 times the resolution. For this reason, even when the touch panel needs to be highly accurate, an error signal having the same frequency as the desired wave signal seems to be a problem.
　図１７は、実施の形態５にかかる信号処理回路５００の構成を模式的に示すブロック図である。信号処理回路５００は、信号処理回路３００の変形例である。信号処理回路５００は、信号処理回路３００に第３の減算器５０及び第４のスイッチＳＷ５４を追加した構成を有する。また、信号処理回路５００は、信号処理回路３００の第１のスイッチＳＷ２１を第１のスイッチＳＷ５１に置換した構成を有する。図１７では、センサ回路として、静電容量方式のタッチパネル１０２ｂを表示している。また、信号処理回路５００及び５０１～５０３は、タッチパネルのタッチ位置を４隅から検出する信号処理回路に相当する。信号処理回路５０１～５０３は、それぞれ信号処理回路５００と同等の回路である。 FIG. 17 is a block diagram schematically showing the configuration of the signal processing circuit 500 according to the fifth embodiment. The signal processing circuit 500 is a modification of the signal processing circuit 300. The signal processing circuit 500 has a configuration in which a third subtracter 50 and a fourth switch SW54 are added to the signal processing circuit 300. The signal processing circuit 500 has a configuration in which the first switch SW21 of the signal processing circuit 300 is replaced with a first switch SW51. In FIG. 17, a capacitive touch panel 102b is displayed as a sensor circuit. The signal processing circuits 500 and 501 to 503 correspond to signal processing circuits that detect touch positions of the touch panel from four corners. Each of the signal processing circuits 501 to 503 is a circuit equivalent to the signal processing circuit 500.
　第３の減算器５０の反転入力端子はＤＡＣ１６の出力と接続され、非反転入力端子は出力端子Ｔｏｕｔ接続される。第４のスイッチＳＷ５４は、第３の減算器５０の出力とＡＤＣ１３の入力との間に接続される。第１のスイッチＳＷ５１は、第１の減算器１１の反転入力端子と信号源１０１との間に接続される。第１のスイッチＳＷ５１及び第４のスイッチＳＷ５４は、それぞれ制御回路１８からの制御信号ＳＩＧ５１及びＳＩＧ５４により、オン／オフする。信号処理回路５００のその他の構成は信号処理回路３００と同様であるので、説明を省略する。 The inverting input terminal of the third subtracter 50 is connected to the output of the DAC 16, and the non-inverting input terminal is connected to the output terminal Tout. The fourth switch SW54 is connected between the output of the third subtracter 50 and the input of the ADC 13. The first switch SW51 is connected between the inverting input terminal of the first subtractor 11 and the signal source 101. The first switch SW51 and the fourth switch SW54 are turned on / off by control signals SIG51 and SIG54 from the control circuit 18, respectively. Since the other configuration of the signal processing circuit 500 is the same as that of the signal processing circuit 300, the description thereof is omitted.
　続いて、信号処理回路５００の誤差信号除去動作について説明する。図１８は、信号処理回路５００の誤差信号除去動作を示すフローチャートである。図１９Ａ～図１９Ｃは、信号処理回路５００の第１～第４のスイッチＳＷ５１、ＳＷ１２、ＳＷ１３及びＳＷ５４のオン／オフを示すブロック図である。図２０は、信号処理回路５００の動作を示すタイミングチャートである。なお、図２０におけるタイミングＴ５１～Ｔ５４は、それぞれ図４のタイミングＴ１１～Ｔ１４に対応する。 Subsequently, the error signal removal operation of the signal processing circuit 500 will be described. FIG. 18 is a flowchart showing the error signal removal operation of the signal processing circuit 500. 19A to 19C are block diagrams showing on / off of the first to fourth switches SW51, SW12, SW13, and SW54 of the signal processing circuit 500. FIG. FIG. 20 is a timing chart showing the operation of the signal processing circuit 500. Note that timings T51 to T54 in FIG. 20 correspond to timings T11 to T14 in FIG. 4, respectively.
　本実施の形態におけるセンサ回路であるタッチパネル１０２ｂがＯＮの場合、タッチを検出していないとき、すなわち被検出信号の未検出時には、理想的には入力と同じ信号を出力する。すなわち、未検出時のタッチパネル１０２ｂは、理想的には希望波信号Ｓｄをそのまま出力する。ところが、実際にはタッチパネル１０２ｂに起因する、希望波信号とお同じ周波数の誤差信号も出力される。従って、実施の形態１～４と同様に、この誤差信号を除去する必要が生じる。 When the touch panel 102b which is the sensor circuit in this embodiment is ON, when the touch is not detected, that is, when the detected signal is not detected, ideally the same signal as the input is output. That is, the touch panel 102b when not detected ideally outputs the desired wave signal Sd as it is. However, an error signal having the same frequency as that of the desired wave signal, which is actually caused by the touch panel 102b, is also output. Therefore, it is necessary to remove this error signal as in the first to fourth embodiments.
　ステップＳ５０１～Ｓ５０３は、図１０のステップＳ３０１～Ｓ３０３と同様であるので、説明を省略する。ステップＳ５０３の後、制御回路１８は、図１９Ａに示すように、制御信号ＳＩＧ５１及びＳＩＧ１３により、第１のスイッチＳＷ５１及び第３のスイッチＳＷ１３をオンにする。また、制御回路１８は、制御信号ＳＩＧ１２及びＳＩＧ５４により、第２のスイッチＳＷ１２及び第４のスイッチＳＷ５４をオフにする（図１８のステップＳ５０４）。 Steps S501 to S503 are the same as steps S301 to S303 in FIG. After step S503, the control circuit 18 turns on the first switch SW51 and the third switch SW13 by the control signals SIG51 and SIG13 as shown in FIG. 19A. Further, the control circuit 18 turns off the second switch SW12 and the fourth switch SW54 by the control signals SIG12 and SIG54 (step S504 in FIG. 18).
　この際、図２０に示すように、第１の減算器１１は、誤差信号を含むセンサ回路の出力信号Ｓ＿ｏｕｔから希望波信号Ｓｄを減算する。これにより、第１の減算器１１は、誤差信号ｅｒｒ５を抽出する。抽出された誤差信号ｅｒｒ５は、フィルタ２７及び第３のスイッチＳＷ１３を介して、ＡＤＣ１３供給される。 At this time, as shown in FIG. 20, the first subtracter 11 subtracts the desired wave signal Sd from the output signal S_out of the sensor circuit including the error signal. As a result, the first subtractor 11 extracts the error signal err5. The extracted error signal err5 is supplied to the ADC 13 via the filter 27 and the third switch SW13.
　ＡＤＣ１３は、誤差信号ｅｒｒ５をＡ／Ｄ変換したデジタル誤差信号ｅｒｒ５＿Ｄを、記憶装置１５に出力する（図１８のステップＳ５０５）。記憶装置１５は、デジタル誤差信号ｅｒｒ５＿Ｄの各ビットの値を記憶する（図８のステップＳ５０６）。なお、記憶装置１５の具体的な記憶動作については、実施の形態１と同様であるので、説明を省略する。その後のステップＳ５０７～Ｓ５０９については、図１０のステップＳ３０７～３０９と同様であるので、説明を省略する。 The ADC 13 outputs a digital error signal err5_D obtained by A / D converting the error signal err5 to the storage device 15 (step S505 in FIG. 18). The storage device 15 stores the value of each bit of the digital error signal err5_D (step S506 in FIG. 8). Note that the specific storage operation of the storage device 15 is the same as that of the first embodiment, and thus the description thereof is omitted. Subsequent steps S507 to S509 are the same as steps S307 to 309 in FIG.
　ステップＳ５０９の後、制御回路１８は、図１９Ｂに示すように、制御信号ＳＩＧ５１及びＳＩＧ５４により、第１のスイッチＳＷ５１及び第４のスイッチＳＷ５４をオンにする。また、制御回路１８は、制御信号ＳＩＧ１２及びＳＩＧ１３により、第２のスイッチＳＷ１２及び第３のスイッチＳＷ１３をオフにする（図１８のステップＳ５１０）。 After step S509, the control circuit 18 turns on the first switch SW51 and the fourth switch SW54 by the control signals SIG51 and SIG54 as shown in FIG. 19B. Further, the control circuit 18 turns off the second switch SW12 and the third switch SW13 by the control signals SIG12 and SIG13 (step S510 in FIG. 18).
　次いで、制御回路１８は、制御信号ＳＩＧｍにより、記憶装置１５に記憶されたデジタル誤差信号ｅｒｒ５＿Ｄを出力させる。ＤＡＣ１６は、デジタル誤差信号ｅｒｒ５＿ＤをＤ／Ａ変換した再生誤差信号ｅｒｒ５＿Ｒを、第３の減算器５０の反転入力端子へ出力する（図１８のステップＳ５１１）。 Next, the control circuit 18 outputs the digital error signal err5_D stored in the storage device 15 by the control signal SIGm. The DAC 16 outputs a reproduction error signal err5_R obtained by D / A converting the digital error signal err5_D to the inverting input terminal of the third subtracter 50 (step S511 in FIG. 18).
　第３の減算器５０は、誤差信号ｅｒｒ５から再生誤差信号ｅｒｒ５＿Ｒを減算した出力信号ＡＭＰ＿ｏｕｔを、第４のスイッチＳＷ５４を介してＡＤＣ１３へ出力する（図１８のステップＳ５１２）。 The third subtracter 50 outputs the output signal AMP_out obtained by subtracting the reproduction error signal err5_R from the error signal err5 to the ADC 13 via the fourth switch SW54 (step S512 in FIG. 18).
　上述のように、再生誤差信号ｅｒｒ５＿Ｒは記憶装置１５に記憶したデジタル誤差信号ｅｒｒ５＿Ｄを再生したものである。そのため、Ｄ／Ａ変換、Ａ／Ｄ変換により、ある程度の波形の変化が生じるとしても、再生誤差信号ｅｒｒ５＿Ｒ及び誤差信号ｅｒｒ５の波形は近似する。 As described above, the reproduction error signal err5_R is a reproduction of the digital error signal err5_D stored in the storage device 15. Therefore, even if the waveform changes to some extent by D / A conversion and A / D conversion, the waveforms of the reproduction error signal err5_R and the error signal err5 are approximated.
　誤差信号ｅｒｒ５及び再生誤差信号ｅｒｒ５＿Ｒのタイミングが一致していれば、出力信号Ｖｏｕｔに含まれる誤差信号成分も最小化することができ、理想的には０とすることができる。よって、出力信号Ｖｏｕｔに含まれる誤差信号成分を最小化するためには、誤差信号ｅｒｒ５及び再生誤差信号ｅｒｒ５＿Ｒのタイミングを一致させる必要がある。 If the timings of the error signal err5 and the reproduction error signal err5_R coincide with each other, the error signal component included in the output signal Vout can be minimized, and can be ideally zero. Therefore, in order to minimize the error signal component included in the output signal Vout, it is necessary to match the timings of the error signal err5 and the reproduction error signal err5_R.
　誤差信号ｅｒｒ５及び再生誤差信号ｅｒｒ５＿Ｒのタイミングが一致している場合には出力信号Ｖｏｕｔは０レベルである。従って、ＡＤＣ１３により生成されたデジタル信号ＡＭＰ＿ｏｕｔ＿Ｄのいずれかのビットが「１」である場合には、誤差信号ｅｒｒ５及び再生誤差信号ｅｒｒ５＿Ｒのタイミングがずれていることを意味する。多入力ＯＲ回路１４の出力ＯＲ＿ｏｕｔは、デジタル信号ＡＭＰ＿ｏｕｔ＿Ｄのいずれかのビットが「１」である場合には「１」となり、デジタル信号ＡＭＰ＿ｏｕｔ＿Ｄの全てのビットが「０」である場合には「０」となる。すなわち、多入力ＯＲ回路１４は、誤差信号ｅｒｒ５及び再生誤差信号ｅｒｒ５＿Ｒのタイミングのずれの有無を検出することができる（図１８のステップＳ５１３）。その後のステップＳ５１４は、図１０のステップＳ２１４と同様であるので、説明を省略する。 When the timings of the error signal err5 and the reproduction error signal err5_R match, the output signal Vout is 0 level. Therefore, when any bit of the digital signal AMP_out_D generated by the ADC 13 is “1”, it means that the timing of the error signal err5 and the reproduction error signal err5_R is shifted. The output OR_out of the multi-input OR circuit 14 is “1” when any bit of the digital signal AMP_out_D is “1”, and “0” when all the bits of the digital signal AMP_out_D are “0”. " That is, the multi-input OR circuit 14 can detect the presence / absence of a timing shift between the error signal err5 and the reproduction error signal err5_R (step S513 in FIG. 18). Subsequent step S514 is the same as step S214 in FIG.
　多入力ＯＲ回路１４の出力ＯＲ＿ｏｕｔが「０」であるならば、誤差信号ｅｒｒ５及び再生誤差信号ｅｒｒ５＿Ｒのタイミングが一致している。この場合、制御回路１８は、制御信号ＳＩＧ２により、第２のスイッチＳＷ１２をオンにする。また、制御回路１８は、制御信号ＳＩＧ５１、ＳＩＧ１３及びＳＩＧ５４により、第１、第３及び第４のスイッチＳＷ５１、ＳＷ１３及びＳＷ５４をオフにする（図１８のステップＳ５１５）。その後のステップＳ５１６は、図１０のステップＳ２１６同様であるので、説明を省略する。 If the output OR_out of the multi-input OR circuit 14 is “0”, the timings of the error signal err5 and the reproduction error signal err5_R match. In this case, the control circuit 18 turns on the second switch SW12 by the control signal SIG2. Further, the control circuit 18 turns off the first, third and fourth switches SW51, SW13 and SW54 by the control signals SIG51, SIG13 and SIG54 (step S515 in FIG. 18). Subsequent step S516 is the same as step S216 in FIG.
　信号処理回路５００では、再生誤差信号ｅｒｒ５＿Ｒをフィルタリングしないので、再生誤差信号ｅｒｒ５＿Ｒには高周波成分が残存している。しかし、フィルタ２７が第１の減算器１１の出力と出力端子Ｔｏｕｔとの間に接続されているので、第１の減算器１１の出力からは、信号処理回路３００と同様に、Ｄ／Ａ変換に起因する高周波成分は除去される。従って、この場合、信号処理回路５００の出力信号Ｖｏｕｔは、信号処理回路３００と同等となる。 Since the signal processing circuit 500 does not filter the reproduction error signal err5_R, a high frequency component remains in the reproduction error signal err5_R. However, since the filter 27 is connected between the output of the first subtractor 11 and the output terminal Tout, the D / A conversion is performed from the output of the first subtractor 11 in the same manner as the signal processing circuit 300. The high-frequency component resulting from is removed. Therefore, in this case, the output signal Vout of the signal processing circuit 500 is equivalent to that of the signal processing circuit 300.
　タイミング調整の終了後、信号処理回路５００は、信号処理回路３００と同様に、通常動作を行う。以上のように、信号処理回路５００は、誤差信号ｅｒｒ５から再生誤差信号ｅｒｒ５＿Ｒを適切なタイミングで減算することにより、出力信号Ｖｏｕｔの誤差信号を除去している。これにより、被検出信号が検出されていない場合のセンサ回路の出力が０ではない場合でも、出力信号Ｖｏｕｔに含まれる誤差信号成分を除去することができる。よって、出力信号Ｖｏｕｔには、被検出信号のみが反映される。従って、本構成によれば、信号処理回路３００と同様に、希望波信号と同じ又は近接する周波数の誤差信号を除去することができる。 After completion of timing adjustment, the signal processing circuit 500 performs a normal operation in the same manner as the signal processing circuit 300. As described above, the signal processing circuit 500 removes the error signal of the output signal Vout by subtracting the reproduction error signal err5_R from the error signal err5 at an appropriate timing. Thereby, even when the output of the sensor circuit when the detected signal is not detected is not 0, the error signal component included in the output signal Vout can be removed. Therefore, only the detected signal is reflected in the output signal Vout. Therefore, according to this configuration, similarly to the signal processing circuit 300, it is possible to remove an error signal having a frequency that is the same as or close to that of the desired wave signal.
　上述のように、信号処理回路５００では、タイミング調整時にのみ、第３の減算器５０が減算動作を行う。つまり、タイミング調整時以外では、第３の減算器５０は機能しない。よって、タイミング調整時以外の信号処理回路５００の回路構成は、実質的に信号処理回路３００と同様である。従って、信号処理回路３００に第３の減算器５０及び第４のスイッチＳＷ５４を追加するだけで、容易に被検出信号が検出されていない場合のセンサ回路の出力が０ではない場合でも出力信号Ｖｏｕｔに含まれる誤差信号成分を除去することができる信号処理回路を実現できる。 As described above, in the signal processing circuit 500, the third subtracter 50 performs the subtraction operation only at the time of timing adjustment. That is, the third subtracter 50 does not function except during timing adjustment. Therefore, the circuit configuration of the signal processing circuit 500 other than the timing adjustment is substantially the same as that of the signal processing circuit 300. Therefore, the output signal Vout can be obtained even when the output of the sensor circuit is not 0 by simply adding the third subtractor 50 and the fourth switch SW54 to the signal processing circuit 300 and the detected signal is not easily detected. It is possible to realize a signal processing circuit that can remove the error signal component included in the.
　同様に、信号処理回路１００、２００及び４００の第３のスイッチＳＷ１３とＡＤＣ１３の入力との間に第３の減算器５０及び第４のスイッチＳＷ５４を追加するだけで、容易に被検出信号が検出されていない場合のセンサ回路の出力が０ではない場合でも出力信号Ｖｏｕｔに含まれる誤差信号成分を除去することができる信号処理回路を実現できる。 Similarly, the detected signal can be easily detected simply by adding the third subtractor 50 and the fourth switch SW54 between the third switch SW13 of the signal processing circuits 100, 200 and 400 and the input of the ADC 13. Even when the output of the sensor circuit when it is not performed is not 0, it is possible to realize a signal processing circuit that can remove the error signal component included in the output signal Vout.
　信号処理回路１００に第３減算器５０及び第４のスイッチＳＷ５４を追加する場合には、信号処理回路１００の第１のスイッチＳＷ２１が、信号処理回路５００の第１のスイッチＳＷ５１に相当する。また、信号処理回路１００の第２の減算器１２の反転入力が、信号源１０１と接続される。 When adding the third subtractor 50 and the fourth switch SW 54 to the signal processing circuit 100, the first switch SW 21 of the signal processing circuit 100 corresponds to the first switch SW 51 of the signal processing circuit 500. Further, the inverting input of the second subtractor 12 of the signal processing circuit 100 is connected to the signal source 101.
　信号処理回路２００又は４００に第２の減算器５０及び第４のスイッチＳＷ５４を追加する場合には、信号処理回路２００又は４００の第１のスイッチＳＷ２１を、信号源１０１と第１の減算器１１の反転入力との間に接続する。 When the second subtractor 50 and the fourth switch SW54 are added to the signal processing circuit 200 or 400, the first switch SW21 of the signal processing circuit 200 or 400 is replaced with the signal source 101 and the first subtractor 11. Connect to the inverting input of.
　実施の形態６
　次に、本発明の実施の形態６にかかる信号処理システム１０００について説明する。図２１は、実施の形態６にかかる信号処理システム１０００の構成を模式的に示すブロック図である。信号処理システム１０００は、実施の形態３にかかる信号処理回路３００にＣＰＵ１００１が接続された構成を有する。 Embodiment 6
Next, a signal processing system 1000 according to the sixth exemplary embodiment of the present invention will be described. FIG. 21 is a block diagram schematically illustrating a configuration of a signal processing system 1000 according to the sixth embodiment. The signal processing system 1000 has a configuration in which a CPU 1001 is connected to the signal processing circuit 300 according to the third embodiment.
　ＣＰＵ１００１は、信号処理回路３００の信号端子Ｔｅｎに、イネーブル信号ｅｎを供給する。また、ＣＰＵ１００１は、信号処理回路３００の信号端子Ｔｅｎｄから、完了信号ｅｎｄを受ける。 The CPU 1001 supplies an enable signal en to the signal terminal Ten of the signal processing circuit 300. Further, the CPU 1001 receives a completion signal end from the signal terminal Tend of the signal processing circuit 300.
　ＣＰＵ１００１は、イネーブル信号ｅｎにより、信号処理回路３００に誤差信号除去動作の開始を命ずることができる。この開始命令は、ＣＰＵ１００１がシステムのユーザの指示を受けて行うことができる。また、ＣＰＵ１００１が、環境温度を監視し、一定の温度変動が有った場合に、開始命令を発することも可能である。 The CPU 1001 can instruct the signal processing circuit 300 to start the error signal removal operation by the enable signal en. This start command can be issued by the CPU 1001 in response to an instruction from the user of the system. Further, the CPU 1001 monitors the environmental temperature, and can issue a start command when there is a certain temperature fluctuation.
　また、ＣＰＵ１００１は、信号処理回路３００から完了信号ｅｎｄを受けることにより、誤差信号除去動作の完了を認識する。そして、ＣＰＵ１００１は、イネーブル信号ｅｎのレベルを遷移させ、信号処理回路３００に誤差信号除去動作を終了させることができる。 The CPU 1001 recognizes the completion of the error signal removal operation by receiving the completion signal end from the signal processing circuit 300. Then, the CPU 1001 can transition the level of the enable signal en, and cause the signal processing circuit 300 to end the error signal removal operation.
　なお、本実施の形態では、信号処理回路３００を用いたが、信号処理回路１００、２００、３００又は５００を用いることができることは言うまでもない。 In the present embodiment, the signal processing circuit 300 is used, but it goes without saying that the signal processing circuit 100, 200, 300, or 500 can be used.
　また、本実施の形態では、信号処理回路にＣＰＵが接続される構成としたが、信号処理回路との信号の受け渡しが可能であれば、他のコンピュータやマイコンなどと接続して、シスムを構築することも可能である。 In this embodiment, the CPU is connected to the signal processing circuit. However, if a signal can be exchanged with the signal processing circuit, it is connected to another computer or a microcomputer to construct a system. It is also possible to do.
　よって、本構成によれば、上述の実施の形態１～５にかかる信号処理回路を好適に運用することができる信号処理システムを提供することができる。 Therefore, according to this configuration, it is possible to provide a signal processing system that can suitably operate the signal processing circuit according to the first to fifth embodiments.
　なお、本発明は上記実施の形態に限られたものではなく、趣旨を逸脱しない範囲で適宜変更することが可能である。例えば、信号処理回路のフィルタ１７に代えて、実施の形態３にかかるフィルタ２７を適用することも可能である。また、信号処理回路１００及び２００に、実施の形態４にかかるディレイライン４０を適用することも可能である。 Note that the present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit of the present invention. For example, instead of the filter 17 of the signal processing circuit, the filter 27 according to the third embodiment can be applied. Also, the delay line 40 according to the fourth embodiment can be applied to the signal processing circuits 100 and 200.
　また、信号処理回路５００は、第１のスイッチＳＷ５１、第４のスイッチＳＷ５４及び第３の減算器５０を、信号処理回路１００、２００、３００、４００及び上述の構成転換例に適宜適用した信号処理回路により、置換することも可能である。 Further, the signal processing circuit 500 is a signal processing in which the first switch SW51, the fourth switch SW54, and the third subtracter 50 are appropriately applied to the signal processing circuits 100, 200, 300, 400, and the above configuration change examples. It can also be replaced by a circuit.
　さらに、実施の形態６における信号処理回路３００を、信号処理回路１００、２００、４００及び５００のみならず、上述の構成転換例にかかる信号処理回路に置換することも可能である。 Furthermore, the signal processing circuit 300 according to the sixth embodiment can be replaced not only with the signal processing circuits 100, 200, 400, and 500 but also with the signal processing circuit according to the above-described configuration change example.
　実施の形態５においては、センサ回路としてタッチパネルを用いたが、例示に過ぎない。従って、上述の信号処理回路は、タッチパネル以外の任意のセンサ回路に適用することも可能である。 In Embodiment 5, a touch panel is used as a sensor circuit, but this is only an example. Therefore, the above-described signal processing circuit can be applied to any sensor circuit other than the touch panel.
　記憶装置１５は、書き込み／読み出しが可能な記憶装置であればよく、例えばフラッシュメモリや、その他の書き込み／読み出しが可能な記憶装置などの記憶素子を用いることが可能である。 The storage device 15 may be any storage device capable of writing / reading, and for example, a storage element such as a flash memory or other storage device capable of writing / reading may be used.
　この出願は、２０１１年３月３１日に出願された日本出願特願２０１１－７９８６５を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2011-79865 filed on March 31, 2011, the entire disclosure of which is incorporated herein.
１１　第１の減算器
１２　第２の減算器
１３　ＡＤＣ
１４　多入力ＯＲ回路
１５　記憶装置
１６　ＤＡＣ
１７、２７　フィルタ
１８　制御回路
４０　ディレイライン
５０　第３の減算器
１００、２００、３００、４００、５００～５０３　信号処理回路
１０１　信号源
１０２ａ　センサ回路
１０２ｂ　タッチパネル
６００　フィルタ回路
６０１　周波数変換器
６０２、６２１　Ａ／Ｄコンバータ
６１０　サンプラ
６２２　デジタルフィルタ
６３０　Ｄ／Ａコンバータ
６４０　遅延器
６５０　減算器
７００　ノイズキャンセル回路
７０１　アンテナ
７０２　フィルタ
７０３　位相反転部
７０４　位相同期部
７０５　レベル調節部
７０６　発振部
７０７　加算器
７０８　ＬＮＡ
７５０　妨害波対策部
１０００　信号処理システム
ＯＲ＿ｏｕｔ　多入力ＯＲ回路の出力
Ｓ＿ｏｕｔ　センサ回路の出力信号
ＳＩＧ１１～１３、ＳＩＧ２１、ＳＩＧ４０、ＳＩＧ５１、ＳＩＧ５４、ＳＩＧｍ　制御信号
ＳＷ１１～ＳＷ１３、ＳＷ２１、ＳＷ５１、ＳＷ５４　スイッチ
Ｓｄ　希望波信号
Ｔｅｎ、Ｔｅｎｄ　信号端子
Ｔｏｕｔ　出力端子
Ｖｏｕｔ　出力信号
Ｖｏｕｔ＿Ｄ　デジタル信号
ｅｎ　イネーブル信号
ｅｎｄ　完了信号
ｅｒｒ１、ｅｒｒ５　誤差信号
ｅｒｒ１＿Ｄ、ｅｒｒ５＿Ｄ　デジタル誤差信号
ｅｒｒ１＿Ｆ、ｅｒｒ１＿Ｒ、ｅｒｒ１＿ＲＤ、ｅｒｒ５＿Ｒ　再生誤差信号 11 First subtractor 12 Second subtractor 13 ADC
14 Multi-input OR circuit 15 Storage device 16 DAC
17, 27 Filter 18 Control circuit 40 Delay line 50 Third subtractor 100, 200, 300, 400, 500 to 503 Signal processing circuit 101 Signal source 102a Sensor circuit 102b Touch panel 600 Filter circuit 601 Frequency converter 602, 621 A / D converter 610 Sampler 622 Digital filter 630 D / A converter 640 Delay unit 650 Subtractor 700 Noise cancellation circuit 701 Antenna 702 Filter 703 Phase inversion unit 704 Phase synchronization unit 705 Level adjustment unit 706 Oscillation unit 707 Adder 708 LNA
750 Interference wave countermeasure unit 1000 Signal processing system OR_out Output of multi-input OR circuit S_out Output signal of sensor circuit SIG11 to 13, SIG21, SIG40, SIG51, SIG54, SIGm Control signal SW11 to SW13, SW21, SW51, SW54 Switch Sd Desired wave Signal Ten, Tend signal terminal Tout output terminal Vout output signal Vout_D digital signal en enable signal end completion signal err1, err5 error signal err1_D, err5_D digital error signal err1_F, err1_R, err1_RD, err5_R reproduction error signal

Claims (19)

  1. 　信号源と接続されるセンサ回路が検出対象となる信号を検出していない場合において、前記センサ回路から出力される前記信号源が出力する信号と同じ周波数の誤差信号の所定期間の信号波形を記憶する記憶装置と、
    　前記記憶装置に記憶された前記信号波形から前記誤差信号を再生した再生誤差信号を、前記所定期間ごとに繰り返し出力する再生誤差信号出力部と、
    　前記誤差信号から前記再生誤差信号を減算した信号を、出力端子へ出力する第１の減算器と、
    　前記センサ回路が検出対象となる信号を検出していない状態で、前記第１の減算器の出力信号の信号レベルが最小化するように、前記第１の減算器への前記再生誤差信号の供給タイミングを調整する制御回路と、を備える、
    　信号処理回路。     When the sensor circuit connected to the signal source does not detect the signal to be detected, the signal waveform of the error signal having the same frequency as the signal output from the signal source output from the sensor circuit is stored for a predetermined period. A storage device to
    A reproduction error signal output unit that repeatedly outputs a reproduction error signal obtained by reproducing the error signal from the signal waveform stored in the storage device every predetermined period;
    A first subtractor that outputs a signal obtained by subtracting the reproduction error signal from the error signal to an output terminal;
    Supplying the reproduction error signal to the first subtractor so that the signal level of the output signal of the first subtractor is minimized while the sensor circuit is not detecting a signal to be detected. A control circuit for adjusting the timing,
    Signal processing circuit.
  2. 　前記誤差信号をＡ／Ｄ変換したデジタル誤差信号を前記記憶装置へ出力するＡ／Ｄコンバータを更に備え、
    　再生誤差信号出力部は、前記記憶装置からの出力をＤ／Ａ変換するＤ／Ａコンバータであり、
    　前記記憶装置は、前記デジタル誤差信号を記憶し、
    　前記制御回路は、前記記憶装置に記憶された前記デジタル誤差信号を前記Ｄ／Ａコンバータへ出力させることを特徴とする、
    　請求項１に記載の信号処理回路。     An A / D converter that outputs a digital error signal obtained by A / D converting the error signal to the storage device;
    The reproduction error signal output unit is a D / A converter that D / A converts the output from the storage device,
    The storage device stores the digital error signal;
    The control circuit outputs the digital error signal stored in the storage device to the D / A converter.
    The signal processing circuit according to claim 1.
  3. 　前記制御回路は、前記記憶装置が前記再生誤差信号出力部へ前記デジタル誤差信号を出力するタイミングを調整することを特徴とする、
    　請求項２に記載の信号処理回路。     The control circuit adjusts a timing at which the storage device outputs the digital error signal to the reproduction error signal output unit.
    The signal processing circuit according to claim 2.
  4. 　前記制御回路は、前記記憶装置に記憶された前記デジタル誤差信号を前記Ｄ／Ａコンバータへ出力させるタイミングを調整することを特徴とする、
    　請求項３に記載の信号処理回路。     The control circuit adjusts a timing for outputting the digital error signal stored in the storage device to the D / A converter.
    The signal processing circuit according to claim 3.
  5. 　前記Ｄ／Ａコンバータと前記第１の減算器との間に挿入され、前記再生誤差信号を遅延させる遅延部を更に備え、
    　前記制御回路は、前記遅延部が前記再生誤差信号に与える遅延量を制御することを特徴とする、
    　請求項２に記載の信号処理回路。     A delay unit inserted between the D / A converter and the first subtractor for delaying the reproduction error signal;
    The control circuit controls a delay amount given to the reproduction error signal by the delay unit,
    The signal processing circuit according to claim 2.
  6. 　前記第１の減算器の反転入力端子と前記Ｄ／Ａコンバータの出力との間に接続される第２のスイッチと、
    　前記第１の減算器の出力端子と前記Ａ／Ｄコンバータの入力との間に接続される第３のスイッチと、を更に備えることを特徴とする、
    　請求項２乃至５のいずれか一項に記載の信号処理回路。     A second switch connected between an inverting input terminal of the first subtractor and an output of the D / A converter;
    A third switch connected between an output terminal of the first subtractor and an input of the A / D converter;
    The signal processing circuit according to claim 2.
  7. 　非反転入力端子が前記センサ回路の出力と接続され、反転入力端子がグランドと接続される第２の減算器と、
    　前記第２の減算器の出力端子と、前記Ａ／Ｄコンバータの前記入力との間に接続される第１のスイッチと、を更に備え、
    　前記制御回路は、前記第１のスイッチをオン、前記第２及び第３のスイッチをオフにすることにより、前記Ａ／Ｄコンバータへ前記誤差信号を供給し、
    　前記Ａ／Ｄコンバータは、前記第２の減算器からの前記誤差信号を前記デジタル誤差信号に変換することを特徴とする、
    　請求項６に記載の信号処理回路。     A second subtractor having a non-inverting input terminal connected to the output of the sensor circuit and an inverting input terminal connected to ground;
    A first switch connected between the output terminal of the second subtractor and the input of the A / D converter;
    The control circuit supplies the error signal to the A / D converter by turning on the first switch and turning off the second and third switches,
    The A / D converter converts the error signal from the second subtractor into the digital error signal.
    The signal processing circuit according to claim 6.
  8. 　前記第１の減算器の前記反転入力端子とグランドとの間に接続される第１のスイッチを更に備え、
    　前記第１の減算器の非反転入力端子は前記センサ回路の出力と接続され、前記第１の減算器の前記出力端子は、前記Ａ／Ｄコンバータの前記入力と接続され、　
    　前記制御回路は、前記第１及び第３のスイッチをオン、前記第２のスイッチをオフにすることにより、前記Ａ／Ｄコンバータへ前記誤差信号を供給し、
    　前記Ａ／Ｄコンバータは、前記第１の減算器からの前記誤差信号を前記デジタル誤差信号に変換することを特徴とする、
    　請求項６に記載の信号処理回路。     A first switch connected between the inverting input terminal of the first subtractor and ground;
    A non-inverting input terminal of the first subtractor is connected to an output of the sensor circuit, and an output terminal of the first subtractor is connected to the input of the A / D converter;
    The control circuit supplies the error signal to the A / D converter by turning on the first and third switches and turning off the second switch,
    The A / D converter converts the error signal from the first subtractor into the digital error signal.
    The signal processing circuit according to claim 6.
  9. 　前記制御回路は、前記第１のスイッチをオフ、前記第２及び第３のスイッチをオンにし、前記Ｄ／Ａコンバータから前記再生誤差信号を出力させ、
    　前記第１の減算器は、前記誤差信号から前記再生誤差信号を減算した信号を出力することを特徴とする、
    　請求項７又は８に記載の信号処理回路。     The control circuit turns off the first switch, turns on the second and third switches, and outputs the reproduction error signal from the D / A converter,
    The first subtractor outputs a signal obtained by subtracting the reproduction error signal from the error signal.
    The signal processing circuit according to claim 7 or 8.
  10. 　前記第１の減算器から出力される信号のレベルを検出する検出回路を更に備え、
    　前記制御回路は、前記検出回路が検出した前記第１の減算器から出力される前記信号のレベルに応じて、前記第１の減算器への前記再生誤差信号の供給タイミングを調整することを特徴とする、
    　請求項７乃至９のいずれか一項に記載の信号処理回路。     A detection circuit for detecting a level of a signal output from the first subtractor;
    The control circuit adjusts the supply timing of the reproduction error signal to the first subtracter according to the level of the signal output from the first subtractor detected by the detection circuit. And
    The signal processing circuit according to claim 7.
  11. 　前記検出回路は前記Ａ／Ｄコンバータの出力と前記制御回路との間に接続された多入力ＯＲ回路であり、
    　前記制御回路は、前記多入力ＯＲ回路が、前記デジタル誤差信号のいずれかのビットが１である場合には、前記第１の減算器への前記再生誤差信号の供給タイミングを遅らせることを特徴とする、
    　請求項１０に記載の信号処理回路。     The detection circuit is a multi-input OR circuit connected between the output of the A / D converter and the control circuit;
    The control circuit is characterized in that the multi-input OR circuit delays the supply timing of the reproduction error signal to the first subtracter when any bit of the digital error signal is 1. To
    The signal processing circuit according to claim 10.
  12. 　前記第１の減算器の前記反転入力端子と前記信号源との間に接続される第１のスイッチを更に備え、
    　前記第１の減算器の非反転入力端子は前記センサ回路の出力と接続され、前記第１の減算器の前記出力端子は、前記Ａ／Ｄコンバータの前記入力と接続され、
    　前記制御回路は、前記第１及び第３のスイッチをオン、前記第２のスイッチをオフにすることにより、前記Ａ／Ｄコンバータへ前記誤差信号を供給し、
    　前記Ａ／Ｄコンバータは、前記第１の減算器からの前記誤差信号を前記デジタル誤差信号に変換することを特徴とする、
    　請求項６に記載の信号処理回路。     A first switch connected between the inverting input terminal of the first subtractor and the signal source;
    A non-inverting input terminal of the first subtractor is connected to an output of the sensor circuit, and an output terminal of the first subtractor is connected to the input of the A / D converter;
    The control circuit supplies the error signal to the A / D converter by turning on the first and third switches and turning off the second switch,
    The A / D converter converts the error signal from the first subtractor into the digital error signal.
    The signal processing circuit according to claim 6.
  13. 　反転入力端子が前記Ｄ／Ａコンバータと接続され、非反転入力端子が前記第１の減算器の前記出力端子と接続される第３の減算器と、
    　前記第３の減算器の出力端子と前記Ａ／Ｄコンバータの前記入力との間に接続される第４のスイッチと、を備え、
    　前記制御回路が前記第１及び第４のスイッチをオン、前記第２及び第３のスイッチをオフにし、
    　前記第３の減算器は前記誤差信号から前記再生誤差信号を減算した信号を、前記Ａ／Ｄコンバータに出力する、
    　請求項１２に記載の信号処理回路。     A third subtractor having an inverting input terminal connected to the D / A converter and a non-inverting input terminal connected to the output terminal of the first subtractor;
    A fourth switch connected between the output terminal of the third subtractor and the input of the A / D converter;
    The control circuit turns on the first and fourth switches, turns off the second and third switches,
    The third subtracter outputs a signal obtained by subtracting the reproduction error signal from the error signal to the A / D converter;
    The signal processing circuit according to claim 12.
  14. 　前記第３の減算器から出力される信号のレベルを検出する検出回路を更に備え、
    　前記制御回路は、前記検出回路が検出した前記第３の減算器から出力される前記信号のレベルに応じて、前記第３の減算器からの信号の信号レベルが最小になるように、前記第３の減算器への前記再生誤差信号の供給タイミングを調整することを特徴とする、
    　請求項１３に記載の信号処理回路。     A detection circuit for detecting a level of a signal output from the third subtractor;
    The control circuit is configured to reduce the signal level of the signal from the third subtractor according to the level of the signal output from the third subtractor detected by the detection circuit. Adjusting the supply timing of the reproduction error signal to the subtractor of No. 3;
    The signal processing circuit according to claim 13.
  15. 　前記検出回路は前記Ａ／Ｄコンバータの出力と前記制御回路との間に接続された多入力ＯＲ回路であり、
    　前記制御回路は、前記多入力ＯＲ回路が、前記デジタル誤差信号のいずれかのビットが１である場合には、前記第３の減算器への前記再生誤差信号の供給タイミングを遅らせることを特徴とする、
    　請求項１４に記載の信号処理回路。     The detection circuit is a multi-input OR circuit connected between the output of the A / D converter and the control circuit;
    The control circuit is characterized in that the multi-input OR circuit delays the supply timing of the reproduction error signal to the third subtracter when any bit of the digital error signal is 1. To
    The signal processing circuit according to claim 14.
  16. 　前記制御回路は、前記第３の減算器からの前記信号の信号レベルが最小である状態で、前記第２のスイッチをオン、前記第１、第３及び第４のスイッチをオフにする、
    　請求項１５に記載の信号処理回路。     The control circuit turns on the second switch and turns off the first, third, and fourth switches in a state where the signal level of the signal from the third subtractor is minimum.
    The signal processing circuit according to claim 15.
  17. 　前記Ｄ／Ａコンバータと前記第１の減算器との間に挿入され、前記信号源が出力する前記信号と同じ周波数の信号を通過させるフィルタを更に備えることを特徴とする、
    　請求項２乃至１６のいずれか一項に記載の信号処理回路。     It further includes a filter inserted between the D / A converter and the first subtracter and passing a signal having the same frequency as the signal output from the signal source.
    The signal processing circuit according to claim 2.
  18. 　前記第１の減算器の前記出力端子と当該信号処理回路の前記出力端子との間に挿入され、前記信号源が出力する前記信号と同じ周波数の信号を通過させるフィルタを更に備えることを特徴とする、
    　請求項２乃至１６のいずれか一項に記載の信号処理回路。     A filter that is inserted between the output terminal of the first subtractor and the output terminal of the signal processing circuit and passes a signal having the same frequency as the signal output from the signal source; To
    The signal processing circuit according to claim 2.
  19. 　信号源と接続されるセンサ回路が検出対象となる信号を検出していない場合において、前記センサ回路から出力される前記信号源が出力する信号と同じ周波数の誤差信号の所定期間の信号波形を、記憶装置に記憶させ、
    　前記記憶装置に記憶された前記信号波形から前記誤差信号を再生した再生誤差信号を、前記所定期間ごとに繰り返し出力し、
    　第１の減算器が前記誤差信号から前記再生誤差信号を減算した信号を、出力端子へ出力し、
    　前記センサ回路が検出対象となる信号を検出していない状態で、前記第１の減算器の出力信号の信号レベルが最小化するように、前記第１の減算器への前記再生誤差信号の供給タイミングを調整する、
    　信号処理方法。     When the sensor circuit connected to the signal source does not detect the signal to be detected, the signal waveform of the error signal of the same frequency as the signal output from the signal source output from the sensor circuit is a predetermined period, Store it in a storage device,
    A reproduction error signal obtained by reproducing the error signal from the signal waveform stored in the storage device is repeatedly output every predetermined period,
    A first subtracter outputs a signal obtained by subtracting the reproduction error signal from the error signal to an output terminal,
    Supplying the reproduction error signal to the first subtractor so that the signal level of the output signal of the first subtractor is minimized while the sensor circuit is not detecting a signal to be detected. Adjust the timing,
    Signal processing method.
PCT/JP2012/001278 2011-03-31 2012-02-24 Signal processing circuit and signal processing method WO2012132216A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59223897A (en) * 1983-06-01 1984-12-15 帝人株式会社 Noise processing method and apparatus
JPS6277719A (en) * 1985-09-30 1987-04-09 Nec Corp Interference wave eliminating device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59223897A (en) * 1983-06-01 1984-12-15 帝人株式会社 Noise processing method and apparatus
JPS6277719A (en) * 1985-09-30 1987-04-09 Nec Corp Interference wave eliminating device

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