WO2012128401A1 - Dispositif de traitement d'un signal de radiofréquence et procédé de traitement d'un signal de radiofréquence - Google Patents

Dispositif de traitement d'un signal de radiofréquence et procédé de traitement d'un signal de radiofréquence Download PDF

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Publication number
WO2012128401A1
WO2012128401A1 PCT/KR2011/001954 KR2011001954W WO2012128401A1 WO 2012128401 A1 WO2012128401 A1 WO 2012128401A1 KR 2011001954 W KR2011001954 W KR 2011001954W WO 2012128401 A1 WO2012128401 A1 WO 2012128401A1
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Prior art keywords
signal
sampling
frequency
current
voltage
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PCT/KR2011/001954
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English (en)
Korean (ko)
Inventor
권효근
이상원
김형준
Original Assignee
주식회사 플라즈마트
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Priority to PCT/KR2011/001954 priority Critical patent/WO2012128401A1/fr
Publication of WO2012128401A1 publication Critical patent/WO2012128401A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/1607—Supply circuits

Definitions

  • the present invention relates to an RF signal processing apparatus, and more particularly, to processing of an output signal of an RF power supply.
  • a radio frequency (RF) plasma apparatus may generate a plasma by applying RF power of a predetermined frequency (for example, 13.56 Mhz) to an antenna or an electrode.
  • the load containing the plasma is a time varying load that varies with time.
  • the RF power supply needs to respond quickly in response to the time varying load. Therefore, there is a need for an RF signal processing apparatus for controlling the RF power supply.
  • One technical problem to be solved of the present invention is to provide an RF signal processing apparatus having a stable and fast operating characteristics.
  • One technical problem to be solved by the present invention is to provide an RF signal processing method having a stable and fast operating characteristics.
  • the driving frequency (f rf) the sensor section the driving frequency (f rf) for generating a voltage signal and a current signal by measuring the output voltage and current of the RF power supply which is driven by A sampling unit synchronized with the sampling unit to generate a sampling current signal and a sampling voltage signal by sampling the current signal and the voltage signal at a sampling frequency f s which is an integer multiple of the driving frequency f rf , and the sampling current signal;
  • a signal processor for processing the sampling voltage signal through a pipeline.
  • the signal processor provides an operation signal for each clock of the sampling frequency.
  • the RF power supply includes a power supply, amplification, summing, and a power filter, wherein the signal processing unit adds the sum using the current signal and the voltage signal at the output of the RF power.
  • the RF signal may be provided with a warning signal for shutting down the RF power by extracting an impedance or reflection coefficient of a secondary front end.
  • the signal processing unit modulates the sampling current signal and the sampling voltage signal by calculating a sine wave and a cosine wave having a conversion sampling frequency ( ⁇ s ) defined as a product of a driving angular frequency and a sampling period.
  • a modulator for generating a current signal and a modulated voltage signal, a filter part for extracting an in-phase voltage signal, a phase-phase voltage signal, an in-phase current signal, and a phase-phase current signal which are direct current components of the modulated current signal and the modulated voltage signal.
  • a calculation unit for calculating a direct current component of the modulation current signal and the modulation voltage signal and providing the calculation signal as a function of a magnitude of the voltage signal, a magnitude of the current signal, and a phase difference between the voltage signal and the current signal. It may include.
  • the operation signal may include at least one of impedance, forward power, reflected power, power consumption, reflection coefficient, and voltage sine wave ratio (SWR).
  • control unit for providing a control signal for controlling the RF power
  • the control unit may receive the operation signal and output the control signal for controlling the RF power.
  • the operation unit may process the operation signal to provide a warning signal to at least one of the RF power source and the control unit.
  • the sampling frequency f s may be four times the driving frequency f rf .
  • it may further include an intermediate clock generator for outputting an intermediate clock, and a frequency multiplier and a frequency attenuator.
  • the frequency multiplier receives the intermediate clock to increase the frequency by an integer multiple to generate the sampling clock having the sampling frequency
  • the frequency attenuator receives the intermediate clock to reduce the frequency to an integer multiple by the driving frequency f rf.
  • Generate the driving clock wherein the sampling clock is provided to the signal processor and the driving clock is provided to the RF power supply.
  • the RF signal processing method is the drive frequency (f rf) steps, the drive frequency (f rf) for generating a voltage signal and a current signal by measuring the output voltage and current of the RF power supply which is driven by Sampling the voltage signal and the current signal at a sampling frequency f s that is synchronized and is an integer multiple of the driving frequency f rf to generate a sampling voltage signal and a sampling current signal, and the sampling voltage signal and sampling current Generating an operation signal through a pipeline, wherein the operation signal may be provided for each clock at a sampling frequency.
  • the RF power supply includes a power supply, amplification, summing, and a power filter, wherein the signal processing unit adds the sum using the current signal and the voltage signal at the output of the RF power.
  • the method may further include providing a warning signal to shut down the RF power by extracting an impedance or reflection coefficient of a secondary front end to the RF power.
  • generating the operation signal is a sine wave and a cosine wave having a converted sampling frequency ( ⁇ s ) defined as a product of a driving angular frequency and a sampling period of the sampling voltage signal and the sampling current signal.
  • Generating a modulated voltage signal and a modulated current signal extracting an in-phase voltage signal, a phase-phase voltage signal, a phase-phase current signal, and a phase-phase current signal which are direct current components of the modulated voltage signal and the modulated current signal.
  • calculating direct current components of the modulated voltage signal and the modulated current signal to provide the calculated signal as a function of the magnitude of the voltage signal, the magnitude of the current signal, and the phase difference between the voltage signal and the current signal. It may include a step.
  • the method may further include generating an intermediate clock, a sampling clock, and a driving clock, generating the sampling clock by receiving the intermediate clock, increasing the frequency by an integer multiple, and generating the intermediate clock.
  • the driving clock may be reduced by an integer multiple to generate the driving clock, and the sampling clock may provide timing for generating the sampling and the operation signal, and the driving clock may be provided to the RF power supply.
  • the method may further include generating a control signal for receiving the operation signal and controlling the RF power.
  • the RF signal processing apparatus may oversample the output signals in synchronization with a driving frequency of an output signal of an RF power supply and perform a high-speed pipeline operation to provide an operation signal for each sampling clock. . Accordingly, the RF power source can be stably controlled at a sampling frequency.
  • the RF power supply may include a power supply unit, an amplifier unit, an adder unit, and a power filter unit, and the signal processing unit may use the current signal and the voltage signal at the output terminal of the RF power source to adjust the impedance or reflection coefficient of the front end of the adder unit.
  • a warning signal for extracting and shutting down the RF power may be provided to the RF power. Accordingly, by measuring the current and the voltage at the output terminal of the RF power supply at once, the RF power supply can be controlled to improve reliability.
  • FIG. 1 is a view showing a waveform of a voltage signal and a current signal of the output terminal of the RF power source according to an embodiment of the present invention.
  • FIG. 2 is a block diagram illustrating an RF signal processing apparatus according to an embodiment of the present invention.
  • FIG. 3 is a flowchart illustrating an RF signal processing method according to an embodiment of the present invention.
  • 4 to 12 are diagrams illustrating signals of an RF signal processing apparatus according to an embodiment of the present invention.
  • FIG. 13 is a diagram illustrating clocks of an RF signal processing apparatus according to an embodiment of the present invention.
  • FIG. 14 is a diagram illustrating an RF signal processing apparatus according to another embodiment of the present invention.
  • An RF (radio frequency) power source may be connected to a time varying load.
  • the RF signal processing apparatus needs to detect an output characteristic of the RF power supply and feed back to the RF power supply as soon as possible.
  • the RF power source may be opened or shorted by abnormal operation. In this case, the RF power may be damaged. Therefore, there is a need for a method of processing an RF signal having a high processing speed.
  • the time-varying load is a plasma, it may be an abnormal operation such as an arc (arc).
  • the duration of the arc may be several usec to several msec. If the arc persists, the RF power source may be damaged. Therefore, there is a need for a method of processing an RF signal having a high processing speed.
  • the RF power supply may include a power supply unit, an amplifier unit, an adder unit, and a power supply filter unit.
  • the impedance characteristics of the power supply filter unit and the summing unit may be previously investigated.
  • the output impedance of the output terminal of the RF power supply can be detected promptly, and converted into an impedance at the front end of the summing unit to quickly calculate whether the output terminal of the amplifier is open or shorted. Accordingly, by measuring the current and the voltage at the output terminal of the RF power supply, it is determined whether the output terminal of the amplifier is open or short-circuit, and the RF power supply can be shut down as soon as it is processed by an interrupt method.
  • the RF power supply needs to be controlled.
  • the output power of the RF power supply may be controlled to be maintained below a predetermined value.
  • the output current signal and output voltage signal of the RF power supply can be converted into a digital signal by a high speed analog-to-digital converter.
  • a field programmable gate array processes the digital signal and provides an output signal through communication with a central processing unit (CPU).
  • the speed and communication speed of the external central processing unit are slower than the speed of the output signal of the FPGA. Therefore, the FPGA outputs by reducing the speed of the output signal. Therefore, the central processing unit has a limitation in quickly calculating and processing an abnormal state of the RF power supply.
  • the RF signal processing apparatus may control the RF power by calculating the output characteristic of the RF power through a synchronous oversampling and a pipeline having a high speed.
  • the RF signal processing apparatus may include an FPGA and a central processing unit.
  • the FPGA may control the RF power supply within several usec by processing the interrupt processing method with the CPU instead of McBSP communication.
  • FIG. 1 is a view showing a waveform of a voltage signal and a current signal of the output terminal of the RF power source according to an embodiment of the present invention.
  • the voltage signal is a harmonic wave and may be represented by a sine function.
  • the voltage signal V (t) may have a driving frequency f rf of the RF power supply, and the voltage signal V (t) may have a voltage phase ⁇ V.
  • the current signal I (t) is a harmonic wave and may be represented by a sine function.
  • the current signal I (t) may have a driving frequency f rf of the RF power supply, and the current signal I (t) may have a current phase ⁇ I.
  • the voltage signal V (t) and the current signal I (t) may be expressed as follows.
  • Vm is the amplitude of the voltage signal V (t) and Im is the amplitude of the current signal I (t).
  • the voltage signal V (t) and the current signal I (t) may be represented as a complex voltage signal V and a complex current signal I as follows.
  • the voltage signal V (t) and the current signal I (t) may be sampled at a sampling period Ts or a sampling frequency f s . Accordingly, the sampled voltage signal V (n) and the sampled current signal I (n) may be represented as follows.
  • Voltage modulated signals V (n) sin ( ⁇ s n), V (n) cos ( ⁇ s n) and current modulated signals I (n) sin ( ⁇ s n), I (n) cos ( ⁇ s n) is the periodic functions (cos ( ⁇ s n), sin ( ⁇ s ) of the sampled voltage signal V (n) and the sampled current signal I (n) and the converted sampling frequency. n)) can be expressed as follows.
  • the voltage modulated signals V (n) sin ( ⁇ s n), V (n) cos ( ⁇ s n) and the current modulated signals I (n) sin ( ⁇ s n), I (n) cos ( ⁇ s n)) may be generated using a mixer.
  • the voltage modulated signals V (n) sin ( ⁇ s n), V (n) cos ( ⁇ s n) and the current modulated signals I (n) sin ( ⁇ s n), I (n) cos ( ⁇ s n))) and remove the high frequency components, only DC components can be extracted. Removal of the high frequency component may be performed through a low pass filter.
  • the DC components may be defined as follows.
  • the DC components may satisfy the following relation through calculation.
  • the DC components can be calculated through the pipeline.
  • the magnitude Vm of the voltage signal, the magnitude Im of the current signal, and the phase difference ⁇ of the voltage signal and the current signal may be calculated as follows.
  • the impedance Z in the load direction at the measurement position, the reflection coefficient ⁇ , and the voltage standing wave ratio VSWR can be expressed as follows.
  • Z 0 is the characteristic impedance of the transmission line.
  • Normalized incident power wave can be defined as follows.
  • Normalized reflected power wave can be defined as follows.
  • phase difference ⁇ is a difference between the phase ⁇ I of the current signal and the phase ⁇ V of the voltage signal.
  • the impedance Z, the reflection coefficient ⁇ , or the voltage standing wave ratio VSWR may be calculated for each sampling clock through a pipeline.
  • the RF power supply may include a power supply unit, an amplifier unit, an adder unit, and a power supply filter unit.
  • the impedance of the output terminal of the power filter unit may be converted into an impedance in the load direction at the front end of the summation unit.
  • the impedance characteristics of the power supply filter unit and the summing unit may be previously investigated. Thus, the impedance in the load direction at the front of the adder can provide whether the RF power is shorted or open.
  • the RF power may be immediately controlled by checking whether the amplification unit is shorted by inverting by using the impedance of the output terminal of the RF power or the reflection coefficient ⁇ . Accordingly, the reliability of the RF power supply can be improved.
  • FIG. 2 is a block diagram illustrating an RF signal processing apparatus according to an embodiment of the present invention.
  • the RF signal processing apparatus measures an output voltage and a current of an RF power source 101 driven at a driving frequency f rf , thereby measuring a voltage signal V (t) and a current signal I (t).
  • the sensor unit 140 the drive frequency (f rf), synchronized to the drive frequency (f rf), an integer multiple of the sampling frequency (f s) to said voltage signal (V (t)) and the current signal to generate a
  • a signal processor 201 for processing the current signal I (n) through a pipeline.
  • the signal processor 201 provides an operation signal CAL for each clock of the sampling frequency fs.
  • the RF power supply 101 may include a power supply unit 110, an amplifier 120, an adder 130, and a power filter unit 132.
  • the power supply unit 110 may supply DC power for the operation of the amplifier 120.
  • the amplifier 120 may include a power transistor, and the amplifier 120 may output a harmonic wave at the driving frequency f rf . Power of the amplifier 120 may be combined by the adder 130.
  • the driving frequency f rf of the RF power source 101 may be in the range of several hundred Khz to several hundred Mhz.
  • the power filter unit 132 may remove harmonic components other than a driving frequency component from the output signal of the summing unit 130. Impedance characteristics of the power filter unit 132 and the summation unit 130 may be previously investigated.
  • the sensor unit 140 generates a voltage signal V (t) and a current signal I (t) by measuring the current and the voltage at the output terminal of the RF power source 101.
  • the sensor unit 140 may include a measuring electrode measuring the voltage and a measuring coil measuring the current.
  • the sensor unit 140 may be variously modified.
  • the sampling unit 210 samples the current signal V (t) and the current signal I (t) at a sampling frequency f s that is an integer multiple of the driving frequency f rf , thereby sampling sampling voltage signal ( V (n) and the sampling current signal I (n) are generated.
  • the sampling unit 210 may include an analog-to-digital converter (A / D converter) and a sampling clock (SCLK).
  • the sampling clock SCLK may provide a sampling pulse to the analog-to-digital converters 212 and 214, and the sampling pulse may provide a timing reference to the analog-to-digital converters 212 and 214.
  • the frequency fs of the sampling clock SCLK may be an integer multiple of the driving frequency f rf of the RF power source 101.
  • the frequency fs of the sampling clock SCLK may be four times the driving frequency f rf of the RF power source 101.
  • the modulator 230 converts the sampling voltage signal V (n) and the sampling current signal I (n) into a conversion sampling frequency defined as a product of a driving angular frequency ⁇ rf and a sampling period T s .
  • ⁇ s the sine wave (sin ( ⁇ s n)) and a cosine wave (cos ( ⁇ s n)) for modulating ⁇ s n
  • the current signal (I (n) sin calculates
  • the sine waves sin ( ⁇ s n) and cosine waves cos ( ⁇ s n) may be tabled and stored in the memories 222, 224, 226 and 228.
  • the modulator 230 may include first to fourth digital mixers 232, 234, 236, and 238.
  • the first digital mixer 232 may perform an operation of multiplying the sampling voltage signal V (n) by the sine wave sin ( ⁇ s n).
  • the second digital mixer 234 may perform an operation of multiplying the sampling voltage signal V (n) by the cosine wave cos ( ⁇ s n).
  • the third digital mixer 236 may perform an operation of multiplying the sampling current signal I (n) by the sine wave sin ( ⁇ s n).
  • the fourth digital mixer 238 may perform an operation of multiplying the sampling current signal I (n) by the cosine wave cos ( ⁇ s n).
  • the modulator 230 may operate in synchronization with the sampling clock SCLK.
  • the modulation current signals I (n) sin ( ⁇ s n), I (n) cos ( ⁇ s n) and the modulation voltage signals V (n) sin ( ⁇ s n), V (n) cos ( ⁇ s n)) may use one sampling clock SCLK.
  • the filter unit 240 includes the modulation voltage signal V (n) sin ( ⁇ s n), V (n) cos ( ⁇ s n) and the modulation current signal I (n) sin ( ⁇ s n). Extract the in-phase voltage signal Va, the phase-phase voltage signal Vb, the in-phase current signal Ia, and the phase-phase current signal Ib, which are DC components of I (n) cos ( ⁇ s n)). can do.
  • the filter unit 240 may include a finite impulse response (FIR) filter. The filter unit 240 may operate in synchronization with the sampling clock SCLK.
  • FIR finite impulse response
  • the calculation of the in-phase voltage signal Va, the phase-phase voltage signal Vb, the in-phase current signal Ia, and the phase-phase current signal Ib may use one sampling clock SCLK.
  • the filter unit 240 may output an average value of the input signals with a time delay.
  • the calculation unit 250 calculates the direct current components Va, Vb, Ia, and Ib of the modulation voltage signal and the modulation current signal to obtain the magnitude (
  • the operation signal (CAL) may include V 2/4, I 2/ 4, VIcos ⁇ / 4, and VIsin ⁇ / 4.
  • the calculator 250 may operate in synchronization with the sampling clock SCLK. The operation may be performed through a pipeline. Thus, high speed computation is possible.
  • the operation unit 250 calculates the direct current components Va, Vb, Ia, and Ib of the modulated current signal and the modulated voltage signal to generate impedance Z, forward power P fwd , reflected power P rev ,
  • An operation signal CAL including at least one of power consumption P load , a reflection coefficient ⁇ , and a voltage sine wave ratio SWR may be provided.
  • the operation may be performed through a pipeline.
  • the operation signal CAL may be generated for each sampling clock. For example, when the driving frequency is 13.56 Mhz and the frequency of the sampling clock SCLK is 54.24 Mhz, the calculation unit 250 outputs the operation signal CAL every clock of the sampling clock SCLK. can do.
  • the calculation of the operation signal CAL may use a predetermined clock.
  • the operation unit 250 may provide a stable and fast operation signal CAL after a predetermined clock. That is, the operation signal CAL may have a faster speed than the driving frequency. Accordingly, the operation signal CAL may provide an output variation of the RF power supply 101 that is earlier than or equal to the driving frequency.
  • the reflection coefficient ⁇ or the reflected power P rev may provide information regarding the opening or shorting of the load.
  • the reflection coefficient ( ⁇ ) or the impedance (Z) at the output terminal of the RF power source 101 is the front end of the summing unit 130 in consideration of the impedance characteristics of the power filter unit 132 and the summing unit 130 It can be converted into a reflection coefficient or impedance of.
  • the reflection coefficient or impedance of the front end of the adder 130 may provide information regarding whether the amplifier 120 is shorted or opened.
  • the calculator 250 may provide a warning signal ALM to the controller 300 or the RF power source 101 in an interrupt manner with respect to the open / short of the amplifier 120.
  • the warning signal ALM may be calculated through a pipeline.
  • the RF power source 101 may be shut down.
  • the modulator 230, the filter 240, and the calculator 250 may be implemented with a field programmable gate array (FPGA) 202.
  • the modulator 230, the filter unit 240, and the calculator 250 may be implemented as an ASIC.
  • the controller 300 may provide a control signal CTRL for controlling the RF power source 101.
  • the control unit 300 may receive the operation signal CAL and output the control signal CTRL for controlling the RF power supply 101.
  • the operation signal CAL may include at least one of impedance Z, forward power P fwd , reflected power P rev , power consumption P load , reflection coefficient ⁇ , and voltage sine wave ratio SWR. It may include.
  • the reflection coefficient ⁇ at the output terminal of the RF power source 101 may be compared with a critical reflection coefficient ⁇ c .
  • the reflected power P rev may be compared with a threshold reflected power. When the reflection coefficient ⁇ or the reflection power P rev is greater than or equal to a threshold value, the controller 300 provides a control signal CTRL to the RF power supply 101 to maintain the reflection power at a predetermined value or less. can do.
  • the controller 300 may receive a setting value by communicating with an input / output device.
  • the controller 300 may communicate with a server.
  • the set value may include forward power of the RF power source 101.
  • the control unit 300 may change the DC voltage of the power supply unit 110 so that the forward power reaches the set value.
  • the control signal CTRL may include a signal for changing the DC voltage of the power supply unit.
  • the control signal CTRL may include a warning signal ALM for shutting down the RF power supply 101.
  • the controller may be a digital signal processor (DSP).
  • DSP digital signal processor
  • the control unit 300 may communicate with the FPGA 202 or the operation unit 250 through McBSP.
  • the control unit 300 may increase or decrease the voltage of the power supply unit 110 by using a predetermined algorithm.
  • the output of the RF power source 101 may be measured through the sensing unit 140 according to the voltage change of the power source unit 110.
  • the intermediate clock generator 270 may output the intermediate clock MCLK.
  • the frequency f M of the intermediate clock MCLK may be twice the frequency of the driving frequency f rf .
  • the signal processor 201 may include a frequency multiplier 264 and a frequency reducer 262.
  • the frequency multiplier 264 may receive the intermediate clock MCLK and increase the frequency by an integer multiple to generate a sampling clock SCLK having the sampling frequency fs.
  • the frequency multiplier 262 may double the frequency of the intermediate clock MCLK.
  • the frequency reduction unit 262 may generate the driving clock DCLK having the driving frequency frf by receiving the intermediate clock MCLK and decreasing the frequency by an integer multiple.
  • the sampling clock SCLK and the driving clock DCLK may be synchronized.
  • the sampling clock SCLK may be provided to the calculator 250, the filter 240, and the modulator 230, and the driving clock DCLK may be provided to the amplifier 120.
  • the operation unit 250, the filter unit 240, and the modulation unit 230 may operate as the sampling clock SCLK when the pipeline is operated.
  • the driving clock DCLK may be provided to the RF power supply 101 so that an output signal of the RF power supply 101 may be operated at the driving frequency frf.
  • the frequency reducer 262 and the frequency multiplier 264 may be implemented by a field programmable gate array (FPGA).
  • FIG. 3 is a flowchart illustrating an RF signal processing method according to an embodiment of the present invention.
  • the RF signal processing method generates a voltage signal V (t) and a current signal I (t) by measuring an output voltage and a current of an RF power source driven at a driving frequency f rf . It includes a step (S100).
  • the voltage signal V (t) and the current signal I (t) may be generated by a detector.
  • a sampling voltage signals (V (n)) and a sampling current signals (I (n)) is synchronized to the drive frequency (f rf), the drive frequency (f rf) the sampling frequency (f s) an integral multiple of the voltage
  • the signal V (t) and the current signal I (t) are sampled and generated (S200).
  • the sampling frequency f s may be four times the driving frequency f rf .
  • the sampling voltage signal V (n) and the sampling current signal I (n) may be generated by an analog-to-digital converter in synchronization with a sampling clock SCLK having the sampling frequency.
  • the operation signal CAL may be generated by calculating the sampling voltage signal V (n) and the sampling current signal I (n) through a pipeline (S300).
  • the operation signal CAL is provided for each clock of the sampling frequency.
  • the generating of the operation signal (S300) may be performed by calculating a sine wave and a cosine wave having the converted sampling frequency ⁇ s defined as a product of a driving angular frequency and a sampling period of the sampling voltage signal and the sampling current signal. And generating a modulated current signal (S310).
  • Generating the operation signal (CAL) (S300) is the in-phase voltage signal (Va), a phase voltage signal (Vb), a phase current signal (Ia), which is a DC component of the modulation voltage signal and the modulation current signal And (S320) extracting the phase current signal Ib.
  • the operation signal CAL may be obtained by multiplying a product of an in-phase voltage signal Va, a phase-phase voltage signal Vb, an in-phase current signal Ia, and a phase-phase current signal Ib.
  • Obtaining may include a step (S332).
  • the providing of the operation signal (S330) may include calculating the magnitude (Vm) of the voltage signal, the magnitude (Im) of the current signal, and the phase difference ( ⁇ ) between the voltage signal and the current signal (S334). It may include.
  • the providing of the operation signal CAL may include impedance Z, forward power P fwd , reflected power P rev , power consumption P load , reflection coefficient ⁇ , and voltage sine wave ratio SWR. It may include the step of calculating at least one of (S336).
  • the step S500 may include generating the intermediate clock MCLK, the sampling clock SCLK, and the driving clock DCLK.
  • the sampling clock SLCK may be generated by receiving the intermediate clock MCLK and increasing the frequency by an integer multiple.
  • the driving clock DCLK may be generated by receiving the intermediate clock MCLK and decreasing the frequency by an integer multiple.
  • the sampling clock SCLK provides timing for generating the sampling and the operation signal CAL, and the driving clock DCLK may be provided to an RF power source.
  • the arithmetic signal CAL may be provided to further arithmetic to generate a warning signal ALM.
  • the impedance or reflection coefficient of the output terminal of the RF power source may be converted into the impedance or reflection coefficient of the front end of the adder.
  • the impedance or reflection coefficient of the front end of the adder may generate the warning signal ALM by additional calculation.
  • the warning signal ALM may be generated when the amplifier is opened or shorted.
  • the warning signal ALM may be generated using a reflection coefficient that exceeds a threshold.
  • the warning signal ALM may be provided to the RF power supply to shut down the RF power supply.
  • the control signal CTRL may be a signal for controlling forward power of the amplifier.
  • 4 to 12 are diagrams illustrating signals of an RF signal processing apparatus according to an embodiment of the present invention.
  • the voltage signal and the current signal at the output terminal of the RF power source may be signed.
  • the voltage signal V (t) may have a driving frequency f rf
  • the voltage signal V (t) may have a voltage phase ⁇ V.
  • the current signal I (t) may have the driving frequency f rf
  • the current signal I (t) may have a current phase ⁇ I.
  • the driving frequency f rf may be 13.56 Mhz.
  • the voltage signal V (t) may be sampled at a sampling frequency to form a sampling voltage signal V (n).
  • the current signal I (t) may be sampled at a sampling frequency to form a sampling current signal I (n).
  • the sampling frequency fs may be 54.24 Mhz, which is four times the driving frequency f rf .
  • the sampling frequency fs and the driving frequency f rf may be synchronized with each other.
  • sinusoidal waves sin ( ⁇ s n) and cosine waves cos ( ⁇ s n) may be expressed as converted sampling frequencies.
  • the sine wave may include (0,1,0, -1).
  • the cosine wave may include (1.0, -1,0).
  • the modulation voltage signal V (n) sin ( ⁇ s n), V (n) cos ( ⁇ s n), and the modulation current signal I (n) sin ( ⁇ s n). ), I (n) cos ( ⁇ s n)) can be generated through a digital mixer.
  • the sampling frequency is four times the driving frequency, the generation of the modulation voltage signal and the generation of the modulation current signal may be simple to calculate. Accordingly, the calculation speed can be increased.
  • an in-phase voltage signal Va, a phase-phase voltage signal Vb, an in-phase current signal Ia, and a phase-phase current signal Ib may be generated through a filter.
  • the filter may be an M-first order FIR filter having M coefficients.
  • the filter may include an infinite impulse response (IIR) filter.
  • IIR infinite impulse response
  • the filter can average 16 consecutive data. When an abnormal condition occurs, the abnormal condition may continue for several periods of the driving frequency.
  • the filter may detect perturbation of the current signal and the voltage signal caused by the abnormal situation.
  • an amplitude Vm of the voltage signal and an amplitude Im of the current signal may be calculated.
  • the phase ⁇ V of the voltage signal and the phase ⁇ I of the current signal may be calculated.
  • the operation signal CAL may include an amplitude Vm of the voltage signal, an amplitude Im of the current signal, a phase ⁇ V of the voltage signal, and a phase ⁇ I of the current signal.
  • the operation signal CAL includes an impedance Z, a forward power P fwd , a reflected power P rev , a power consumption P load , a reflection coefficient ⁇ , and a voltage sine wave ratio SWR. can do.
  • the operation signal CAL is performed by an operation unit and is calculated for each sampling clock, and thus can be output at a high speed.
  • the operation signal CAL may be generated to generate a warning signal
  • the warning signal may be input to an RF power source to control the RF power source.
  • the operation signal CAL may be input to a controller to generate a control signal.
  • the control signal may control the RF power supply.
  • FIG. 13 is a diagram illustrating clocks of an RF signal processing apparatus according to an embodiment of the present invention.
  • the operation cycle of the signal processing may use 9 clocks of the sampling clock SCLK.
  • arithmetic signal CAL is output.
  • the frequency of the sampling clock SCLK is twice the frequency of the intermediate clock MCLK.
  • the frequency of the intermediate clock MCLK is twice the frequency of the driving clock DCLK.
  • the calculation cycle is not limited to nine clocks.
  • FIG. 14 is a diagram illustrating an RF signal processing apparatus according to another embodiment of the present invention. Descriptions overlapping with those described in FIG. 2 will be omitted.
  • the RF signal processing apparatus may receive an external clock ECLK.
  • the external clock ECLK may be provided to the RF power supply 101 and the frequency multipliers 264a and 264b.
  • the frequency multipliers 264a and 264b may include a first frequency multiplier 264a and a second frequency multiplier 264b.
  • the first frequency multiplier 264a may double the frequency of the external clock ECLK to provide the intermediate clock MCLK.
  • the second frequency multiplier 264b may receive the intermediate clock MCLK and double the frequency to provide a sampling clock SCLK.
  • the external clock ECLK may be used when a plurality of RF power supplies are used in parallel.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)
  • Plasma Technology (AREA)

Abstract

L'invention concerne un dispositif de traitement de signal RF et un procédé de traitement de signal RF. Le dispositif de traitement de signal RF comprend : une unité de détection pour générer un signal de tension et un signal de courant par la mesure d'un courant et d'une tension de sortie d'une puissance RF régulée par une fréquence de régulation (frf) ; une unité d'échantillonnage pour générer un signal de courant par l'utilisation d'une fréquence d'échantillonnage (fs), qui est synchronisée avec la fréquence de régulation (frf) et est faite d'un multiple d'un nombre entier de la fréquence de régulation (frf), un signal de courant d'échantillonnage, et un signal de tension d'échantillonnage, par l'échantillonnage du signal de courant ; et une unité de traitement de signal pour le traitement du signal de courant d'échantillonnage et le signal de tension d'échantillonnage grâce à un pipeline. L'unité de traitement de signal fournit un signal d'opération à chaque horloge d'une fréquence d'échantillonnage.
PCT/KR2011/001954 2011-03-22 2011-03-22 Dispositif de traitement d'un signal de radiofréquence et procédé de traitement d'un signal de radiofréquence WO2012128401A1 (fr)

Priority Applications (1)

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PCT/KR2011/001954 WO2012128401A1 (fr) 2011-03-22 2011-03-22 Dispositif de traitement d'un signal de radiofréquence et procédé de traitement d'un signal de radiofréquence

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PCT/KR2011/001954 WO2012128401A1 (fr) 2011-03-22 2011-03-22 Dispositif de traitement d'un signal de radiofréquence et procédé de traitement d'un signal de radiofréquence

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WO2012128401A1 true WO2012128401A1 (fr) 2012-09-27

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104348508A (zh) * 2013-08-02 2015-02-11 活点信息技术有限公司 基于电流调制的通讯电路

Citations (4)

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Publication number Priority date Publication date Assignee Title
KR100450765B1 (ko) * 2002-10-11 2004-10-02 한국전자통신연구원 무선통신매체 및 그 동작방법
US20040248537A1 (en) * 2001-08-10 2004-12-09 Emil Zellweger Radio-frequency signal frequency conversion device for a low power rf receiver
US20060262889A1 (en) * 2005-05-19 2006-11-23 Mks Instruments, Inc. Synchronous undersampling for high-frequency voltage and current measurements
KR20110043874A (ko) * 2009-10-22 2011-04-28 주식회사 플라즈마트 라디오 주파수 신호 처리 장치 및 라디오 주파수 신호 처리 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040248537A1 (en) * 2001-08-10 2004-12-09 Emil Zellweger Radio-frequency signal frequency conversion device for a low power rf receiver
KR100450765B1 (ko) * 2002-10-11 2004-10-02 한국전자통신연구원 무선통신매체 및 그 동작방법
US20060262889A1 (en) * 2005-05-19 2006-11-23 Mks Instruments, Inc. Synchronous undersampling for high-frequency voltage and current measurements
KR20110043874A (ko) * 2009-10-22 2011-04-28 주식회사 플라즈마트 라디오 주파수 신호 처리 장치 및 라디오 주파수 신호 처리 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104348508A (zh) * 2013-08-02 2015-02-11 活点信息技术有限公司 基于电流调制的通讯电路

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