WO2012127934A1 - Dispositif de commande et dispositif d'affichage - Google Patents

Dispositif de commande et dispositif d'affichage Download PDF

Info

Publication number
WO2012127934A1
WO2012127934A1 PCT/JP2012/053337 JP2012053337W WO2012127934A1 WO 2012127934 A1 WO2012127934 A1 WO 2012127934A1 JP 2012053337 W JP2012053337 W JP 2012053337W WO 2012127934 A1 WO2012127934 A1 WO 2012127934A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
power supply
terminal
input
buffer unit
Prior art date
Application number
PCT/JP2012/053337
Other languages
English (en)
Japanese (ja)
Inventor
理史 橋本
正彦 中溝
下敷領　文一
卓哉 渡邉
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Publication of WO2012127934A1 publication Critical patent/WO2012127934A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing

Definitions

  • the present invention relates to a display device used in an electronic device typified by a word processor, a personal computer, a television device or the like.
  • the present invention relates to an active matrix liquid crystal display device.
  • liquid crystal display devices having excellent features such as high definition, thinness, light weight, and low power consumption have become widespread.
  • improvements on various issues are being studied, one of which is the viewing angle dependence of ⁇ characteristics (the relationship between pixel gradation data and display brightness; the same shall apply hereinafter).
  • the problem is that the ⁇ characteristic when the liquid crystal display device is observed in the front direction is different from the ⁇ characteristic when observed in the oblique direction.
  • the display brightness at the time of front direction observation is appropriate, the display brightness at the time of oblique direction observation is higher than that at the time of front direction observation, so that it appears whitish (floats), It becomes prominent when displaying TV broadcasts.
  • Patent Document 1 proposes a technique called “multi-picture element driving”.
  • this multi-picture element drive one picture element is composed of a plurality of sub-picture elements whose display brightness can be varied, so that the display brightness during oblique viewing is changed to the display brightness during front viewing. It is close.
  • the display brightness of a plurality of sub-picture elements constituting one picture element is made different, and the average display brightness of the plurality of picture elements is targeted (at the time of front observation). ) Display brightness.
  • FIG. 11 is a graph showing the ⁇ characteristic of the liquid crystal display device.
  • the horizontal axis represents pixel gradation data (voltage applied to the pixel, 256 gradations from 0 to 255 in this example) X
  • the vertical axis represents the luminance ratio (gradation data).
  • the ⁇ characteristic at the time of front direction observation in the liquid crystal display device that does not perform the multi-picture element driving is indicated by a solid line
  • the ⁇ characteristic at the time of oblique direction observation in the liquid crystal display device is indicated by a broken line.
  • the ⁇ characteristic at the time of oblique observation in the liquid crystal display device that performs multi-picture element driving is indicated by a one-dot chain line.
  • the display luminance during oblique direction observation is larger than the display luminance during front direction observation (whitening occurs).
  • the difference becomes larger as the display luminance is in the middle tone away from the vicinity of the dark luminance (the gradation data X is near the minimum value 0) and the bright luminance (the gradation data X is near the maximum value 255) (white).
  • the float becomes noticeable).
  • the display luminance at the time of oblique direction observation is close to the display luminance at the time of front direction observation.
  • FIG. 12 is a circuit diagram showing a configuration example of one picture element of a display device that performs multi-picture element driving.
  • one picture element PE of the display device that performs multi-picture element driving is composed of a plurality of sub-picture elements SPE1 and SPE2.
  • the sub-picture element SPE1 includes a liquid crystal capacitor LS1 and an auxiliary capacitor CCS1, and a drain electrode of a TFT (Thin Film Transistor) t1 is connected to one end of the liquid crystal capacitor LS1 and one end of the auxiliary capacitor CCS1.
  • a counter electrode COM is connected to the other end of the liquid crystal capacitor LS1, and a counter electrode voltage (hereinafter referred to as a common voltage) can be applied.
  • TFT Thin Film Transistor
  • an auxiliary capacitance line CSL1 is connected to the other end of the auxiliary capacitance CCS1, and an auxiliary capacitance driving voltage (hereinafter referred to as CS voltage) can be applied.
  • the sub-pixel SPE2 includes a liquid crystal capacitor LS2 and an auxiliary capacitor CCS2, and the drain electrode of the TFT t2 is connected to one end of the liquid crystal capacitor LS2 and one end of the auxiliary capacitor CCS2. Further, the counter electrode COM is connected to the other end of the liquid crystal capacitor LS2, and a common voltage can be applied.
  • an auxiliary capacitance line CSL2 is connected to the other end of the auxiliary capacitance CCS2, and a CS voltage can be applied.
  • the gate electrodes of TFTs t1 and t2 are connected to a common (same) scanning line GL, and the source electrodes of TFTs t1 and t2 are connected to a common (same) signal line SL.
  • a common (same) scanning line GL and the source electrodes of TFTs t1 and t2 are connected to a common (same) signal line SL.
  • a plurality of picture elements PE are arranged in a row direction and a column direction (in a matrix).
  • the same scanning line GL can be connected to the TFTs t1 and t2 of the picture elements PE arranged in the same row, and the same scanning line voltage can be applied.
  • the same signal line SL can be connected to the TFTs t1 and t2 of the picture elements PE arranged in the same column, and the same signal line voltage can be applied.
  • the same counter electrode COM is connected to the liquid crystal capacitors LS1 and LS2 of all the picture elements PE, and the same common voltage can be applied.
  • auxiliary capacitance lines CSL1 and CSL2 are connected to the auxiliary capacitances CCS1 and CCS2 included in one picture element PE, and different CS voltages can be applied.
  • the same auxiliary capacity line CSL1 is connected to the auxiliary capacity CCS1 of each sub-picture element SPE1
  • the same auxiliary capacity CCS2 is assigned to the auxiliary capacity CCS2 of each sub-picture element SPE2.
  • a capacitor line CSL2 is connected.
  • FIG. 13 is a graph showing an example of the waveform of the signal line voltage and the CS voltage applied to each sub-picture element shown in FIG.
  • the upper graph in the figure shows an example of the waveform of the signal line voltage and the CS voltage applied to the sub-picture element SPE1 in FIG. 12, and the lower graph in the figure shows the sub-picture element SPE2 in FIG.
  • the example of the waveform of the applied signal line voltage and CS voltage is shown.
  • shaft of the graph shown in FIG. 12 has shown the voltage value, and the horizontal axis has shown time.
  • the example shown in FIG. 13 is for AC (Alternating Current) driving in which the polarity of the voltage applied to the liquid crystal is inverted every predetermined period.
  • AC Alternating Current
  • the same signal line voltage and the same scanning line voltage are applied to the TFTs t1 and t2. Therefore, as shown in FIG. 13, the signal line voltages applied to the sub-picture elements SPE1 and SPE2 via the TFTs t1 and t2 are the same. However, the CS voltages applied to the auxiliary capacitors CCS1 and CCS2 via the auxiliary capacitor lines CSL1 and CSL2 can be different. Therefore, as shown in FIG. 13, the voltage Va applied to the sub-picture element SPE1 may be different from the voltage Vb applied to the sub-picture element SPE2. As a result, the display luminances of the sub-picture elements SPE1 and SPE2 can be made different.
  • the CS voltage applied to the sub-picture element SPE1 and the CS voltage applied to the sub-picture element SPE2 have the same amplitude and frequency but have a phase difference of 180 degrees.
  • the desired voltages Va and Vb are applied to the sub picture elements SPE1 and SPE2 by inverting the CS voltage applied to each of the sub picture elements SPE1 and SPE2 in synchronization with the inversion of the signal line voltage.
  • a horizontal scanning period (a period in which a voltage is applied to one line of picture elements PE) is shortened, and the number of auxiliary capacitors CCS1 and CCS2 is increased.
  • the waveform of the CS voltage may become dull from the intended waveform.
  • the degree of the waveform dullness varies depending on the arrangement location of the picture element PE.
  • the effective voltage applied to the sub-picture elements SPE1 and SPE2 varies depending on the arrangement location of the picture elements PE, so that uneven display luminance can occur.
  • Patent Document 2 proposes a method for reducing the above-described display luminance unevenness by making the reversal of the CS voltage longer than one horizontal scanning period. This method will be described with reference to the drawings.
  • FIG. 14 is a graph showing an example of a waveform of a CS voltage that reduces unevenness in display luminance.
  • FIG. 15 is a circuit diagram showing a configuration example of a liquid crystal display device to which the CS voltage shown in FIG. 14 is applied.
  • FIG. 16 is a circuit diagram showing an arrangement example of each part of the liquid crystal display device shown in FIG.
  • shaft of the graph shown in FIG. 14 shows a voltage value, and the horizontal axis has shown time.
  • FIG. 14 illustrates a case where each CS voltage is inverted every two horizontal scanning periods (that is, four horizontal scanning periods are set as one cycle).
  • the CS voltage CSVX1 and the CS voltage CSVX2, and the CS voltage CSVX3 and the CS voltage CSVX4 are different in phase from each other by two horizontal scanning periods (180 degrees).
  • the CS voltage CSVX1 and the CS voltage CSVX3, and the CS voltage CSVX2 and the CS voltage CSVX4 are different in phase by one horizontal scanning period (90 degrees).
  • the CS voltages CSVX1 to CSVX4 are arranged in each row via the auxiliary capacity main line CSLX and the auxiliary capacity lines CSL1 and CSL2 drawn from the auxiliary capacity main line CSLX. Applied to the sub-picture elements SPE1 and SPE2 constituting the picture element PE.
  • the CS voltage CSVX1 and the CS voltage CSVX2 are applied to the sub-picture elements SPE1 and SPE2 provided in the picture element PE arranged in a certain row, the sub-picture element SPE1 provided in the picture element PE adjacent to the picture element PE.
  • SPE2 are applied with CS voltage CSVX3 and CS voltage CSVX4.
  • a CS voltage CSVX1 is applied to one of the auxiliary capacity trunk lines CSLX
  • a CS voltage CSVX2 is applied to one of the auxiliary capacity trunk lines CSLX
  • a CS voltage CSVX3 is applied to one of the auxiliary capacity trunk lines CSLX.
  • the CS voltage CSVX4 is applied to one of the auxiliary capacity trunk lines CSLX.
  • the auxiliary capacitance lines CSL1 and CSL2 extend in the row direction in order to apply the same CS voltage to the sub-picture elements SPE1 and SPE2 provided in the picture elements PE arranged in the same row.
  • the auxiliary capacity trunk line CSLX is arranged to be orthogonal to the auxiliary capacity lines CSL1 and CSL2 (extend in the column direction) so that the auxiliary capacity lines CSL1 and CSL2 can be easily drawn out. Further, the auxiliary capacity trunk line CSLX is arranged at both ends of the auxiliary capacity lines CSL1 and CSL2, respectively.
  • the liquid crystal display device 100 (particularly, a liquid crystal display panel) includes a gate driver 110, a source driver 120, and a glass substrate 130.
  • a gate driver to which a gate driver control signal for controlling the picture element PE, the scanning line GL, the auxiliary capacity trunk line CSLX, the auxiliary capacity lines CSL1 and CSL2, the signal line SL, and the gate driver 110 is applied to the glass substrate 130.
  • Each of the control signal lines CGL is formed.
  • gate driver control signals and CS voltages CSVX1 to CSVX4 generated by a controller are applied to the gate driver control signal line CGL and the auxiliary capacity trunk line CSLX.
  • the gate driver 110 includes a scanning line voltage generation unit 111 that generates a scanning line voltage and applies the scanning line voltage to the scanning line GL based on a gate driver control signal input via the gate driver control signal line CGL.
  • the source driver 120 includes a signal line voltage generation unit 121 that generates a signal line voltage based on an input source driver control signal (for example, generated by a controller (not shown)) and applies the signal line voltage to the signal line SL.
  • a plurality of gate drivers 110 may be provided along the column direction. As shown in FIG. 16, when a plurality of gate drivers 110 are provided in one liquid crystal display device 100, adjacent gate drivers 110 are connected, and a gate driver control signal is transmitted from the preceding gate driver 110 to the succeeding gate driver 110. Are transmitted sequentially.
  • the auxiliary capacity trunk line CSLX needs to be formed on the glass substrate 130, but the wiring on the glass substrate 130 has a large wiring resistance. In this case, from the viewpoint of suppressing unevenness in display brightness of the picture element PE, it is necessary to increase the respective line widths of the auxiliary capacity trunk line CSLX to reduce the impedance. Then, since the area occupied by the auxiliary capacity trunk line CSLX becomes larger on the glass substrate 130, the frame portion of the glass substrate 130 (the peripheral portion excluding the portion where the picture element PE is arranged; the same applies hereinafter) is narrowed. Becomes difficult.
  • the CS voltage is taken into the gate driver, and the waveform of the CS voltage is shaped by a buffer unit provided in the gate driver (for example, auxiliary capacitance such as waveform blunting and noise reduction is reduced).
  • a buffer unit provided in the gate driver
  • auxiliary capacitance such as waveform blunting and noise reduction is reduced.
  • a configuration for applying the sub-pixel to each sub-capacitor line after each of the auxiliary capacitance lines has been proposed. According to this configuration, it is not necessary to extend the auxiliary capacity main line along the column direction as shown in FIG. 16, and each can be divided. Therefore, since the line width can be reduced by suppressing the wiring resistance of the auxiliary capacity trunk line, the frame portion can be narrowed.
  • FIG. 17 is a block diagram schematically showing a configuration example of a main part of a liquid crystal display device that applies a CS voltage to an auxiliary capacitance line using a buffer unit.
  • FIG. 18 is a graph showing respective states of the CS voltage input and output by the buffer unit shown in FIG. 17 and the power supply voltage of the buffer unit.
  • the buffer unit BF is supplied with a voltage VCSH, which is a high-voltage power supply voltage, and a voltage VCSL, which is a low-voltage power supply voltage, from a predetermined power supply (for example, the above-described controller). .
  • a resistor RL shown between the buffer unit BF and the respective voltages VCSH and VCSL in the drawing is a wiring resistance between the power supply and the buffer unit BF.
  • four CS voltages CSVY1a to CSVY4a having different phases are input to the four input terminals IN1 to IN4 of the buffer unit BF, and each of the four output terminals OUT1 to OUT4 of the buffer unit BF is the buffer unit.
  • the CS voltages CSVY1b to CSVY4b whose waveforms are shaped by BF are output.
  • Each of these CS voltages CSVY1b to CSVY4b corresponds to the auxiliary capacitor CCS (which corresponds to the above-described auxiliary capacitor lines CSL1 and CSL2, and is referred to in this way unless otherwise distinguished. The same applies hereinafter).
  • the auxiliary capacitors CCS1 and CCS2 are referred to as above when they are not particularly distinguished.
  • the resistor RCSL shown in each of the storage capacitor lines CSL in the drawing is a wiring resistance of the storage capacitor line CSL.
  • FIG. 18 is a graph showing the waveforms of the CS voltages CSVY1a to CSVY4a input to the input terminals IN1 to IN4.
  • the CS voltage CSVY1a is indicated by a thick solid line
  • the other CS voltages CSVY2a to CSVY4a are indicated by thin broken lines.
  • the lower graph in FIG. 18 shows the state of the CS voltage CSVY1b output from the output terminal OUT1 with a thick solid line when the CS voltages CSVY1a to CSVY4a shown in the upper graph are input to the input terminals IN1 to IN4 of the buffer unit BF.
  • the states of the voltages VCSH and VCSL supplied to the buffer unit BF are indicated by broken lines.
  • shaft of the graph shown in FIG. 18 shows a voltage value
  • the horizontal axis has shown time.
  • the CS voltage CSVY1b when the CS voltage CSVY1a tries to rise, the CS voltage CSVY1b also rises accordingly.
  • the voltage VCSH supplied to the buffer unit BF becomes unstable (decreases), and the CS voltage CSVY1b has an intended voltage value (for example, VCSH). It may happen that it does not stand up. This can also occur at the falling edge of the CS voltage CSVY1a. That is, the voltage VCSL supplied to the buffer unit BF may become unstable (rise), and the CS voltage CSVY1b may not fall to the intended voltage value (for example, VCSH).
  • the luminance of the sub-picture elements may not be intended, and problems such as uneven display luminance may occur.
  • the buffer unit BF consumes a large amount of current due to a large capacitive load of the auxiliary capacitor CCS and an increase in the wiring resistance RL as a result of reducing the line width for narrowing the frame. obtain.
  • the line width must be increased, and it becomes difficult to narrow the frame.
  • the present invention realizes a narrower frame of a display device and a drive device capable of accurately applying an intended voltage to an auxiliary capacitor, and a display device including the drive device.
  • the purpose is to provide.
  • the present invention is connected to one end of a different auxiliary capacitance line connected to an auxiliary capacitance provided in each of a plurality of sub-picture elements constituting one picture element, and the auxiliary capacitance line
  • a driving device capable of differentiating the display luminance of the sub-pixel by applying different auxiliary capacitance driving voltages to each of the sub-pixels, Using the supplied first voltage as a common power supply voltage, shaping the waveform of each of the auxiliary capacitance driving voltages, and applying the buffer portion to each of the auxiliary capacitance lines;
  • a stabilized power supply unit that supplies the first voltage to the buffer unit, Provided is a driving device in which the stabilized power supply unit generates the first voltage by using a second voltage that is equal to or higher than the first voltage and a third voltage that is equal to or lower than the first voltage as a power supply voltage.
  • a fourth voltage that is a voltage value to be supplied to the buffer unit is input to the stabilized power source unit.
  • the stabilized power supply unit generates the first voltage to be equal to the fourth voltage.
  • the stabilized power supply unit is configured such that the fourth voltage is input to a non-inverting input terminal, the second voltage and the third voltage are input to a power supply terminal, and an output terminal outputs the output voltage.
  • the first voltage is preferably an operational amplifier that is input to an inverting input terminal.
  • the stabilized power supply unit includes an input terminal to which the second voltage or the third voltage is input, an output terminal that outputs the first voltage, and a ground terminal that is grounded.
  • a three-terminal regulator having
  • the drive device having the above-described characteristics includes a plurality of the stabilized power supply units for supplying the one first voltage to the buffer unit.
  • the buffer unit may perform waveform shaping in which the auxiliary capacitor driving voltage before waveform shaping is input to a non-inverting input terminal, the first voltage is input to a power supply terminal, and an output terminal outputs. It is preferable that the later storage capacitor driving voltage is composed of an operational amplifier inputted to the inverting input terminal.
  • the drive device having the above characteristics includes the two stabilized power supply units,
  • the first voltage supplied by one of the stabilized power supply units is a power supply voltage on the high voltage side of the buffer unit, It is preferable that the first voltage supplied by the other stabilized power supply unit is a low-voltage power supply voltage of the buffer unit.
  • the present invention is connected to one end of a different auxiliary capacitance line connected to an auxiliary capacitance provided in each of a plurality of sub-picture elements constituting one picture element, and different auxiliary capacitance lines are connected to the auxiliary capacitance lines.
  • a driving device capable of varying the display luminance of the sub-picture element by applying a capacitive driving voltage, Using the supplied first voltage as a common power supply voltage, and shaping the waveform of each of the auxiliary capacitance drive voltages, and including a buffer unit that applies to each of the auxiliary capacitance lines,
  • the buffer unit the auxiliary capacitance driving voltage before waveform shaping is input to the non-inverting input terminal, the supplied power supply voltage is input to the power supply terminal, and the auxiliary capacitance driving voltage after waveform shaping output from the output terminal is Provided is a driving device including an operational amplifier input to an inverting input terminal.
  • the driving device having each feature described above is connected in common to the plurality of sub-pixels that constitute each of the pixels arranged along the auxiliary capacitance line among the pixels arranged in a matrix, and the auxiliary devices
  • the present invention also provides a display device comprising at least one drive device having the above characteristics.
  • the power supply voltage of the buffer unit can be stabilized. Therefore, it is possible for the buffer unit to apply the auxiliary capacitance driving voltage having the expected voltage value to the auxiliary capacitance line without increasing the wiring for supplying the power supply voltage of the buffer unit. Therefore, it is possible to realize a narrow frame of the display device and to accurately apply an intended voltage to the auxiliary capacitor.
  • the block diagram shown about the schematic structural example of the gate driver which concerns on embodiment of this invention 1 is a circuit diagram showing a configuration example of the buffer unit in FIG.
  • the circuit diagram which shows an example of the arrangement method and connection method of the gate driver which concern on embodiment of this invention Block diagram showing the first example of the stabilized power supply unit
  • FIG. 12 is a graph showing an example of the waveform of the signal line voltage and the CS voltage applied to each sub-picture element shown in FIG.
  • Graph showing waveform example of CS voltage to reduce unevenness of display brightness 14 is a circuit diagram showing a configuration example of a liquid crystal display device to which the CS voltage shown in FIG. 14 is applied.
  • the circuit diagram which shows the example of arrangement
  • the block diagram which showed typically the example of a principal part structure of the liquid crystal display device which applies CS voltage to an auxiliary capacity line using a buffer part
  • the graph which showed each state of CS voltage which the buffer part shown in FIG. 17 inputs and outputs, and the power supply voltage of the said buffer part
  • a gate driver that applies a voltage to the auxiliary capacitance line and the scanning line is exemplified as the driving device according to the embodiment of the present invention. It may be a drive device that applies a voltage only to the.
  • the gate driver described below drives the picture element PE shown in FIG. 12 (performs multi-picture element driving).
  • FIG. 1 is a block diagram showing a schematic configuration of a gate driver according to an embodiment of the present invention.
  • the gate driver 1 includes control logics 11A and 11B, a bidirectional shift register 12, a level shifter 13, an output circuit 14, buffer units 21A and 21B, and various terminals (white coating in the figure). A portion indicated by a circle). Although details will be described later, the terminals of the same name can be connected by wiring in the gate driver 1.
  • FIG. 1 shows the terminals arranged at positions that may be different from actual positions.
  • the terminal LBR is an input terminal to which a control signal indicating the shift direction of the bidirectional shift register 12 is input. For example, a signal that can take two states of H (high) and L (low) is input to the terminal LBR.
  • the control logics 11A and 11B control the shift direction of the bidirectional shift register 12 so as to correspond to the state of the control signal.
  • the scanning direction of the picture element PE is determined by the shift direction of the bidirectional shift register 12.
  • Each of the terminal GSPOI and the terminal GSPIO is an IO (Input / Output) terminal capable of switching between an input terminal and an output terminal.
  • the control logics 11A and 11B perform the switching according to the state of the control signal input to the terminal LBR. Specifically, for example, when the state of the control signal input to the terminal LBR is H, the control logics 11A and 11B use the terminal GSPOI as an input terminal and the terminal GSPIO as an output terminal. For example, when the state of the control signal input to the terminal LBR is L, the control logics 11A and 11B use the terminal GSPOI as an output terminal and the terminal GSPIO as an input terminal.
  • a signal for starting the operation of the bidirectional shift register 12 (hereinafter referred to as a scanning start signal) is input to a terminal serving as an input terminal among the terminals GSPOI and GSPIO. Further, when a plurality of gate drivers are used in cascade connection, if there is a subsequent gate driver, the terminal serving as an output terminal among the terminals GSPOI and GSPIO outputs the scanning start signal to the subsequent gate driver. (See FIG. 4 described later).
  • the terminal GCKOI and the terminal GCKIO are IO terminals that can be switched between the input terminal and the output terminal.
  • the control logics 11A and 11B perform the switching according to the state of the control signal input to the terminal LBR. Specifically, for example, when the state of the control signal input to the terminal LBR is H, the control logics 11A and 11B use the terminal GCKOI as an input terminal and the terminal GCKIO as an output terminal. For example, when the state of the control signal input to the terminal LBR is L, the control logics 11A and 11B use the terminal GCKOI as an output terminal and the terminal GCKIO as an input terminal.
  • a driving clock signal of the bidirectional shift register 12 is input to a terminal serving as an input terminal among the terminals GCKOI and the terminal GCKIO.
  • the terminal GCKOI and the terminal GCKIO which is an output terminal, outputs the drive clock signal to the subsequent gate driver. (See FIG. 4 described later).
  • the terminal VGL and the terminal VGH are terminals to which a power supply voltage for operating the output circuit 14 is supplied.
  • the output circuit 14 generates a scanning line voltage and outputs it to each of terminals OG1 to OG272 described later. If the voltage value of the voltage supplied to the terminal VGL is vgl and the voltage value of the voltage supplied to the terminal VGH is vgh, the scanning line voltage can be a voltage having an amplitude from the voltage value vgl to the voltage value vgh, for example.
  • the terminal VCC is a terminal to which a power supply voltage for operating the entire gate driver 1 is supplied.
  • the terminal GND is a ground terminal and supplies the ground voltage to the entire gate driver 1.
  • Scan lines are connected to the 272 terminals OG1 to OG272 from the outside of the gate driver 1, respectively.
  • Terminals OG1 to OG272 are terminals that apply the scanning line voltage generated by the output circuit 14 to the connected scanning lines, respectively.
  • Each of the terminals CSVA1a to CSVA4a and the terminals CSVB1a to CSVB4a is a terminal to which a CS voltage input to the buffer units 21A and 21B is supplied.
  • Each of the terminals CSVA1b to CSVA4b and the terminals CSVB1b to CSVB4b is a terminal for applying the CS voltage shaped by the buffer units 21A and 21B to the auxiliary capacitance line CSL.
  • the terminal CSVA1a and the terminal CSVB1a, the terminal CSVA2a and the terminal CSVB2a, the terminal CSVA3a and the terminal CSVB3a, the terminal CSVA4a and the terminal CSVB4a are respectively connected. Therefore, for example, the CS voltage input from one of the terminals CSVA1a to CSVA4a and the terminals CSVB1a to CSVB4a can be output from the other and can be input to each of the buffer units 21A and 21B.
  • the buffer units 21A and 21B reshape the waveform of the input CS voltage, and the reshaped CS voltage is output from the terminals CSVA1b to CSVA4b and the terminals CSVB1b to CSVB4b and applied to the auxiliary capacitance line CSL. Then, the auxiliary capacitor CCS is driven.
  • the terminal VCSH and the terminal VCSL are terminals to which the voltage VCSH and the voltage VCSL, which are the respective power supply voltages of the buffer units 21A and 21B, are supplied.
  • the voltage VCSH is the power supply voltage on the high voltage side of the buffer units 21A and 21B
  • the voltage VCSL is the power supply voltage on the low voltage side of the buffer units 21A and 21B.
  • the gate driver 1 further includes a stabilized power supply unit in order to stabilize the voltage VCSH and the voltage VCSL which are the power supply voltages of the buffer unit 21. Details of the stabilized power supply unit will be described later with reference to the drawings.
  • the scan start signal generated based on the vertical synchronization signal is input from the terminal GSPOI, and the bidirectional shift register 12 is synchronized with the drive clock signal generated based on the horizontal synchronization signal input from the terminal GCKOI. (For example, every horizontal scanning period), the shift operation is started.
  • the first pulse signal that is a pulse signal is generated by this shift operation.
  • the first pulse signal is converted by the level shifter 13 into a scanning line voltage having an amplitude of the voltage vgh from the voltage vgl, and is output from the output circuit 14 to the terminal OG1.
  • the bidirectional shift register 12 generates a second pulse signal that is a pulse signal different from the first pulse signal by the above-described shift operation.
  • This second pulse signal is converted by the level shifter 13 into a scanning line voltage having an amplitude of the voltage value vgh from the voltage value vgl, and is output from the output circuit 14 to the terminal OG2.
  • the bidirectional shift register 12 sequentially generates the nth pulse signal by the above shift operation
  • the level shifter 13 sequentially converts the nth pulse signal from the voltage value vgl to the scanning line voltage having the amplitude of the voltage value vgh.
  • the output circuit 14 sequentially outputs the scanning line voltage via the terminal OGn (n is a natural number). Therefore, in this example, the scanning direction of the scanning line voltage output from the output circuit 14, that is, the order of the scanning lines to which the scanning line voltage is applied is connected to the scanning line connected to the terminal OG1 and the terminal OG2. Scan lines,..., Scan lines connected to the terminal OG272.
  • the gate driver 1 When the above shift operation is completed (when the scanning line voltage is output to the terminal OG272), the gate driver 1 outputs a scanning start signal from the terminal GSPIO to the subsequent gate driver 1 and is driven from the terminal GCKIO. Outputs a clock signal. As a result, the subsequent gate driver performs the same operation as that of the gate driver 1, and sequentially applies the scanning line voltage to the connected scanning lines.
  • FIG. 2 is a circuit diagram illustrating a configuration example of a buffer circuit included in the buffer unit of FIG.
  • the buffer circuit 210 includes an input terminal IN, two inverters 211 and 212, and an output terminal OUT. Further, the input terminal IN, the inverter 211, the inverter 212, and the output terminal OUT are connected in series in this order. Note that a plurality of buffer circuits 210 may be provided in the buffer unit 21.
  • the CS voltages CSVA1a to CSVA4a or the CS voltages CSVB1a to CSVB4a input to the gate driver 1 from the terminals CSVA1a to CSVA4a or the terminals CSVB1a to CSVB4a are input to the input terminal IN.
  • an input terminal IN is connected to terminals CSVA1a and CSVB1a
  • an input terminal IN is connected to terminals CSVA2a and CSVB2a
  • an input terminal IN is connected to terminals CSVA3a and CSVB3a
  • an input terminal IN is connected to terminals CSVA4a and CSVA4a.
  • the inverter 211 includes a p-channel MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) 211P to which the voltage VCSH is applied to the source, and an n-channel MOSFET 211N to which the voltage VCSL is applied to the source.
  • the CS voltage input to the input terminal IN is input to the gates of the MOSFET 211P and the MOSFET 211N. Also, the respective drains of the MOSFET 211P and the MOSFET 211N are connected, and the voltage at this connection node is output to the inverter 212 at the subsequent stage.
  • MOSFET Metal Oxide Semiconductor Field-Effect Transistor
  • the inverter 212 includes a p-channel MOSFET 212P to which the voltage VCSH is applied to the source and an n-channel MOSFET 212N to which the voltage VCSL is applied to the source.
  • the voltage output from the inverter 211 is input to the respective gates of the MOSFET 212P and the MOSFET 212N. Further, the respective drains of the MOSFET 212P and the MOSFET 212N are connected, and the voltage of this connection node is output to the output terminal OUT at the subsequent stage.
  • the output terminal OUT outputs the CS voltage whose waveform is shaped to the terminals CSVA1b to CSVA4b or the terminals CSVB1b to CSVB4b.
  • a certain output terminal OUT is connected to the terminal CSVA1b
  • a certain output terminal OUT is connected to the terminal CSVA2b
  • a certain output terminal OUT is connected to the terminal CSVA3b
  • a certain output The terminal OUT is connected to the terminal CSVA4b.
  • a certain output terminal OUT is connected to the terminal CSVB1b
  • a certain output terminal OUT is connected to the terminal CSVB2b
  • a certain output terminal OUT is connected to the terminal CSVB3b
  • a certain output terminal. OUT is connected to the terminal CSVB4b.
  • FIG. 3 is a diagram illustrating an example of terminal arrangement and internal wiring of the gate driver according to the embodiment of the present invention.
  • a part related to the CS voltage mainly wiring
  • a part related to cascade connection of the gate driver 1 mainly wiring
  • the gate driver 1 includes a tape portion 31 where various wirings are formed, an integrated circuit portion 32 including at least buffer portions 21A and 21B, and a terminal portion 33 where the above-described various terminals are disposed. .
  • terminals OG1 to OG272 are arranged in this order. From the terminal OG1 toward one end of the gate driver 1, the terminals CSVA4b to CSVA1b, the terminal GCKOI, the terminal GSPOI, the terminal VCSL, the terminal VCSH, the terminal VCC, the terminal LBR, the terminal GND, the terminal VGH, the terminal VGL, and the terminal CSVA4a to The CSVA 1a is arranged in this order.
  • terminals CSVB1b to CSVB4b are arranged in this order.
  • this arrangement example is merely an example, and the arrangement of arbitrary terminals may be changed as appropriate.
  • the gate driver 1 is connected as shown in FIG. 4 to be described later, the first stage gate driver 1 and the rear stage gate driver 1 (in the first stage gate driver 1, a device for outputting a signal or voltage from a controller or the like instead of the previous stage gate driver. It is preferable to arrange a terminal that can be connected to the end of the gate driver 1.
  • terminals of the same name are connected by wiring in the gate driver 1.
  • terminal GPKOI and the terminal GCKIO, and the terminal GPPOI and the terminal GCOPIO are also connected by wiring in the gate driver 1, respectively. Note that this wiring is a direct connection or an indirect connection between terminals (for example, when a signal or voltage is transmitted between the terminals while some processing is performed on the signal or voltage). ).
  • Terminals CSVA1a to CSVA4a are connected to terminals CSVB1a to CSVB4a, respectively.
  • the terminals CSVA1a to CSVA4a and the terminals CSVB1a to CSVB4a are indirectly connected to the terminals CSVA1b to CSVA4b and the terminals CSVB1b to CSVB4b via the buffers 21A and 21B.
  • FIG. 3 and FIG. 4 to be described later a part of the wiring through which the CS voltage in the gate driver 1 passes is shown as a single thick line for convenience of illustration.
  • FIG. 4 is a circuit diagram illustrating an example of a gate driver arrangement method and connection method according to an embodiment of the present invention. 4 shows the first stage gate driver 1F and the subsequent stage gate driver 1S, it is possible to connect three or more gate drivers in the same manner.
  • Each picture element PE shown in FIG. 4 has the same configuration as the picture element PE shown in FIG. 12, and includes a plurality of sub-picture elements SPE1 and SPE2.
  • the liquid crystal display device 40 (particularly a liquid crystal display panel) includes a plurality of cascade-connected gate drivers 1F and 1S, a source driver 40, a controller 50, and a glass substrate 60.
  • a source driver 40 On the glass substrate 60, each of the picture element PE, the scanning line GL, the signal line SL, the auxiliary capacity trunk line CSLA, the auxiliary capacity lines CSL1 and CSL2, and the control line CL that connects the controller 50 and the first stage gate driver 1 is provided. It is formed.
  • the source driver 40 includes a signal line voltage generation unit 41 that generates a signal line voltage and applies the signal line voltage to the signal line SL.
  • a part of the control line CL is collectively shown as one thick line for convenience of illustration.
  • the controller 50 inputs the CS voltages CSVA1a to CSVA4a to the terminals CSVA1a to CSVA4a of the gate driver 1F via the control line CL. Similarly, the controller 50 inputs the above-described various voltages to the terminal VCSL, terminal VCSH, terminal VCC, terminal LBR, terminal GND, terminal VGH, and terminal VGL of the gate driver 1F via the control line CL. However, the same voltage as the voltage supplied to the terminal VCC is input to the terminal LBR of the gate driver 1F.
  • the controller 50 when the state of the voltage input to the terminal LBR of the gate driver 1F is H (when each of the terminal GSPOI and the terminal GCKOI of the gate driver 1F is an input terminal as in the above example), the controller 50 The scan start signal and the drive clock signal are input to the terminal GSPOI and the terminal GCKOI of the gate driver 1F via the control line CL, respectively.
  • the gate drivers 1F and 1S are arranged so that the end portion where the terminals CSVB1a to CSVB4a of the gate driver 1F are arranged and the end portion where the terminals CSVA1a to CSVA4a of the gate driver 1S are arranged are close to each other.
  • the terminals CSVA1a to CSVA4a near the end, the terminal VCSL, the terminal VCSH, the terminal VCC, the terminal LBR, the terminal GND, the terminal VGH, and the terminal VGL are connected to each other with the same name by wiring formed on the glass substrate 60. Is done.
  • terminal GCKIO and the terminal GSPIO of the gate driver 1F and the terminal GCKOI and the terminal GSPOI of the gate driver 1S are also connected by wirings formed on the glass substrate 60, respectively.
  • the signal and voltage input by the controller 50 to the gate driver 1F can be transmitted to the gate driver 1S subsequent to the gate driver 1F.
  • the terminals OG1 to OG272 of the gate drivers 1F and 1S apply the scanning line voltage to the scanning lines GL connected to the respective picture elements PE.
  • the signal line voltage generation unit 41 of the source driver 40 generates a signal line voltage based on, for example, a source driver control signal input from the controller 50 and applies it to the signal line SL. Thereby, each picture element PE is driven and a display operation is performed.
  • the waveforms of the CS voltages CSVA1a to CSVA4a input from the controller 50 to the gate driver 1F as described above are shaped by the buffer units 21A and 21B in the integrated circuit 32, and the terminals CSVA1b to CSVA4b and the terminals CSVB1b to CSVB4b respectively. Is output from.
  • the CS voltage output from each of the terminals CSVA1b to CSVA4b and the terminals CSVB1b to CSVB4b is applied to the auxiliary capacity main line CSLA connected to the terminals, and further, the auxiliary capacity lines CSL1 and CSL2 connected to the auxiliary capacity main line CSLA.
  • the subsequent gate driver 1S also drives the auxiliary capacitors CCS1 and CCS2 in the same manner as the gate driver 1F, except that the CS voltages CSVA1a to CSVA4a are input from the gate driver 1F.
  • the auxiliary capacity trunk line CSLA can be divided according to the number of buffers 21A and 21B included in the gate drivers 1F and 1S. Therefore, unlike the auxiliary capacity main line CSLX shown in FIGS. 15 and 16, the auxiliary capacity main line CSLA can be divided and shortened. Accordingly, since the wiring resistance of the auxiliary capacity main line CSLA is reduced, it is possible to reduce the line width of the auxiliary capacity main line CSLA (to narrow the frame). In addition, since it is related to the size of the buffer units 21A and 21B, it cannot be generally stated. However, in the case where the liquid crystal display device 40 shown in FIG. 4 includes four gate drivers, eight auxiliary capacity trunk lines CSLA are provided. Can be divided. Therefore, as compared with the conventional liquid crystal display device 100 as shown in FIG. 16, it is possible to make the auxiliary capacitor main line narrow to about 1/8 (to narrow the frame).
  • the buffer units 21A and 21B in the gate driver (that is, providing the buffer units 21A and 21B in a distributed manner throughout the liquid crystal display device 40), it is possible to suitably drive the auxiliary capacitor. Therefore, when the line width is narrowed without dividing the auxiliary capacity trunk line, it may be possible to suppress unevenness in display luminance and the like.
  • FIG. 5 is a block diagram illustrating a first example of the stabilized power supply unit.
  • regulators 711 and 712 are provided as stabilized power supply units.
  • the regulator 711 supplies a voltage VCSH which is a power supply voltage on the high voltage side of the buffer unit 21, and the regulator 712 supplies a voltage VCSL which is a power supply voltage on the low voltage side of the buffer unit 21.
  • the voltage VCSH supplied via the terminal VCSH of the gate driver 1 described above is input to the regulator 711.
  • the regulator 711 is supplied with a voltage AVCH, which is a high-voltage side power supply voltage, and a voltage AVCL, which is a low-voltage power supply voltage, from a predetermined power supply (for example, the controller 50 described above).
  • the voltage VCSL supplied through the terminal VCSL of the gate driver 1 described above is input to the regulator 712.
  • the regulator 712 is supplied with a voltage AVCH, which is a high-voltage side power supply voltage, and a voltage AVCL, which is a low-voltage power supply voltage, from a predetermined power supply (for example, the controller 50 described above).
  • the voltage AVCH is equal to or higher than the voltage VCSH
  • the voltage AVCL is equal to or lower than the voltage VCSL.
  • a resistor RL shown between the regulators 711 and 712 and the respective voltages AVCH and AVCL in the figure is a wiring resistance between the power supply and the regulators 711 and 712.
  • the regulators 711 and 712 use the voltage AVCH and the voltage AVCL as power supply voltages to suppress fluctuations in the voltages VCSH and VCSL supplied to the buffer unit 21 (in other words, the voltages VCSH and VCSL supplied to the buffer unit 21 are , So as to be equal to the input voltages VCSH and VCSL).
  • FIG. 6 is a graph showing the states of the CS voltage output from the buffer unit shown in FIG. 5, the power supply voltage of the buffer unit, and the power supply voltage of the regulator.
  • the CS voltage CSVA1b is illustrated as the CS voltage output from the buffer unit 21, and the state of the voltage is indicated by a thick solid line.
  • the power supply voltage state of the regulators 711 and 712 is indicated by a broken line, and the power supply voltage state of the buffer unit 21 is indicated by a one-dot chain line.
  • shaft of the graph shown in FIG. 6 shows the voltage value, and the horizontal axis has shown time.
  • the regulator 711 uses the voltage AVCH equal to or higher than the voltage VCSH to be supplied to the buffer unit 21 and the voltage AVCL equal to or lower than the voltage VCSH to be supplied to the buffer unit 21 as the power supply voltage, the buffer unit 21. Even when another CS voltage having a different phase is input and a large amount of current is consumed due to the influence of the wiring resistance RL, the capacitive load of the auxiliary capacitor CCS, or the like, the voltage AVCH is suppressed from becoming smaller than the voltage VCSH. Therefore, the regulator 711 can stably supply the voltage VCSH to the buffer unit 21.
  • the regulator 712 uses a voltage AVCH equal to or higher than the voltage VCSL to be supplied to the buffer unit 21 and a voltage AVCL equal to or lower than the voltage VCSL to be supplied to the buffer unit 21 as a power supply voltage, Even if another CS voltage having a different phase is input to the unit 21 and a large amount of current is consumed due to the influence of the wiring resistance RL or the capacitive load of the auxiliary capacitor CCS, the voltage AVCL is suppressed from becoming larger than the voltage VCSL. The Therefore, the regulator 712 can stably supply the voltage VCSL to the buffer unit 21.
  • FIG. 7 is a block diagram illustrating a second example of the stabilized power supply unit.
  • operational amplifiers 721 and 722 are provided as stabilized power supply units.
  • the operational amplifier 721 supplies a voltage VCSH which is a power supply voltage on the high voltage side of the buffer unit 21, and the operational amplifier 722 supplies a voltage VCSL which is a power supply voltage on the low voltage side of the buffer unit 21.
  • the voltage VCSH supplied via the terminal VCSH of the gate driver 1 described above is input to the non-inverting input terminal of the operational amplifier 721.
  • the power terminal of the operational amplifier 721 is supplied with a voltage AVCH, which is a high-voltage side power supply voltage, and a voltage AVCL, which is a low-voltage power supply voltage, from a predetermined power supply (for example, the controller 50 described above).
  • the voltage VCSH output from the output terminal of the operational amplifier 721 is input to the inverting input terminal of the operational amplifier 721.
  • a voltage VCSL supplied via the terminal VCSL of the gate driver 1 described above is input to the non-inverting input terminal of the operational amplifier 722.
  • the power terminal of the operational amplifier 722 is supplied with a voltage AVCH, which is a high-voltage power supply voltage, and a voltage AVCL, which is a low-voltage power voltage, from a predetermined power supply (for example, the controller 50 described above).
  • the voltage VCSL output from the output terminal of the operational amplifier 722 is input to the inverting input terminal of the operational amplifier 722.
  • the voltage AVCH is equal to or higher than the voltage VCSH
  • the voltage AVCL is equal to or lower than the voltage VCSL.
  • a resistor RL shown between the operational amplifiers 721 and 722 and the respective voltages AVCH and AVCL in the figure is a wiring resistance between the power supply and the operational amplifiers 721 and 722.
  • the operational amplifiers 721 and 722 in this example also use the voltage AVCH and the voltage AVCL as power supply voltages to suppress fluctuations in the voltages VCSH and VCSL supplied to the buffer unit 21 (in other words, Then, the voltages VCSH and VCSL supplied to the buffer unit 21 are made equal to the input voltages VCSH and VCSL).
  • the operational amplifier 721 uses the voltage AVCH that is higher than or equal to the voltage VCSH to be supplied to the buffer unit 21 and the voltage AVCL that is lower than or equal to the voltage VCSH that is to be supplied to the buffer unit 21 as power supply voltages, Even if a voltage is input and a large amount of current is consumed due to the influence of the wiring resistance RL, the capacitive load of the auxiliary capacitor CCS, or the like, the influence of the fluctuation of the voltage AVCH can be suppressed and the voltage VCSH can be output. Therefore, the operational amplifier 721 can stably supply the voltage VCSH to the buffer unit 21.
  • the buffer unit 21 has a different phase. Even if a large current is consumed due to the influence of the wiring resistance RL, the capacitive load of the auxiliary capacitor CCS, and the like, the influence of the fluctuation of the voltage AVCL can be suppressed and the voltage VCSL can be output. Therefore, the operational amplifier 722 can stably supply the voltage VCSL to the buffer unit 21.
  • FIG. 8 is a block diagram illustrating a third example of the stabilized power supply unit.
  • three-terminal regulators 731 and 732 are provided as stabilized power supply units.
  • the three-terminal regulator 731 supplies a voltage VCSH that is a high-voltage side power supply voltage of the buffer unit 21, and the three-terminal regulator 732 supplies a voltage VCSL that is a low-voltage side power supply voltage of the buffer unit 21. is there.
  • the input terminal of the three-terminal regulator 731 receives a voltage AVCH, which is a high-voltage power supply voltage, from a predetermined power source (for example, the controller 50 described above).
  • AVCH a high-voltage power supply voltage
  • the ground terminal of the three-terminal regulator 731 is grounded.
  • a voltage AVCL which is a low-voltage power supply voltage
  • AVCL a voltage AVCL
  • the ground terminal of the three-terminal regulator 732 is grounded.
  • the voltage AVCH is equal to or higher than the voltage VCSH
  • the voltage AVCL is equal to or lower than the voltage VCSL.
  • a resistor RL shown between the three-terminal regulators 731 and 732 and the respective voltages AVCH and AVCL in the figure is a wiring resistance between the power supply and the three-terminal regulators 731 and 732.
  • the three-terminal regulators 731 and 732 in this example absorb the fluctuation within the range up to the supplied voltage AVCH or voltage AVCL when the voltages VCSH and VCSL supplied to the buffer unit 21 are about to fluctuate. is there.
  • the three-terminal regulator 731 When the voltage AVCH equal to or higher than the voltage VCSH to be supplied to the buffer unit 21 is supplied to the three-terminal regulator 731, another CS voltage having a different phase is input to the buffer unit 21, and the wiring resistance RL and the auxiliary capacitor CCS Even if a large amount of current is consumed due to the influence of a capacitive load or the like, the voltage AVCH is suppressed from becoming smaller than the voltage VCSH. Therefore, the three-terminal regulator 731 can stably supply the voltage VCSH to the buffer unit 21.
  • the three-terminal regulator 732 When the voltage AVCL equal to or lower than the voltage VCSL to be supplied to the buffer unit 21 is supplied to the three-terminal regulator 732, another CS voltage having a different phase is input to the buffer unit 21, and the wiring resistance RL or the auxiliary capacitance Even if a large amount of current is consumed due to the influence of the capacitive load of the CCS, the voltage AVCL is suppressed from becoming larger than the voltage VCSL. Therefore, the three-terminal regulator 732 can stably supply the voltage VCSL to the buffer unit 21.
  • FIG. 9 is a block diagram showing a fourth example of the stabilized power supply unit.
  • operational amplifiers 7411, 7412, 7421, and 7422 are provided as stabilized power supply units.
  • the operational amplifiers 7411 and 7412 supply the voltage VCSH that is the power supply voltage on the high voltage side of the buffer unit 21, and the operational amplifiers 7421 and 7422 supply both the voltage VCSL that is the power supply voltage on the low voltage side of the buffer unit 21. Is.
  • the voltage VCSH supplied via the terminal VCSH of the gate driver 1 described above is input to the non-inverting input terminals of the operational amplifiers 7411 and 7412, respectively.
  • a voltage AVCH that is a high-voltage side power supply voltage and a voltage AVCL that is a low-voltage power supply voltage are respectively supplied from a predetermined power supply (for example, the above-described controller 50) to the power supply terminals of the operational amplifiers 7411 and 7412. Is done.
  • the voltage VCSH output from the output terminal of the operational amplifier 7411 is input to the inverting input terminal of the operational amplifier 7411, and the voltage VCSH output from the output terminal of the operational amplifier 7412 is input to the inverting input terminal of the operational amplifier 7412.
  • the voltage VCSL supplied via the terminal VCSL of the gate driver 1 described above is input to the non-inverting input terminals of the operational amplifiers 7421 and 7422, respectively.
  • a voltage AVCH which is a high-voltage side power supply voltage
  • a voltage AVCL which is a low-voltage side power supply voltage
  • the voltage VCSL output from the output terminal of the operational amplifier 7421 is input to the inverting input terminal of the operational amplifier 7421, and the voltage VCSL output from the output terminal of the operational amplifier 7422 is input to the inverting input terminal of the operational amplifier 7422.
  • the voltage AVCH is equal to or higher than the voltage VCSH
  • the voltage AVCL is equal to or lower than the voltage VCSL.
  • a resistor RL shown between the operational amplifiers 7411, 7412, 7421, 7422 and the respective voltages AVCH, AVCL in the figure is a wiring resistance between the power supply and the operational amplifiers 7411, 7412, 7421, 7422.
  • the voltage supplied is more than that provided with only one stabilized power supply unit. It becomes possible to stabilize VCSH.
  • the plurality of stabilized power supply units (operational amplifiers 7421 and 7422) supply the voltage VCSL to the buffer unit 21, the voltage VCSL to be supplied is more than that provided with only one stabilized power supply unit. It becomes possible to stabilize.
  • the power supply voltage of the buffer unit 21 can be stabilized by providing the gate driver 1 with the stabilized power supply unit. Therefore, it is possible for the buffer unit 21 to apply the CS voltage having the expected voltage value to the auxiliary capacitance line CSL without increasing the wiring for supplying the power supply voltage of the buffer unit 21. Therefore, it is possible to realize a narrow frame of the liquid crystal display device 40 and to accurately apply an intended voltage to the auxiliary capacitor CCS.
  • the voltages AVCH and AVCL used as the power supply voltage by the stabilized power supply unit in each of the above examples may be supplied from the controller 50 to the gate driver 1 in the same manner as the voltages VCSH and VCSL described above. Further, in this case, similarly to the voltages VCSH and VCSL, the gate driver 1 may include terminals corresponding to the voltages AVCH and AVCL, and wiring and connections similar to those of the terminals VCSH and VCSL may be made inside and outside the gate driver 1. (See FIG. 4).
  • [2] A configuration in which the stabilized power supply unit that supplies the power supply voltage on the high voltage side of the buffer unit 21 and the stabilized power supply unit that supplies the power supply voltage on the low voltage side uses the same voltage AVCH and AVCL as the power supply voltage is illustrated. However, at least one voltage may be different. However, the configuration of the gate driver 1 and the liquid crystal display device 40 can be simplified by using the same voltage.
  • FIG. 1 the configuration in which the two buffer units 21A and 21B are provided in one gate driver 1, 1F, and 1S is illustrated, but the configuration in which one buffer unit 21 is provided. Alternatively, a configuration including three or more may be used.
  • FIG. 2 The configuration shown in FIG. 2 is exemplified as the configuration of the buffer unit 21, but other configurations may be used. Another configuration example of the buffer unit 21 will be described with reference to FIG.
  • FIG. 10 is a block diagram illustrating another configuration example of the buffer unit.
  • the buffer unit 210a of this example includes an operational amplifier 211a.
  • the input terminal IN of the buffer unit 210a is connected to the non-inverting input terminal of the operational amplifier 211a.
  • the voltage VCSH and the voltage VCSL supplied as the power supply voltage of the buffer unit 210a are supplied to the power supply terminal of the operational amplifier 211a, respectively.
  • the CS voltage output from the output terminal of the operational amplifier 211a is input to the inverting input terminal of the operational amplifier 211a.
  • the output terminal OUT of the buffer unit 210a is connected to the output terminal of the operational amplifier 211a.
  • the buffer unit 210a By using the operational amplifier 211a as the buffer unit 210a, it is possible to suppress the influence of fluctuations in the voltage VCSH and the voltage VCSL, which are power supply voltages, and to output a stable CS voltage. Therefore, the buffer unit 210a can apply the CS voltage having the expected voltage value to the auxiliary capacitance line CSL without increasing the wiring for supplying the power supply voltage of the buffer unit 210a. Therefore, it is possible to realize a narrow frame of the liquid crystal display device 40 and to accurately apply an intended voltage to the auxiliary capacitor CCS.
  • the buffer unit 210a of this modification can stably output the CS voltage without applying the stabilized power supply unit of each example described above.
  • the configuration including the stabilized power supply unit of each example described above is preferable because the buffer unit 210a can output a more stable CS voltage.
  • the present invention can be applied to a driving device that drives an auxiliary capacitor provided in a display device such as a liquid crystal display device.
  • a driving device that drives an auxiliary capacitor provided in a display device such as a liquid crystal display device.
  • a gate driver that drives a scanning line of a display device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)

Abstract

L'invention concerne un dispositif de commande permettant de restreindre le cadre d'un dispositif d'affichage et d'appliquer avec précision une tension prévue à un condensateur auxiliaire, et concerne également un dispositif d'affichage équipé dudit dispositif de commande. Le dispositif de commande comprend des unités d'alimentation stabilisée (régulateurs (711, 712)) permettant de fournir une tension d'alimentation à une unité de tampon (21). Les unités d'alimentation stabilisée génèrent des tensions (VCSH, VCSL) au moyen d'une tension (AVCH) supérieure ou égale aux tensions (VCSH, VCSL) et d'une tension (AVCL) inférieure ou égale aux tensions (VCSH, VCSL) en tant que tension d'alimentation et fournissent les tensions générées (VCSH, VCSL) à l'unité tampon (21). Cela permet à l'unité tampon (21) d'appliquer une tension de commande de condensateur auxiliaire ayant une valeur de tension attendue à une ligne de condensateur auxiliaire sans épaissir le câblage permettant de fournir la tension d'alimentation à l'unité tampon (21).
PCT/JP2012/053337 2011-03-23 2012-02-14 Dispositif de commande et dispositif d'affichage WO2012127934A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011063520A JP5250072B2 (ja) 2011-03-23 2011-03-23 駆動装置及び表示装置
JP2011-063520 2011-03-23

Publications (1)

Publication Number Publication Date
WO2012127934A1 true WO2012127934A1 (fr) 2012-09-27

Family

ID=46879098

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/053337 WO2012127934A1 (fr) 2011-03-23 2012-02-14 Dispositif de commande et dispositif d'affichage

Country Status (3)

Country Link
JP (1) JP5250072B2 (fr)
TW (1) TW201246172A (fr)
WO (1) WO2012127934A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03230116A (ja) * 1990-02-05 1991-10-14 Seiko Instr Inc 液晶駆動用高電圧バイアス回路
JP2001282164A (ja) * 2000-03-31 2001-10-12 Sanyo Electric Co Ltd 表示装置用駆動装置
JP2004078216A (ja) * 2002-08-20 2004-03-11 Samsung Electronics Co Ltd 液晶表示装置を低電力で駆動する回路及びその方法
JP2004157580A (ja) * 2002-11-01 2004-06-03 Matsushita Electric Ind Co Ltd 電源回路、半導体集積回路装置及び液晶表示装置
JP2009128533A (ja) * 2007-11-21 2009-06-11 Sharp Corp 表示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02246422A (ja) * 1989-03-18 1990-10-02 Fujitsu Ltd 位相同期ループ回路
JP3568615B2 (ja) * 1994-07-08 2004-09-22 富士通ディスプレイテクノロジーズ株式会社 液晶駆動装置，その制御方法及び液晶表示装置
JP2006189593A (ja) * 2005-01-06 2006-07-20 Brother Ind Ltd 液晶表示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03230116A (ja) * 1990-02-05 1991-10-14 Seiko Instr Inc 液晶駆動用高電圧バイアス回路
JP2001282164A (ja) * 2000-03-31 2001-10-12 Sanyo Electric Co Ltd 表示装置用駆動装置
JP2004078216A (ja) * 2002-08-20 2004-03-11 Samsung Electronics Co Ltd 液晶表示装置を低電力で駆動する回路及びその方法
JP2004157580A (ja) * 2002-11-01 2004-06-03 Matsushita Electric Ind Co Ltd 電源回路、半導体集積回路装置及び液晶表示装置
JP2009128533A (ja) * 2007-11-21 2009-06-11 Sharp Corp 表示装置

Also Published As

Publication number Publication date
JP5250072B2 (ja) 2013-07-31
JP2012198440A (ja) 2012-10-18
TW201246172A (en) 2012-11-16

Similar Documents

Publication Publication Date Title
US8810491B2 (en) Liquid crystal display with color washout improvement and method of driving same
EP1863010A1 (fr) Affichage à cristaux liquides et procédé de commande correspondant
JP5426167B2 (ja) 表示装置
WO2010073775A1 (fr) Dispositif d'affichage et procédé de gestion de dispositif d'affichage
US10269319B2 (en) Display device and driving method thereof
JP5889421B2 (ja) 表示装置およびその駆動方法
WO2016155157A1 (fr) Panneau d'affichage et son procédé de pilotage, et dispositif d'affichage à cristaux liquides
WO2010087051A1 (fr) Dispositif d'affichage et procédé de commande de dispositif d'affichage
KR20130084811A (ko) 표시 패널 및 이의 구동 방법
JP2007025644A (ja) 液晶ディスプレイパネルの駆動方法及び該駆動方法を用いた液晶ディスプレイパネル並びに該液晶ディスプレイパネルの駆動に用いる駆動モジュール
WO2012132630A1 (fr) Dispositif d'affichage à cristaux liquides
JP5117633B2 (ja) 液晶表示装置
KR20080001052A (ko) 액정표시장치 및 그의 구동방법
US9111503B2 (en) Display device and method for driving same
JP4478710B2 (ja) 表示装置
WO2012093630A1 (fr) Dispositif d'affichage à cristaux liquides
JP2010039205A (ja) 液晶表示装置
TWI757813B (zh) 抑制顯示面板閃爍之驅動方法及其驅動電路
JP5250072B2 (ja) 駆動装置及び表示装置
KR101996339B1 (ko) 표시 패널 및 이의 구동 방법
WO2009128281A1 (fr) Circuit de pilotage d'un appareil d'affichage à cristaux liquides
TW201333610A (zh) 顯示裝置及其驅動方法
JP2008145886A (ja) 液晶表示装置、およびその駆動方法、並びに駆動回路
US8878832B2 (en) Pixel circuit, display device, and method for driving display device
KR20120050113A (ko) 액정 표시 장치 및 그 구동 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12761262

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12761262

Country of ref document: EP

Kind code of ref document: A1