WO2012124309A1 - Liquid crystal display device and electronic apparatus - Google Patents

Liquid crystal display device and electronic apparatus Download PDF

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Publication number
WO2012124309A1
WO2012124309A1 PCT/JP2012/001700 JP2012001700W WO2012124309A1 WO 2012124309 A1 WO2012124309 A1 WO 2012124309A1 JP 2012001700 W JP2012001700 W JP 2012001700W WO 2012124309 A1 WO2012124309 A1 WO 2012124309A1
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Prior art keywords
electrode
liquid crystal
crystal display
gate
display device
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PCT/JP2012/001700
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French (fr)
Japanese (ja)
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泰 高丸
耕平 田中
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シャープ株式会社
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Publication of WO2012124309A1 publication Critical patent/WO2012124309A1/en

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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00Materials and properties
    • G02F2202/10Materials and properties semiconductor
    • G02F2202/103Materials and properties semiconductor a-Si
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3614Control of polarity reversal in general
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3648Control of matrices with row and column drivers using an active matrix
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41733Source or drain electrodes for field effect devices for thin film transistors with insulated gate

Definitions

  • the present invention relates to a liquid crystal display device and an electronic apparatus including the same.
  • liquid crystal display devices are widely used as display devices.
  • the 1H line inversion driving method is a driving method in which the polarity of all source signals is inverted every 1H period (one horizontal scanning period).
  • this driving method the polarity of all signal lines becomes positive when scanning a certain scanning line, and the polarity of all signal lines is inverted and becomes negative when scanning the next scanning line.
  • each pixel is alternately arranged with a row in which a positive signal is written in one horizontal row and a row in which a negative signal is written in one horizontal row. It becomes.
  • the 1H dot inversion driving method is a driving method in which the polarities of the signal lines are alternately inverted.
  • this driving method when a certain scanning line is scanned, the polarity of a certain signal line becomes positive, and the polarity of the adjacent signal line becomes negative.
  • the next scanning line is scanned, the polarity of the signal line is inverted and becomes negative, and the polarity of the adjacent signal line becomes positive.
  • the AC drive type liquid crystal display device displays a flicker pattern on the screen for the purpose of suppressing flicker, and generates a signal voltage and a common electrode voltage.
  • Initial adjustment is known. For example, a display state such as pseudo halftone frame inversion driving is displayed on a flicker pattern display screen in which one polarity pixel is displayed in black (or white display) and the other polarity pixel is displayed in halftone. In this state, the voltage applied to the common electrode is adjusted so that the flicker is minimized.
  • FIG. 21 is a plan view showing a TFT (thin film transistor) 100 used in a conventional liquid crystal display device
  • the TFT 100 has a U-shaped source electrode 102 having a pair of electrode limbs 101 formed in a bifurcated shape.
  • the drain electrode 103 disposed between the pair of electrode limbs 101, and the semiconductor layer 104 and the gate electrode 105 overlapping with the source electrode 102 and the drain electrode 103, thereby reducing the W length of the channel region 106. It is known to ensure a large amount (see Patent Documents 5 and 6, etc.).
  • TFTs used in liquid crystal display devices are usually formed of a-Si (amorphous silicon).
  • a photocurrent is generated, and an off-leakage current is generated.
  • the present inventors have made an AC drive for inverting the polarity of a signal voltage applied to a source electrode in a liquid crystal display device having a TFT having a source electrode shape different from that of a drain electrode, such as the TFT having the U-shaped source electrode.
  • a drain electrode such as the TFT having the U-shaped source electrode.
  • the present invention has been made in view of such a point, and the object of the present invention is to significantly reduce flicker while AC driving a liquid crystal display device having a TFT whose source electrode shape is different from that of the drain electrode. It is in trying to suppress.
  • a liquid crystal display device includes a plurality of source lines, a plurality of gate lines crossing the source lines, a plurality of pixels provided in a matrix, A thin film transistor provided in each of a plurality of pixels and connected to the source wiring and the gate wiring, a pixel electrode provided in each of the plurality of pixels and connected to a drain electrode of the thin film transistor, and at least one of the gate wirings
  • An AC drive control unit that reverses the polarity of the signal voltage applied to the plurality of source wirings for each scanning period is provided.
  • a pixel column composed of the plurality of pixels arranged along the gate wiring includes a plurality of first pixels in which the first thin film transistor is formed and a plurality of second pixels in which the second thin film transistor is formed. Yes.
  • flicker can be significantly suppressed while AC driving a liquid crystal display device having a TFT whose source electrode shape is different from that of the drain electrode.
  • FIG. 1 is an enlarged plan view showing a part of the TFT substrate according to the first embodiment.
  • FIG. 2 is an enlarged plan view showing the first TFT and the second TFT.
  • FIG. 3 is a plan view schematically showing a flicker pattern.
  • FIG. 4 is a cross-sectional view showing a schematic configuration of the TFT.
  • FIG. 5 is a plan view schematically showing a TFT having a first electrode and a second electrode smaller than the first electrode.
  • FIG. 6 is a graph showing the results of Example 1.
  • FIG. 7 is a graph showing the results of Example 2.
  • FIG. 8 is a graph showing off-leakage currents in Examples 1 and 2.
  • FIG. 9 is a cross-sectional view illustrating a schematic structure of a liquid crystal display device provided in the electronic apparatus according to the first embodiment.
  • FIG. 10 is a plan view showing 1H line inversion driving of the liquid crystal display device according to the first embodiment.
  • FIG. 11 is a plan view showing 1H line inversion driving of a liquid crystal display device as a comparative example.
  • FIG. 12 is a graph showing a simulation result with respect to temporal change in luminance in the comparative example.
  • FIG. 13 is a graph illustrating a simulation result of a change in luminance with time in the example.
  • FIG. 14 is an enlarged plan view showing a part of the TFT substrate according to the second embodiment.
  • FIG. 10 is a plan view showing 1H line inversion driving of the liquid crystal display device according to the first embodiment.
  • FIG. 11 is a plan view showing 1H line inversion driving of a liquid crystal display device as a comparative example.
  • FIG. 12 is a graph showing a simulation result with respect
  • FIG. 15 is a plan view showing 1H dot inversion driving of the liquid crystal display device according to the second embodiment.
  • FIG. 16 is a plan view showing 1H dot inversion driving of a liquid crystal display device as a comparative example.
  • FIG. 17 is a plan view showing an enlarged part of the TFT substrate 13 in the third embodiment.
  • FIG. 18 is an enlarged plan view showing the first TFT and the second TFT in the third embodiment.
  • FIG. 19 is a plan view showing 1H line inversion driving of the liquid crystal display device 1 according to the third embodiment.
  • FIG. 20 is a plan view showing 1H line inversion driving of a liquid crystal display device as a comparative example.
  • FIG. 21 is a plan view showing a TFT used in a conventional liquid crystal display device.
  • Embodiment 1 of the Invention 1 to 13 show Embodiment 1 of the present invention.
  • FIG. 1 is a plan view showing an enlarged part of the TFT substrate according to the first embodiment.
  • FIG. 2 is an enlarged plan view showing the first TFT and the second TFT.
  • FIG. 9 is a cross-sectional view illustrating a schematic structure of a liquid crystal display device provided in the electronic apparatus according to the first embodiment.
  • the electronic device 10 in the first embodiment is, for example, a liquid crystal television.
  • the electronic device 10 may be a mobile device such as a smartphone or a mobile phone, or other electronic device.
  • the electronic device 10 includes a liquid crystal display device 1 as a display unit inside a housing 2.
  • the liquid crystal display device 1 includes a liquid crystal display panel 11 and a backlight unit 12 that is a light source disposed on the back side of the liquid crystal display panel 11. That is, the liquid crystal display device 1 is configured to perform transmissive display by selectively transmitting at least light from the backlight unit 12.
  • the liquid crystal display panel 11 includes a TFT substrate 13 that is a first substrate, and a counter substrate 14 that is a second substrate disposed to face the TFT substrate 13.
  • a liquid crystal layer 15 is sealed between the TFT substrate 13 and the counter substrate 14 by a seal member 16.
  • the liquid crystal display panel 11 has a display area (not shown) and a frame-like non-display area (not shown) provided around the display area.
  • a plurality of pixels 18 provided in a matrix are formed in the display area.
  • the pixel 18 is a minimum unit for controlling display.
  • the TFT substrate 13 is composed of an active matrix substrate.
  • the TFT substrate 13 has a glass substrate (not shown) as a transparent substrate.
  • a plurality of source lines 23 extending in parallel with each other and a plurality of gate lines 22 extending so as to intersect the source lines 23 are formed on the glass substrate.
  • the plurality of gate lines 22 and the plurality of source lines 23 are formed in a lattice shape as a whole, and the pixels 18 are formed in regions surrounded by the gate lines 22 and the source lines 23 in a rectangular shape.
  • Each of the gate wiring 22 and the source wiring 23 is configured by a single-layer film made of one type or a multi-layer film made of a plurality of types, for example, among Al, Cu, Mo, Ti, and the like.
  • Each pixel 18 is provided with a TFT (thin film transistor) 20 in the vicinity of the intersection of the gate wiring 22 and the source wiring 23.
  • the gate wiring 22 and the source wiring 23 are connected to the TFT 20.
  • the TFT 20 in the first embodiment is a bottom gate type TFT, and a gate electrode 26 branched from the gate wiring 22 and a semiconductor layer (not shown) facing the gate electrode 26 via a gate insulating film (not shown).
  • a source electrode 25 that is branched from the source wiring 23, and a drain electrode 29.
  • the gate electrode 26 and the gate wiring 22 are formed on a glass substrate and covered with the gate insulating film.
  • the gate insulating film is composed of, for example, a single-layer film made of one of SiNx (silicon nitride) and SiO 2 or a multi-layer film made of a plurality of kinds.
  • the semiconductor layer is formed in a rectangular island shape, for example.
  • the semiconductor layer is formed of a semiconductor such as a-Si, for example.
  • a part of the source electrode 25 and a part of the drain electrode 29 are overlapped with the semiconductor layer and the gate electrode 26, respectively.
  • the source electrode 25, the drain electrode 29, and the like are covered with an interlayer insulating film (not shown).
  • the interlayer insulating film is made of, for example, SiNx.
  • the plurality of pixels 18 are formed with pixel electrodes 30 connected to the drain electrodes 29 of the TFTs 20 provided in the pixels 18.
  • the pixel electrode 30 is formed on the surface of the interlayer insulating film, and is composed of a transparent conductive film such as ITO (Indium Tin Oxide).
  • a common electrode (not shown) provided in common with the plurality of pixel electrodes 30 is formed on the counter substrate 14. Similar to the pixel electrode 30, the common electrode is also formed of a transparent conductive film such as ITO. Thus, the orientation of the liquid crystal layer 15 is controlled for each pixel 18 by controlling the potential difference between the common electrode having a predetermined potential and the pixel electrode 30 of each pixel 18.
  • the TFT 20 in this embodiment includes a first TFT 20 a in which the source electrode 25 is larger than the drain electrode 29 and a second TFT 20 b in which the drain electrode 29 is larger than the source electrode 25.
  • the source electrode 25 of the first TFT 20 a includes a pair of electrode limbs 32 formed in a bifurcated shape, and a base end portion 33 formed wide on the base end side of the electrode limbs 32. have.
  • the drain electrode 29 of the first TFT 20 a has a linear portion 34 extending linearly, and the tip of the linear portion 34 is disposed between the pair of electrode limbs 32.
  • the entire electrode limb 32 of the source electrode 25 and a part of the base end portion 33 overlap the gate electrode 26.
  • the overlapping width A of the source electrode 25 and the gate electrode 26 at the base end portion 33 is wider than the overlapping width B of the drain electrode 29 and the gate electrode 26.
  • the drain electrode 29 of the second TFT 20b has a pair of electrode limbs 36 formed in a bifurcated shape and a base end portion 37 formed wide on the base end side of the electrode limbs 36.
  • the source electrode 25 of the second TFT 20 b has a linear portion 38 that extends linearly, and the tip of the linear portion 38 is disposed between the pair of electrode limbs 36.
  • the entire electrode limb 36 of the drain electrode 29 and a part of the base end portion 37 overlap the gate electrode 26.
  • the overlap width A between the source electrode 25 and the gate electrode 26 is narrower than the overlap width B between the drain electrode 29 and the gate electrode 26 at the base end portion 37.
  • ⁇ Pixel arrangement configuration> As shown in FIG. 1, a plurality of first pixels 18 a in which first TFTs 20 a are formed and a plurality of pixels in which second TFTs 20 b are formed are arranged in a pixel column 19 including a plurality of pixels 18 arranged along the gate wiring 22. The second pixel 18b is included.
  • each pixel column 19 one first pixel 18 a and one second pixel 18 b are alternately arranged along the gate wiring 22.
  • a plurality of first pixels 18a or a plurality of second pixels 18b are arranged side by side.
  • first pixel 18 a and the second pixel 18 b for example, in each pixel column 19, two first pixels 18 a and two second pixels 18 b are alternately arranged along the gate wiring 22. May be arranged. That is, at least one first pixel 18 a and the same number of second pixels 18 b as the at least one first pixel 18 a are alternately arranged along the gate wiring 22 in the pixel column 19. Also good.
  • the liquid crystal display device 1 further includes an AC drive control unit 40 that applies signal voltages having the same polarity to the plurality of source lines 23 during a period of scanning one gate line 22.
  • the AC drive control unit 40 is configured to invert the polarity of the signal voltage applied to the plurality of source lines 23 for each period of scanning one gate line 22. That is, the driving method of the liquid crystal display device 1 is a 1H line inversion driving method in which the polarity of the signal voltage is inverted every 1H period (one horizontal scanning period).
  • the AC drive control unit 40 may be configured to invert the polarity of the signal voltage every time the plurality of gate wirings 22 are scanned. That is, the AC drive control unit 40 may be configured to perform nH line inversion driving. Therefore, the AC drive control unit 40 can be configured to apply signal voltages having the same polarity to the plurality of source lines 23 in each of the periods in which at least one gate line 22 is scanned.
  • the liquid crystal display device 1 is a liquid crystal display panel in which a TFT substrate 13 manufactured by forming a plurality of TFTs 20 and the like and a counter substrate 14 formed with a common electrode and the like are bonded together via a liquid crystal layer 15 and a seal member 16. 11 and the backlight unit 12 is disposed opposite to the liquid crystal display panel 11. Further, the electronic apparatus 10 is manufactured by incorporating the liquid crystal display device 1 into the housing 2 together with other functional circuits and the like.
  • a flicker pattern is displayed on the screen for the purpose of suppressing flickering on the liquid crystal display panel 11 with the backlight unit 12 facing each other, and the signal voltage and the common electrode voltage are initially adjusted. Voltage adjusting step is included.
  • FIG. 3 is a plan view schematically showing a flicker pattern.
  • the flicker pattern 42 is a pattern in which the pixel 18 to which a signal voltage of one polarity is applied is displayed in black (Black), and the pixel 18 in the other polarity is displayed in halftone (Gray). is there. Since the flicker pattern 42 is a display pattern in which flicker is most easily recognized on the display screen, the flicker pattern 42 is used as a display pattern when adjusting the voltage (common electrode voltage) applied to the common electrode in the counter substrate 14.
  • the flicker pattern 42 in the present embodiment is a stripe pattern in which the pixel columns 19 displayed in black and the pixel columns 19 displayed in halftone are alternately arranged one by one. .
  • the polarity of the signal voltage in each pixel column 19 is inverted for each frame. That is, the pixel column 19 in which the polarity of each pixel 18 in the n ⁇ 1 frame is “ ⁇ ...” Becomes “+++...” In the n frame and “ ⁇ . ⁇ ⁇
  • the magnitude of the common electrode voltage is adjusted so that the flicker on the display screen is minimized while the flicker pattern 42 is displayed on the display screen of the liquid crystal display device 1.
  • FIG. 4 is a cross-sectional view showing a schematic configuration of the TFT 20.
  • the TFT 20 includes a gate electrode 26 formed on the glass substrate 17, a gate insulating film 27 covering the gate electrode 26, and a semiconductor made of a-Si opposed to the center of the gate electrode 26. It has a layer 28, a source electrode 25 facing one end side of the gate electrode 26, and a drain electrode 29 facing the other end side of the gate electrode 26.
  • Part of the light of the backlight unit 12 passes through the glass substrate 17 and enters between the source electrode 25 or the drain electrode 29 and the gate electrode 26. Then, as indicated by an arrow in FIG. 4, the incident light repeatedly reflects between the source electrode 25 or the drain electrode 29 and the gate electrode 26 and enters the semiconductor layer 28. As a result, an off-leakage current is generated in the TFT 20.
  • FIG. 5 is a plan view schematically showing a TFT 50 having a first electrode 51 and a second electrode 52 smaller than the first electrode 51 as a source electrode or a drain electrode.
  • a semiconductor layer 54 is formed between the first electrode 51 and the second electrode 52.
  • the TFT 50 having the first electrode 51 formed in a U-shape and the second electrode 52 formed in an I-shape as a source electrode or a drain electrode will be described.
  • the L length of the semiconductor layer 54 is 4 ⁇ m and the W length is 50 ⁇ m.
  • the overlapping width D between the U-shaped first electrode 51 and the gate electrode 53 is 26 ⁇ m, and the overlapping width d between the I-shaped second electrode 52 and the gate electrode 53 is 6 ⁇ m.
  • a voltage of ⁇ 20 to 20 V was applied to the gate electrode.
  • the applied voltage to the drain electrode was 4.1V, and the applied voltage to the source electrode was 0V.
  • Example 1 the U-shaped first electrode 51 is used as a source electrode and the I-shaped second electrode 52 is used as a drain electrode, and light having an intensity of 1750 cd / m 2 is irradiated.
  • the state X1 and the dark state Y1 where no light is irradiated the change in drain current with respect to the gate voltage was measured. The measurement results are shown in the graph of FIG.
  • the light state X2 is irradiated with light having an intensity of 1750 cd / m 2.
  • the change in drain current with respect to the gate voltage was measured for the dark state Y2 where no light was irradiated. The measurement results are shown in the graph of FIG.
  • Example 1 and Example 2 in the dark states Y1 and Y2, as indicated by broken lines in FIGS. 6 and 7, since the light itself applied to the TFT 50 is small, the drain current value indicating the off-leakage current is relatively low. small.
  • Example 1 in the bright state X1, although the voltage applied to the I-shaped second electrode (drain current) 52 is larger than the U-shaped first electrode (source electrode) 51, the second electrode 52 Since the overlap width between the first electrode 51 and the gate electrode 53 is smaller than the overlap width between the first electrode 51 and the gate electrode 53, the off-leakage current is relatively small as shown by the solid line in FIG.
  • Example 2 in the bright state X2, the applied voltage to the U-shaped first electrode (drain electrode) 51 is larger than that of the I-shaped second electrode (source electrode) 52, and the application thereof Since the overlapping width between the U-shaped first electrode 51 and the gate electrode 53 having a large voltage is larger than the overlapping width between the second electrode 52 and the gate electrode 53, as shown by the solid line in FIG. It became relatively large.
  • the graph of FIG. 8 shows a comparison of the off-leakage current (drain current value) in Examples 1 and 2.
  • the off-leakage current X2 in the bright state X2 of Example 2 is larger than the off-leakage current X1 in the bright state X1 of Example 1.
  • the off-leakage current Y1 in the dark state Y1 of Example 1 and the off-leakage current Y2 in the dark state Y2 of Example 2 are substantially the same and smaller than X1 and X2.
  • the off-leakage current increases when a + polarity signal voltage is applied to the second electrode 52, while the off-leakage current decreases when the + polarity signal voltage is applied to the second electrode 52.
  • FIG. 10 is a plan view showing 1H line inversion driving of the liquid crystal display device 1 according to the first embodiment.
  • the signal voltage applied to the source line 23 is set to ⁇ polarity in the 1H period of scanning the pixel column 19 a for black display of a certain n ⁇ 1 frame.
  • the signal voltage applied to the source line 23 is inverted to have a positive polarity.
  • the arrow of each pixel 18 in FIG. 10 indicates the direction in which the off-leakage current flows.
  • the off-leak current of the first pixel 18a is relatively small (S)
  • the off-leak current of the second pixel 18b is relatively large. (L). Therefore, the same number of pixels with half-tone display on the entire screen includes the first pixel 18a having a relatively small off-leakage current (S) and the second pixel 18b having a relatively large off-leakage current (L).
  • the off-leak current of the first pixel 18a becomes relatively large (L), and the off-leak current of the second pixel 18b. Becomes relatively small (S). Therefore, the same number of pixels with half-tone display on the entire screen includes the first pixels 18a having a relatively large off-leakage current (L) and the second pixels 18b having a relatively small off-leakage current (S).
  • any frame as a result of including the same number of (S) pixels 18 having a relatively small off-leakage current and (L) pixels 18 having a relatively large off-leakage current. Since the total leak amount of the entire display screen is the same before and after the change, flicker can be significantly suppressed. Therefore, according to the present embodiment, flicker can be significantly suppressed while ensuring a large W length of each TFT 20.
  • FIG. 11 is a plan view showing 1H line inversion driving of a liquid crystal display device as a comparative example.
  • all the pixels 118 have the same configuration, and each source electrode 125 is formed in a U shape, while each drain electrode 129 is formed in an I shape.
  • the signal voltage applied to the source line 123 is set to -polarity in the 1H period during which the pixel column 119a for black display of a certain n-1 frame is scanned. To do. In the 1H period during which the next pixel row 119b for halftone display is scanned, the signal voltage applied to the source wiring 123 is inverted to have a positive polarity.
  • the arrow of each pixel 118 in FIG. 11 indicates the direction in which the off-leakage current flows.
  • the off-leak current of each pixel 118 is relatively small (S). Accordingly, the entire screen is displayed in halftone by the (S) pixel 118 having a relatively small off-leakage current.
  • the off-leak current of each pixel 118 is relatively large (L) in the pixel column 119b displaying halftone in the next n frames. Therefore, the entire screen is displayed in halftone by the (L) pixel 118 having a relatively large off-leakage current.
  • the off-leak current of all the pixels 118 that perform halftone display is relatively small (S) before and after the frame changes, and the off-leakage of all the pixels 118 that perform halftone display. Since the state where the current is relatively large (L) is alternately switched, the flicker is easily visually recognized.
  • FIG. 12 is a graph showing a simulation result with respect to a temporal change in luminance of the liquid crystal display device in the comparative example.
  • FIG. 13 is a graph showing a simulation result with respect to a temporal change in luminance of the liquid crystal display device 1 in the present embodiment.
  • the waveform of the luminance change has a distorted shape as shown in the graph of FIG.
  • the waveform in one frame period is symmetric as shown in the graph of FIG. It turns out that it will become a shape.
  • Embodiment 2 of the Invention >> 14 to 16 show Embodiment 2 of the present invention.
  • FIG. 14 is a plan view showing an enlarged part of the TFT substrate 13 in the second embodiment.
  • FIG. 15 is a plan view showing 1H dot inversion driving of the liquid crystal display device 1 according to the second embodiment.
  • FIG. 16 is a plan view showing 1H dot inversion driving of a liquid crystal display device as a comparative example.
  • the same portions as those in FIGS. 1 to 13 are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the AC drive control unit 40 performs 1H line inversion drive.
  • the AC drive control unit 40 is not limited to this, and a plurality of AC drive control units 40 are provided for each period of scanning at least one gate wiring 22.
  • the polarity of the signal voltage applied to the source wiring 23 may be reversed.
  • the AC drive control unit 40 in the second embodiment is configured to perform 1H dot inversion drive.
  • the electronic device 10 includes a liquid crystal display device 1 as a display unit inside a housing 2 as shown in FIG.
  • the electronic device 10 is, for example, a mobile device such as a liquid crystal television or a smartphone or other electronic devices.
  • the liquid crystal display device 1 includes a liquid crystal display panel 11 and a backlight unit 12 that is a light source disposed on the back side of the liquid crystal display panel 11. That is, the liquid crystal display device 1 is configured to perform transmissive display by selectively transmitting at least light from the backlight unit 12.
  • the liquid crystal display panel 11 includes a TFT substrate 13 that is a first substrate, and a counter substrate 14 that is a second substrate disposed to face the TFT substrate 13.
  • a liquid crystal layer 15 is sealed between the TFT substrate 13 and the counter substrate 14 by a seal member 16.
  • the liquid crystal display panel 11 has a display area (not shown) and a frame-like non-display area (not shown) provided around the display area.
  • a plurality of pixels 18 provided in a matrix are formed in the display area.
  • the TFT substrate 13 is composed of an active matrix substrate.
  • the TFT substrate 13 has a glass substrate (not shown) as a transparent substrate.
  • a plurality of source lines 23 extending in parallel to each other and a plurality of gate lines 22 extending so as to cross the source lines 23 are formed on the glass substrate.
  • the plurality of gate lines 22 and the plurality of source lines 23 are formed in a lattice shape as a whole, and the pixels 18 are formed in regions surrounded by the gate lines 22 and the source lines 23 in a rectangular shape.
  • Each of the gate wiring 22 and the source wiring 23 is configured by a single-layer film made of one type or a multi-layer film made of a plurality of types, for example, among Al, Cu, Mo, Ti, and the like.
  • Each pixel 18 is provided with a TFT 20 in the vicinity of the intersection of the gate wiring 22 and the source wiring 23.
  • the gate wiring 22 and the source wiring 23 are connected to the TFT 20.
  • the TFT 20 in the second embodiment is a bottom gate type TFT, and a gate electrode 26 branched from the gate wiring 22 and a semiconductor layer (not shown) facing the gate electrode 26 via a gate insulating film (not shown).
  • the gate electrode 26 and the gate wiring 22 are formed on a glass substrate and covered with the gate insulating film.
  • the gate insulating film is composed of, for example, a single-layer film made of one of SiNx (silicon nitride) and SiO 2 or a multi-layer film made of a plurality of kinds.
  • the semiconductor layer is formed in a rectangular island shape, for example.
  • the semiconductor layer is formed of a semiconductor such as a-Si, for example.
  • a part of the source electrode 25 and a part of the drain electrode 29 are overlapped with the semiconductor layer and the gate electrode 26, respectively.
  • the source electrode 25, the drain electrode 29, and the like are covered with an interlayer insulating film (not shown).
  • the interlayer insulating film is made of, for example, SiNx.
  • the plurality of pixels 18 are formed with pixel electrodes 30 connected to the drain electrodes 29 of the TFTs 20 provided in the pixels 18.
  • the pixel electrode 30 is formed on the surface of the interlayer insulating film, and is formed of a transparent conductive film such as ITO.
  • a common electrode (not shown) provided in common with the plurality of pixel electrodes 30 is formed on the counter substrate 14. Similar to the pixel electrode 30, the common electrode is also formed of a transparent conductive film such as ITO. Thus, the orientation of the liquid crystal layer 15 is controlled for each pixel 18 by controlling the potential difference between the common electrode having a predetermined potential and the pixel electrode 30 of each pixel 18.
  • the TFT 20 in this embodiment includes a first TFT 20 a in which the source electrode 25 is larger than the drain electrode 29 and a second TFT 20 b in which the drain electrode 29 is larger than the source electrode 25.
  • the source electrode 25 of the first TFT 20 a includes a pair of electrode limbs 32 formed in a bifurcated shape, and a base end portion 33 formed wide on the base end side of the electrode limbs 32. have.
  • the drain electrode 29 of the first TFT 20 a has a linear portion 34 extending linearly, and the tip of the linear portion 34 is disposed between the pair of electrode limbs 32.
  • the entire electrode limb 32 of the source electrode 25 and a part of the base end portion 33 overlap the gate electrode 26.
  • the overlapping width A of the source electrode 25 and the gate electrode 26 at the base end portion 33 is wider than the overlapping width B of the drain electrode 29 and the gate electrode 26.
  • the drain electrode 29 of the second TFT 20b has a pair of electrode limbs 36 formed in a bifurcated shape and a base end portion 37 formed wide on the base end side of the electrode limbs 36.
  • the source electrode 25 of the second TFT 20 b has a linear portion 38 that extends linearly, and the tip of the linear portion 38 is disposed between the pair of electrode limbs 36.
  • the entire electrode limb 36 of the drain electrode 29 and a part of the base end portion 37 overlap the gate electrode 26.
  • the overlap width A between the source electrode 25 and the gate electrode 26 is narrower than the overlap width B between the drain electrode 29 and the gate electrode 26 at the base end portion 37.
  • a pixel column 19 including a plurality of pixels 18 arranged along the gate wiring 22 includes a plurality of first pixels 18 a in which the first TFTs 20 a are formed and a plurality of pixels in which the second TFTs 20 b are formed.
  • the second pixel 18b is included.
  • each pixel column 19 two first pixels 18 a and two second pixels 18 b are alternately arranged along the gate wiring 22.
  • a plurality of first pixels 18a or a plurality of second pixels 18b are arranged side by side.
  • the liquid crystal display device 1 further includes an AC drive control unit 40 that applies signal voltages having different polarities to the source lines 23 adjacent to each other in a period during which one gate line 22 is scanned.
  • the AC drive control unit 40 is configured to invert the polarity of the signal voltage applied to the plurality of source lines 23 for each period of scanning one gate line 22. That is, the driving method of the liquid crystal display device 1 is a 1H dot inversion driving method in which the polarity of the signal voltage is inverted every 1H period (one horizontal scanning period).
  • the AC drive control unit 40 may be configured to invert the polarity of the signal voltage every time the plurality of gate wirings 22 are scanned. That is, the AC drive control unit 40 may be configured to perform nH dot inversion driving. Therefore, the AC drive control unit 40 can be configured to apply signal voltages having different polarities to the source wirings 23 adjacent to each other in each of the scanning periods of at least one gate wiring 22.
  • the liquid crystal display device 1 is a liquid crystal display panel in which a TFT substrate 13 manufactured by forming a plurality of TFTs 20 and the like and a counter substrate 14 formed with a common electrode and the like are bonded together via a liquid crystal layer 15 and a seal member 16. 11 and the backlight unit 12 is disposed opposite to the liquid crystal display panel 11. Further, the electronic apparatus 10 is manufactured by incorporating the liquid crystal display device 1 into the housing 2 together with other functional circuits and the like.
  • a flicker pattern is displayed on the screen for the purpose of suppressing flickering on the liquid crystal display panel 11 with the backlight unit 12 facing each other, and the signal voltage and the common electrode voltage are initially adjusted. Voltage adjusting step is included.
  • the flicker pattern in the present embodiment has, for example, a black checkered pixel 18 and a halftone display pixel 18 arranged in a zigzag pattern, and has a checkered pattern as a whole.
  • the polarity of the signal voltage in each pixel column 19 is inverted for each frame. That is, the pixel column 19 in which the polarity of each pixel 18 in the n ⁇ 1 frame is “ ⁇ ++ ⁇ ...” Becomes “+ ⁇ + ⁇ ...” In the n frame and “ ⁇ ++ ⁇ ” in the n + 1 frame. + ... ".
  • the magnitude of the common electrode voltage is adjusted so that the flicker on the display screen is minimized while the flicker pattern 42 is displayed on the display screen of the liquid crystal display device 1.
  • the present inventors reverse the polarity of the signal voltage applied to the source electrode (source wiring) in a liquid crystal display device including a TFT having a source electrode shape different from that of the drain electrode. It was found that the amount of off-leakage current generated in the TFT changes according to the reversal of the polarity. As a result of the change in the luminance of the pixel provided with the TFT along with the change in the off-leakage current, it has been found that flicker is easily visually recognized.
  • FIG. 15 is a plan view showing 1H dot inversion driving of the liquid crystal display device 1 according to the second embodiment.
  • the liquid crystal display device 1 As shown in the upper part of FIG. 15, in the 1H period in which the pixel row 19 a that performs a certain “black display, halftone display, black display, halftone display...
  • the polarity of the signal voltage applied to the wiring 23 is “+ ⁇ + ⁇ .
  • the polarity of the signal voltage applied to the source wiring 23 is set to “ ⁇ ++ ⁇ + ⁇ for the pixel row 19b for“ halftone display, black display, halftone display, black display. ⁇ ⁇ ⁇
  • a positive polarity signal voltage is applied to the pixel 18 displaying black
  • a negative polarity signal voltage is applied to the pixel 18 displaying halftone.
  • the arrow of each pixel 18 in FIG. 15 indicates the direction in which the off-leakage current flows.
  • the off-leakage current is relatively large (L) in the first pixel 18a displaying the halftone display that is visually recognized.
  • the off-leakage current is relatively small in the second pixel 18b displaying halftone (S). Therefore, the same number of pixels with half-tone display on the entire screen includes the first pixels 18a having a relatively large off-leakage current (L) and the second pixels 18b having a relatively small off-leakage current (S).
  • the off-leakage current is relatively small in the first pixel 18a that is displayed as a halftone display (S).
  • the off-leakage current becomes relatively large (L) in the second pixel 18b displaying halftone. Therefore, the same number of pixels with half-tone display on the entire screen includes the first pixel 18a having a relatively small off-leakage current (S) and the second pixel 18b having a relatively large off-leakage current (L).
  • each frame includes the same number (S) of pixels 18 with relatively small off-leakage current (S) and pixels (L) with relatively large off-leakage current. Since the total leak amount of the entire display screen is the same before and after the change, flicker can be significantly suppressed. Therefore, according to the present embodiment, flicker can be significantly suppressed while ensuring a large W length of each TFT 20.
  • FIG. 16 is a plan view showing 1H dot inversion driving of a liquid crystal display device as a comparative example.
  • all the pixels 118 have the same configuration, and each source electrode 125 is formed in a U shape, while each drain electrode 129 is formed in an I shape.
  • the pixel column 119a that performs certain “black display, halftone display, black display, halftone display...
  • the polarity of the signal voltage applied to the source wiring 123 is “+ ⁇ + ⁇ .
  • the polarity of the signal voltage applied to the source wiring 123 is set to “ ⁇ ++ ⁇ + ⁇ for the pixel column 119b performing“ halftone display, black display, halftone display, black display. ⁇ ⁇ ⁇
  • a positive polarity signal voltage is applied to the pixel 118 displaying black
  • a negative polarity signal voltage is applied to the pixel 118 displaying halftone.
  • the arrow of each pixel 18 in FIG. 16 indicates the direction in which the off-leakage current flows.
  • the off-leakage current is relatively large (L) in the visually recognized pixel 118 displaying halftone. Therefore, the entire screen is displayed in halftone by the (L) pixel 118 having a relatively large off-leakage current.
  • the off-leakage current is relatively small in the pixel 118 that is displayed in halftone in the next n frames (S). Accordingly, the entire screen is displayed in halftone by the (S) pixel 118 having a relatively small off-leakage current.
  • the off-leak current of all the pixels 118 that perform halftone display is relatively large (L) before and after the frame changes, and the off-leakage of all the pixels 118 that perform halftone display. Since the state where the current is relatively small (S) is alternately switched, flicker is likely to be visually recognized.
  • Embodiment 3 of the Invention >> 17 to 20 show Embodiment 3 of the present invention.
  • FIG. 17 is a plan view showing an enlarged part of the TFT substrate 13 in the third embodiment.
  • FIG. 18 is an enlarged plan view showing the first TFT and the second TFT in the third embodiment.
  • the source electrode 25 or the drain electrode 29 of the TFT 20 is formed in a U shape, whereas in the third embodiment, the source electrode 25 and the drain electrode 29 of the TFT 20 are each formed in a rectangular shape. Is different.
  • the electronic device 10 includes a liquid crystal display device 1 as a display unit inside a housing 2 as shown in FIG.
  • the electronic device 10 is, for example, a mobile device such as a liquid crystal television or a smartphone or other electronic devices.
  • the liquid crystal display device 1 includes a liquid crystal display panel 11 and a backlight unit 12 that is a light source disposed on the back side of the liquid crystal display panel 11. That is, the liquid crystal display device 1 is configured to perform transmissive display by selectively transmitting at least light from the backlight unit 12.
  • the liquid crystal display panel 11 includes a TFT substrate 13 that is a first substrate, and a counter substrate 14 that is a second substrate disposed to face the TFT substrate 13.
  • a liquid crystal layer 15 is sealed between the TFT substrate 13 and the counter substrate 14 by a seal member 16.
  • the liquid crystal display panel 11 has a display area (not shown) and a frame-like non-display area (not shown) provided around the display area.
  • a plurality of pixels 18 provided in a matrix are formed in the display area.
  • the TFT substrate 13 is composed of an active matrix substrate.
  • the TFT substrate 13 has a glass substrate (not shown) as a transparent substrate.
  • a plurality of source lines 23 extending in parallel to each other and a plurality of gate lines 22 extending so as to intersect the source lines 23 are formed on the glass substrate.
  • the plurality of gate lines 22 and the plurality of source lines 23 are formed in a lattice shape as a whole, and the pixels 18 are formed in regions surrounded by the gate lines 22 and the source lines 23 in a rectangular shape.
  • Each of the gate wiring 22 and the source wiring 23 is configured by a single-layer film made of one type or a multi-layer film made of a plurality of types, for example, among Al, Cu, Mo, Ti, and the like.
  • Each pixel 18 is provided with a TFT 20 in the vicinity of the intersection of the gate wiring 22 and the source wiring 23.
  • the gate wiring 22 and the source wiring 23 are connected to the TFT 20.
  • the TFT 20 in the third embodiment is a bottom gate type TFT, and a gate electrode 26 branched from the gate wiring 22 and a semiconductor layer (not shown) facing the gate electrode 26 via a gate insulating film (not shown).
  • the gate electrode 26 and the gate wiring 22 are formed on a glass substrate and covered with the gate insulating film.
  • the gate insulating film is composed of, for example, a single-layer film made of one of SiNx (silicon nitride) and SiO 2 or a multi-layer film made of a plurality of kinds.
  • the semiconductor layer is formed in a rectangular island shape, for example.
  • the semiconductor layer is formed of a semiconductor such as a-Si, for example.
  • a part of the source electrode 25 and a part of the drain electrode 29 are overlapped with the semiconductor layer and the gate electrode 26, respectively.
  • the source electrode 25, the drain electrode 29, and the like are covered with an interlayer insulating film (not shown).
  • the interlayer insulating film is made of, for example, SiNx.
  • the plurality of pixels 18 are formed with pixel electrodes 30 connected to the drain electrodes 29 of the TFTs 20 provided in the pixels 18.
  • the pixel electrode 30 is formed on the surface of the interlayer insulating film, and is formed of a transparent conductive film such as ITO.
  • a common electrode (not shown) provided in common with the plurality of pixel electrodes 30 is formed on the counter substrate 14. Similar to the pixel electrode 30, the common electrode is also formed of a transparent conductive film such as ITO. Thus, the orientation of the liquid crystal layer 15 is controlled for each pixel 18 by controlling the potential difference between the common electrode having a predetermined potential and the pixel electrode 30 of each pixel 18.
  • the TFT 20 in this embodiment includes a first TFT 20 a in which the source electrode 25 is larger than the drain electrode 29 and a second TFT 20 b in which the drain electrode 29 is larger than the source electrode 25.
  • the source electrode 25 and the drain electrode 29 of the first TFT 20a each have a rectangular portion, and are arranged so that one sides thereof face each other.
  • the source electrode 25 of the first TFT 20 a is larger than the drain electrode 29.
  • one end of the source electrode 25 of the first TFT 20a overlaps the gate electrode. Further, one end portion of the drain electrode 29 of the first TFT 20 a also overlaps the gate electrode 26.
  • the overlapping width A between the source electrode 25 and the gate electrode 26 in the first TFT 20 a is wider than the overlapping width B between the drain electrode 29 and the gate electrode 26.
  • the source electrode 25 and the drain electrode 29 of the second TFT 20b each have a rectangular portion, and are arranged so that the sides thereof face each other.
  • the source electrode 25 of the second TFT 20 b is smaller than the drain electrode 29.
  • one end portion of the source electrode 25 overlaps the gate electrode 26, and one end portion of the drain electrode 29 overlaps the gate electrode 26.
  • the overlap width A between the source electrode 25 and the gate electrode 26 in the second TFT 20 b is narrower than the overlap width B between the drain electrode 29 and the gate electrode 26.
  • ⁇ Pixel arrangement configuration> As shown in FIG. 17, a plurality of first pixels 18 a in which first TFTs 20 a are formed and a plurality of pixels in which second TFTs 20 b are formed are arranged in a pixel column 19 including a plurality of pixels 18 arranged along the gate wiring 22. The second pixel 18b is included.
  • each pixel column 19 one first pixel 18 a and one second pixel 18 b are alternately arranged along the gate wiring 22.
  • a plurality of first pixels 18a or a plurality of second pixels 18b are arranged side by side.
  • first pixel 18 a and the second pixel 18 b for example, in each pixel column 19, two first pixels 18 a and two second pixels 18 b are alternately arranged along the gate wiring 22. May be arranged. That is, at least one first pixel 18 a and the same number of second pixels 18 b as the at least one first pixel 18 a are alternately arranged along the gate wiring 22 in the pixel column 19. Also good.
  • the liquid crystal display device 1 further includes an AC drive control unit 40 that applies signal voltages having the same polarity to the plurality of source lines 23 during a period of scanning one gate line 22.
  • the AC drive control unit 40 is configured to invert the polarity of the signal voltage applied to the plurality of source lines 23 for each period of scanning one gate line 22. That is, the driving method of the liquid crystal display device 1 is a 1H line inversion driving method in which the polarity of the signal voltage is inverted every 1H period.
  • the AC drive control unit 40 may be configured to invert the polarity of the signal voltage every time the plurality of gate wirings 22 are scanned. That is, the AC drive control unit 40 may be configured to perform nH line inversion driving. Therefore, the AC drive control unit 40 can be configured to apply signal voltages having the same polarity to the plurality of source lines 23 in each of the periods in which at least one gate line 22 is scanned.
  • the liquid crystal display device 1 is a liquid crystal display panel in which a TFT substrate 13 manufactured by forming a plurality of TFTs 20 and the like and a counter substrate 14 formed with a common electrode and the like are bonded together via a liquid crystal layer 15 and a seal member 16. 11 and the backlight unit 12 is disposed opposite to the liquid crystal display panel 11. Further, the electronic apparatus 10 is manufactured by incorporating the liquid crystal display device 1 into the housing 2 together with other functional circuits and the like.
  • a flicker pattern is displayed on the screen for the purpose of suppressing flickering on the liquid crystal display panel 11 with the backlight unit 12 facing each other, and the signal voltage and the common electrode voltage are initially adjusted. Voltage adjusting step is included.
  • the magnitude of the common electrode voltage is adjusted so that the flicker on the display screen is minimized while the flicker pattern 42 is displayed on the display screen of the liquid crystal display device 1.
  • FIG. 19 is a plan view showing 1H line inversion driving of the liquid crystal display device 1 according to the third embodiment.
  • the signal voltage applied to the source line 23 is set to + polarity in the 1H period during which the pixel column 19 a for halftone display of a certain n ⁇ 1 frame is scanned. To do.
  • the signal voltage applied to the source line 23 is inverted to have a negative polarity.
  • the arrow of each pixel 18 in FIG. 19 indicates the direction in which the off-leakage current flows.
  • the off-leak current is relatively small in the pixel column 19a displaying the halftone display that is visually recognized (S), and the off-leak current is relatively large in the second pixel 18b (L). Therefore, the same number of pixels with half-tone display on the entire screen includes the first pixel 18a having a relatively small off-leakage current (S) and the second pixel 18b having a relatively large off-leakage current (L).
  • the off-leak current of the first pixel 18a becomes relatively large (L), and the off-leak current of the second pixel 18b. Becomes relatively small (S). Therefore, the same number of pixels with half-tone display on the entire screen includes the first pixels 18a having a relatively large off-leakage current (L) and the second pixels 18b having a relatively small off-leakage current (S).
  • FIG. 20 is a plan view showing 1H line inversion driving of a liquid crystal display device as a comparative example.
  • all the pixels 118 have the same configuration, and each source electrode 125 is formed larger than the drain electrode 129.
  • the signal voltage applied to the source line 123 is set to + polarity in the 1H period in which the pixel column 119a for halftone display of a certain n ⁇ 1 frame is scanned. And In the 1H period during which the next pixel column 119b for black display is scanned, the signal voltage applied to the source wiring 123 is inverted to have a negative polarity.
  • the arrow of each pixel 118 in FIG. 20 indicates the direction in which the off-leakage current flows.
  • the off-leak current of each pixel 118 is relatively small (S). Accordingly, the entire screen is displayed in halftone by the (S) pixel 118 having a relatively small off-leakage current.
  • the off-leak current of each pixel 118 is relatively large (L). Therefore, the entire screen is displayed in halftone by the (L) pixel 118 having a relatively large off-leakage current.
  • the off-leak current of all the pixels 118 that perform halftone display is relatively small (S) before and after the frame changes, and the off-leakage of all the pixels 118 that perform halftone display. Since the state where the current is relatively large (L) is alternately switched, the flicker is likely to be visually recognized.
  • the present invention is not limited to the first to third embodiments, and the present invention includes a configuration in which these first to third embodiments are appropriately combined.
  • the present invention is useful for a liquid crystal display device and an electronic apparatus including the same.
  • Liquid crystal display device 10 Electronic equipment 18 pixels 18a first pixel 18b second pixel 19 pixel array 20 TFT 20a 1st TFT 20b 2nd TFT 22 Gate wiring 23 Source wiring 25 Source electrode 29 Drain electrode 30 pixel electrode 32 electrode limbs 36 electrode limbs 40 AC drive controller 51 First electrode 52 Second electrode

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Abstract

This liquid crystal display device is provided with an alternating current drive control unit which reverses, by each period when a gate wiring line is scanned, polarity of a signal voltage to be applied to a plurality of source wiring lines. Thin film transistors include a first thin film transistor, in which a width with which a source electrode and a gate electrode overlap each other is larger than a width with which the drain electrode and the gate electrode overlap each other, and a second thin film transistor, in which a width with which the source electrode and the gate electrode overlap each other is smaller than a width with which the drain electrode and the gate electrode overlap each other. A pixel column composed of a plurality of pixels aligned along the gate wiring line includes a plurality of first pixels, each of which has a first thin film transistor formed therein, and a plurality of second pixels, each of which has a second thin film transistor formed therein.

Description

液晶表示装置及び電子機器Liquid crystal display device and electronic device
 本発明は、液晶表示装置及びそれを備えた電子機器に関するものである。 The present invention relates to a liquid crystal display device and an electronic apparatus including the same.
 近年、例えば液晶テレビやスマートフォン等の電子機器の需要が拡大しており、その表示装置として液晶表示装置が広く用いられている。 In recent years, demand for electronic devices such as liquid crystal televisions and smartphones has increased, and liquid crystal display devices are widely used as display devices.
 液晶表示装置の液晶層に直流電圧が印加されると、表示不良や液晶劣化が生じるため、液晶表示装置は交流駆動することが望ましい。そこで、例えば特許文献1及び2等に開示されているように、液晶表示装置の交流駆動方式として、1Hライン反転駆動方式及び1Hドット反転駆動方式が知られている。 When a DC voltage is applied to the liquid crystal layer of the liquid crystal display device, display defects and liquid crystal deterioration occur, and therefore it is desirable that the liquid crystal display device be AC driven. Therefore, as disclosed in Patent Documents 1 and 2, for example, a 1H line inversion driving method and a 1H dot inversion driving method are known as AC driving methods for liquid crystal display devices.
 1Hライン反転駆動方式は、1H期間(1水平走査期間)毎に全てのソース信号の極性を反転させる駆動方式である。この駆動方式では、ある走査線の走査時に、全ての信号線の極性がプラスとなり、次の走査線の走査時に、全ての信号線の極性が反転してマイナスとなる。その結果、1フレームの走査が終了したときに、各画素には、プラスの信号が横一列に書き込まれた行と、マイナスの信号が横一列に書き込まれた行とが交互に配置されることとなる。 The 1H line inversion driving method is a driving method in which the polarity of all source signals is inverted every 1H period (one horizontal scanning period). In this driving method, the polarity of all signal lines becomes positive when scanning a certain scanning line, and the polarity of all signal lines is inverted and becomes negative when scanning the next scanning line. As a result, when scanning for one frame is completed, each pixel is alternately arranged with a row in which a positive signal is written in one horizontal row and a row in which a negative signal is written in one horizontal row. It becomes.
 1Hドット反転駆動方式は、信号線の極性が交互に反転する駆動方式である。この駆動方式では、ある走査線の走査時に、ある信号線の極性がプラスとなり、その横隣の信号線の極性がマイナスとなる。そして、次の走査線の走査時に、上記信号線の極性が反転してマイナスとなり、上記横隣の信号線の極性がプラスとなる。その結果、1フレームの走査が終了したときに、各画素には、プラス及びマイナスの信号が縦方向及び横方向にそれぞれ交互に書き込まれることとなる。 The 1H dot inversion driving method is a driving method in which the polarities of the signal lines are alternately inverted. In this driving method, when a certain scanning line is scanned, the polarity of a certain signal line becomes positive, and the polarity of the adjacent signal line becomes negative. When the next scanning line is scanned, the polarity of the signal line is inverted and becomes negative, and the polarity of the adjacent signal line becomes positive. As a result, when one frame of scanning is completed, plus and minus signals are alternately written in the vertical direction and the horizontal direction in each pixel.
 さらに、上記交流駆動方式の液晶表示装置について、特許文献3及び4等に開示されているように、フリッカを抑制する目的で、フリッカパターンを画面に表示させて、信号電圧と共通電極電圧とを初期調整することが知られている。例えば、一方の極性の画素を黒表示(又は白表示)させると共に、他方の極性の画素を中間調表示させたフリッカパターンの表示画面により、擬似的に中間調のフレーム反転駆動のような表示状態を再現し、その状態において、フリッカが最小となるように共通電極に印加する電圧を調整する。 Further, as disclosed in Patent Documents 3 and 4, etc., the AC drive type liquid crystal display device displays a flicker pattern on the screen for the purpose of suppressing flicker, and generates a signal voltage and a common electrode voltage. Initial adjustment is known. For example, a display state such as pseudo halftone frame inversion driving is displayed on a flicker pattern display screen in which one polarity pixel is displayed in black (or white display) and the other polarity pixel is displayed in halftone. In this state, the voltage applied to the common electrode is adjusted so that the flicker is minimized.
 一方、従来の液晶表示装置に用いるTFT(薄膜トランジスタ)100を示す平面図である図21に示すように、TFT100について、二股状に形成された一対の電極肢101を有するU字状のソース電極102と、その一対の電極肢101の間に配置されたドレイン電極103と、これらのソース電極102及びドレイン電極103に重なる半導体層104及びゲート電極105とを備えることにより、チャネル領域106のW長を大きく確保することが知られている(特許文献5及び6等参照)。 On the other hand, as shown in FIG. 21, which is a plan view showing a TFT (thin film transistor) 100 used in a conventional liquid crystal display device, the TFT 100 has a U-shaped source electrode 102 having a pair of electrode limbs 101 formed in a bifurcated shape. And the drain electrode 103 disposed between the pair of electrode limbs 101, and the semiconductor layer 104 and the gate electrode 105 overlapping with the source electrode 102 and the drain electrode 103, thereby reducing the W length of the channel region 106. It is known to ensure a large amount (see Patent Documents 5 and 6, etc.).
特開2002-149117号公報JP 2002-149117 A 特開2003-202542号公報JP 2003-202542 A 特開2004-117749号公報JP 2004-117749 A 特開2007-171358号公報JP 2007-171358 A 特開2010-055065号公報JP 2010-055065 A 特開2008-004771号公報JP 2008-004771 A
 ところで、液晶表示装置に用いられるTFTは、通常、a-Si(アモルファスシリコン)によって形成されている。そのTFTのチャネル領域に光が入射すると光電流が発生するため、オフリーク電流が生じる。 Incidentally, TFTs used in liquid crystal display devices are usually formed of a-Si (amorphous silicon). When light enters the channel region of the TFT, a photocurrent is generated, and an off-leakage current is generated.
 本発明者らは、上記U字状のソース電極を有するTFTのようにソース電極の形状がドレイン電極と異なるTFTを有する液晶表示装置について、ソース電極に印加する信号電圧の極性を反転させる交流駆動を行うと、上述のようにチャネル領域のW長を大きく確保することが可能になるものの、フリッカが特に視認されやすくなるという問題を見出した。 The present inventors have made an AC drive for inverting the polarity of a signal voltage applied to a source electrode in a liquid crystal display device having a TFT having a source electrode shape different from that of a drain electrode, such as the TFT having the U-shaped source electrode. As described above, it was possible to secure a large W length in the channel region as described above, but the problem was found that flicker is particularly easily visible.
 本発明は、斯かる点に鑑みてなされたものであり、その目的とするところは、ソース電極の形状がドレイン電極と異なるTFTを備えた液晶表示装置を交流駆動しながらも、フリッカを大幅に抑制しようとすることにある。 The present invention has been made in view of such a point, and the object of the present invention is to significantly reduce flicker while AC driving a liquid crystal display device having a TFT whose source electrode shape is different from that of the drain electrode. It is in trying to suppress.
 本発明者らは、ソース電極の形状がドレイン電極と異なるTFTを備えた液晶表示装置について、鋭意研究を重ねた結果、当該ソース電極(ソース配線)に印加する信号電圧の極性を反転させると、その極性の反転に応じて、当該TFTに生じるオフリーク電流の量が変化することを見出した。そして、そのオフリーク電流の変化に伴って当該TFTが設けられている画素の輝度が変化する結果、フリッカが視認されやすくなることが分かった。 As a result of intensive studies on a liquid crystal display device having a TFT whose source electrode shape is different from that of the drain electrode, the inventors have reversed the polarity of the signal voltage applied to the source electrode (source wiring). It was found that the amount of off-leakage current generated in the TFT changes according to the reversal of the polarity. As a result of the change in the luminance of the pixel provided with the TFT along with the change in the off-leakage current, it has been found that flicker is easily visually recognized.
 そこで、上記の目的を達成するために、本発明に係る液晶表示装置は、複数のソース配線と、上記ソース配線に交差する複数のゲート配線と、マトリクス状に設けられた複数の画素と、上記複数の画素にそれぞれ設けられて上記ソース配線及びゲート配線に接続された薄膜トランジスタと、上記複数の画素にそれぞれ設けられて上記薄膜トランジスタのドレイン電極に接続された画素電極と、少なくとも1つの上記ゲート配線を走査する期間毎に、上記複数のソース配線に印加する信号電圧の極性を反転させる交流駆動制御部とを備えている。 In order to achieve the above object, a liquid crystal display device according to the present invention includes a plurality of source lines, a plurality of gate lines crossing the source lines, a plurality of pixels provided in a matrix, A thin film transistor provided in each of a plurality of pixels and connected to the source wiring and the gate wiring, a pixel electrode provided in each of the plurality of pixels and connected to a drain electrode of the thin film transistor, and at least one of the gate wirings An AC drive control unit that reverses the polarity of the signal voltage applied to the plurality of source wirings for each scanning period is provided.
 そして、上記薄膜トランジスタのドレイン電極の一部及びソース電極の一部は、当該薄膜トランジスタのゲート電極にそれぞれ重なっており、上記薄膜トランジスタには、上記ソース電極と上記ゲート電極との重なり幅が上記ドレイン電極と上記ゲート電極との重なり幅よりも広い第1薄膜トランジスタと、上記ソース電極と上記ゲート電極との重なり幅が上記ドレイン電極と上記ゲート電極との重なり幅よりも狭い第2薄膜トランジスタとが含まれ、上記ゲート配線に沿って並ぶ複数の上記画素からなる画素列には、上記第1薄膜トランジスタが形成された複数の第1画素と、上記第2薄膜トランジスタが形成された複数の第2画素とが含まれている。 In addition, part of the drain electrode and part of the source electrode of the thin film transistor overlap with the gate electrode of the thin film transistor, respectively, and the overlapping width of the source electrode and the gate electrode is different from that of the drain electrode. A first thin film transistor wider than an overlap width with the gate electrode; and a second thin film transistor in which an overlap width between the source electrode and the gate electrode is narrower than an overlap width between the drain electrode and the gate electrode. A pixel column composed of the plurality of pixels arranged along the gate wiring includes a plurality of first pixels in which the first thin film transistor is formed and a plurality of second pixels in which the second thin film transistor is formed. Yes.
 本発明によれば、ソース電極の形状がドレイン電極と異なるTFTを備えた液晶表示装置を交流駆動しながらも、フリッカを大幅に抑制することができる。 According to the present invention, flicker can be significantly suppressed while AC driving a liquid crystal display device having a TFT whose source electrode shape is different from that of the drain electrode.
図1は、本実施形態1におけるTFT基板の一部を拡大してを示す平面図である。FIG. 1 is an enlarged plan view showing a part of the TFT substrate according to the first embodiment. 図2は、第1TFT及び第2TFTを拡大して示す平面図である。FIG. 2 is an enlarged plan view showing the first TFT and the second TFT. 図3は、フリッカパターンを模式的に示す平面図である。FIG. 3 is a plan view schematically showing a flicker pattern. 図4は、TFTの概略構成を示す断面図である。FIG. 4 is a cross-sectional view showing a schematic configuration of the TFT. 図5は、第1電極と、第1電極よりも小さい第2電極とを有するTFTを模式的に示す平面図である。FIG. 5 is a plan view schematically showing a TFT having a first electrode and a second electrode smaller than the first electrode. 図6は、実施例1の結果を示すグラフである。FIG. 6 is a graph showing the results of Example 1. 図7は、実施例2の結果を示すグラフである。FIG. 7 is a graph showing the results of Example 2. 図8は、実施例1及び2におけるオフリーク電流を示すグラフである。FIG. 8 is a graph showing off-leakage currents in Examples 1 and 2. 図9は、本実施形態1における電子機器に設けられた液晶表示装置の概略構造を示す断面図である。FIG. 9 is a cross-sectional view illustrating a schematic structure of a liquid crystal display device provided in the electronic apparatus according to the first embodiment. 図10は、本実施形態1における液晶表示装置の1Hライン反転駆動を示す平面図である。FIG. 10 is a plan view showing 1H line inversion driving of the liquid crystal display device according to the first embodiment. 図11は、比較例としての液晶表示装置の1Hライン反転駆動を示す平面図である。FIG. 11 is a plan view showing 1H line inversion driving of a liquid crystal display device as a comparative example. 図12は、比較例における輝度の時間変化についてのシミュレーション結果を示すグラフである。FIG. 12 is a graph showing a simulation result with respect to temporal change in luminance in the comparative example. 図13は、実施例における輝度の時間変化についてのシミュレーション結果を示すグラフである。FIG. 13 is a graph illustrating a simulation result of a change in luminance with time in the example. 図14は、本実施形態2におけるTFT基板の一部を拡大してを示す平面図である。FIG. 14 is an enlarged plan view showing a part of the TFT substrate according to the second embodiment. 図15は、本実施形態2における液晶表示装置の1Hドット反転駆動を示す平面図である。FIG. 15 is a plan view showing 1H dot inversion driving of the liquid crystal display device according to the second embodiment. 図16は、比較例としての液晶表示装置の1Hドット反転駆動を示す平面図である。FIG. 16 is a plan view showing 1H dot inversion driving of a liquid crystal display device as a comparative example. 図17は、本実施形態3におけるTFT基板13の一部を拡大してを示す平面図である。FIG. 17 is a plan view showing an enlarged part of the TFT substrate 13 in the third embodiment. 図18は、本実施形態3における第1TFT及び第2TFTを拡大して示す平面図である。FIG. 18 is an enlarged plan view showing the first TFT and the second TFT in the third embodiment. 図19は、本実施形態3における液晶表示装置1の1Hライン反転駆動を示す平面図である。FIG. 19 is a plan view showing 1H line inversion driving of the liquid crystal display device 1 according to the third embodiment. 図20は、比較例としての液晶表示装置の1Hライン反転駆動を示す平面図である。FIG. 20 is a plan view showing 1H line inversion driving of a liquid crystal display device as a comparative example. 図21は、従来の液晶表示装置に用いるTFTを示す平面図である。FIG. 21 is a plan view showing a TFT used in a conventional liquid crystal display device.
 以下、本発明の実施形態を図面に基づいて詳細に説明する。尚、本発明は、以下の実施形態に限定されるものではない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiment.
 《発明の実施形態1》
 図1~図13は、本発明の実施形態1を示している。
Embodiment 1 of the Invention
1 to 13 show Embodiment 1 of the present invention.
 図1は、本実施形態1におけるTFT基板の一部を拡大してを示す平面図である。図2は、第1TFT及び第2TFTを拡大して示す平面図である。図9は、本実施形態1における電子機器に設けられた液晶表示装置の概略構造を示す断面図である。 FIG. 1 is a plan view showing an enlarged part of the TFT substrate according to the first embodiment. FIG. 2 is an enlarged plan view showing the first TFT and the second TFT. FIG. 9 is a cross-sectional view illustrating a schematic structure of a liquid crystal display device provided in the electronic apparatus according to the first embodiment.
 本実施形態1における電子機器10は例えば液晶テレビである。尚、電子機器10は、例えばスマートフォンや携帯電話等のモバイル機器その他の電子機器とすることができる。電子機器10は、図9に示すように、筐体2の内部に表示ユニットとしての液晶表示装置1を備えている。 The electronic device 10 in the first embodiment is, for example, a liquid crystal television. The electronic device 10 may be a mobile device such as a smartphone or a mobile phone, or other electronic device. As shown in FIG. 9, the electronic device 10 includes a liquid crystal display device 1 as a display unit inside a housing 2.
 液晶表示装置1は、図9に示すように、液晶表示パネル11と、この液晶表示パネル11の背面側に配置された光源であるバックライトユニット12とを備えている。すなわち、液晶表示装置1は、少なくともバックライトユニット12の光を選択的に透過させて透過表示を行うように構成されている。 As shown in FIG. 9, the liquid crystal display device 1 includes a liquid crystal display panel 11 and a backlight unit 12 that is a light source disposed on the back side of the liquid crystal display panel 11. That is, the liquid crystal display device 1 is configured to perform transmissive display by selectively transmitting at least light from the backlight unit 12.
 液晶表示パネル11は、図9に示すように、第1基板であるTFT基板13と、TFT基板13に対向して配置された第2基板である対向基板14とを有している。TFT基板13と対向基板14との間には、液晶層15がシール部材16によって封入されている。 As shown in FIG. 9, the liquid crystal display panel 11 includes a TFT substrate 13 that is a first substrate, and a counter substrate 14 that is a second substrate disposed to face the TFT substrate 13. A liquid crystal layer 15 is sealed between the TFT substrate 13 and the counter substrate 14 by a seal member 16.
 液晶表示パネル11は、表示領域(図示省略)と、その周囲に設けられた額縁状の非表示領域(図示省略)とを有している。表示領域には、マトリクス状に設けられた複数の画素18が形成されている。ここで、画素18とは、表示を制御するための最小単位である。 The liquid crystal display panel 11 has a display area (not shown) and a frame-like non-display area (not shown) provided around the display area. A plurality of pixels 18 provided in a matrix are formed in the display area. Here, the pixel 18 is a minimum unit for controlling display.
 TFT基板13は、アクティブマトリクス基板によって構成されている。TFT基板13は、透明基板としてのガラス基板(図示省略)を有している。図1に示すように、上記ガラス基板上には、互いに並行して延びる複数のソース配線23と、ソース配線23に交差して延びる複数のゲート配線22とが形成されている。 The TFT substrate 13 is composed of an active matrix substrate. The TFT substrate 13 has a glass substrate (not shown) as a transparent substrate. As shown in FIG. 1, a plurality of source lines 23 extending in parallel with each other and a plurality of gate lines 22 extending so as to intersect the source lines 23 are formed on the glass substrate.
 すなわち、複数のゲート配線22及び複数のソース配線23は、全体として格子状に形成され、ゲート配線22及びソース配線23に矩形状に囲まれた領域に画素18がそれぞれ形成されている。ゲート配線22及びソース配線23は、それぞれ、例えばAl、Cu、Mo及びTi等のうち1種からなる単層膜又は複数種からなる複数層膜によって構成されている。 That is, the plurality of gate lines 22 and the plurality of source lines 23 are formed in a lattice shape as a whole, and the pixels 18 are formed in regions surrounded by the gate lines 22 and the source lines 23 in a rectangular shape. Each of the gate wiring 22 and the source wiring 23 is configured by a single-layer film made of one type or a multi-layer film made of a plurality of types, for example, among Al, Cu, Mo, Ti, and the like.
 各画素18には、ゲート配線22及びソース配線23の交差部分近傍にTFT(薄膜トランジスタ)20がそれぞれ設けられている。TFT20には、上記ゲート配線22及びソース配線23が接続されている。本実施形態1におけるTFT20は、ボトムゲート型TFTであって、ゲート配線22から分岐して形成されたゲート電極26と、ゲート電極26にゲート絶縁膜(図示省略)を介して対向する半導体層(図示省略)と、ソース配線23から分岐して形成されたソース電極25と、ドレイン電極29とを有している。 Each pixel 18 is provided with a TFT (thin film transistor) 20 in the vicinity of the intersection of the gate wiring 22 and the source wiring 23. The gate wiring 22 and the source wiring 23 are connected to the TFT 20. The TFT 20 in the first embodiment is a bottom gate type TFT, and a gate electrode 26 branched from the gate wiring 22 and a semiconductor layer (not shown) facing the gate electrode 26 via a gate insulating film (not shown). A source electrode 25 that is branched from the source wiring 23, and a drain electrode 29.
 ゲート電極26及びゲート配線22は、ガラス基板上に形成されると共に上記ゲート絶縁膜によって覆われている。上記ゲート絶縁膜は、例えばSiNx(窒化シリコン)及びSiO等のうち1種からなる単層膜又は複数種からなる複数層膜によって構成されている。上記ゲート絶縁膜の表面には、上記半導体層が例えば矩形島状に形成されている。上記半導体層は、例えばa-Si等の半導体によって形成されている。 The gate electrode 26 and the gate wiring 22 are formed on a glass substrate and covered with the gate insulating film. The gate insulating film is composed of, for example, a single-layer film made of one of SiNx (silicon nitride) and SiO 2 or a multi-layer film made of a plurality of kinds. On the surface of the gate insulating film, the semiconductor layer is formed in a rectangular island shape, for example. The semiconductor layer is formed of a semiconductor such as a-Si, for example.
 上記半導体層及びゲート電極26には、ソース電極25の一部及びドレイン電極29の一部がそれぞれ重なっている。また、ソース電極25及びドレイン電極29等は、層間絶縁膜(図示省略)によって覆われている。上記層間絶縁膜は、例えばSiNx等によって形成されている。 A part of the source electrode 25 and a part of the drain electrode 29 are overlapped with the semiconductor layer and the gate electrode 26, respectively. The source electrode 25, the drain electrode 29, and the like are covered with an interlayer insulating film (not shown). The interlayer insulating film is made of, for example, SiNx.
 また、上記複数の画素18には、当該画素18に設けられているTFT20のドレイン電極29に接続された画素電極30が形成されている。画素電極30は、上記層間絶縁膜の表面に形成され、例えばITO(Indium Tin Oxide)等の透明導電性膜によって構成されている。 Further, the plurality of pixels 18 are formed with pixel electrodes 30 connected to the drain electrodes 29 of the TFTs 20 provided in the pixels 18. The pixel electrode 30 is formed on the surface of the interlayer insulating film, and is composed of a transparent conductive film such as ITO (Indium Tin Oxide).
 一方、対向基板14には、上記複数の画素電極30に共通して設けられた共通電極(図示省略)が形成されている。上記共通電極も、画素電極30と同様に例えばITO等の透明導電性膜によって形成されている。そうして、所定電位の共通電極と、各画素18の画素電極30との電位差を制御することによって、液晶層15を各画素18毎に配向制御するようになっている。 On the other hand, a common electrode (not shown) provided in common with the plurality of pixel electrodes 30 is formed on the counter substrate 14. Similar to the pixel electrode 30, the common electrode is also formed of a transparent conductive film such as ITO. Thus, the orientation of the liquid crystal layer 15 is controlled for each pixel 18 by controlling the potential difference between the common electrode having a predetermined potential and the pixel electrode 30 of each pixel 18.
 <TFTの構成>
 本実施形態におけるTFT20には、ソース電極25がドレイン電極29よりも大きい第1TFT20aと、ドレイン電極29がソース電極25よりも大きい第2TFT20bとが含まれている。
<TFT configuration>
The TFT 20 in this embodiment includes a first TFT 20 a in which the source electrode 25 is larger than the drain electrode 29 and a second TFT 20 b in which the drain electrode 29 is larger than the source electrode 25.
 図1及び図2に示すように、第1TFT20aのソース電極25は、二股状に形成された一対の電極肢32と、この電極肢32の基端側に幅広に形成された基端部33とを有している。一方、第1TFT20aのドレイン電極29は、直線状に延びる直線部34を有し、この直線部34の先端が上記一対の電極肢32の間に配置されている。 As shown in FIGS. 1 and 2, the source electrode 25 of the first TFT 20 a includes a pair of electrode limbs 32 formed in a bifurcated shape, and a base end portion 33 formed wide on the base end side of the electrode limbs 32. have. On the other hand, the drain electrode 29 of the first TFT 20 a has a linear portion 34 extending linearly, and the tip of the linear portion 34 is disposed between the pair of electrode limbs 32.
 図2に示すように、ソース電極25の電極肢32の全体と、基端部33の一部とが、ゲート電極26に重なっている。そのことにより、基端部33におけるソース電極25とゲート電極26との重なり幅Aは、ドレイン電極29とゲート電極26との重なり幅Bよりも広くなっている。 As shown in FIG. 2, the entire electrode limb 32 of the source electrode 25 and a part of the base end portion 33 overlap the gate electrode 26. As a result, the overlapping width A of the source electrode 25 and the gate electrode 26 at the base end portion 33 is wider than the overlapping width B of the drain electrode 29 and the gate electrode 26.
 一方、第2TFT20bのドレイン電極29は、二股状に形成された一対の電極肢36と、この電極肢36の基端側に幅広に形成された基端部37とを有している。一方、第2TFT20bのソース電極25は、直線状に延びる直線部38を有し、この直線部38の先端が上記一対の電極肢36の間に配置されている。 On the other hand, the drain electrode 29 of the second TFT 20b has a pair of electrode limbs 36 formed in a bifurcated shape and a base end portion 37 formed wide on the base end side of the electrode limbs 36. On the other hand, the source electrode 25 of the second TFT 20 b has a linear portion 38 that extends linearly, and the tip of the linear portion 38 is disposed between the pair of electrode limbs 36.
 図2に示すように、ドレイン電極29の電極肢36の全体と、基端部37の一部とが、ゲート電極26に重なっている。そのことにより、ソース電極25とゲート電極26との重なり幅Aは、基端部37におけるドレイン電極29とゲート電極26との重なり幅Bよりも狭くなっている。 As shown in FIG. 2, the entire electrode limb 36 of the drain electrode 29 and a part of the base end portion 37 overlap the gate electrode 26. As a result, the overlap width A between the source electrode 25 and the gate electrode 26 is narrower than the overlap width B between the drain electrode 29 and the gate electrode 26 at the base end portion 37.
 <画素の配列構成>
 そして、図1に示すように、ゲート配線22に沿って並ぶ複数の画素18からなる画素列19には、第1TFT20aが形成された複数の第1画素18aと、第2TFT20bが形成された複数の第2画素18bとが含まれている。
<Pixel arrangement configuration>
As shown in FIG. 1, a plurality of first pixels 18 a in which first TFTs 20 a are formed and a plurality of pixels in which second TFTs 20 b are formed are arranged in a pixel column 19 including a plurality of pixels 18 arranged along the gate wiring 22. The second pixel 18b is included.
 さらに、各画素列19には、1つの第1画素18aと、1つの第2画素18bとが、ゲート配線22に沿って交互に配置されている。一方、ソース配線23に沿った方向には、複数の第1画素18a又は複数の第2画素18bが並んで配置されている。 Further, in each pixel column 19, one first pixel 18 a and one second pixel 18 b are alternately arranged along the gate wiring 22. On the other hand, in the direction along the source wiring 23, a plurality of first pixels 18a or a plurality of second pixels 18b are arranged side by side.
 尚、第1画素18a及び第2画素18bの他の配置例としては、各画素列19において、例えば2つの第1画素18aと、2つの第2画素18bとが、ゲート配線22に沿って交互に配置されていてもよい。すなわち、画素列19には、少なくとも1つの第1画素18aと、この少なくとも1つの第1画素18aと同じ数の第2画素18bとが、ゲート配線22に沿って交互に配置されるようにしてもよい。 As another arrangement example of the first pixel 18 a and the second pixel 18 b, for example, in each pixel column 19, two first pixels 18 a and two second pixels 18 b are alternately arranged along the gate wiring 22. May be arranged. That is, at least one first pixel 18 a and the same number of second pixels 18 b as the at least one first pixel 18 a are alternately arranged along the gate wiring 22 in the pixel column 19. Also good.
 <交流駆動制御回路>
 液晶表示装置1は、さらに、1つのゲート配線22を走査する期間において、複数のソース配線23に互いに同じ極性の信号電圧を印加する交流駆動制御部40を備えている。交流駆動制御部40は、1つのゲート配線22を走査する期間毎に、複数のソース配線23に印加する信号電圧の極性を反転させるように構成されている。つまり、液晶表示装置1の駆動方式は、1H期間(1水平走査期間)毎に信号電圧の極性を反転させる1Hライン反転駆動方式となっている。
<AC drive control circuit>
The liquid crystal display device 1 further includes an AC drive control unit 40 that applies signal voltages having the same polarity to the plurality of source lines 23 during a period of scanning one gate line 22. The AC drive control unit 40 is configured to invert the polarity of the signal voltage applied to the plurality of source lines 23 for each period of scanning one gate line 22. That is, the driving method of the liquid crystal display device 1 is a 1H line inversion driving method in which the polarity of the signal voltage is inverted every 1H period (one horizontal scanning period).
 尚、交流駆動制御部40は、複数本のゲート配線22を走査する毎に信号電圧の極性を反転するように構成してもよい。つまり、交流駆動制御部40は、nHライン反転駆動するように構成してもよい。したがって、交流駆動制御部40は、少なくとも1つのゲート配線22を走査する期間のそれぞれにおいて、複数のソース配線23に互いに同じ極性の信号電圧を印加するように構成することが可能である。 The AC drive control unit 40 may be configured to invert the polarity of the signal voltage every time the plurality of gate wirings 22 are scanned. That is, the AC drive control unit 40 may be configured to perform nH line inversion driving. Therefore, the AC drive control unit 40 can be configured to apply signal voltages having the same polarity to the plurality of source lines 23 in each of the periods in which at least one gate line 22 is scanned.
  -製造方法-
 次に、上記液晶表示装置1の製造方法について説明する。
-Production method-
Next, a method for manufacturing the liquid crystal display device 1 will be described.
 液晶表示装置1は、複数のTFT20等を形成して製造したTFT基板13と、共通電極等を形成した対向基板14とを、液晶層15及びシール部材16を介して貼り合わせることによって液晶表示パネル11を製造し、この液晶表示パネル11にバックライトユニット12を対向配置させることによって製造する。さらに、この液晶表示装置1を、他の機能回路等と共に筐体2内に組み込むことによって、上記電子機器10を製造する。 The liquid crystal display device 1 is a liquid crystal display panel in which a TFT substrate 13 manufactured by forming a plurality of TFTs 20 and the like and a counter substrate 14 formed with a common electrode and the like are bonded together via a liquid crystal layer 15 and a seal member 16. 11 and the backlight unit 12 is disposed opposite to the liquid crystal display panel 11. Further, the electronic apparatus 10 is manufactured by incorporating the liquid crystal display device 1 into the housing 2 together with other functional circuits and the like.
 液晶表示装置の製造方法には、バックライトユニット12が対向配置された液晶表示パネル11について、フリッカを抑制する目的で、フリッカパターンを画面に表示させて、信号電圧と共通電極電圧とを初期調整する電圧調整工程が含まれる。 In the method of manufacturing a liquid crystal display device, a flicker pattern is displayed on the screen for the purpose of suppressing flickering on the liquid crystal display panel 11 with the backlight unit 12 facing each other, and the signal voltage and the common electrode voltage are initially adjusted. Voltage adjusting step is included.
 ここで、図3は、フリッカパターンを模式的に示す平面図である。図3に示すように、フリッカパターン42とは、一方の極性の信号電圧が印加された画素18を黒表示(Black)すると共に、他方の極性の画素18を中間調表示(Gray)したパターンである。フリッカパターン42は、表示画面にフリッカが最も視認されやすい表示パターンであるため、対向基板14における共通電極に印加する電圧(共通電極電圧)を調整する際の表示パターンとして用いられる。 Here, FIG. 3 is a plan view schematically showing a flicker pattern. As shown in FIG. 3, the flicker pattern 42 is a pattern in which the pixel 18 to which a signal voltage of one polarity is applied is displayed in black (Black), and the pixel 18 in the other polarity is displayed in halftone (Gray). is there. Since the flicker pattern 42 is a display pattern in which flicker is most easily recognized on the display screen, the flicker pattern 42 is used as a display pattern when adjusting the voltage (common electrode voltage) applied to the common electrode in the counter substrate 14.
 本実施形態におけるフリッカパターン42は、例えば、図3に示すように、黒表示させた画素列19と、中間調表示させた画素列19とを1列ずつ交互に配置したストライプ模様となっている。そして、各画素列19における信号電圧の極性は、それぞれフレーム毎に反転される。すなわち、n-1フレームにおいて各画素18における極性が「----・・・」である画素列19は、nフレームにおいて「++++・・・」となり、n+1フレームにおいて「----・・・」となる。 For example, as shown in FIG. 3, the flicker pattern 42 in the present embodiment is a stripe pattern in which the pixel columns 19 displayed in black and the pixel columns 19 displayed in halftone are alternately arranged one by one. . The polarity of the signal voltage in each pixel column 19 is inverted for each frame. That is, the pixel column 19 in which the polarity of each pixel 18 in the n−1 frame is “−−−−...” Becomes “+++...” In the n frame and “−−−−.・ 」
 そして、電圧調整工程では、液晶表示装置1の表示画面にフリッカパターン42を表示させた状態で、その表示画面におけるフリッカが最小となるように、上記共通電極電圧の大きさを調整する。 In the voltage adjustment step, the magnitude of the common electrode voltage is adjusted so that the flicker on the display screen is minimized while the flicker pattern 42 is displayed on the display screen of the liquid crystal display device 1.
  -実施形態1の効果-
 したがって、本実施形態1によれば、各TFT20のW長を大きく確保しながらも、フリッカを大幅に抑制することができる。以下、本発明の効果について詳述する。
-Effect of Embodiment 1-
Therefore, according to the first embodiment, flicker can be significantly suppressed while ensuring a large W length of each TFT 20. Hereinafter, the effects of the present invention will be described in detail.
 本発明者らは、ソース電極の形状がドレイン電極と異なるTFTを備えた液晶表示装置について、鋭意研究を重ねた結果、当該ソース電極(ソース配線)に印加する信号電圧の極性を反転させると、その極性の反転に応じて、当該TFTに生じるオフリーク電流の量が変化することを見出した。そして、そのオフリーク電流の変化に伴って当該TFTが設けられている画素の輝度が変化する結果、フリッカが視認されやすくなることが分かった。 As a result of intensive studies on a liquid crystal display device having a TFT whose source electrode shape is different from that of the drain electrode, the inventors have reversed the polarity of the signal voltage applied to the source electrode (source wiring). It was found that the amount of off-leakage current generated in the TFT changes according to the reversal of the polarity. As a result of the change in the luminance of the pixel provided with the TFT along with the change in the off-leakage current, it has been found that flicker is easily visually recognized.
 ここで、図4は、TFT20の概略構成を示す断面図である。図4に示すように、TFT20は、ガラス基板17上に形成されたゲート電極26と、ゲート電極26を覆うゲート絶縁膜27と、ゲート電極26の中央に対向配置されたa-Siからなる半導体層28と、ゲート電極26の一端側に対向するソース電極25と、ゲート電極26の他端側に対向するドレイン電極29とを有している。 Here, FIG. 4 is a cross-sectional view showing a schematic configuration of the TFT 20. As shown in FIG. 4, the TFT 20 includes a gate electrode 26 formed on the glass substrate 17, a gate insulating film 27 covering the gate electrode 26, and a semiconductor made of a-Si opposed to the center of the gate electrode 26. It has a layer 28, a source electrode 25 facing one end side of the gate electrode 26, and a drain electrode 29 facing the other end side of the gate electrode 26.
 バックライトユニット12の光の一部は、ガラス基板17を透過して、ソース電極25又はドレイン電極29とゲート電極26との間に入射する。そして、図4に矢印で示すように、この入射光は、ソース電極25又はドレイン電極29とゲート電極26との間で反射を繰り返して半導体層28に入射する。その結果、TFT20にオフリーク電流が生じることとなる。 Part of the light of the backlight unit 12 passes through the glass substrate 17 and enters between the source electrode 25 or the drain electrode 29 and the gate electrode 26. Then, as indicated by an arrow in FIG. 4, the incident light repeatedly reflects between the source electrode 25 or the drain electrode 29 and the gate electrode 26 and enters the semiconductor layer 28. As a result, an off-leakage current is generated in the TFT 20.
 図5は、第1電極51と、第1電極51よりも小さい第2電極52とをソース電極又はドレイン電極として有するTFT50を模式的に示す平面図である。TFT50には、第1電極51と第2電極52との間に半導体層54が形成されている。 FIG. 5 is a plan view schematically showing a TFT 50 having a first electrode 51 and a second electrode 52 smaller than the first electrode 51 as a source electrode or a drain electrode. In the TFT 50, a semiconductor layer 54 is formed between the first electrode 51 and the second electrode 52.
 図5に示すように、例えば、第1電極51とゲート電極53との重なり幅Dが、第2電極52とゲート電極53との重なり幅dよりも広いTFT50については、第1電極51に+極性の信号電圧が印加されている場合に、第1電極51とゲート電極53との間に多くの光が入射することから、オフリーク電流が大きく発生すると考えられる。一方、第2電極52に+極性の信号電圧が印加されている場合には、第2電極52とゲート電極53との間に入射する光が少ないことから、オフリーク電流が小さくなると考えられる。 As shown in FIG. 5, for example, for the TFT 50 in which the overlap width D between the first electrode 51 and the gate electrode 53 is wider than the overlap width d between the second electrode 52 and the gate electrode 53, Since a large amount of light is incident between the first electrode 51 and the gate electrode 53 when a polar signal voltage is applied, it is considered that a large off-leakage current is generated. On the other hand, when a + polarity signal voltage is applied to the second electrode 52, the amount of light incident between the second electrode 52 and the gate electrode 53 is small, so the off-leakage current is considered to be small.
 ここで、U字型に形成された第1電極51と、I字型に形成された第2電極52とをソース電極又はドレイン電極として有するTFT50について、実際に実施した実施例について説明する。 Here, an actual implementation example of the TFT 50 having the first electrode 51 formed in a U-shape and the second electrode 52 formed in an I-shape as a source electrode or a drain electrode will be described.
 実施例に係るTFT50は、半導体層54のL長が4μmでありW長が50μmである。U字状の第1電極51とゲート電極53との重なり幅Dは26μmであり、I字状の第2電極52とゲート電極53との重なり幅dは6μmである。ゲート電極には-20~20Vの電圧を印加した。また、ドレイン電極への印加電圧を4.1Vとし、ソース電極への印加電圧を0Vとした。 In the TFT 50 according to the example, the L length of the semiconductor layer 54 is 4 μm and the W length is 50 μm. The overlapping width D between the U-shaped first electrode 51 and the gate electrode 53 is 26 μm, and the overlapping width d between the I-shaped second electrode 52 and the gate electrode 53 is 6 μm. A voltage of −20 to 20 V was applied to the gate electrode. The applied voltage to the drain electrode was 4.1V, and the applied voltage to the source electrode was 0V.
 そして、実施例1では、U字状の第1電極51をソース電極にすると共に、I字状の第2電極52をドレイン電極にした構成において、1750cd/mの強度の光を照射した明状態X1と、光を照射しない暗状態Y1とについて、ゲート電圧に対するドレイン電流の変化を測定した。その測定結果を図6のグラフに示す。 In Example 1, the U-shaped first electrode 51 is used as a source electrode and the I-shaped second electrode 52 is used as a drain electrode, and light having an intensity of 1750 cd / m 2 is irradiated. For the state X1 and the dark state Y1 where no light is irradiated, the change in drain current with respect to the gate voltage was measured. The measurement results are shown in the graph of FIG.
 実施例2では、U字状の第1電極51をドレイン電極にすると共に、I字状の第2電極52をソース電極にした構成において、1750cd/mの強度の光を照射した明状態X2と、光を照射しない暗状態Y2とについて、ゲート電圧に対するドレイン電流の変化を測定した。その測定結果を図7のグラフに示す。 In the second embodiment, in the configuration in which the U-shaped first electrode 51 is used as the drain electrode and the I-shaped second electrode 52 is used as the source electrode, the light state X2 is irradiated with light having an intensity of 1750 cd / m 2. The change in drain current with respect to the gate voltage was measured for the dark state Y2 where no light was irradiated. The measurement results are shown in the graph of FIG.
 実施例1及び実施例2について、暗状態Y1,Y2では、図6及び図7に破線で示すように、TFT50に照射される光自体が少ないため、それぞれオフリーク電流を示すドレイン電流値は比較的小さい。 Regarding Example 1 and Example 2, in the dark states Y1 and Y2, as indicated by broken lines in FIGS. 6 and 7, since the light itself applied to the TFT 50 is small, the drain current value indicating the off-leakage current is relatively low. small.
 実施例1について、明状態X1では、I字状の第2電極(ドレイン電流)52への印加電圧が、U字状の第1電極(ソース電極)51よりも大きいものの、その第2電極52とゲート電極53との重なり幅が、第1電極51とゲート電極53との重なり幅よりも小さいため、図6に実線で示すように、オフリーク電流は比較的小さくなった。 Regarding Example 1, in the bright state X1, although the voltage applied to the I-shaped second electrode (drain current) 52 is larger than the U-shaped first electrode (source electrode) 51, the second electrode 52 Since the overlap width between the first electrode 51 and the gate electrode 53 is smaller than the overlap width between the first electrode 51 and the gate electrode 53, the off-leakage current is relatively small as shown by the solid line in FIG.
 一方、実施例2について、明状態X2では、U字状の第1電極(ドレイン電極)51への印加電圧が、I字状の第2電極(ソース電極)52よりも大きく、且つ、その印加電圧が大きいU字状の第1電極51とゲート電極53との重なり幅が、第2電極52とゲート電極53との重なり幅よりも大きいため、図7に実線で示すように、オフリーク電流は比較的大きくなった。 On the other hand, in Example 2, in the bright state X2, the applied voltage to the U-shaped first electrode (drain electrode) 51 is larger than that of the I-shaped second electrode (source electrode) 52, and the application thereof Since the overlapping width between the U-shaped first electrode 51 and the gate electrode 53 having a large voltage is larger than the overlapping width between the second electrode 52 and the gate electrode 53, as shown by the solid line in FIG. It became relatively large.
 このオフリーク電流(ドレイン電流値)を実施例1及び2で比較したものを図8のグラフに示す。図8に示すように、実施例2の明状態X2におけるオフリーク電流X2は、実施例1の明状態X1におけるオフリーク電流X1よりも大きいことが分かる。一方、実施例1の暗状態Y1におけるオフリーク電流Y1と、実施例2における暗状態Y2におけるオフリーク電流Y2とは、互いにほぼ同程度であって、上記X1及びX2よりも小さいことが確認された。 The graph of FIG. 8 shows a comparison of the off-leakage current (drain current value) in Examples 1 and 2. As shown in FIG. 8, it can be seen that the off-leakage current X2 in the bright state X2 of Example 2 is larger than the off-leakage current X1 in the bright state X1 of Example 1. On the other hand, it was confirmed that the off-leakage current Y1 in the dark state Y1 of Example 1 and the off-leakage current Y2 in the dark state Y2 of Example 2 are substantially the same and smaller than X1 and X2.
 以上より、例えば図5に示すように、第1電極51とゲート電極53との重なり幅Dが、第2電極52とゲート電極53との重なり幅dよりも広いTFT50については、第1電極51に+極性の信号電圧が印加されている場合にオフリーク電流が大きくなる一方、第2電極52に+極性の信号電圧が印加されている場合にオフリーク電流が小さくなることが確認できた。 As described above, for example, as shown in FIG. 5, for the TFT 50 in which the overlap width D between the first electrode 51 and the gate electrode 53 is wider than the overlap width d between the second electrode 52 and the gate electrode 53, It can be confirmed that the off-leakage current increases when a + polarity signal voltage is applied to the second electrode 52, while the off-leakage current decreases when the + polarity signal voltage is applied to the second electrode 52.
 次に、図10は、本実施形態1における液晶表示装置1の1Hライン反転駆動を示す平面図である。上記液晶表示装置1については、図10の上側部分に示すように、あるn-1フレームの黒表示する画素列19aを走査する1H期間において、ソース配線23に印加する信号電圧を-極性とする。次の中間調表示する画素列19bを走査する1H期間には、ソース配線23に印加する信号電圧を反転して+極性とする。ここで、図10における各画素18の矢印は、オフリーク電流が流れる方向を示している。 Next, FIG. 10 is a plan view showing 1H line inversion driving of the liquid crystal display device 1 according to the first embodiment. In the liquid crystal display device 1, as shown in the upper part of FIG. 10, the signal voltage applied to the source line 23 is set to −polarity in the 1H period of scanning the pixel column 19 a for black display of a certain n−1 frame. . In the 1H period during which the next halftone display pixel row 19b is scanned, the signal voltage applied to the source line 23 is inverted to have a positive polarity. Here, the arrow of each pixel 18 in FIG. 10 indicates the direction in which the off-leakage current flows.
 このn-1フレームにおいて、視認される中間調表示をしている画素列19bでは、第1画素18aのオフリーク電流が比較的小さくなり(S)、第2画素18bのオフリーク電流が比較的大きくなる(L)。したがって、画面全体において中間調表示する画素には、オフリーク電流が比較的小さい(S)第1画素18aと、オフリーク電流が比較的大きい(L)第2画素18bとが同数含まれることとなる。 In the n-1 frame, in the pixel column 19b that is visually recognized as a halftone display, the off-leak current of the first pixel 18a is relatively small (S), and the off-leak current of the second pixel 18b is relatively large. (L). Therefore, the same number of pixels with half-tone display on the entire screen includes the first pixel 18a having a relatively small off-leakage current (S) and the second pixel 18b having a relatively large off-leakage current (L).
 図10の下側部分に示すように、次のnフレームにおいて中間調表示している画素列19bでは、第1画素18aのオフリーク電流が比較的大きくなり(L)、第2画素18bのオフリーク電流が比較的小さくなる(S)。したがって、画面全体において中間調表示する画素には、オフリーク電流が比較的大きい(L)第1画素18aと、オフリーク電流が比較的小さい(S)第2画素18bとが同数含まれることとなる。 As shown in the lower part of FIG. 10, in the pixel column 19b that is displayed in halftone in the next n frame, the off-leak current of the first pixel 18a becomes relatively large (L), and the off-leak current of the second pixel 18b. Becomes relatively small (S). Therefore, the same number of pixels with half-tone display on the entire screen includes the first pixels 18a having a relatively large off-leakage current (L) and the second pixels 18b having a relatively small off-leakage current (S).
 すなわち、本実施形態によれば、何れのフレームにおいても、オフリーク電流が比較的小さい(S)画素18と、オフリーク電流が比較的大きい(L)画素18とが互いに同じ数だけ含まれる結果、フレームが変化する前後において表示画面全体の総リーク量が同じになるため、フリッカを大幅に抑制することができる。よって、本実施形態によれば、各TFT20のW長を大きく確保しながらも、フリッカを大幅に抑制できることとなる。 That is, according to this embodiment, in any frame, as a result of including the same number of (S) pixels 18 having a relatively small off-leakage current and (L) pixels 18 having a relatively large off-leakage current. Since the total leak amount of the entire display screen is the same before and after the change, flicker can be significantly suppressed. Therefore, according to the present embodiment, flicker can be significantly suppressed while ensuring a large W length of each TFT 20.
 一方、図11は、比較例としての液晶表示装置の1Hライン反転駆動を示す平面図である。この比較例では、全ての画素118が同じ構成をしており、各ソース電極125が全てU字状に形成される一方、各ドレイン電極129が全てI字状に形成されている。 On the other hand, FIG. 11 is a plan view showing 1H line inversion driving of a liquid crystal display device as a comparative example. In this comparative example, all the pixels 118 have the same configuration, and each source electrode 125 is formed in a U shape, while each drain electrode 129 is formed in an I shape.
 そして、この液晶表示装置については、図11の上側部分に示すように、あるn-1フレームの黒表示する画素列119aを走査する1H期間において、ソース配線123に印加する信号電圧を-極性とする。次の中間調表示する画素列119bを走査する1H期間には、ソース配線123に印加する信号電圧を反転して+極性とする。ここで、図11における各画素118の矢印は、オフリーク電流が流れる方向を示している。 In this liquid crystal display device, as shown in the upper part of FIG. 11, the signal voltage applied to the source line 123 is set to -polarity in the 1H period during which the pixel column 119a for black display of a certain n-1 frame is scanned. To do. In the 1H period during which the next pixel row 119b for halftone display is scanned, the signal voltage applied to the source wiring 123 is inverted to have a positive polarity. Here, the arrow of each pixel 118 in FIG. 11 indicates the direction in which the off-leakage current flows.
 このn-1フレームにおいて、視認される中間調表示をしている画素列119bでは、各画素118のオフリーク電流が比較的小さくなる(S)。したがって、画面全体では、全てオフリーク電流が比較的小さい(S)画素118によって中間調表示されることとなる。 In this n-1 frame, in the pixel column 119b displaying a halftone that is visually recognized, the off-leak current of each pixel 118 is relatively small (S). Accordingly, the entire screen is displayed in halftone by the (S) pixel 118 having a relatively small off-leakage current.
 図11の下側部分に示すように、次のnフレームにおいて中間調表示している画素列119bでは、各画素118のオフリーク電流が比較的大きくなる(L)。したがって、画面全体では、全てオフリーク電流が比較的大きい(L)画素118によって中間調表示されることとなる。 As shown in the lower part of FIG. 11, the off-leak current of each pixel 118 is relatively large (L) in the pixel column 119b displaying halftone in the next n frames. Therefore, the entire screen is displayed in halftone by the (L) pixel 118 having a relatively large off-leakage current.
 すなわち、この比較例としての液晶表示装置では、フレームが変化する前後において、中間調表示する全ての画素118のオフリーク電流が比較的小さい(S)状態と、中間調表示する全ての画素118のオフリーク電流が比較的大きい(L)状態とが交互に切り替わることになるため、フリッカが視認されやすくなってしまう。 That is, in the liquid crystal display device as the comparative example, the off-leak current of all the pixels 118 that perform halftone display is relatively small (S) before and after the frame changes, and the off-leakage of all the pixels 118 that perform halftone display. Since the state where the current is relatively large (L) is alternately switched, the flicker is easily visually recognized.
 ここで、図12は、比較例における液晶表示装置の輝度の時間変化についてのシミュレーション結果を示すグラフである。図13は、本実施形態における液晶表示装置1の輝度の時間変化についてのシミュレーション結果を示すグラフである。 Here, FIG. 12 is a graph showing a simulation result with respect to a temporal change in luminance of the liquid crystal display device in the comparative example. FIG. 13 is a graph showing a simulation result with respect to a temporal change in luminance of the liquid crystal display device 1 in the present embodiment.
 図11に示すように、n-1フレームにおける総リーク量と、nフレームにおける総リーク量とが異なる場合には、図12のグラフに示すように、輝度変化の波形は歪んだ形状となる。一方、図10に示すように、n-1フレームにおける総リーク量と、nフレームにおける総リーク量とが同じである場合には、図13のグラフに示すように、1フレーム期間の波形が対称な形状となることが分かる。 As shown in FIG. 11, when the total leak amount in the n-1 frame is different from the total leak amount in the n frame, the waveform of the luminance change has a distorted shape as shown in the graph of FIG. On the other hand, as shown in FIG. 10, when the total leak amount in the (n−1) frame is the same as the total leak amount in the n frame, the waveform in one frame period is symmetric as shown in the graph of FIG. It turns out that it will become a shape.
 人間の目には、図12のように歪んだ輝度波形を示す比較例の表示が、駆動周波数(本実施形態では20Hz)の半分の周波数(つまり10Hz)で認識されるため、フリッカは視認され易くなる。これに対し、図13に示す実施例の表示では、駆動周波数と同じ周波数(つまり20Hz)として認識されるため、フリッカを視認され難くすることができる。 Since the display of the comparative example showing the distorted luminance waveform as shown in FIG. 12 is recognized by the human eye at a half frequency (that is, 10 Hz) of the drive frequency (20 Hz in this embodiment), flicker is visually recognized. It becomes easy. On the other hand, in the display of the embodiment shown in FIG. 13, since it is recognized as the same frequency as the drive frequency (that is, 20 Hz), flicker can be made difficult to be visually recognized.
 《発明の実施形態2》
 図14~図16は、本発明の実施形態2を示している。
<< Embodiment 2 of the Invention >>
14 to 16 show Embodiment 2 of the present invention.
 図14は、本実施形態2におけるTFT基板13の一部を拡大してを示す平面図である。図15は、本実施形態2における液晶表示装置1の1Hドット反転駆動を示す平面図である。図16は、比較例としての液晶表示装置の1Hドット反転駆動を示す平面図である。尚、以降の各実施形態では、図1~図13と同じ部分については同じ符号を付して、その詳細な説明を省略する。 FIG. 14 is a plan view showing an enlarged part of the TFT substrate 13 in the second embodiment. FIG. 15 is a plan view showing 1H dot inversion driving of the liquid crystal display device 1 according to the second embodiment. FIG. 16 is a plan view showing 1H dot inversion driving of a liquid crystal display device as a comparative example. In the following embodiments, the same portions as those in FIGS. 1 to 13 are denoted by the same reference numerals, and detailed description thereof is omitted.
 上記実施形態1では、交流駆動制御部40が1Hライン反転駆動を行う例について説明したが、交流駆動制御部40は、これに限らず、少なくとも1つのゲート配線22を走査する期間毎に、複数のソース配線23に印加する信号電圧の極性を反転させるように構成してもよい。本実施形態2における交流駆動制御部40は、1Hドット反転駆動を行うように構成されている。 In the first embodiment, an example in which the AC drive control unit 40 performs 1H line inversion drive has been described. However, the AC drive control unit 40 is not limited to this, and a plurality of AC drive control units 40 are provided for each period of scanning at least one gate wiring 22. The polarity of the signal voltage applied to the source wiring 23 may be reversed. The AC drive control unit 40 in the second embodiment is configured to perform 1H dot inversion drive.
 本実施形態2における電子機器10は、図9に示すように、筐体2の内部に表示ユニットとしての液晶表示装置1を備えている。電子機器10は例えば液晶テレビやスマートフォン等のモバイル機器その他の電子機器である。 The electronic device 10 according to the second embodiment includes a liquid crystal display device 1 as a display unit inside a housing 2 as shown in FIG. The electronic device 10 is, for example, a mobile device such as a liquid crystal television or a smartphone or other electronic devices.
 液晶表示装置1は、図9に示すように、液晶表示パネル11と、この液晶表示パネル11の背面側に配置された光源であるバックライトユニット12とを備えている。すなわち、液晶表示装置1は、少なくともバックライトユニット12の光を選択的に透過させて透過表示を行うように構成されている。 As shown in FIG. 9, the liquid crystal display device 1 includes a liquid crystal display panel 11 and a backlight unit 12 that is a light source disposed on the back side of the liquid crystal display panel 11. That is, the liquid crystal display device 1 is configured to perform transmissive display by selectively transmitting at least light from the backlight unit 12.
 液晶表示パネル11は、図9に示すように、第1基板であるTFT基板13と、TFT基板13に対向して配置された第2基板である対向基板14とを有している。TFT基板13と対向基板14との間には、液晶層15がシール部材16によって封入されている。 As shown in FIG. 9, the liquid crystal display panel 11 includes a TFT substrate 13 that is a first substrate, and a counter substrate 14 that is a second substrate disposed to face the TFT substrate 13. A liquid crystal layer 15 is sealed between the TFT substrate 13 and the counter substrate 14 by a seal member 16.
 液晶表示パネル11は、表示領域(図示省略)と、その周囲に設けられた額縁状の非表示領域(図示省略)とを有している。表示領域には、マトリクス状に設けられた複数の画素18が形成されている。 The liquid crystal display panel 11 has a display area (not shown) and a frame-like non-display area (not shown) provided around the display area. A plurality of pixels 18 provided in a matrix are formed in the display area.
 TFT基板13は、アクティブマトリクス基板によって構成されている。TFT基板13は、透明基板としてのガラス基板(図示省略)を有している。図14に示すように、上記ガラス基板上には、互いに並行して延びる複数のソース配線23と、ソース配線23に交差して延びる複数のゲート配線22とが形成されている。 The TFT substrate 13 is composed of an active matrix substrate. The TFT substrate 13 has a glass substrate (not shown) as a transparent substrate. As shown in FIG. 14, a plurality of source lines 23 extending in parallel to each other and a plurality of gate lines 22 extending so as to cross the source lines 23 are formed on the glass substrate.
 すなわち、複数のゲート配線22及び複数のソース配線23は、全体として格子状に形成され、ゲート配線22及びソース配線23に矩形状に囲まれた領域に画素18がそれぞれ形成されている。ゲート配線22及びソース配線23は、それぞれ、例えばAl、Cu、Mo及びTi等のうち1種からなる単層膜又は複数種からなる複数層膜によって構成されている。 That is, the plurality of gate lines 22 and the plurality of source lines 23 are formed in a lattice shape as a whole, and the pixels 18 are formed in regions surrounded by the gate lines 22 and the source lines 23 in a rectangular shape. Each of the gate wiring 22 and the source wiring 23 is configured by a single-layer film made of one type or a multi-layer film made of a plurality of types, for example, among Al, Cu, Mo, Ti, and the like.
 各画素18には、ゲート配線22及びソース配線23の交差部分近傍にTFT20がそれぞれ設けられている。TFT20には、上記ゲート配線22及びソース配線23が接続されている。本実施形態2におけるTFT20は、ボトムゲート型TFTであって、ゲート配線22から分岐して形成されたゲート電極26と、ゲート電極26にゲート絶縁膜(図示省略)を介して対向する半導体層(図示省略)と、ソース配線23から分岐して形成されたソース電極25と、ドレイン電極29とを有している。 Each pixel 18 is provided with a TFT 20 in the vicinity of the intersection of the gate wiring 22 and the source wiring 23. The gate wiring 22 and the source wiring 23 are connected to the TFT 20. The TFT 20 in the second embodiment is a bottom gate type TFT, and a gate electrode 26 branched from the gate wiring 22 and a semiconductor layer (not shown) facing the gate electrode 26 via a gate insulating film (not shown). A source electrode 25 that is branched from the source wiring 23, and a drain electrode 29.
 ゲート電極26及びゲート配線22は、ガラス基板上に形成されると共に上記ゲート絶縁膜によって覆われている。上記ゲート絶縁膜は、例えばSiNx(窒化シリコン)及びSiO等のうち1種からなる単層膜又は複数種からなる複数層膜によって構成されている。上記ゲート絶縁膜の表面には、上記半導体層が例えば矩形島状に形成されている。上記半導体層は、例えばa-Si等の半導体によって形成されている。 The gate electrode 26 and the gate wiring 22 are formed on a glass substrate and covered with the gate insulating film. The gate insulating film is composed of, for example, a single-layer film made of one of SiNx (silicon nitride) and SiO 2 or a multi-layer film made of a plurality of kinds. On the surface of the gate insulating film, the semiconductor layer is formed in a rectangular island shape, for example. The semiconductor layer is formed of a semiconductor such as a-Si, for example.
 上記半導体層及びゲート電極26には、ソース電極25の一部及びドレイン電極29の一部がそれぞれ重なっている。また、ソース電極25及びドレイン電極29等は、層間絶縁膜(図示省略)によって覆われている。上記層間絶縁膜は、例えばSiNx等によって形成されている。 A part of the source electrode 25 and a part of the drain electrode 29 are overlapped with the semiconductor layer and the gate electrode 26, respectively. The source electrode 25, the drain electrode 29, and the like are covered with an interlayer insulating film (not shown). The interlayer insulating film is made of, for example, SiNx.
 また、上記複数の画素18には、当該画素18に設けられているTFT20のドレイン電極29に接続された画素電極30が形成されている。画素電極30は、上記層間絶縁膜の表面に形成され、例えばITO等の透明導電性膜によって構成されている。 Further, the plurality of pixels 18 are formed with pixel electrodes 30 connected to the drain electrodes 29 of the TFTs 20 provided in the pixels 18. The pixel electrode 30 is formed on the surface of the interlayer insulating film, and is formed of a transparent conductive film such as ITO.
 一方、対向基板14には、上記複数の画素電極30に共通して設けられた共通電極(図示省略)が形成されている。上記共通電極も、画素電極30と同様に例えばITO等の透明導電性膜によって形成されている。そうして、所定電位の共通電極と、各画素18の画素電極30との電位差を制御することによって、液晶層15を各画素18毎に配向制御するようになっている。 On the other hand, a common electrode (not shown) provided in common with the plurality of pixel electrodes 30 is formed on the counter substrate 14. Similar to the pixel electrode 30, the common electrode is also formed of a transparent conductive film such as ITO. Thus, the orientation of the liquid crystal layer 15 is controlled for each pixel 18 by controlling the potential difference between the common electrode having a predetermined potential and the pixel electrode 30 of each pixel 18.
 <TFTの構成>
 本実施形態におけるTFT20には、ソース電極25がドレイン電極29よりも大きい第1TFT20aと、ドレイン電極29がソース電極25よりも大きい第2TFT20bとが含まれている。
<TFT configuration>
The TFT 20 in this embodiment includes a first TFT 20 a in which the source electrode 25 is larger than the drain electrode 29 and a second TFT 20 b in which the drain electrode 29 is larger than the source electrode 25.
 図14及び図2に示すように、第1TFT20aのソース電極25は、二股状に形成された一対の電極肢32と、この電極肢32の基端側に幅広に形成された基端部33とを有している。一方、第1TFT20aのドレイン電極29は、直線状に延びる直線部34を有し、この直線部34の先端が上記一対の電極肢32の間に配置されている。 As shown in FIGS. 14 and 2, the source electrode 25 of the first TFT 20 a includes a pair of electrode limbs 32 formed in a bifurcated shape, and a base end portion 33 formed wide on the base end side of the electrode limbs 32. have. On the other hand, the drain electrode 29 of the first TFT 20 a has a linear portion 34 extending linearly, and the tip of the linear portion 34 is disposed between the pair of electrode limbs 32.
 図2に示すように、ソース電極25の電極肢32の全体と、基端部33の一部とが、ゲート電極26に重なっている。そのことにより、基端部33におけるソース電極25とゲート電極26との重なり幅Aは、ドレイン電極29とゲート電極26との重なり幅Bよりも広くなっている。 As shown in FIG. 2, the entire electrode limb 32 of the source electrode 25 and a part of the base end portion 33 overlap the gate electrode 26. As a result, the overlapping width A of the source electrode 25 and the gate electrode 26 at the base end portion 33 is wider than the overlapping width B of the drain electrode 29 and the gate electrode 26.
 一方、第2TFT20bのドレイン電極29は、二股状に形成された一対の電極肢36と、この電極肢36の基端側に幅広に形成された基端部37とを有している。一方、第2TFT20bのソース電極25は、直線状に延びる直線部38を有し、この直線部38の先端が上記一対の電極肢36の間に配置されている。 On the other hand, the drain electrode 29 of the second TFT 20b has a pair of electrode limbs 36 formed in a bifurcated shape and a base end portion 37 formed wide on the base end side of the electrode limbs 36. On the other hand, the source electrode 25 of the second TFT 20 b has a linear portion 38 that extends linearly, and the tip of the linear portion 38 is disposed between the pair of electrode limbs 36.
 図2に示すように、ドレイン電極29の電極肢36の全体と、基端部37の一部とが、ゲート電極26に重なっている。そのことにより、ソース電極25とゲート電極26との重なり幅Aは、基端部37におけるドレイン電極29とゲート電極26との重なり幅Bよりも狭くなっている。 As shown in FIG. 2, the entire electrode limb 36 of the drain electrode 29 and a part of the base end portion 37 overlap the gate electrode 26. As a result, the overlap width A between the source electrode 25 and the gate electrode 26 is narrower than the overlap width B between the drain electrode 29 and the gate electrode 26 at the base end portion 37.
 <画素の配列構成>
 そして、図14に示すように、ゲート配線22に沿って並ぶ複数の画素18からなる画素列19には、第1TFT20aが形成された複数の第1画素18aと、第2TFT20bが形成された複数の第2画素18bとが含まれている。
<Pixel arrangement configuration>
As shown in FIG. 14, a pixel column 19 including a plurality of pixels 18 arranged along the gate wiring 22 includes a plurality of first pixels 18 a in which the first TFTs 20 a are formed and a plurality of pixels in which the second TFTs 20 b are formed. The second pixel 18b is included.
 さらに、各画素列19には、2つの第1画素18aと、2つの第2画素18bとが、ゲート配線22に沿って交互に配置されている。一方、ソース配線23に沿った方向には、複数の第1画素18a又は複数の第2画素18bが並んで配置されている。 Further, in each pixel column 19, two first pixels 18 a and two second pixels 18 b are alternately arranged along the gate wiring 22. On the other hand, in the direction along the source wiring 23, a plurality of first pixels 18a or a plurality of second pixels 18b are arranged side by side.
 <交流駆動制御回路>
 液晶表示装置1は、さらに、1つのゲート配線22を走査する期間において、互いに隣り合うソース配線23に互いに異なる極性の信号電圧を印加する交流駆動制御部40を備えている。交流駆動制御部40は、1つのゲート配線22を走査する期間毎に、複数のソース配線23に印加する信号電圧の極性を反転させるように構成されている。つまり、液晶表示装置1の駆動方式は、1H期間(1水平走査期間)毎に信号電圧の極性を反転させる1Hドット反転駆動方式となっている。
<AC drive control circuit>
The liquid crystal display device 1 further includes an AC drive control unit 40 that applies signal voltages having different polarities to the source lines 23 adjacent to each other in a period during which one gate line 22 is scanned. The AC drive control unit 40 is configured to invert the polarity of the signal voltage applied to the plurality of source lines 23 for each period of scanning one gate line 22. That is, the driving method of the liquid crystal display device 1 is a 1H dot inversion driving method in which the polarity of the signal voltage is inverted every 1H period (one horizontal scanning period).
 尚、交流駆動制御部40は、複数本のゲート配線22を走査する毎に信号電圧の極性を反転するように構成してもよい。つまり、交流駆動制御部40は、nHドット反転駆動するように構成してもよい。したがって、交流駆動制御部40は、少なくとも1つのゲート配線22を走査する期間のそれぞれにおいて、互いに隣り合うソース配線23に互いに異なる極性の信号電圧を印加するように構成することが可能である。 The AC drive control unit 40 may be configured to invert the polarity of the signal voltage every time the plurality of gate wirings 22 are scanned. That is, the AC drive control unit 40 may be configured to perform nH dot inversion driving. Therefore, the AC drive control unit 40 can be configured to apply signal voltages having different polarities to the source wirings 23 adjacent to each other in each of the scanning periods of at least one gate wiring 22.
  -製造方法-
 次に、上記液晶表示装置1の製造方法について説明する。
-Production method-
Next, a method for manufacturing the liquid crystal display device 1 will be described.
 液晶表示装置1は、複数のTFT20等を形成して製造したTFT基板13と、共通電極等を形成した対向基板14とを、液晶層15及びシール部材16を介して貼り合わせることによって液晶表示パネル11を製造し、この液晶表示パネル11にバックライトユニット12を対向配置させることによって製造する。さらに、この液晶表示装置1を、他の機能回路等と共に筐体2内に組み込むことによって、上記電子機器10を製造する。 The liquid crystal display device 1 is a liquid crystal display panel in which a TFT substrate 13 manufactured by forming a plurality of TFTs 20 and the like and a counter substrate 14 formed with a common electrode and the like are bonded together via a liquid crystal layer 15 and a seal member 16. 11 and the backlight unit 12 is disposed opposite to the liquid crystal display panel 11. Further, the electronic apparatus 10 is manufactured by incorporating the liquid crystal display device 1 into the housing 2 together with other functional circuits and the like.
 液晶表示装置の製造方法には、バックライトユニット12が対向配置された液晶表示パネル11について、フリッカを抑制する目的で、フリッカパターンを画面に表示させて、信号電圧と共通電極電圧とを初期調整する電圧調整工程が含まれる。 In the method of manufacturing a liquid crystal display device, a flicker pattern is displayed on the screen for the purpose of suppressing flickering on the liquid crystal display panel 11 with the backlight unit 12 facing each other, and the signal voltage and the common electrode voltage are initially adjusted. Voltage adjusting step is included.
 本実施形態におけるフリッカパターンは、例えば、黒表示した画素18と、中間調表示した画素18とが千鳥状に配置され、全体として市松模様となっている。そして、各画素列19における信号電圧の極性は、それぞれフレーム毎に反転される。すなわち、n-1フレームにおいて各画素18における極性が「-+-+・・・」である画素列19は、nフレームにおいて「+-+-・・・」となり、n+1フレームにおいて「-+-+・・・」となる。 The flicker pattern in the present embodiment has, for example, a black checkered pixel 18 and a halftone display pixel 18 arranged in a zigzag pattern, and has a checkered pattern as a whole. The polarity of the signal voltage in each pixel column 19 is inverted for each frame. That is, the pixel column 19 in which the polarity of each pixel 18 in the n−1 frame is “− ++ −...” Becomes “+ − + −...” In the n frame and “− ++ −” in the n + 1 frame. + ... ".
 そして、電圧調整工程では、液晶表示装置1の表示画面にフリッカパターン42を表示させた状態で、その表示画面におけるフリッカが最小となるように、上記共通電極電圧の大きさを調整する。 In the voltage adjustment step, the magnitude of the common electrode voltage is adjusted so that the flicker on the display screen is minimized while the flicker pattern 42 is displayed on the display screen of the liquid crystal display device 1.
  -実施形態2の効果-
 したがって、本実施形態2によれば、各TFT20のW長を大きく確保しながらも、フリッカを大幅に抑制することができる。以下、本発明の効果について詳述する。
-Effect of Embodiment 2-
Therefore, according to the second embodiment, flicker can be significantly suppressed while ensuring a large W length of each TFT 20. Hereinafter, the effects of the present invention will be described in detail.
 上記実施形態1で説明したように、本発明者らは、ソース電極の形状がドレイン電極と異なるTFTを備えた液晶表示装置について、ソース電極(ソース配線)に印加する信号電圧の極性を反転させると、その極性の反転に応じて、当該TFTに生じるオフリーク電流の量が変化することを見出した。そして、そのオフリーク電流の変化に伴って当該TFTが設けられている画素の輝度が変化する結果、フリッカが視認されやすくなることが分かった。 As described in Embodiment 1 above, the present inventors reverse the polarity of the signal voltage applied to the source electrode (source wiring) in a liquid crystal display device including a TFT having a source electrode shape different from that of the drain electrode. It was found that the amount of off-leakage current generated in the TFT changes according to the reversal of the polarity. As a result of the change in the luminance of the pixel provided with the TFT along with the change in the off-leakage current, it has been found that flicker is easily visually recognized.
 ここで、図15は、本実施形態2における液晶表示装置1の1Hドット反転駆動を示す平面図である。上記液晶表示装置1については、図15の上側部分に示すように、ある「黒表示、中間調表示、黒表示、中間調表示・・・」をする画素列19aを走査する1H期間において、ソース配線23に印加する信号電圧の極性を「+-+-・・・」とする。 Here, FIG. 15 is a plan view showing 1H dot inversion driving of the liquid crystal display device 1 according to the second embodiment. As for the liquid crystal display device 1, as shown in the upper part of FIG. 15, in the 1H period in which the pixel row 19 a that performs a certain “black display, halftone display, black display, halftone display... The polarity of the signal voltage applied to the wiring 23 is “+ − + −.
 次の1H期間には、「中間調表示、黒表示、中間調表示、黒表示・・・」をする画素列19bに対し、ソース配線23に印加する信号電圧の極性を「-+-+・・・」とする。そうして、黒表示している画素18に+極性の信号電圧を印加し、中間調表示している画素18に-極性の信号電圧を印加する。ここで、図15における各画素18の矢印は、オフリーク電流が流れる方向を示している。 In the next 1H period, the polarity of the signal voltage applied to the source wiring 23 is set to “− ++ − + · for the pixel row 19b for“ halftone display, black display, halftone display, black display.・ ・ 」 Then, a positive polarity signal voltage is applied to the pixel 18 displaying black, and a negative polarity signal voltage is applied to the pixel 18 displaying halftone. Here, the arrow of each pixel 18 in FIG. 15 indicates the direction in which the off-leakage current flows.
 このn-1フレームにおいて、視認される中間調表示をしている第1画素18aでは、オフリーク電流が比較的大きくなる(L)。一方、中間調表示している第2画素18bでは、オフリーク電流が比較的小さくなる(S)。したがって、画面全体において中間調表示する画素には、オフリーク電流が比較的大きい(L)第1画素18aと、オフリーク電流が比較的小さい(S)第2画素18bとが同数含まれることとなる。 In the n-1 frame, the off-leakage current is relatively large (L) in the first pixel 18a displaying the halftone display that is visually recognized. On the other hand, the off-leakage current is relatively small in the second pixel 18b displaying halftone (S). Therefore, the same number of pixels with half-tone display on the entire screen includes the first pixels 18a having a relatively large off-leakage current (L) and the second pixels 18b having a relatively small off-leakage current (S).
 図15の下側部分に示すように、次のnフレームにおいて、視認される中間調表示をしている第1画素18aでは、オフリーク電流が比較的小さくなる(S)。一方、中間調表示している第2画素18bでは、オフリーク電流が比較的大きくなる(L)。したがって、画面全体において中間調表示する画素には、オフリーク電流が比較的小さい(S)第1画素18aと、オフリーク電流が比較的大きい(L)第2画素18bとが同数含まれることとなる。 As shown in the lower part of FIG. 15, in the next n frames, the off-leakage current is relatively small in the first pixel 18a that is displayed as a halftone display (S). On the other hand, the off-leakage current becomes relatively large (L) in the second pixel 18b displaying halftone. Therefore, the same number of pixels with half-tone display on the entire screen includes the first pixel 18a having a relatively small off-leakage current (S) and the second pixel 18b having a relatively large off-leakage current (L).
 すなわち、本実施形態によれば、何れのフレームにもオフリーク電流が比較的小さい(S)画素18と、オフリーク電流が比較的大きい(L)画素18とが互いに同じ数だけ含まれる結果、フレームが変化する前後において表示画面全体の総リーク量が同じになるため、フリッカを大幅に抑制することができる。よって、本実施形態によれば、各TFT20のW長を大きく確保しながらも、フリッカを大幅に抑制できることとなる。 That is, according to the present embodiment, each frame includes the same number (S) of pixels 18 with relatively small off-leakage current (S) and pixels (L) with relatively large off-leakage current. Since the total leak amount of the entire display screen is the same before and after the change, flicker can be significantly suppressed. Therefore, according to the present embodiment, flicker can be significantly suppressed while ensuring a large W length of each TFT 20.
 一方、図16は、比較例としての液晶表示装置の1Hドット反転駆動を示す平面図である。この比較例では、全ての画素118が同じ構成をしており、各ソース電極125が全てU字状に形成される一方、各ドレイン電極129が全てI字状に形成されている。 On the other hand, FIG. 16 is a plan view showing 1H dot inversion driving of a liquid crystal display device as a comparative example. In this comparative example, all the pixels 118 have the same configuration, and each source electrode 125 is formed in a U shape, while each drain electrode 129 is formed in an I shape.
 そして、この液晶表示装置については、図16の上側部分に示すように、ある「黒表示、中間調表示、黒表示、中間調表示・・・」をする画素列119aを走査する1H期間において、ソース配線123に印加する信号電圧の極性を「+-+-・・・」とする。 In the liquid crystal display device, as shown in the upper part of FIG. 16, in the 1H period of scanning the pixel column 119a that performs certain “black display, halftone display, black display, halftone display... The polarity of the signal voltage applied to the source wiring 123 is “+ − + −.
 次の1H期間には、「中間調表示、黒表示、中間調表示、黒表示・・・」をする画素列119bに対し、ソース配線123に印加する信号電圧の極性を「-+-+・・・」とする。そうして、黒表示している画素118に+極性の信号電圧を印加し、中間調表示している画素118に-極性の信号電圧を印加する。ここで、図16における各画素18の矢印は、オフリーク電流が流れる方向を示している。 In the next 1H period, the polarity of the signal voltage applied to the source wiring 123 is set to “− ++ − + · for the pixel column 119b performing“ halftone display, black display, halftone display, black display.・ ・ 」 Then, a positive polarity signal voltage is applied to the pixel 118 displaying black, and a negative polarity signal voltage is applied to the pixel 118 displaying halftone. Here, the arrow of each pixel 18 in FIG. 16 indicates the direction in which the off-leakage current flows.
 このn-1フレームにおいて、視認される中間調表示をしている画素118では、オフリーク電流が比較的大きくなる(L)。したがって、画面全体では、全てオフリーク電流が比較的大きい(L)画素118によって中間調表示されることとなる。 In the n-1 frame, the off-leakage current is relatively large (L) in the visually recognized pixel 118 displaying halftone. Therefore, the entire screen is displayed in halftone by the (L) pixel 118 having a relatively large off-leakage current.
 図16の下側部分に示すように、次のnフレームにおいて中間調表示している画素118では、オフリーク電流が比較的小さくなる(S)。したがって、画面全体では、全てオフリーク電流が比較的小さい(S)画素118によって中間調表示されることとなる。 As shown in the lower part of FIG. 16, the off-leakage current is relatively small in the pixel 118 that is displayed in halftone in the next n frames (S). Accordingly, the entire screen is displayed in halftone by the (S) pixel 118 having a relatively small off-leakage current.
 すなわち、この比較例としての液晶表示装置では、フレームが変化する前後において、中間調表示する全ての画素118のオフリーク電流が比較的大きい(L)状態と、中間調表示する全ての画素118のオフリーク電流が比較的小さい(S)状態とが交互に切り替わることになるため、フリッカが視認されやすくなってしまう。 That is, in the liquid crystal display device as the comparative example, the off-leak current of all the pixels 118 that perform halftone display is relatively large (L) before and after the frame changes, and the off-leakage of all the pixels 118 that perform halftone display. Since the state where the current is relatively small (S) is alternately switched, flicker is likely to be visually recognized.
 《発明の実施形態3》
 図17~図20は、本発明の実施形態3を示している。
<< Embodiment 3 of the Invention >>
17 to 20 show Embodiment 3 of the present invention.
 図17は、本実施形態3におけるTFT基板13の一部を拡大してを示す平面図である。図18は、本実施形態3における第1TFT及び第2TFTを拡大して示す平面図である。 FIG. 17 is a plan view showing an enlarged part of the TFT substrate 13 in the third embodiment. FIG. 18 is an enlarged plan view showing the first TFT and the second TFT in the third embodiment.
 上記実施形態1では、TFT20のソース電極25又はドレイン電極29をU字状に形成したのに対し、本実施形態3は、TFT20のソース電極25及びドレイン電極29を、それぞれ矩形状に形成した点で相違している。 In the first embodiment, the source electrode 25 or the drain electrode 29 of the TFT 20 is formed in a U shape, whereas in the third embodiment, the source electrode 25 and the drain electrode 29 of the TFT 20 are each formed in a rectangular shape. Is different.
 本実施形態3における電子機器10は、図9に示すように、筐体2の内部に表示ユニットとしての液晶表示装置1を備えている。電子機器10は例えば液晶テレビやスマートフォン等のモバイル機器その他の電子機器である。 The electronic device 10 according to the third embodiment includes a liquid crystal display device 1 as a display unit inside a housing 2 as shown in FIG. The electronic device 10 is, for example, a mobile device such as a liquid crystal television or a smartphone or other electronic devices.
 液晶表示装置1は、図9に示すように、液晶表示パネル11と、この液晶表示パネル11の背面側に配置された光源であるバックライトユニット12とを備えている。すなわち、液晶表示装置1は、少なくともバックライトユニット12の光を選択的に透過させて透過表示を行うように構成されている。 As shown in FIG. 9, the liquid crystal display device 1 includes a liquid crystal display panel 11 and a backlight unit 12 that is a light source disposed on the back side of the liquid crystal display panel 11. That is, the liquid crystal display device 1 is configured to perform transmissive display by selectively transmitting at least light from the backlight unit 12.
 液晶表示パネル11は、図9に示すように、第1基板であるTFT基板13と、TFT基板13に対向して配置された第2基板である対向基板14とを有している。TFT基板13と対向基板14との間には、液晶層15がシール部材16によって封入されている。 As shown in FIG. 9, the liquid crystal display panel 11 includes a TFT substrate 13 that is a first substrate, and a counter substrate 14 that is a second substrate disposed to face the TFT substrate 13. A liquid crystal layer 15 is sealed between the TFT substrate 13 and the counter substrate 14 by a seal member 16.
 液晶表示パネル11は、表示領域(図示省略)と、その周囲に設けられた額縁状の非表示領域(図示省略)とを有している。表示領域には、マトリクス状に設けられた複数の画素18が形成されている。 The liquid crystal display panel 11 has a display area (not shown) and a frame-like non-display area (not shown) provided around the display area. A plurality of pixels 18 provided in a matrix are formed in the display area.
 TFT基板13は、アクティブマトリクス基板によって構成されている。TFT基板13は、透明基板としてのガラス基板(図示省略)を有している。図17に示すように、上記ガラス基板上には、互いに並行して延びる複数のソース配線23と、ソース配線23に交差して延びる複数のゲート配線22とが形成されている。 The TFT substrate 13 is composed of an active matrix substrate. The TFT substrate 13 has a glass substrate (not shown) as a transparent substrate. As shown in FIG. 17, a plurality of source lines 23 extending in parallel to each other and a plurality of gate lines 22 extending so as to intersect the source lines 23 are formed on the glass substrate.
 すなわち、複数のゲート配線22及び複数のソース配線23は、全体として格子状に形成され、ゲート配線22及びソース配線23に矩形状に囲まれた領域に画素18がそれぞれ形成されている。ゲート配線22及びソース配線23は、それぞれ、例えばAl、Cu、Mo及びTi等のうち1種からなる単層膜又は複数種からなる複数層膜によって構成されている。 That is, the plurality of gate lines 22 and the plurality of source lines 23 are formed in a lattice shape as a whole, and the pixels 18 are formed in regions surrounded by the gate lines 22 and the source lines 23 in a rectangular shape. Each of the gate wiring 22 and the source wiring 23 is configured by a single-layer film made of one type or a multi-layer film made of a plurality of types, for example, among Al, Cu, Mo, Ti, and the like.
 各画素18には、ゲート配線22及びソース配線23の交差部分近傍にTFT20がそれぞれ設けられている。TFT20には、上記ゲート配線22及びソース配線23が接続されている。本実施形態3におけるTFT20は、ボトムゲート型TFTであって、ゲート配線22から分岐して形成されたゲート電極26と、ゲート電極26にゲート絶縁膜(図示省略)を介して対向する半導体層(図示省略)と、ソース配線23から分岐して形成されたソース電極25と、ドレイン電極29とを有している。 Each pixel 18 is provided with a TFT 20 in the vicinity of the intersection of the gate wiring 22 and the source wiring 23. The gate wiring 22 and the source wiring 23 are connected to the TFT 20. The TFT 20 in the third embodiment is a bottom gate type TFT, and a gate electrode 26 branched from the gate wiring 22 and a semiconductor layer (not shown) facing the gate electrode 26 via a gate insulating film (not shown). A source electrode 25 that is branched from the source wiring 23, and a drain electrode 29.
 ゲート電極26及びゲート配線22は、ガラス基板上に形成されると共に上記ゲート絶縁膜によって覆われている。上記ゲート絶縁膜は、例えばSiNx(窒化シリコン)及びSiO等のうち1種からなる単層膜又は複数種からなる複数層膜によって構成されている。上記ゲート絶縁膜の表面には、上記半導体層が例えば矩形島状に形成されている。上記半導体層は、例えばa-Si等の半導体によって形成されている。 The gate electrode 26 and the gate wiring 22 are formed on a glass substrate and covered with the gate insulating film. The gate insulating film is composed of, for example, a single-layer film made of one of SiNx (silicon nitride) and SiO 2 or a multi-layer film made of a plurality of kinds. On the surface of the gate insulating film, the semiconductor layer is formed in a rectangular island shape, for example. The semiconductor layer is formed of a semiconductor such as a-Si, for example.
 上記半導体層及びゲート電極26には、ソース電極25の一部及びドレイン電極29の一部がそれぞれ重なっている。また、ソース電極25及びドレイン電極29等は、層間絶縁膜(図示省略)によって覆われている。上記層間絶縁膜は、例えばSiNx等によって形成されている。 A part of the source electrode 25 and a part of the drain electrode 29 are overlapped with the semiconductor layer and the gate electrode 26, respectively. The source electrode 25, the drain electrode 29, and the like are covered with an interlayer insulating film (not shown). The interlayer insulating film is made of, for example, SiNx.
 また、上記複数の画素18には、当該画素18に設けられているTFT20のドレイン電極29に接続された画素電極30が形成されている。画素電極30は、上記層間絶縁膜の表面に形成され、例えばITO等の透明導電性膜によって構成されている。 Further, the plurality of pixels 18 are formed with pixel electrodes 30 connected to the drain electrodes 29 of the TFTs 20 provided in the pixels 18. The pixel electrode 30 is formed on the surface of the interlayer insulating film, and is formed of a transparent conductive film such as ITO.
 一方、対向基板14には、上記複数の画素電極30に共通して設けられた共通電極(図示省略)が形成されている。上記共通電極も、画素電極30と同様に例えばITO等の透明導電性膜によって形成されている。そうして、所定電位の共通電極と、各画素18の画素電極30との電位差を制御することによって、液晶層15を各画素18毎に配向制御するようになっている。 On the other hand, a common electrode (not shown) provided in common with the plurality of pixel electrodes 30 is formed on the counter substrate 14. Similar to the pixel electrode 30, the common electrode is also formed of a transparent conductive film such as ITO. Thus, the orientation of the liquid crystal layer 15 is controlled for each pixel 18 by controlling the potential difference between the common electrode having a predetermined potential and the pixel electrode 30 of each pixel 18.
 <TFTの構成>
 本実施形態におけるTFT20には、ソース電極25がドレイン電極29よりも大きい第1TFT20aと、ドレイン電極29がソース電極25よりも大きい第2TFT20bとが含まれている。
<Configuration of TFT>
The TFT 20 in this embodiment includes a first TFT 20 a in which the source electrode 25 is larger than the drain electrode 29 and a second TFT 20 b in which the drain electrode 29 is larger than the source electrode 25.
 図17及び図18に示すように、第1TFT20aのソース電極25及びドレイン電極29は、それぞれ矩形状部分を有し、その一辺同士が対向するように配置されている。第1TFT20aのソース電極25は、ドレイン電極29よりも大きい。 As shown in FIG. 17 and FIG. 18, the source electrode 25 and the drain electrode 29 of the first TFT 20a each have a rectangular portion, and are arranged so that one sides thereof face each other. The source electrode 25 of the first TFT 20 a is larger than the drain electrode 29.
 図17に示すように、第1TFT20aのソース電極25の一端部は、ゲート電極26に重なっている。また、第1TFT20aのドレイン電極29の一端部もゲート電極26に重なっている。そして、第1TFT20aにおけるソース電極25とゲート電極26との重なり幅Aは、ドレイン電極29とゲート電極26との重なり幅Bよりも広くなっている。 As shown in FIG. 17, one end of the source electrode 25 of the first TFT 20a overlaps the gate electrode. Further, one end portion of the drain electrode 29 of the first TFT 20 a also overlaps the gate electrode 26. The overlapping width A between the source electrode 25 and the gate electrode 26 in the first TFT 20 a is wider than the overlapping width B between the drain electrode 29 and the gate electrode 26.
 第2TFT20bのソース電極25及びドレイン電極29も、それぞれ矩形状部分を有し、その一辺同士が対向するように配置されている。第2TFT20bのソース電極25は、ドレイン電極29よりも小さい。 The source electrode 25 and the drain electrode 29 of the second TFT 20b each have a rectangular portion, and are arranged so that the sides thereof face each other. The source electrode 25 of the second TFT 20 b is smaller than the drain electrode 29.
 図17に示すように、第2TFT20bについても、ソース電極25の一端部がゲート電極26に重なっており、ドレイン電極29の一端部がゲート電極26に重なっている。一方、第2TFT20bにおけるソース電極25とゲート電極26との重なり幅Aは、ドレイン電極29とゲート電極26との重なり幅Bよりも狭くなっている。 17, also in the second TFT 20b, one end portion of the source electrode 25 overlaps the gate electrode 26, and one end portion of the drain electrode 29 overlaps the gate electrode 26. On the other hand, the overlap width A between the source electrode 25 and the gate electrode 26 in the second TFT 20 b is narrower than the overlap width B between the drain electrode 29 and the gate electrode 26.
 <画素の配列構成>
 そして、図17に示すように、ゲート配線22に沿って並ぶ複数の画素18からなる画素列19には、第1TFT20aが形成された複数の第1画素18aと、第2TFT20bが形成された複数の第2画素18bとが含まれている。
<Pixel arrangement configuration>
As shown in FIG. 17, a plurality of first pixels 18 a in which first TFTs 20 a are formed and a plurality of pixels in which second TFTs 20 b are formed are arranged in a pixel column 19 including a plurality of pixels 18 arranged along the gate wiring 22. The second pixel 18b is included.
 さらに、各画素列19には、1つの第1画素18aと、1つの第2画素18bとが、ゲート配線22に沿って交互に配置されている。一方、ソース配線23に沿った方向には、複数の第1画素18a又は複数の第2画素18bが並んで配置されている。 Further, in each pixel column 19, one first pixel 18 a and one second pixel 18 b are alternately arranged along the gate wiring 22. On the other hand, in the direction along the source wiring 23, a plurality of first pixels 18a or a plurality of second pixels 18b are arranged side by side.
 尚、第1画素18a及び第2画素18bの他の配置例としては、各画素列19において、例えば2つの第1画素18aと、2つの第2画素18bとが、ゲート配線22に沿って交互に配置されていてもよい。すなわち、画素列19には、少なくとも1つの第1画素18aと、この少なくとも1つの第1画素18aと同じ数の第2画素18bとが、ゲート配線22に沿って交互に配置されるようにしてもよい。 As another arrangement example of the first pixel 18 a and the second pixel 18 b, for example, in each pixel column 19, two first pixels 18 a and two second pixels 18 b are alternately arranged along the gate wiring 22. May be arranged. That is, at least one first pixel 18 a and the same number of second pixels 18 b as the at least one first pixel 18 a are alternately arranged along the gate wiring 22 in the pixel column 19. Also good.
 <交流駆動制御回路>
 液晶表示装置1は、さらに、1つのゲート配線22を走査する期間において、複数のソース配線23に互いに同じ極性の信号電圧を印加する交流駆動制御部40を備えている。交流駆動制御部40は、1つのゲート配線22を走査する期間毎に、複数のソース配線23に印加する信号電圧の極性を反転させるように構成されている。つまり、液晶表示装置1の駆動方式は、1H期間毎に信号電圧の極性を反転させる1Hライン反転駆動方式となっている。
<AC drive control circuit>
The liquid crystal display device 1 further includes an AC drive control unit 40 that applies signal voltages having the same polarity to the plurality of source lines 23 during a period of scanning one gate line 22. The AC drive control unit 40 is configured to invert the polarity of the signal voltage applied to the plurality of source lines 23 for each period of scanning one gate line 22. That is, the driving method of the liquid crystal display device 1 is a 1H line inversion driving method in which the polarity of the signal voltage is inverted every 1H period.
 尚、交流駆動制御部40は、複数本のゲート配線22を走査する毎に信号電圧の極性を反転するように構成してもよい。つまり、交流駆動制御部40は、nHライン反転駆動するように構成してもよい。したがって、交流駆動制御部40は、少なくとも1つのゲート配線22を走査する期間のそれぞれにおいて、複数のソース配線23に互いに同じ極性の信号電圧を印加するように構成することが可能である。 The AC drive control unit 40 may be configured to invert the polarity of the signal voltage every time the plurality of gate wirings 22 are scanned. That is, the AC drive control unit 40 may be configured to perform nH line inversion driving. Therefore, the AC drive control unit 40 can be configured to apply signal voltages having the same polarity to the plurality of source lines 23 in each of the periods in which at least one gate line 22 is scanned.
  -製造方法-
 次に、上記液晶表示装置1の製造方法について説明する。
-Production method-
Next, a method for manufacturing the liquid crystal display device 1 will be described.
 液晶表示装置1は、複数のTFT20等を形成して製造したTFT基板13と、共通電極等を形成した対向基板14とを、液晶層15及びシール部材16を介して貼り合わせることによって液晶表示パネル11を製造し、この液晶表示パネル11にバックライトユニット12を対向配置させることによって製造する。さらに、この液晶表示装置1を、他の機能回路等と共に筐体2内に組み込むことによって、上記電子機器10を製造する。 The liquid crystal display device 1 is a liquid crystal display panel in which a TFT substrate 13 manufactured by forming a plurality of TFTs 20 and the like and a counter substrate 14 formed with a common electrode and the like are bonded together via a liquid crystal layer 15 and a seal member 16. 11 and the backlight unit 12 is disposed opposite to the liquid crystal display panel 11. Further, the electronic apparatus 10 is manufactured by incorporating the liquid crystal display device 1 into the housing 2 together with other functional circuits and the like.
 液晶表示装置の製造方法には、バックライトユニット12が対向配置された液晶表示パネル11について、フリッカを抑制する目的で、フリッカパターンを画面に表示させて、信号電圧と共通電極電圧とを初期調整する電圧調整工程が含まれる。 In the method of manufacturing a liquid crystal display device, a flicker pattern is displayed on the screen for the purpose of suppressing flickering on the liquid crystal display panel 11 with the backlight unit 12 facing each other, and the signal voltage and the common electrode voltage are initially adjusted. Voltage adjusting step is included.
 そして、電圧調整工程では、液晶表示装置1の表示画面にフリッカパターン42を表示させた状態で、その表示画面におけるフリッカが最小となるように、上記共通電極電圧の大きさを調整する。 In the voltage adjustment step, the magnitude of the common electrode voltage is adjusted so that the flicker on the display screen is minimized while the flicker pattern 42 is displayed on the display screen of the liquid crystal display device 1.
  -実施形態3の効果-
 したがって、本実施形態3によれば、各TFT20のソース電極25の形状がドレイン電極29と異なっていても、フリッカを大幅に抑制することができる。以下、本発明の効果について詳述する。
-Effect of Embodiment 3-
Therefore, according to the third embodiment, even if the shape of the source electrode 25 of each TFT 20 is different from that of the drain electrode 29, flicker can be significantly suppressed. Hereinafter, the effects of the present invention will be described in detail.
 図19は、本実施形態3における液晶表示装置1の1Hライン反転駆動を示す平面図である。上記液晶表示装置1については、図19の上側部分に示すように、あるn-1フレームの中間調表示する画素列19aを走査する1H期間において、ソース配線23に印加する信号電圧を+極性とする。次の黒表示する画素列19bを走査する1H期間には、ソース配線23に印加する信号電圧を反転して-極性とする。ここで、図19における各画素18の矢印は、オフリーク電流が流れる方向を示している。 FIG. 19 is a plan view showing 1H line inversion driving of the liquid crystal display device 1 according to the third embodiment. In the liquid crystal display device 1, as shown in the upper part of FIG. 19, the signal voltage applied to the source line 23 is set to + polarity in the 1H period during which the pixel column 19 a for halftone display of a certain n−1 frame is scanned. To do. In the 1H period during which the next black display pixel column 19b is scanned, the signal voltage applied to the source line 23 is inverted to have a negative polarity. Here, the arrow of each pixel 18 in FIG. 19 indicates the direction in which the off-leakage current flows.
 このn-1フレームにおいて、視認される中間調表示をしている画素列19aでは、オフリーク電流が比較的小さくなり(S)、第2画素18bでは、オフリーク電流が比較的大きくなる(L)。したがって、画面全体において中間調表示する画素には、オフリーク電流が比較的小さい(S)第1画素18aと、オフリーク電流が比較的大きい(L)第2画素18bとが同数含まれることとなる。 In the n-1 frame, the off-leak current is relatively small in the pixel column 19a displaying the halftone display that is visually recognized (S), and the off-leak current is relatively large in the second pixel 18b (L). Therefore, the same number of pixels with half-tone display on the entire screen includes the first pixel 18a having a relatively small off-leakage current (S) and the second pixel 18b having a relatively large off-leakage current (L).
 図19の下側部分に示すように、次のnフレームにおいて中間調表示している画素列19aでは、第1画素18aのオフリーク電流が比較的大きくなり(L)、第2画素18bのオフリーク電流が比較的小さくなる(S)。したがって、画面全体において中間調表示する画素には、オフリーク電流が比較的大きい(L)第1画素18aと、オフリーク電流が比較的小さい(S)第2画素18bとが同数含まれることとなる。 As shown in the lower part of FIG. 19, in the pixel column 19a that is displayed in halftone in the next n frames, the off-leak current of the first pixel 18a becomes relatively large (L), and the off-leak current of the second pixel 18b. Becomes relatively small (S). Therefore, the same number of pixels with half-tone display on the entire screen includes the first pixels 18a having a relatively large off-leakage current (L) and the second pixels 18b having a relatively small off-leakage current (S).
 すなわち、本実施形態によれば、何れのフレームにおいても、オフリーク電流が比較的小さい(S)画素18と、オフリーク電流が比較的大きい(L)画素18とが互いに同じ数だけ含まれる結果、フレームが変化する前後において表示画面全体の総リーク量が同じになるため、フリッカを大幅に抑制することができる。よって、本実施形態によれば、各TFT20のソース電極25の形状がドレイン電極29と異なっていても、フリッカを大幅に抑制できることとなる。 That is, according to this embodiment, in any frame, as a result of including the same number of (S) pixels 18 having a relatively small off-leakage current and (L) pixels 18 having a relatively large off-leakage current. Since the total leak amount of the entire display screen is the same before and after the change, flicker can be significantly suppressed. Therefore, according to this embodiment, even if the shape of the source electrode 25 of each TFT 20 is different from that of the drain electrode 29, flicker can be significantly suppressed.
 一方、図20は、比較例としての液晶表示装置の1Hライン反転駆動を示す平面図である。この比較例では、全ての画素118が同じ構成をしており、各ソース電極125がそれぞれドレイン電極129よりも大きく形成されている。 On the other hand, FIG. 20 is a plan view showing 1H line inversion driving of a liquid crystal display device as a comparative example. In this comparative example, all the pixels 118 have the same configuration, and each source electrode 125 is formed larger than the drain electrode 129.
 そして、この液晶表示装置については、図20の上側部分に示すように、あるn-1フレームの中間調表示する画素列119aを走査する1H期間において、ソース配線123に印加する信号電圧を+極性とする。次の黒表示する画素列119bを走査する1H期間には、ソース配線123に印加する信号電圧を反転して-極性とする。ここで、図20における各画素118の矢印は、オフリーク電流が流れる方向を示している。 In this liquid crystal display device, as shown in the upper part of FIG. 20, the signal voltage applied to the source line 123 is set to + polarity in the 1H period in which the pixel column 119a for halftone display of a certain n−1 frame is scanned. And In the 1H period during which the next pixel column 119b for black display is scanned, the signal voltage applied to the source wiring 123 is inverted to have a negative polarity. Here, the arrow of each pixel 118 in FIG. 20 indicates the direction in which the off-leakage current flows.
 このn-1フレームにおいて、視認される中間調表示をしている画素列119aでは、各画素118のオフリーク電流が比較的小さくなる(S)。したがって、画面全体では、全てオフリーク電流が比較的小さい(S)画素118によって中間調表示されることとなる。 In this n-1 frame, in the pixel column 119a displaying the halftone display that is visually recognized, the off-leak current of each pixel 118 is relatively small (S). Accordingly, the entire screen is displayed in halftone by the (S) pixel 118 having a relatively small off-leakage current.
 図20の下側部分に示すように、次のnフレームにおいて中間調表示している画素列119aでは、各画素118のオフリーク電流が比較的大きくなる(L)。したがって、画面全体では、全てオフリーク電流が比較的大きい(L)画素118によって中間調表示されることとなる。 As shown in the lower part of FIG. 20, in the pixel row 119a that is displayed in halftone in the next n frames, the off-leak current of each pixel 118 is relatively large (L). Therefore, the entire screen is displayed in halftone by the (L) pixel 118 having a relatively large off-leakage current.
 すなわち、この比較例としての液晶表示装置では、フレームが変化する前後において、中間調表示する全ての画素118のオフリーク電流が比較的小さい(S)状態と、中間調表示する全ての画素118のオフリーク電流が比較的大きい(L)状態とが交互に切り替わることになるため、フリッカが視認されやすくなってしまうこととなる。 That is, in the liquid crystal display device as the comparative example, the off-leak current of all the pixels 118 that perform halftone display is relatively small (S) before and after the frame changes, and the off-leakage of all the pixels 118 that perform halftone display. Since the state where the current is relatively large (L) is alternately switched, the flicker is likely to be visually recognized.
 尚、本発明は上記実施形態1~3に限定されるものでなく、本発明には、これらの実施形態1~3を適宜組み合わせた構成が含まれる。 The present invention is not limited to the first to third embodiments, and the present invention includes a configuration in which these first to third embodiments are appropriately combined.
 以上説明したように、本発明は、液晶表示装置及びそれを備えた電子機器について有用である。 As described above, the present invention is useful for a liquid crystal display device and an electronic apparatus including the same.
      1   液晶表示装置 
     10   電子機器 
     18   画素 
     18a  第1画素 
     18b  第2画素 
     19   画素列 
     20   TFT 
     20a  第1TFT 
     20b  第2TFT 
     22   ゲート配線 
     23   ソース配線 
     25   ソース電極 
     29   ドレイン電極 
     30   画素電極 
     32   電極肢 
     36   電極肢 
     40   交流駆動制御部 
     51   第1電極 
     52   第2電極   
1 Liquid crystal display device
10 Electronic equipment
18 pixels
18a first pixel
18b second pixel
19 pixel array
20 TFT
20a 1st TFT
20b 2nd TFT
22 Gate wiring
23 Source wiring
25 Source electrode
29 Drain electrode
30 pixel electrode
32 electrode limbs
36 electrode limbs
40 AC drive controller
51 First electrode
52 Second electrode

Claims (8)

  1.  複数のソース配線と、
     上記ソース配線に交差する複数のゲート配線と、
     マトリクス状に設けられた複数の画素と、
     上記複数の画素にそれぞれ設けられて上記ソース配線及びゲート配線に接続された薄膜トランジスタと、
     上記複数の画素にそれぞれ設けられて上記薄膜トランジスタのドレイン電極に接続された画素電極と、
     少なくとも1つの上記ゲート配線を走査する期間毎に、上記複数のソース配線に印加する信号電圧の極性を反転させる交流駆動制御部とを備え、
     上記薄膜トランジスタのドレイン電極の一部及びソース電極の一部は、当該薄膜トランジスタのゲート電極にそれぞれ重なっており、
     上記薄膜トランジスタには、上記ソース電極と上記ゲート電極との重なり幅が上記ドレイン電極と上記ゲート電極との重なり幅よりも広い第1薄膜トランジスタと、上記ソース電極と上記ゲート電極との重なり幅が上記ドレイン電極と上記ゲート電極との重なり幅よりも狭い第2薄膜トランジスタとが含まれ、
     上記ゲート配線に沿って並ぶ複数の上記画素からなる画素列には、上記第1薄膜トランジスタが形成された複数の第1画素と、上記第2薄膜トランジスタが形成された複数の第2画素とが含まれている
    ことを特徴とする液晶表示装置。
    Multiple source wires,
    A plurality of gate lines crossing the source lines;
    A plurality of pixels provided in a matrix;
    A thin film transistor provided in each of the plurality of pixels and connected to the source wiring and the gate wiring;
    A pixel electrode provided in each of the plurality of pixels and connected to a drain electrode of the thin film transistor;
    An AC drive controller that inverts the polarity of the signal voltage applied to the plurality of source lines for each period of scanning at least one of the gate lines;
    Part of the drain electrode and part of the source electrode of the thin film transistor overlap with the gate electrode of the thin film transistor,
    The thin film transistor includes a first thin film transistor in which an overlap width between the source electrode and the gate electrode is wider than an overlap width between the drain electrode and the gate electrode, and an overlap width between the source electrode and the gate electrode is the drain. A second thin film transistor narrower than an overlapping width of the electrode and the gate electrode,
    A pixel column including a plurality of the pixels arranged along the gate wiring includes a plurality of first pixels in which the first thin film transistor is formed and a plurality of second pixels in which the second thin film transistor is formed. A liquid crystal display device.
  2.  請求項1に記載された液晶表示装置において、
     上記画素列には、少なくとも1つの上記第1画素と、該少なくとも1つの第1画素と同じ数の上記第2画素とが、上記ゲート配線に沿って交互に配置されている
    ことを特徴とする液晶表示装置。
    The liquid crystal display device according to claim 1,
    In the pixel column, at least one of the first pixels and the same number of the second pixels as the at least one first pixel are alternately arranged along the gate wiring. Liquid crystal display device.
  3.  請求項1又は2に記載された液晶表示装置において、
     上記交流駆動制御部は、上記少なくとも1つのゲート配線を走査する期間のそれぞれにおいて、上記複数のソース配線に互いに同じ極性の信号電圧を印加するように構成されている
    ことを特徴とする液晶表示装置。
    The liquid crystal display device according to claim 1 or 2,
    The AC drive control unit is configured to apply signal voltages having the same polarity to the plurality of source lines in each of the scanning periods of the at least one gate line. .
  4.  請求項3に記載された液晶表示装置において、
     上記画素列には、1つの上記第1画素と、1つの第2画素とが、上記ゲート配線に沿って交互に配置され、
     上記交流駆動制御部は、1つの上記ゲート配線を走査する期間において、上記複数のソース配線に互いに同じ極性の信号電圧を印加すると共に、上記1つのゲート配線を走査する期間毎に、上記複数のソース配線に印加する信号電圧の極性を反転させるように構成されている
    ことを特徴とする液晶表示装置。
    The liquid crystal display device according to claim 3,
    In the pixel column, the one first pixel and the one second pixel are alternately arranged along the gate wiring,
    The AC drive control unit applies signal voltages having the same polarity to the plurality of source lines in a period for scanning the one gate line, and also performs the plurality of times for each period in which the one gate line is scanned. A liquid crystal display device configured to invert the polarity of a signal voltage applied to a source wiring.
  5.  請求項1又は2に記載された液晶表示装置において、
     上記交流駆動制御部は、上記少なくとも1つのゲート配線を走査する期間のそれぞれにおいて、互いに隣り合う上記ソース配線に互いに異なる極性の信号電圧を印加するように構成されている
    ことを特徴とする液晶表示装置。
    The liquid crystal display device according to claim 1 or 2,
    The AC drive control unit is configured to apply signal voltages having different polarities to the source lines adjacent to each other in each of the scanning periods of the at least one gate line. apparatus.
  6.  請求項5に記載された液晶表示装置において、
     上記画素列には、2つの上記第1画素と、2つの第2画素とが、上記ゲート配線に沿って交互に配置され、
     上記交流駆動制御部は、1つの上記ゲート配線を走査する期間のそれぞれにおいて、互いに隣り合う上記ソース配線に互いに異なる極性の信号電圧を印加すると共に、上記1つのゲート配線を走査する期間毎に、上記複数のソース配線に印加する信号電圧の極性を反転させるように構成されている
    ことを特徴とする液晶表示装置。
    The liquid crystal display device according to claim 5,
    In the pixel column, two first pixels and two second pixels are alternately arranged along the gate wiring,
    The AC drive control unit applies signal voltages of different polarities to the source lines adjacent to each other in each period of scanning the one gate line, and for each period of scanning the one gate line. A liquid crystal display device configured to invert the polarity of a signal voltage applied to the plurality of source lines.
  7.  請求項1乃至6の何れか1つに記載された液晶表示装置において、
     上記第1薄膜トランジスタは、二股状に形成された一対の電極肢を有する上記ソース電極と、該一対の電極肢の間に配置された上記ドレイン電極とを有し、
     上記第2薄膜トランジスタは、二股状に形成された一対の電極肢を有する上記ドレイン電極と、該一対の電極肢の間に配置された上記ソース電極とを有している
    ことを特徴とする液晶表示装置。
    The liquid crystal display device according to claim 1,
    The first thin film transistor includes the source electrode having a pair of electrode limbs formed in a bifurcated shape, and the drain electrode disposed between the pair of electrode limbs,
    The second thin film transistor includes the drain electrode having a pair of electrode limbs formed in a bifurcated shape and the source electrode disposed between the pair of electrode limbs. apparatus.
  8.  請求項1乃至7の何れか1つに記載された液晶表示装置を備えている
    ことを特徴とする電子機器。
    An electronic apparatus comprising the liquid crystal display device according to any one of claims 1 to 7.
PCT/JP2012/001700 2011-03-16 2012-03-12 Liquid crystal display device and electronic apparatus WO2012124309A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003315766A (en) * 2001-09-18 2003-11-06 Sharp Corp Liquid crystal display
JP2008009375A (en) * 2006-05-31 2008-01-17 Hitachi Displays Ltd Display device
JP2008026908A (en) * 2006-07-24 2008-02-07 Samsung Electronics Co Ltd Liquid crystal display device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003315766A (en) * 2001-09-18 2003-11-06 Sharp Corp Liquid crystal display
JP2008009375A (en) * 2006-05-31 2008-01-17 Hitachi Displays Ltd Display device
JP2008026908A (en) * 2006-07-24 2008-02-07 Samsung Electronics Co Ltd Liquid crystal display device

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