WO2012119451A1 - Single-phase three-level inverter - Google Patents

Abstract

A single-phase three-level inverter includes an input capacitor (C_dc), six power switches (S₁, S₂, S₃, S₄, S₅, S₆), two free-wheeling diodes (D₇, D₈) and a single-phase output filter (F). The switching operation is performed by the cooperation of the six power switches and the free-wheeling diodes, so that when the output voltage from the inverter is zero level, the output AC side and the input DC side of the inverter are in a decoupled state, which insures that the common-mode voltage is maintained at a constant while the output voltage from the inverter is performed with three levels, so as to completely eliminate the common-mode current.

Description

 Single-phase three-level inverter Technical field

 The invention relates to an inverter in the field of power electronic technology DC-AC converter, in particular to a single-phase three-level transformerless inverter.

Background technique

With the world's energy shortage and environmental pollution becoming more and more serious, energy and the environment have become one of the most important issues facing humanity in the 21st century. The development and application of clean renewable energy has received increasing attention from all over the world. . A large amount of renewable energy is emitted from direct current, which needs to be converted into commercial frequency alternating current through an inverter to be applied in large quantities. Therefore, inverter technology plays a vital role in the development and utilization of renewable energy.

Inverter refers to a power electronic converter that converts DC power into AC power through the turn-on and turn-off functions of a semiconductor power switching device. The early inverter circuit was usually a square wave circuit. Due to the successful application of pulse width modulation (PWM) technology in power electronics, a PWM inverter circuit with voltage regulation and frequency conversion function was developed. Common inverter circuit topologies using PWM modulation include full-bridge circuits, half-bridge circuits, half-bridge midpoint clamp circuits, and various multilevel circuits.

According to the output level, the PWM inverter circuit system can be divided into a two-level circuit, a three-level circuit, and a multi-level circuit. The two-level circuit refers to the level of positive and negative polarity of the output voltage waveform in each PWM circuit control mode under the PWM modulation control mode, and the traditional square wave inverter or phase shift voltage regulation full bridge inverse Compared with the variable circuit, the output voltage adjustment of the two-level inverter circuit is convenient, and the output harmonic performance is good. The three-level circuit means that the output voltage of the inverter is only zero and one positive or negative level in each switching cycle. Compared with the two-level circuit, the output voltage and current harmonic performance of the three-level inverter circuit is better. At the same time, since the change of the inverter output voltage is half of the two-level circuit in each switching cycle, the parameters of the output filter will be significantly reduced, and the volume and weight of the entire circuit device are also significantly reduced. Multi-level circuits are mainly used in high-voltage and high-power applications. Due to the limited voltage blocking capability and current output capability of power switching devices, multi-level circuits using power devices in series-parallel expansion and expansion are used in high-voltage and high-power applications. More suitable.

According to the inverter application and control mode, the inverter system can be divided into a stand-alone inverter and a grid-connected inverter; according to the transformer configuration in the inverter, the inverter system can be divided into Power frequency transformer type inverter with high frequency transformer type inverter and transformerless type inverter. The inverter with power frequency transformer or high frequency transformer can realize the functions of boosting and isolation. However, the inverter with power frequency transformer is bulky, the weight is increased, the price is expensive, and the system is inconvenient to install; Although the size and weight of the inverter are greatly reduced, such inverter systems are often composed of multiple stages, resulting in a complicated system structure and reduced system efficiency. The transformerless inverter has been rapidly developed in the world due to its simple system structure, high efficiency, small size and low cost.

technical problem

The invention provides a transformerless single-phase three-level inverter with a simple structure and capable of eliminating a common mode current while using a unipolar pulse width modulation method.

Technical solution

A single-phase three-level inverter of the present invention includes an input capacitor, a first power switch, a second power switch, a third power switch, a fourth power switch, a fifth power switch, and a sixth power switch, first a freewheeling diode, a second freewheeling diode and a filter; a drain of the first power switch, a drain of the third power switch, a positive terminal of the input capacitor connected to the anode of the input DC terminal; a source of the first power switch, a drain of the second power switch, an anode of the first freewheeling diode, a cathode of the second freewheeling diode connected to the first input end of the filter; a source of the second power switch, a source of the sixth power switch, and an input capacitor The negative terminal is connected to the negative terminal of the input DC terminal; the source of the third power switch, the cathode of the first freewheeling diode is connected to the drain of the fourth power switch; the drain of the sixth power switch, and the anode of the second freewheeling diode Connected to the source of the fifth power switch; the source of the fourth power switch, the drain of the fifth power switch is connected to the second input of the filter.

The first power switch is composed of a first switching transistor and a first anti-parallel diode in parallel, the second power switch is composed of a second switching transistor and a second anti-parallel diode in parallel, and the third power switch is composed of a third switching transistor and a third The third reverse parallel diode is composed of a parallel connection. The fourth power switch is composed of a fourth switching transistor and a fourth reverse parallel diode. The fifth power switch is composed of a fifth switching transistor and a fifth reverse parallel diode. The sixth power switch is composed of a sixth power switch. The switching transistor and the sixth anti-parallel diode are formed in parallel; the parallel connection manner of the switching transistor and the anti-parallel diode is: the drain or collector of the switching transistor is connected with the cathode of the anti-parallel diode to form the drain of the power switch, the source of the switching transistor or The emitter is connected to the anode of the reverse diode to form the source of the power switch.

The freewheeling diode is a separate diode or a switching transistor with a reversed diode.

The input capacitor is a capacitor or a combination of capacitors composed of a plurality of capacitors connected in parallel.

The filter is a single inductor filter, an inductor-capacitor filter or an inductor-capacitor-inductive filter.

The switching transistor is a high voltage metal oxide silicon field effect transistor or an insulated bipolar transistor.

The anti-parallel diode is a diode built in a separate diode or a switching transistor.

There are two types of modulation methods for the inverter of the present invention, a unipolar pulse width modulation method 1 and a unipolar pulse width modulation method 2.

In the unipolar pulse width modulation mode 1, the first switching transistor, the second switching transistor, the third switching transistor, and the sixth switching transistor are alternately switched in a power frequency cycle (for example, 50 Hz) and a high frequency cycle (for example, 20 kHz). . In the positive half cycle of the power frequency, the first switching transistor and the sixth switching transistor synchronously operate at a high frequency, the second switching transistor and the third switching transistor are normally closed, the fourth switching transistor is normally closed, and the fifth switching transistor is normally open; In the negative half cycle, the first switching transistor and the sixth switching transistor are normally closed, the second switching transistor and the third switching transistor are synchronized in high frequency operation, the fourth switching transistor is normally open, and the fifth switching transistor is normally closed.

In the unipolar pulse width modulation mode 2, the first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, the fifth switching transistor, and the sixth switching transistor are alternated in a power frequency cycle (for example, 50 Hz) and The switching operation is performed at a high frequency period (for example, 20 kHz). In the positive half cycle of the power frequency, the first switching transistor and the sixth switching transistor synchronously operate at a high frequency, the second switching transistor and the third switching transistor are normally closed, the fourth switching transistor is complementary to the first switching transistor, and the fifth switching transistor is often In the negative half cycle of the power frequency, the first switching transistor and the sixth switching transistor are normally closed, the second switching transistor and the third switching transistor are synchronized with high frequency operation, the fourth switching transistor is normally open, and the fifth switching transistor and the second switch are The transistors are complementarily turned on.

When the single-phase three-level inverter of the present invention is operated, six power switches with inverted diodes are coordinated with two freewheeling diodes to perform switching operations, so that the inverter output voltage is at zero level, the inverter output The AC side and the input DC side are decoupled, ensuring that the inverter output voltage is three-level during the entire modulation process, while the common-mode voltage on the output side of the inverter remains constant, thus completely eliminating Common mode current.

In the inverter of the present invention, when the above two unipolar pulse width modulation modes are adopted, when the operating mode of the circuit is switched, the parasitic junction capacitance voltage of the power switch is always balanced, so that no additional pulse width modulation strategy or hardware circuit is required. To compensate the voltage balance problem of the parasitic junction capacitance, so its control mode is relatively simple; the inverter output voltage of the invention is three-level, thereby greatly reducing the volume of the output filter and reducing the loss on the filter; The inverter of the invention only needs to set a dead zone when the output current is near the power frequency zero crossing point, so the circuit output power quality is good and the stability of the circuit is high. The inverter of the invention can be applied to a stand-alone inverter and a grid-connected inverter system, and is particularly suitable for use in a distributed photovoltaic grid-connected power generation system.

Beneficial effect

The invention utilizes six power switches with anti-parallel diodes and two freewheeling diodes to coordinate the switching action, completely eliminating the common mode current; the circuit has a simple control mode and a reliable dead zone working mechanism in a suitable modulation mode. . The invention adopts the unipolar pulse width modulation mode, and the output current ripple is reduced, thereby improving the output power quality of the inverter, reducing the volume and weight of the filter, and reducing the copper loss and magnetic force generated on the filter inductor. damage. The invention has a simple structure and can realize a three-level output voltage while eliminating the common mode current.

DRAWINGS

 1 is a circuit diagram of a single-phase three-level inverter of the present invention.

 2 is a waveform diagram of the unipolar pulse width modulation method 1 of the present invention.

 Fig. 3 is a schematic diagram showing the waveform of the unipolar pulse width modulation mode 2 of the present invention.

 4a-4j are schematic views of ten operational modes of the single-phase three-level inverter of the present invention.

Embodiments of the invention

Referring to Figure 1, a single-phase three-level inverter of the present invention includes an input capacitor C _dc , a first power switch S ₁ , a second power switch S ₂ , a third power switch S ₃ , and a fourth power switch. S ₄ , a fifth power switch S ₅ , a sixth power switch S ₆ , a first freewheeling diode D ₇ , a second freewheeling diode D ₈ and a filter F;

The first power switch S _{1 of} this embodiment is composed of a first switching transistor T ₁ and a first reverse-parallel diode D _{1 in} parallel, and the second power switch S _{2 is} composed of a second switching transistor T ₂ and a second reverse-diode D _{2 is} composed in parallel, the third power switch S _{3 is} composed of a third switching transistor T ₃ and a third anti-parallel diode D _{3 in} parallel, and the fourth power switch S ₄ is connected in parallel by the fourth switching transistor T ₄ and the fourth anti-parallel diode D ₄ The fifth power switch S _{5 is} composed of a fifth switching transistor T ₅ and a fifth reverse parallel diode D _{5 in} parallel, and the sixth power S ₆ switch is composed of a sixth switching transistor T ₆ and a sixth reverse parallel diode D _{6 in} parallel; The parallel connection between the switching transistor and the anti-parallel diode is such that the drain or collector of the switching transistor is connected to the cathode of the anti-parallel diode to form the drain of the power switch, and the source or emitter of the switching transistor is connected to the anode of the anti-parallel diode to form a power. The source of the switch.

The drain of the first power switch S ₁ , the drain of the third power switch S ₃ , and the positive terminal of the input capacitor C _dc are connected to the anode of the input DC terminal; the source of the first power switch S ₁ and the second power switch S ₂ drain of a first freewheeling diode D the anode _7, a first input of the second cathode of the freewheeling diode D ₈ is connected to the filter; a second power source switch S pole _{2,. 6} of the sixth power switch S a source, a negative terminal of the input capacitor C _dc is connected to a negative terminal of the input DC terminal; a source of the third power switch S _{3 ,} a cathode of the first freewheeling diode D ₇ is connected to a drain of the fourth power switch S ₄ ; S drain of the power _{switch. 6,} the second anode of the freewheeling diode D and the fifth power source switch ₈ is connected to the source _{S. 5;} the fourth power source switch S pole _4, the fifth drain of the power switch of the _{filter. 5} S The second input of the device is connected;

The modulation method of the inverter of the present invention is unipolar pulse width modulation.

2 is a waveform diagram of a unipolar pulse width modulation scheme 1 in which u _c is a high frequency carrier (eg, 20 kHz) and u _g is a power frequency modulated wave (eg, 50 Hz). The first switching transistor T ₁ , the second switching transistor T ₂ , the third switching transistor T _{3 ,} and the sixth switching transistor T ₆ alternately perform switching operations at a power frequency period (for example, 50 Hz) and a high frequency period (for example, 20 kHz). When the modulated wave u _{g is} in the positive half cycle, the first switching transistor T ₁ and the sixth switching transistor T ₆ synchronously operate at a high frequency, the second switching transistor T ₂ and the third switching transistor T _{3 are} normally closed, and the fourth switching transistor T ₄ normally closed, the fifth switching transistor T _{5 is} normally open; when the modulation wave u _{g is} in the negative half cycle, the first switching transistor T ₁ and the sixth switching transistor T _{6 are} normally closed, and the second switching transistor T ₂ and the third switching transistor are T ₃ synchronous high-frequency operation, a fourth normally open switching transistor T _4, the fifth switching transistor T ₅ normally closed.

3 is a waveform diagram of a unipolar pulse width modulation method 2, wherein u _c is a high frequency carrier (eg, 20 kHz), u _g is a power frequency modulated wave (eg, 50 Hz), and the first switching transistor T ₁ , the second The switching transistor T ₂ , the third switching transistor T ₃ , the fourth switching transistor T ₄ , the fifth switching transistor T _{5 ,} and the sixth switching transistor T ₆ are alternately performed at a power frequency period (for example, 50 Hz) and a high frequency period (for example, 20 kHz). Switch action. When the modulated wave u _{g is} in the positive half cycle, the first switching transistor T ₁ and the sixth switching transistor T ₆ synchronously operate at a high frequency, the second switching transistor T ₂ and the third switching transistor T _{3 are} normally closed, and the fourth switching transistor T ₄ is complementary to the first switching transistor T ₁ , the fifth switching transistor T _{5 is} normally open; when the modulation wave u _{g is} in the negative half cycle, the first switching transistor T ₁ and the sixth switching transistor T _{6 are} normally closed, and the second switching transistor T ₂ and the third switching transistor T _{3 are} synchronized in high frequency operation, the fourth switching transistor T _{4 is} normally open, and the fifth switching transistor T ₅ is complementary to the second switching transistor T ₂ .

Referring to Figures 4a - 4j, there are mainly 10 modes of operation for the inverter of the present invention throughout its operation. Wherein: the operation mode 1, the current flowing through the first switching transistor T _1, the fifth and the sixth switching transistor the switching transistor T ₅ T _6, the inverter output voltage is positive; mode 2 during operation, current flows through the fifth The switching transistor T ₅ and the second freewheeling diode D ₈ , the inverter outputs a zero level; in the operating mode 3, the current flows through the sixth reverse parallel diode D ₆ , and the fifth reverse parallel diode D ₅ and the first reverse Diode D ₁ , the inverter outputs a positive voltage; in the operating mode 4, the current flows through the first freewheeling diode D ₇ , the fourth switching transistor T ₄ , the inverter outputs a zero level; in the operating mode 5, the current Flowing through the third switching transistor T ₃ , the fourth switching transistor T ₄ and the second switching transistor T ₂ , the inverter outputs a negative voltage; in the operating mode 6, the current flows through the first freewheeling diode D ₇ and the fourth switch Transistor T ₄ , the inverter outputs a zero level; in operation mode 7, current flows through the second switching transistor T ₂ , the fourth reverse parallel diode D ₄ and the third reverse parallel diode D ₃ , and the inverter outputs a negative voltage ; 8 when the operating mode, current flows through the fifth switching transistor T _5, Two freewheeling diode D _8, the inverter output voltage is zero. 9 when the mode of operation, a current flows through the sixth diode and the anti-D _6, and a fifth inverse diode D _5, and the first inverse diode D _1, the inverter output positive level. In operation mode 10, current flows through the second reverse parallel diode D ₂ , the fourth reverse parallel diode D ₄ , and the third reverse parallel diode D ₃ , and the inverter outputs a negative level. In the operating mode 2, the operating mode 4, the operating mode 6 and the operating mode 8, the first switching transistor T ₁ and the first anti-parallel diode D ₁ are both in an off state, the second switching transistor T ₂ and the second inversion And the diode D ₂ is in an off state, the third switching transistor T ₃ and the third anti-parallel diode D ₃ are both in an off state, and the sixth switching transistor T ₆ and the sixth anti-parallel diode D ₆ Both are in the off state, so that the inverter output AC side and the input DC side are in a decoupled state, thereby ensuring that the output of the inverter has no common mode leakage current.

The power switch of the embodiment may be composed of a switching transistor with an internal anti-parallel diode therein, or may be composed of an independent switching transistor and an independent diode in anti-parallel; the freewheeling diode is a separate diode or internal a switching transistor having a reverse-diode diode; the switching transistor may be a fully-controlled power semiconductor device such as a power metal oxide silicon field effect transistor or an insulated bipolar transistor; and the anti-parallel diode is an independent diode or a switching transistor internal The diode F is an inductive filter, and can also be replaced by an inductor-capacitor filter or an inductor-capacitor-inductive filter; the transformerless inverter structure described in this embodiment is applicable. The grid-connected inverter is also suitable for stand-alone inverter structures or other transformerless inverters.

Claims (7)

1. A single-phase three-level inverter comprising an input capacitor (C _dc ), a first power switch (S ₁ ), a second power switch (S ₂ ), a third power switch (S ₃ ), and a fourth power switch (S ₄ ), a fifth power switch (S ₅ ), a sixth power switch (S ₆ ), a first freewheeling diode (D ₇ ), a second freewheeling diode (D ₈ ), and a filter (F); The drain of a power switch (S ₁ ), the drain of the third power switch (S ₃ ), the positive terminal of the input capacitor (C _dc ) are connected to the anode of the input DC terminal; the source of the first power switch (S ₁ ) a drain of the second power switch (S ₂ ), an anode of the first freewheeling diode (D ₇ ), and a cathode of the second freewheeling diode (D ₈ ) are connected to the first input end of the filter (F); The source of the second power switch (S ₂ ), the source of the sixth power switch (S ₆ ), the negative terminal of the input capacitor (C _dc ) are connected to the negative terminal of the input DC terminal; the source of the third power switch (S ₃ ) The cathode of the first freewheeling diode (D ₇ ) is connected to the drain of the fourth power switch (S ₄ ); the drain of the sixth power switch (S ₆ ), and the anode of the second freewheeling diode (D ₈ ) a fifth power switch (S ₅₎ is connected to a source electrode; a second The power switch (S ₄₎ of a source, a second input terminal connected to a fifth power switch (S ₅₎ and a drain filter (F); and by the first power switch (S _1), second power switch ( S ₂ ), the third power switch (S ₃ ), the fourth power switch (S ₄ ), the fifth power switch (S ₅ ), and the sixth power switch (S ₆ ) are input to the pulse width modulation signal, and the inverse The transformer converts the input DC power into AC power.
2. The single-phase three-level inverter according to claim 1, wherein said power switch is composed of a switching transistor and an anti-parallel diode in anti-parallel, a drain or a collector of the switching transistor and a cathode of the anti-parallel diode Connected to form the drain of the power switch, the source or emitter of the switching transistor is connected to the anode of the opposing diode to form the source of the power switch.
3. The single-phase three-level inverter according to claim 1, wherein the first freewheeling diode (D ₇ ) and the first freewheeling diode (D ₈ ) are independent diodes or are reversed. Diode switching transistor
4. The single-phase three-level inverter according to claim 1, wherein the input capacitance (C _dc ) is a capacitor or a combination of capacitors composed of a plurality of capacitors in series.
5. The single-phase three-level inverter according to claim 1, wherein said filter (F) is a single inductor filter, an inductor-capacitor filter or an inductor-capacitor-inductive filter. .
6. The single-phase three-level inverter according to claim 2, wherein said switching transistor is a high voltage metal oxide silicon field effect transistor or an insulated bipolar transistor.
7. The single-phase three-level inverter according to claim 2, wherein said anti-parallel diode is a self-contained anti-parallel diode of a separate diode or a switching transistor.

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