WO2012116531A1

WO2012116531A1 - Correlator array and realization method thereof

Info

Publication number: WO2012116531A1
Application number: PCT/CN2011/076719
Authority: WO
Inventors: 沈承科
Original assignee: 中兴通讯股份有限公司
Priority date: 2011-03-02
Filing date: 2011-06-30
Publication date: 2012-09-07
Also published as: CN102655421A; CN102655421B

Abstract

A correlator array and a realization method thereof are provided by the present invention. The correlator array de-spreads Code Division Multiple Access (CDMA) signals received by antennas in parallel by an adder array composed of K/2 complex adders, and spreading factors of the CDMA signals are halved for each iteration. Since the present correlator array is a parallel array, each iteration can be simultaneously performed for multiple CDMA signals, or the same symbol of different users or different paths, and an array having K/2 adders only needs 2N/K periods on average to complete de-spreading of a CDMA symbol with spreading factor N. Therefore, the correlator of the present invention has high processing speed, which achieves high speed de-spreading correlation and improves the efficiency of the de-spreading correlation.

Description

Correlator array and implementation method thereof

The present invention relates to a multimode soft baseband platform technology with reconfiguration functionality, and more particularly to a correlator array in a reconfigurable iterative correlation array processor and an implementation method thereof. Background technique

In order to improve the efficiency of the baseband processor and reduce the cost of the baseband processor, a multimode soft baseband platform with reconfiguration function is increasingly widely used. At present, the reconfigurable multi-mode soft baseband platform is basically based on a general-purpose parallel array processor. However, existing arrays with general-purpose computing functions are often inefficient when performing despreading correlation in a code division multiple access (CDMA) system. Summary of the invention

In view of this, the main object of the present invention is to provide a correlator array and an implementation method thereof, which can realize high-speed despreading correlation and improve the efficiency of despreading correlation.

In order to achieve the above object, the technical solution of the present invention is achieved as follows:

An correlator array, including an adder array, a PN buffer, and a local cache, a first loop network and a second loop network respectively corresponding to the PN buffer and the local cache, and a switch;

PN buffer for storing PN code;

a local buffer for storing data from the receiving antenna, or an intermediate result of the operation; the first loop network, connecting the output port of the PN buffer and the input port of the adder array, for processing the input PN code, implementing the antenna Synchronous alignment of data;

a second loop network connecting the output port of the local data buffer and the input port of the adder array for processing the input data from the receiving antenna to achieve synchronous alignment with the PN code;

The adder array is composed of a set of complex adders for performing positive and negative sign conversion on each antenna data according to the PN code corresponding to the antenna data, and the data after each two positive and negative sign conversion is a group. Inputting to an array of operators consisting of K/2 complex adders to complete the merging, and outputting the combined Κ/2 intermediate symbols to the switch;

A switch for selecting to send Κ/2 intermediate symbols from the adder array to the left or right half of the local cache with 独立 separate pages, each half having Κ/2 pages.

The buffer contains one independent memory page, each memory unit is 1 bit or 2 bits, and the data is read and written in one cycle.

The local cache contains a plurality of independent memory pages, each of which has a width (η + η) bits for storing a complex number of (η + η) bits.

The number of the complex adders is Κ/2, and the scale of the adder array is Κ.

The adder array is specifically used to:

Aligning one weight from the first input port and the second input port and one signal data from the receiving antenna, respectively, into the latch array L _PN and the latch array L _s in parallel; Corresponding pseudo code, each signal data is converted into positive and negative sign by the sign conversion array, and each two groups are sent into an operation array composed of K/2 complex adders to complete the combination; the obtained K/2 The result is latched to the output latch array L. _{In ut} , it is output to the switch.

The correlator array is used independently as a programmable soft accelerator; or integrated into a general purpose array processor for use as a programmable soft accelerator.

A method for implementing a correlator array, comprising:

Receiving K PN codes from the first input port, receiving K signal data from the receiving antenna from the second input port, and respectively buffering in the PN buffer and the local buffer;

Synchronizing between the PN code and the signal data by using the first loop network and the second loop network; according to the PN code corresponding to the signal data, each signal data is converted into a sign by the sign conversion array, and then every two Each group is fed into an operation array composed of K/2 complex adders to complete the merging; the obtained K/2 results are outputted to the array of latches and output to the switch;

The switch sends the K/2 intermediate symbols from the adder array to the left or right half of the local cache with K independent pages by selection, each half having a K/2 page. The synchronizing the synchronization between the PN code and the signal data by using the first loop network and the second loop network includes: synchronizing by cyclic shift.

Performing an iteration of the correlator array includes: simultaneously performing multiple symbols, or the same symbol but different users or paths.

It can be seen from the above technical solution provided by the present invention that the correlator array provided by the present invention completes the parallel despreading of the CDMA signals received by the antenna through an adder array composed of K/2 complex addition units. One iteration halve the spreading factor of the CDMA symbol. Since the correlator array is a parallel array, one iteration can be performed on multiple CDMA symbols simultaneously, or the same symbol but different users or paths, and an array with K/2 adders can only average 2N/K cycles. Completion of a CDMA symbol despreading with a spreading factor of N. Therefore, the correlator array of the present invention has a high processing speed, realizes high-speed despreading correlation, and improves the efficiency of understanding the correlation. DRAWINGS

1 is a schematic structural diagram of an application of a reconfigurable iterative correlation array of the present invention; FIG. 2 is a schematic structural diagram of a correlator array of the present invention;

3 is a schematic structural diagram of a loop network in a correlator array of the present invention;

4 is a schematic structural diagram of an adder array in a correlator array of the present invention; FIG. 5a is a schematic structural diagram of a PN buffer in a correlator array of the present invention;

FIG. 5b is a schematic structural diagram of a local cache in a correlator array according to the present invention; FIG.

6 is a schematic diagram of a data structure in a local cache in a correlator array according to the present invention; FIG. 7 is a schematic diagram of an embodiment of a first-stage despreading iteration of a correlator array according to the present invention. detailed description

1 is a schematic structural diagram of an application of a reconfigurable iterative correlation array according to the present invention. As shown in FIG. 1, the application of the reconfigurable iterative correlation array of the present invention includes two parts: The first part is microcode. A controller composed of a buffer and a microcoder, the controller performs the following control functions according to the microcode: reading the external PN code into the PN code buffer; reading the external antenna data into the local buffer; according to the relative relationship between the PN code and the antenna data The position generates a loop control signal of two loop networks; generates an adder array control signal; and generates an output switch control signal. The controller can be implemented by any general-purpose CPU or a controller in a general-purpose array processor, which is well known to those skilled in the art, and the specific implementation is not intended to limit the scope of the present invention, nor is it within the scope of the present invention. The second part is a correlator array including an adder array, a PN buffer and a local cache, a switch, and a respective loop network of the PN buffer and the local cache (ie, the first loop network and the second loop network in FIG. 1).

The correlator array of the present invention is configured to perform CDMA despreading by successive iterative compression of CDMA spread symbols under the control of the controller. The correlator array can be used alone under the control of a general-purpose CPU or integrated into a general-purpose array processor to perform CDMA signal despreading and multipath searching as a CDMA dedicated acceleration array.

2 is a schematic structural diagram of a correlator array according to the present invention. As shown in FIG. 2, the correlator array of the present invention includes an adder array, a PN buffer, and a local cache, and a PN cache and a local cache respectively correspond to the first loop network and the first a second loop network, and a switch F, wherein

The PN buffer is a dual-port data memory, a' mouth read, and e-port write, used to store the PN code. The PN buffer contains K independent memory pages, each of which is 1 bit or 2 bits (complex PN code), and the data is read and written in one cycle. Among them, K is related to the implementation cost. The larger the value of K, the higher the hardware implementation cost, but the processing speed will be higher. Conversely, the smaller the K, the lower the implementation cost and the lower the processing speed.

The local cache is a dual-port data memory, b, port read, d-port write, used to store data and arithmetic intermediate results from the receive antenna. Similar to the PN buffer, the local cache also contains K independent memory pages, each of which has a (n+n)-bit width for storing a complex number of (n+n) bits.

The data from the antenna is written to the local cache at the given address, and the result after each iteration is sequentially written back to the left and right half of the local cache through the output switch.

The PN cache and the local cache may also be single-port data memory, and the specific use is a person skilled in the art. The usual technical means of the staff, no longer repeat them here.

The first loop network, which is connected to the output port a of the PN buffer and the input port a of the adder array, is used for cyclically shifting the input PN code to achieve synchronous alignment with the antenna data.

The second loop network connects the output port b of the local data buffer with the input port b of the adder array for cyclically shifting the input data from the receiving antenna to achieve synchronization with the PN code.

The first and second loop networks are primarily used to synchronize the locally generated PN code with the antenna input data. The PN code and antenna data are placed sequentially in rows in their respective buffers. However, their starting positions are different. The first and second loop networks cyclically shift the PN code and the antenna data to align them, i.e., synchronize, and then send them to the adder array.

The adder array is composed of a set of complex adders for performing positive and negative sign conversion on each antenna data according to the PN code corresponding to the antenna data, and the data after each two positive and negative sign conversion is a group, respectively input The array of operators consisting of K/2 complex adders is merged, and the combined K/2 intermediate symbols are latched into the output latch array and output to switch F.

Wherein, the number of complex adders is half of the scale of the adder array. For example, if the adder array contains K/2 complex adders, then the scale of the adder array is K. The adder array has two input ports, input port a and input port b, and an output port c. Wherein, input port a has K inputs, each input bit width is 1 bit or 2 bits; input port b also has K inputs, each input bit width is 2n bits (used to represent one of (n+n) bits Complex); Output port c has K/2 outputs, and each input is also a complex number of (n+n) bits.

Switch F is an alternative switch. Used to select to send K/2 intermediate symbols from the adder array to the left or right half of the local cache with K independent pages, each with a K/2 page.

The correlator array provided by the present invention completes the parallel despreading of the CDMA signal received by the antenna through an adder array composed of K/2 complex addition units, and halve the spreading factor of the CDMA symbol every iteration. Since the correlator array is a parallel array, one iteration can Simultaneously for multiple CDMA symbols, or the same symbol but different users or paths, an array with K/2 adders requires only 2N/K cycles to complete a CDMA symbol despread with a spreading factor of N. For example: K/2=64, Ν=256, then only 4 cycles are required to complete the despreading operation of the symbol. Therefore, the correlator array of the present invention has a high processing speed, realizes high-speed despreading correlation, and improves the efficiency of understanding the expansion correlation.

The correlator array of the present invention can be used as a despreading correlator in a Rake receiver, a multipath searcher, and a random access channel (RACH) detector in a wireless system such as CDMAAVCDMA/CDMA2000. The correlator array of the present invention can be used independently as a programmable soft accelerator or integrated into a general purpose array processor for use as a programmable soft accelerator.

The various components of the correlator array of the present invention are described in detail below.

3 is a schematic structural diagram of a loop network in a correlator array according to the present invention. As shown in FIG. 3, the loop network converts an input vector X into an output vector Y by cyclic shift, that is, an element of the vector Y is a vector X. The cyclic displacement of the elements. The specific implementation of the loop network belongs to the conventional technical means of those skilled in the art, and will not be described herein.

4 is a schematic structural diagram of an adder array in the correlator array of the present invention, as shown in FIG. 4, the PN code is input to the input port a through the first loop network, and the signal data is input to the input port b through the second loop network; The synchronization between the PN code and the signal data is coordinated by the first loop network and the second loop network. K PN codes from input port a and input port b and K signal data from the receiving antenna, respectively, are latched in parallel into the latch array L _PN and the latch array L _s ; according to their corresponding PN code Each signal data is converted into a sign by a positive and negative sign conversion array, and then each two adjacent groups are fed into an adder array composed of K/2 complex adders to complete the merging; finally, this K/2 The result is latched into the output latch array L. _{In ut} , it is output to the switch.

5a is a schematic structural diagram of a PN buffer in a correlator array according to the present invention, and FIG. 5b is a schematic structural diagram of a local cache in a correlator array according to the present invention. As shown in FIG. 5a and FIG. 5b, each cache array has K independent caches. Storing a page, wherein the PN code storage page is 1 or 2 bits wide per unit bit, and is used for storing a 1-bit real pseudo code or a 2-bit complex pseudo code; The element is 2n bits wide and is used to store (n + n) bits of complex data. In the two caches, each page is a dual-port data memory, an oral read, and a port write. Both are required to operate in parallel, and two cache arrays can be read in parallel by the adder array at each cycle.

The write port of the local data cache array is divided into left and right halves. Since the data from the adder array is only K/2, when the data is from the output of the adder array, only half of the write is written.

6 is a schematic diagram of data structure in a local cache in a correlator array of the present invention, and FIG. 6 shows a data structure of a m-time oversampled signal of a CDMA antenna in a local data buffer, and FIG. 6 assumes m=8, as shown in FIG. As shown in Fig. 6, each m times oversampling chip occupies m units, and the signal sequence data is arranged from left to right in units of m units; after occupying K pages, another line is continued until the end of the line.

The iterative working principle is as follows: 4. Set a CDMA symbol X with a spreading factor of 256. If 8 times oversampling is performed, there are 2048 samples of data. One out of every 8 data (one per chip), a total of 256 sampled data; these 256 sampled data vectors are called original symbols, where the sub-vector consisting of any less than 256 adjacent data is called the original symbol. segment. After multiplication with the corresponding 256 PN chips, each two adjacent data is first compressed and merged by the adder, and the result is 128 intermediate data; the vector composed of the 128 intermediate data is called the intermediate symbol. , where the sub-vector consisting of any less than 128 adjacent data is called the intermediate symbol segment. Each compression iteration completes a 2:1 compression, in which all intermediate results are called intermediate symbols or intermediate symbol segments.

FIG. 7 is a schematic diagram of an embodiment of a first embodiment despreading iteration of a correlator array according to the present invention. As shown in FIG. 7, unlike the subsequent compression, the first step of compression must also complete the multiplication of the signal data with the corresponding bit of the PN code. . It can be seen from Fig. 7 that the PN code and the antenna signal data are respectively read from the PN buffer and the local data buffer, and the synchronization alignment is completed through the respective loop networks; then, the positive and negative of each antenna data is completed according to the corresponding PN code. Number conversion, and simultaneously using the adder array to complete 2: 1 data merging, ie 2:1 symbol compression to generate intermediate symbols; Finally, the generated K/2 intermediate symbols are written back through the left or right half of the local cache.

The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalents, and improvements made within the spirit and scope of the present invention. And so on, should be included in the scope of protection of the present invention.

Claims

Claim

A correlator array, comprising: an adder array, a PN buffer, and a local cache, a first loop network and a second loop network respectively corresponding to the PN buffer and the local cache, and a switch; wherein

PN buffer for storing PN code;

The adder array is composed of a set of complex adders for performing positive and negative sign conversion on each antenna data according to the PN code corresponding to the antenna data, and the data after each two positive and negative sign conversion is a group, respectively input The array of operators consisting of K/2 complex adders is merged, and the merged

K/2 intermediate symbols are latched and output to the switch;

A switch for selecting to send K/2 intermediate symbols from the adder array to the left or right half of the local cache with K independent pages, each half having a K/2 page.

2. The correlator array according to claim 1, wherein the PN buffer contains K independent storage pages, each storage unit is 1 bit or 2 bits, and the data is read and written in one cycle. .

3. The correlator array according to claim 1, wherein the local cache contains K independent memory pages, each memory cell having a width of (n+n) bits for storing one (n+n) ) The plural of the bit.

4. The correlator array according to claim 1, wherein the number of the complex adders is K/2, and the scale of the adder array is K.

5. The correlator array of claim 4, wherein the adder array Specifically used for:

K PN codes from the first input port and the second input port and K signal data from the receiving antenna, respectively, are latched in parallel into the latch array L _PN and the latch array L _{s respectively} ; Corresponding pseudo code, each signal data is converted into positive and negative sign by the sign conversion array, and each two groups are sent into an operation array composed of K/2 complex adders to complete the combination; the obtained K/2 The result is latched to the output latch array L. _{In ut} , it is output to the switch.

6. The correlator array according to any one of claims 1 to 5, wherein the correlator array is used independently as a programmable soft accelerator; or integrated into a general-purpose array processor as a programmable soft accelerator use.

7. A method for implementing a correlator array, comprising:

The switch passes the K/2 intermediate symbols from the adder array to the left or right half of the local cache with K independent pages, each with a K/2 page.

8. The implementation method according to claim 7, wherein the synchronizing the synchronization between the PN code and the signal data by using the first loop network and the second loop network comprises: synchronizing by cyclic shift.

9. The method according to claim 7 or 8, wherein the iterative execution of the correlator array comprises: simultaneously performing a plurality of symbols, or the same symbol but different users or paths.