US9270324B2 - Efficient generation of spreading sequence correlations using lookup tables - Google Patents
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- the technology relates to communications, and in particular, to receiving and detecting multiple symbols transmitted using spreading codes.
- CDMA code division multiple access
- advanced non-linear receivers using joint detection such as sphere decoders, assisted maximum likelihood detection (AMLD), multi-stage group detection (MSGD) etc., or symbol-level interference cancellation (IC) require the computation of spreading code correlations to achieve better performance than linear receivers.
- WCDMA wideband CDMA
- the spreading sequence correlations are symbol-dependent since the scrambling sequence is symbol-dependent. For example, two spreading sequences of spreading factor 16 have one set of correlation values for one symbol period, but another set of correlation values for the next symbol period. Because the correlations change from symbol to symbol, online correlation computation is very demanding.
- the scrambling codes are often long, e.g., for a WCDMA system 10 milliseconds (or 38400 chips long), which also means that precomputed correlations of the spreading sequences require large amounts of memory to store such large number of correlations.
- Apparatus receives a signal containing a block of multiple symbols, each symbol containing information bits spread by a spreading sequence of chips.
- Each spreading sequence is determined by a channelization sequence and a first complex-valued scrambling sequence of chips or a second complex-valued scrambling sequence of chips.
- Correlation circuitry processes each block using a set of multiple spreading sequences using one or more correlations between one or more pairs of spreading sequences in the set.
- Spreading sequence correlation values between each pair of the multiple spreading sequences in the set are manipulated and stored in one or more lookup tables.
- An address generator addresses one of the lookup tables with an address determined using a first set of reduced basic scrambling bits to retrieve one or more correlation values from the addressed lookup table.
- the first set of reduced basic scrambling bits is based on manipulation of one set of the basic scrambling bits that reduces a number of bits included in the determined address to less than a number of binary values in the one set of basic scrambling bits.
- the one set of basic scrambling bits is used to construct one of the first and second complex-valued scrambling sequences.
- Symbol estimation circuitry uses the retrieved one or more correlation values in mitigating spreading sequence correlation interference between spreading sequences in the set in a process to detect symbol values for two or more information symbols in the received block.
- the one set of the basic scrambling bits is the one set of scrambling generation bits.
- the one set of the basic scrambling bits is expressed as the one scrambling sequence. Without loss of generality, the one scrambling sequence or the one set of the basic scrambling bits are used as examples.
- manipulation of the one scrambling sequence includes exploiting one or more redundancies of the one scrambling sequence.
- the manipulation includes eliminating at least one bit in a row address for addressing the one lookup table based on a redundant bit value in the one scrambling sequence.
- the manipulation includes storing only one correlation value for two different correlations between each pair of the multiple spreading sequences.
- the manipulation includes storing rows in the lookup table only where a first bit in each of two of the first set of basic scrambling bits is equal to 0 in a 0/1 representation of binary bits.
- each complex-valued scrambling sequence is determined by a first binary-valued scrambling sequence that determines a real part of the complex-valued scrambling sequence and a second binary-valued scrambling sequence that determines an imaginary part of the complex-valued scrambling sequence.
- a code generator generates the first and second binary-valued scrambling sequences for the first complex-valued scrambling sequence.
- a scrambling bits processor determines the first set of the address bits based on the first and second binary-valued scrambling sequences for the first complex-valued scrambling sequence.
- the address includes a first set of address bits and a second set of address bits.
- the code generator generates the first and second binary-valued scrambling sequences for the second complex-valued scrambling sequence.
- the scrambling bits processor determines a second set of address bits based on the first and second binary-valued scrambling sequences for the second complex-valued scrambling sequence.
- the one lookup table is addressed with an address determined using the first set of address bits and the second set of the address bits to retrieve a first set of correlation values associated with the spreading sequences of the two or more information symbols.
- mapping circuitry maps the first set of correlation values to an actual correlation value.
- determining the first set of address bits includes using an anchor bit among the first set of the basic scrambling bits to obtain an exclusive-OR (XOR) product with each of the other bits among the first set of the basic scrambling bits and forming the first set of address bits based on the XOR products.
- XOR exclusive-OR
- the first set of address bits represents a number that is greater than or equal to the number represented by the second set of address bits.
- the one lookup table is addressed using the first set of the address bits to retrieve a second set of correlation values associated with the spreading sequences of the two or more information symbols.
- a detected symbol value for each of the two or more information symbols is based on the second set of correlation values.
- i a chip index starting at 0,
- the block is a 4-chip symbol block
- the binary values of the scrambling sequence are eight binary values based on the binary values c long,1,n (0), c long,2,n (0), c long,1,n (1), c long,2,n (1), c long,1,n (2), c long,2,n (2), c long,1,n (3), c long,2,n (3) and correspond in this example to the one set of basic scrambling bits, and
- c long,1,n (0), c long,2,n (0), c long,1,n (1), c long,1,n (2), c long,2,n (2), c long,1,n (3) correspond in this example to the reduced basic scrambling bits.
- FIG. 1 illustrates a non-limiting example of a WCDMA channelization code tree from 3GPP TS 25.213;
- FIG. 2 illustrates a non-limiting example radio receiver that uses spreading sequence correlations
- FIG. 3 illustrates how different data symbols and control symbols are spread with particular spreading sequences
- FIG. 4 illustrates two 4-chip blocks for which spreading sequence correlations in a non-limiting example are calculated
- FIG. 5 shows an original lookup table for a specific non-limiting detailed spreading sequence correlation example
- FIG. 6 shows a first technique for reducing size of lookup table and a number of lookup table address bits in accordance with a non-limiting example embodiment
- FIG. 7 shows a second technique for further reducing size of a reduced-size lookup table and a number of lookup table address bits in accordance with another non-limiting example embodiment
- FIG. 8 shows a third technique for reducing a number of bits to be stored in a lookup table in accordance with a non-limiting example embodiment
- FIG. 9 illustrates a non-limiting example radio receiver that uses a processor with a specific non-limiting example scrambling sequence
- FIG. 10 illustrates a non-limiting example radio receiver that uses a processor with a specific non-limiting example scrambling generation bits
- FIG. 11 is a portion of a radio receiver that provides spreading sequence correlations in accordance with a non-limiting example embodiment
- FIG. 12 is a portion of a radio receiver that provides spreading sequence correlations in accordance with another non-limiting example embodiment
- FIG. 13 is a non-limiting example of an uplink long scrambling sequence generator
- FIG. 14 is a flowchart of non-limiting example procedures for generating and using correlation values
- FIG. 15 is a function block diagram of a multicode detector that may be used for example in the radio receiver of FIG. 2 in accordance with a non-limiting example embodiment
- FIG. 16 shows a non-limiting example embodiment that uses multiple spreading sequence correlation lookup tables
- FIG. 17 shows a non-limiting example embodiment that uses multiple spreading sequence correlation lookup tables and optional correlation mappers
- FIG. 18 shows a non-limiting example embodiment with one spreading sequence correlation lookup table and multiple optional correlation mappers
- FIG. 19 shows a non-limiting example of a spreading sequence correlation lookup table output used by an optional correlation mapper
- FIG. 20 shows a non-limiting example embodiment with a spreading sequence correlation lookup table with correlation post-processing
- FIG. 21 shows another non-limiting example embodiment of a spreading sequence correlation lookup table.
- the technology can additionally be embodied within any form of non-transitory, computer-readable memory, such as solid-state memory, magnetic disk, or optical disk containing an appropriate set of computer instructions that would cause one or more processors to carry out the techniques described herein.
- computer-readable memory such as solid-state memory, magnetic disk, or optical disk containing an appropriate set of computer instructions that would cause one or more processors to carry out the techniques described herein.
- block diagrams herein can represent conceptual views of illustrative circuitry or other functional units embodying the principles of the technology.
- any flow charts, state transition diagrams, pseudocode, and the like represent various processes which may be implemented by computer program instructions that may be stored in a non-transitory, computer-readable storage medium and which when executed by one or more computers or processors cause the processes to be performed, whether or not such computer(s) or processor(s) is(are) explicitly shown.
- Hardware implementation may include or encompass, without limitation, digital signal processor (DSP) hardware, a reduced instruction set processor, hardware (e.g., digital or analog) circuitry including but not limited to application specific integrated circuit(s) (ASIC) and/or field programmable gate array(s) (FPGA(s)), and (where appropriate) state machines capable of performing such functions.
- DSP digital signal processor
- ASIC application specific integrated circuit
- FPGA field programmable gate array
- a computer is generally understood to comprise one or more processors or one or more controllers, and the terms computer, processor, and controller may be employed interchangeably.
- the functions may be provided by a single dedicated computer or processor or controller, by a single shared computer or processor or controller, or by a plurality of individual computers or processors or controllers, some of which may be shared or distributed.
- the term “processor” or “controller” also refers to other hardware capable of performing such functions and/or executing software, such as the example hardware recited above.
- the technology provides a structure associated with a set of scrambling sequences or sets of scrambling generation bits together with one or more pre-computed lookup tables to quickly obtain correlations (including auto-correlations and cross-correlations) between the spreading sequences.
- the technology is less computationally demanding than pre-computing and storing all possible correlations and requires only a relatively small memory.
- the one or more pre-computed lookup tables are stored in a memory accessible by a receiver.
- certain basic scrambling bits (which are binary representations of the scrambling sequence or of the scrambling generation bits that generate the scrambling sequence) are used to generate an address to identify appropriate lookup table locations of the one or more lookup tables to access and retrieve desired pre-computed correlation values.
- Correlation values retrieved from a lookup table may be used either directly as the desired correlation, or as an index into one or more other lookup tables to obtain the desired correlation.
- the correlation values stored in the one or more lookup tables include cross-correlations of different time-lags between any pair of spreading sequences within a set of spreading sequences. The same table may be used to store cross-correlations of all the sequence pairs.
- the receiver may use the obtained correlations for joint detection or other receiver processing.
- the following example description is in the example and non-limiting context of joint detection, but those skilled in the art understand that the technology is not limited thereto and has other applications.
- FIG. 2 illustrates a block diagram of a non-limiting example multi-code receiver 10 according to one embodiment for jointly detecting signals in a composite received signal transmitted on different spreading sequences.
- the receiver 10 comprises a RAKE receiver 12 for each sequence to despread the composite received signal and to generate combined values corresponding to each spreading sequence, and a multi-code detector 14 for jointly detecting symbols transmitted on the code channels of interest.
- the RAKE receiver 12 may comprise a conventional RAKE receiver or a generalized RAKE (G-RAKE) receiver.
- the multi-code detector 14 may comprise a linear Minimum Mean Squared Error (MMSE) detector or maximum likelihood (ML) joint symbol detector.
- the example embodiment of the receiver 10 may be configured for a High Speed Packet Access (HSPA) mode, either downlink or uplink, in a WCDMA system and may be used in a base station or a mobile terminal.
- HSPA High Speed Packet Access
- Each RAKE receiver 12 comprises a plurality of RAKE fingers 16 , a plurality of RAKE combiners 18 , and a RAKE processor 20 .
- Each RAKE finger 16 processes different time shifts or multi-path echoes of the received signal r(t).
- each RAKE finger 16 comprises a delay element 22 and a correlator or despreader 24 .
- Delay elements 22 delay the received signal r(t) to time align the multi-path echoes processed by each RAKE finger 16 .
- Correlators 24 correlate the delayed signals with a spreading sequence to extract the assigned multi-path echoes from the received signal r(t).
- Despread values from correlators 24 are combined in combiner 18 .
- Combiner 18 typically includes weighting elements 26 and summer 28 .
- Weighting elements 26 weight the multi-path echoes output from respective correlators 24 .
- the weighted multi-path echoes are summed symbol-by-symbol by summer 28 to form a RAKE combined value during each symbol period.
- the combining weights associated with weighting elements 26 may correspond to the conjugates of the multiplying coefficients of the multi-path echoes (RAKE) or conjugates of weights that depend on the coefficients and a noise and interference correlation matrix (G-RAKE).
- the combining weights are computed by the processor 20 .
- Each RAKE combined value represents a symbol of interest or an interfering symbol. Importantly, symbols of interest also interfere with one another.
- EUL WCDMA Enhanced Uplink
- long scrambling codes are often used. Because they repeat only after 10 milliseconds (or 38400 chips), a large amount of memory is needed to store precomputed sequence correlations for every 4-chip block directly.
- the inventors identified certain scrambling sequence generation properties and exploited those properties to reduce the storage space needed to store spreading sequence correlations so that all spreading sequence correlations between any 4-chip symbol blocks can be stored in less than 10 kbytes of memory, if desired.
- only the correlations of the spreading sequences within one 4-chip symbol block are needed, then only 512 bytes of memory or less is needed for the lookup table, if desired.
- WCDMA spreading codes include orthogonal channelization sequences that are scrambled with a complex-valued scrambling sequence.
- the channelization sequences used are C ch,2,1 and C ch,4,1
- the control channels use sub-branches of the C ch,4,0 channelization code tree as shown in FIG. 1 and described in 3GPP TS 25.213.
- a QPSK scrambling sequence of length 4-chips has the form (u 1 +jv 1 , u 2 +jv 2 , u 3 +jv 3 , and u 4 +jv 4 ), where each u i and v i , may take the value +1 or ⁇ 1. So in general, 8 binary values, or bits, may be used to represent a 4-chip long QPSK scrambling sequence.
- C long,l ( i ) c long,1,1 ( i )(1+ j ( ⁇ 1) i c long,2,1 (2 ⁇ i/ 2 ⁇ )) (1)
- l is the long scrambling code number
- ⁇ ⁇ denotes rounding to the nearest lower integer
- c long,1,1 (i) and c long,2,1 (i) are binary-valued scrambling sequences taking values ⁇ +1, ⁇ 1 ⁇ .
- Each individual scrambling chip is defined by two bits: the values of c long,1,1 (i) and c long,2,l (2 ⁇ i/2 ⁇ ) (with an index i).
- the value of a pair of scrambling chips C long,l (2*k) and C long,l (2*k+1) is completely determined by only three bits, i.e., the values c long,1,1 (2*k), c long,1,1 (2*k+1), and c long,2,1 (2*k).
- the scrambling sequence in a block of four chips is completely determined by 6 bits, in contrast to the 8 bits required to represent a general QPSK scrambling sequence lacking the special structure in equation (1).
- the spreading sequences of spreading factor 2 and 4 used in a 4-chip block include: S 4,1 and S 2,1 for data, and S 4,0 (which is the root for control channel spreading sequences of spreading factors higher than 4) for control information, where n here denotes the chip index of the first chip of the spreading sequence.
- FIG. 3 illustrates how SF2 and SF4 data symbols and SF>4 control symbols are spread with spreading sequences S 2,1 n , S 2,1 n+2 , S 4,1 n and sub-branches of S 4,0 n in a 4-chip symbol block.
- the data symbols in one or more symbol blocks may be jointly detected to alleviate the inter-symbol interference (ISI) among them. Since the ISI between two symbols is characterized by the cross-correlations between their spreading sequences, spreading sequence cross-correlations are essential for the receiver to perform joint detection.
- ISI inter-symbol interference
- the value of the SF4 data spreading sequence S 4,1 n is completely determined by channelization sequence C ch,4,1 and the 6 bits c long,1,1 (n), c long,1,1 (n+1), c long,1,1 (n+2), c long,1,1 (n+3), c long,2,1 (n) and c long 2,l (n+2) of 8 basic scrambling bits.
- this structure is used to manipulate one or more of the scrambling sequences in a way that reduces a number of bits in constructing one of the example lookup tables that store spreading sequence correlation values and in an address used to address the lookup table.
- the reduced number of bits included in the address is less than a number of binary values in the scrambling sequence.
- the values of the spreading sequence are determined by the channelization code C ch,2,1 and by 3 bits of 4 basic scrambling bits.
- S 2,1 n is determined by c long,1,1 (n), c long,1,1 (n+1), and c long,2,1 (n)
- S 2,1 2+2 is determined by c long,1,1 (n+2), c long,1,1 (n+3), and c long,2,1 (n+2).
- FIG. 4 illustrates a pair of 4-chip symbol blocks for which the spreading sequence correlations in the example are calculated.
- the spreading sequence correlations are:
- the spreading sequence correlations are stored in one or more lookup tables in one or more memories. Although it is understood that the correlations may be stored in a variety of ways in memory, for explanation and illustration purposes only, each row in a lookup table stores the correlation value of two spreading sequences. The number of bits needed for one row, i.e., the memory space needed in this example table configuration, is now examined using the correlation of two SF4 sequences.
- (S 4,1 m *S 4,1 n )( ⁇ 2) and (S 4,1 m *S 4,1 n )(2) can be represented by 4 bits each.
- a sum of three terms can take 16 unique values and can be represented by 4 bits
- a sum of four terms can take 25 unique values and can be represented by 5 bits.
- the number of bits required to store (S 4,1 m *S 4,1 n )( ⁇ 3) and (S 4,1 m *S 4,1 n )(3) is 2 bits each, (S 4,1 m *S 4,1 n )( ⁇ 2), (S 4,1 m *S 4,1 n )(2), (S 4,1 m *S 4,1 n )( ⁇ 1) and (S 4,1 m *S 4,1 n )(1) is 4 bits each, and (S 4,1 m *S 4,1 n )(0) is 5 bits.
- the correlation values take 4, 9, 9, 9, and 4 unique values for three different correlation lags. This can be represented by 2, 4, 4, 4, and 2 bits, respectively, and a table of these correlations would thus require 16 bits in each row.
- the correlation values take 4, 9, and 4 unique values for the three different correlation lags. These values may be represented by 2, 4, and 2 bits so that each row holds 8 bits.
- This simplified table structure is referred to as example technique A. Example technique A is described further below in conjunction with FIGS. 5 and 6 .
- FIG. 5 shows an original lookup table for a specific non-limiting detailed spreading sequence correlation example with two spreading codes 1 and 2 (the term code is used in this example rather than sequence).
- Each of code 1 and code 2 is represented by 4 bits.
- the correlation of Code 1 with Code 2 is stored in a lookup table.
- the columns of the lookup table correspond to the different delays or lags at which the correlation is computed. This example shows three columns lags ⁇ 1, 0, and 1.
- the lookup table size reduction now described may be done using one or more of three example techniques A, B, and C. The techniques may be used alone or in any combination among them depending on the code structure and/or the implementation.
- FIG. 6 shows a first technique for reducing a number of lookup table address bits in accordance with example technique A from a row address size of 8 bits as in FIG. 5 to 6 bits in FIG. 6 by exploiting the characteristics of equation (1).
- the real and imaginary parts of s 1 and the real part of s 2 are required to completely determine the values of Code 1
- the real and imaginary parts of t 1 and the real part of t 2 are required to completely determine the values of Code 2 .
- the imaginary part of s 2 and t 2 are redundant and not needed. Only the first three bits in the row contribute to the address.
- FIG. 7 shows a second technique for further reducing a number of lookup table bits and accordingly address bits in accordance with the non-limiting example technique B.
- the real part of complex symbols s 1 and t 1 can be ⁇ 1 with [1, ⁇ 1] binary representation or 0/1 with [0, 1] binary representation, and these real parts of s 1 and t 1 are here denoted “anchor bits”.
- Code 1 is then multiplied by Re(s 1 )—this corresponds to an exclusive OR operation if the binary values are 0 and 1 or a multiplication operation if the binary values are +1 and ⁇ 1, to produce a new set s 1 ′ and s 2 ′.
- FIG. 7 shows that for certain row entries, the first bit is always 1, and the fourth bit is redundant as described above. Thus, only the second and third bits contribute to the row address, and the entries where the first bit is 1 can be removed.
- the required correlation bits are recovered by multiplying by the product of the “anchor bits” Re(s 1 ) ⁇ Re(t 1 ). This removes the effect of the earlier imposed exclusive OR operations described above.
- the technique A and B size reduction for this example is 16/256 or just 6.25% of the original table size. In more realistic cases, the size reduction is even larger.
- Another example technique B discovered by the inventors is to include rows only for those cases where the first bit in each of the two scrambling generation sequences is equal to 1 for ⁇ 1 representation. For 0/1 representation, the first rows with value 0 are kept.
- the 8 scrambling generation bits for the first symbol block of 4 chips in FIG. 4 are determined by 6 of them (c long,1,1 (m), c long,1,1 (m+1), c long,1,1 (M+2), c long,1,1 (m+3), c long,2,1 (m), c long,2,1 (m+2)).
- the correlation values with (c long,1,1 (m), c long,1,1 (m+1), c long,1,1 (m+2), c long,1,1 (m+3), c long,2,1 (m), c long,2,1 (m+2)) and (c long,1,1 (n), c long,1,1 (n+1), c long,1,1 (n+2), c long,1,1 (n+3), c long,2,1 (n), c long,2,1 (n+2)) of the first and second chip symbol blocks are identical to those with (1, c long,1,1 (m) c long,1,1 (m+1), c long,1,1 (m) c long,1,1 (m+2), c long,1,1 (m) c long,1,1 (m+3), c long,1,1 (m)c long,2,1 (m), c long,1,1 (m)c long,2,1 (m+2)) and (1, c long,1,1 (n)c long,1,1
- one or more of the techniques described above may be used to reduce the number of lookup table rows for the correlations between two SF2 codes or correlations between one SF4 code and one SF2 code.
- This table structure is referred to as example technique C and may be realized by storing the correlations as an upper-packed table/matrix where the upper triangular part, including the diagonal, is stored column by column.
- indexing or addressing such a table may be somewhat more complicated.
- FIG. 8 shows this third technique for reducing a number of bits to be stored in a lookup table in accordance with the non-limiting example technique C.
- Techniques A, B, and C may be used alone or in any combinations. Like techniques A and B, technique C employs an “excluding similarities” approach. As observed in technique B in combination with technique A, Code 1 is fully determined by the second and third bits, and Code 2 is fully determined by the second and third bits. So there are four possibilities for Code 1 and four possibilities for Code 2 resulting in a lookup table with 16 rows as shown in FIG. 7 . Looking for similarities between the rows, the inventors swapped the values of Code 1 and Code 2 , and discovered that the value of the correlation between them is the same except for a complex conjugation.
- decimal representation of the first two bits of the row address (shown as dotted background) is greater than or equal to that of the last two bits (shown as vertical swiggly line background)
- that decimal representation is used to compute an address (using equation (2) set forth below) to read one of the lookup table entries (the upper triangle of horizontal lines).
- decimal representation of the first two bits of the row address is less than that of the last two bits, that points to the lower triangle of diagonal lines.
- the first two bits are swapped with the last two bits, as shown, and decimal representations of the resulting bits are used to read one of the lookup table entries, where also the time lag ⁇ t is used to find the correct correlation value in the entry instead of the time lag t.
- Technique C is preferably performed before the last anchor bit multiplication of technique B described above.
- the cumulative effect of using techniques A, B, and C reduces the lookup table size to 10/256 or just 3.9% of the original table size.
- a m decimal value of the 6 of the 8 scrambling generation bits for S 4,1 m .
- a n decimal value of the 6 of the 8 scrambling generation bits for S 4,1 n .
- the rows in the example technique C table correspond to the address bit values a m and a n as illustrated in Table 1 below.
- the correct row in the lookup table may be located using the following example:
- example technique B can be combined with example technique C to achieve further reduction in the number of rows.
- each row takes 32 bits, so the variable “row” simply needs a left-shift of 5 bit positions to formulate the address to the 32 bits that contain the desired correlation.
- SF2 ⁇ SF2 64 rows of 8 bits: 64 bytes
- control channels can be cancelled before joint detection.
- two additional tables for SF4 ⁇ SF4 are preferably employed: one for S 4,0 m correlated with S 4,0 n and one for S 4,0 m correlated with S 4,1 n .
- another SF4 ⁇ SF2 table is preferably employed for correlations of S 4,0 m with the SF2 codes.
- the autocorrelation (S 4,1 n *S 4,1 n )(t) needs storage of 3 correlations which take 4, 9, and 16 unique values.
- (S 2,1 n *S 2,1 n )(t) and (S 2,1 n+2 *S 2,1 n+2 )(t) each have only one correlation value to store, and that correlation can take 4 unique values.
- the cross-correlations (S 4,1 n *S 2,1 n )(t) and (S 4,1 n *S 2,1 n+2 )(t) need storage of 4 correlations, which take 4, 9, 9, and 4 unique values.
- (S 2,1 n *S 2,1 n+2 )(t) needs storage of 3 correlations, which take 4, 9, and 4 unique values.
- each row in the table stores 16 correlations, with 4 bits each. If the table has 64 rows, then the final table size is 512 bytes.
- FIG. 9 is a portion of a radio receiver that provides spreading sequence correlations in accordance with a non-limiting example embodiment in which the technology described in this application may be employed.
- a basic scrambling bitsgenerator 30 receives scrambling information, e.g., a scrambling code number, and generates the basic scrambling bits, in form of either scrambling generation bits or scrambling sequence, in accordance with equation (1) above. These basic scrambling bits are used to formulate an address to one or more spreading sequence correlation lookup tables 32 , which also uses channelization code indices to provide the desired spreading sequence correlation value. Channelization code indices are used to select which table to address.
- FIG. 10 is a portion of a radio receiver that provides spreading sequence correlations in accordance with another non-limiting example embodiment.
- the basic scrambling bits are generated by two basic scrambling bits generators 30 A and 30 B (see the discussion above for two symbol blocks in FIG. 4 and for intra-block code correlations and FIG. 9 ).
- FIG. 11 is a non-limiting example of an uplink long scrambling sequence generator 36 that may be used to generate two component sequences c long,1,n and c long,2,n . These scrambling generation bits are used to generate the complex-valued, uplink long scrambling sequence according to equation (1) above.
- the generator 36 includes two parallel shift registers with various bits being tapped as inputs to exclusive-OR operations as shown.
- FIG. 12 is a flowchart of non-limiting example procedures for generating and using correlation values for a signal received containing a symbol block of multiple symbols, each symbol containing information bits spread by a spreading sequence of chips (step S 1 ).
- Each spreading sequence is determined by a channelization sequence and a first complex-valued scrambling sequence of chips or a second complex-valued scrambling sequence of chips.
- Each symbol block is processed using a set of multiple spreading sequences using one or more correlations between one or more pairs of spreading sequences in the set (step S 2 ).
- Spreading sequence correlation values between each pair of the multiple spreading sequences in the set are stored in one or more lookup tables.
- One of the lookup tables is addressed with an address determined using a first set of reduced basic scrambling bits to retrieve one or more correlation values from the addressed lookup table (step S 3 ).
- the first set of reduced basic scrambling bits is based on manipulation of one set of basic scrambling bits that reduces a number of bits included in the determined address to less than a number of binary values in the one set of basic scrambling bits.
- the one set of basic scrambling bits is based on either the scrambling sequences or on the scrambling generation bits. As described above, for an example 4-chip long QPSK scrambling sequence with 8 binary values, example technique A reduces the 8 bits to 6 bits. Manipulations for example techniques B and C to achieve further reductions were described above.
- the retrieved one or more correlation values is then used in mitigating spreading sequence correlation interference between spreading sequences in the set in a process to detect symbol values for two or more information symbols in one or more symbol blocks (step S 4 ).
- FIG. 13 is a function block diagram of a Rake processor 20 that may be used for example in the radio receiver of FIG. 2 to generate combining weights for the multicode detector 14 in accordance with a non-limiting example embodiment.
- Scrambling sequence generators 36 A and 36 B ( FIG. 11 shows one non-limiting example) in respective basic scrambling bits generators 30 A and 30 B provide a first set and a second set of scrambling generation bits to an address generator 42 .
- the address generator 42 applies technique A, technique B, or technique C or any combination of these techniques to these sets of scrambling generation bits to generate an address to access a desired spreading sequence correlation value stored in one or more lookup tables 44 .
- FIG. 14 is similar to FIG. 13 with additional sequence generators 72 A and 72 B in 30 A and 30 B respectively to use a first set and a second set of scrambling generation bits to generate first and second binary-valued scrambling sequences which are used as input to the address generator 42 .
- the address generator 42 applies technique A, technique B, or technique C or any combination of these techniques to these scrambling sequences to generate an address to access a desired spreading sequence correlation value stored in one or more lookup tables 44 .
- FIG. 15 is a function block diagram of a multicode detector 14 that may be used for example in the radio receiver of FIG. 2 in accordance with a non-limiting example embodiment. Although separate blocks are shown for purposes of illustration, one, multiple ones, or all of these blocks may be implemented using dedicated and/or suitably programmed/configured general purpose data processing circuitry.
- a basic scrambling bits generator 30 ( FIG. 13 and FIG. 14 show two non-limiting examples) provides first and second binary-valued scrambling sequences, or first set and second set of scrambling generation bits, to the address generator 42 to generate an address to access a desired spreading sequence correlation value stored in one or more lookup tables 44 . Channelization code indices are used to select the lookup table to be addressed.
- the accessed spreading sequence correlation value is processed by a symbol waveform correlation estimator 46 along with channel coefficients and path delays to compute for example an effective spreading waveform correlation matrix R. If the correlation value received from the lookup table is not the actual spreading sequence correlation, then one or more optional correlation mappers 48 may be used in the correlator estimator 46 to map the received correlation value to an actual spreading sequence correlation.
- a multicode detector 14 estimates the symbols based on symbol waveform correlations.
- FIG. 16 shows a non-limiting example embodiment that uses multiple spreading sequence correlation lookup tables 60 A, 60 B, and 60 C.
- FIG. 17 shows a non-limiting example embodiment that uses multiple spreading sequence correlation lookup tables 60 A and 60 B and corresponding optional correlation mappers 62 A and 62 B.
- FIG. 18 shows a non-limiting example embodiment with one spreading sequence correlation lookup table 60 and multiple optional correlation mappers 62 A- 62 C.
- FIG. 19 shows a non-limiting example of a spreading sequence correlation lookup table 60 output used by one or more optional correlation mappers 62 .
- the address determined using one example technique applied to the basic scrambling bits (scrambling generation bits or scrambling sequence) chooses the appropriate row in the lookup table. In that row, a sequence of bits is accessed.
- Subsequences of this bit sequence correspond to different spreading code correlations and/or correlation lags
- the first 2 bits might correspond to the correlation of S 4,1 m and S 4,1 n at lag ⁇ 3, that is, (S 4,1 m *S 4,1 n )( ⁇ 3)
- the subsequent 4 bits correspond to the correlation of the same spreading codes but at lag ⁇ 2, that is, (S 4,1 m *S 4,1 n )( ⁇ 2).
- Different correlation mappers may be used to obtain the actual correlation values.
- One example mapper might map 2 bits to correlation coefficient values ⁇ +2, +2j, ⁇ 2, ⁇ 2j ⁇ , while another mapper maps 4 bits to correlation coefficient values ⁇ 0, +2+2j, +2 ⁇ 2j, ⁇ 2+2j, 2 ⁇ 2j, +4, +4j, ⁇ 4, ⁇ 4j ⁇ .
- FIG. 20 shows a non-limiting example embodiment with a spreading sequence correlation lookup table 60 with correlation post-processing 66 that may be used to implement example technique A or C described above which reduces the lookup table storage requirements.
- the address generator 42 can form a n and a m as described above, examine whether a n ⁇ a m or a n ⁇ a m , and in the latter case, exchange values of a n and a m when computing the row address and changing the sign of the time lag t to ⁇ t when determining which correlation value to access in the sequence of bits found at the row address as described above.
- the post-processing 66 then examines the original a n and a m , and if a n ⁇ a m , then the post-processing 66 post-processes the value received from 60 by taking the complex conjugate of that value and using the result as spreading code correlation.
- FIG. 21 shows another non-limiting example embodiment of a spreading sequence correlation lookup table that may be used to implement example technique B described above. Address pre-processing at multipliers/bit flippers 68 A, 68 B and correlation post-processing at multipliers/bit flipper 70 reduces the required storage space of the lookup table(s).
- the first bit c long,1,1 (m) is removed from the sequence of reduced basic scrambling bits c long,1,1 (m), c long,1,1 (m+1), c long,1,1 (m+2), c long,1,1 (m+3), c long,2,1 (m), c long,2,1 (m+2), and in multiplier/bit flipper 68 A, the first bit c long,1,1 (m) is multiplied with the rest of these reduced basic scrambling bits c long,1,1 (m+1), c long,1,1 (m+2), c long,1,1 (m+3), c long,2,1 (m), c long,2,1 (M+2) to obtain the bit sequence c long,1,1 (m)c long,1,1 (m+1), c long,1,1 (m)c long,1,1 (m+2), c long,1,1 (m)c long,1,1 (m+3), c long,1,1 (m)c long,2,1 (m)m
- a corresponding procedure is used in multiplier/bit flipper 68 B but with the bit sequence c long,1,1 (n), c long,1,1 (n+1), c long,1,1 (n+2), c long,1,1 (n+3), c long,2,1 (n), c long,2,1 (n+2) to obtain the bit sequence c long,1,1 (n)c long,1,1 (n+1), c long,1,1 (n)c long,1,1 (n+2), c long,1,1 (n)c long,1,1 (n+3), c long,1,1 (n)c long,2,1 (n), c long,1,1 (n)c long,2,1 (n+2).
- multipliers/bit flippers 68 A and 68 B are used as an address in the look-up table(s).
- the multiplication in multipliers/bit flippers 68 A and 68 B can be realized as bit flips where the input bits denoted “rest of bits” are flipped, that is, changed to the opposite value, if the bit denoted “1 st bit” has a value of ⁇ 1.
- the output of the look-up table(s) denoted “rotated correlations” is multiplied by c long,1,1 (m)c long,1,1 (n) in 70 , or if realized as bit flips, the sign of the real and imaginary values of the correlation values denoted “rotated correlations” is changed if c long,1,1 (m)c long,1,1 (n) has the value ⁇ 1.
- the code correlations computed in the tables may also be used for joint detection of multiple users or for symbol-level IC of multiple users.
- the non-limiting examples use 4-chip blocks, but spreading code correlations for symbol blocks of larger size may be obtained by post-processing (summing) the correct values from the tables.
- the same lookup tables may be used in a variety of applications.
- One example is in maximum likelihood sequence estimation (MLSE) used as a last step in multi-stage group detection (MSGD), also known as assisted maximum likelihood detection, (AMLD).
- the technology described above uses the structure of the scrambling code together with pre-computed lookup tables to quickly obtain correlations between the spreading codes.
- the technology is relatively computationally inexpensive and requires only a small memory compared to pre-computing and storing all possible correlations.
Abstract
Description
C long,n(i)=c long,1,n(i)(1+j(−1)i c long,2,n(2└i/2┘))
wherein:
C long,l(i)=c long,1,1(i)(1+j(−1)i c long,2,1(2└i/2┘)) (1)
where l is the long scrambling code number, └ ┘ denotes rounding to the nearest lower integer, and where clong,1,1(i) and clong,2,1(i) are binary-valued scrambling sequences taking values {+1, −1}. Each individual scrambling chip is defined by two bits: the values of clong,1,1(i) and clong,2,l (2└i/2┘) (with an index i). However, the inventors observed that since the same clong,2,1(i) value is used for two consecutive scrambling chips, (indexes i=2k and i=2k+1, where k is an integer), the value of a pair of scrambling chips Clong,l(2*k) and Clong,l(2*k+1) is completely determined by only three bits, i.e., the values clong,1,1(2*k), clong,1,1(2*k+1), and clong,2,1(2*k). As a result, the scrambling sequence in a block of four chips is completely determined by 6 bits, in contrast to the 8 bits required to represent a general QPSK scrambling sequence lacking the special structure in equation (1). The real and imaginary parts of the chips of the scrambling code described by equation (1) can be separately expressed as:
real(C long,l(i))=c long,1,1(i) (1a)
imag(C long,l(i))=(−1)i c long,1,1(i)c long,2,1(2└i/2┘) (1b)
and, thus, clong,1,1(2*k), clong,1,1(2*k+1), and clong,2,1(2*k) can be expressed as functions of real(Clong,l (i)) and imag(Clong,l(i)):
c long,1,1(2k)=real(C long,l(2k)) (1c)
c long,1,1(2k+1)=real(C long,l(2k+1)) (1d)
c long,2,1(2k)=imag(Clong,l(2k)/real(Clong,l(2k)) (1e)
This way, the value of a pair of scrambling chips Clong,l(2*k) and Clong,l(2*k+1) can also be described as completely determined by the real and imaginary part of Clong,l(2*k) and the real part of Clong,l(2*k+1). The imaginary part of Clong,l(2*k+1) is determined by the real and imaginary parts of Clong,l(2*k) and the real part of Clong,l(2*k+1) as:
imag(C long,l(2k+1))=real(C long,l(2k+1))imag(C long,l(2k))/real(C long,l(2k)) (1f).
So in a pair of scrambling chips, only the real and imaginary part of the first chip (2 bits) together with the real part of the second chip (1 bit) are required to completely determine the values of the chip pair. A benefit from this technique is that only 6 bits are required to determine the scrambling sequence in a block of 4 chips. Although UL short scrambling sequences are much shorter than the long sequences, i.e., only 256 chips, both long and short scrambling sequences benefit from the technology described in this application.
S SF,k(i)=C ch,SF,k(i)*C long,l(i) (2)
where Cch,SF,k(i) is a channelization sequence k of spreading factor SF, and SSF,k(i) is the corresponding spreading sequence k of spreading factor SF, and i is the chip index.
S 2,1 n =[S 2,1(n)S 2,1(n+1)]
S 2,1 n+2 =[S 2,1(n+2)S 2,1(n+3)]
S 4,1 n =[S 4,1(n)S 4,1(n+1)S 4,1(n+2)S 4,1(n+3)]
where n=4*k and k is an integer.
S 2,1 n =[S 2,1(n)S 2,1(n+1)0 0]
S 2,1 n+2=[0 0S 2,1(n+2)S 2,1(n+3)]
and so on. The min and max functions are used to keep the correlation calculations within the spreading sequence length.
(S 4,1 m *S 4,1 n)(3)=S 4,1*(m)S 4,1(n+3)
(S 4,1 m *S 4,1 n)(2)=S 4,1*(m)S 4,1(n+2)+S 4,1(m+1)S 4,1(n+3)
(S 4,1 m *S 4,1 n)(1)=S 4,1*(m)S 4,1(n+1)+S 4,1*(m+1)S 4,1(n+2)+S 4,1*(m+2)S 4,1(n+3)
(S 4,1 m *S 4,1 n)(0)=S 4,1*(m)S 4,1(n)+S 4,1*(m+1)S 4,1(n+1)+S 4,1*(m+2)S 4,1(n+2)+S 4,1*(m+3)S 4,1(n+3)
and so on.
row=a m ±a n26 (2)
The address into the table of technique C would be
row=a m +a n(a n+1)/2 (3)
if an≧am. If an<am, the relation (S4,1 n*S4,1 m)(t)=(S4,1 m*S4,1 n)*(−t) would be utilized by exchanging am and an and using these exchanged values to compute the address and by using the time lag −t instead of t to find the correlation value. The complex conjugate of the value found using the look-up table would then be used as the correlation value.
TABLE 1 |
Illustration of how the address bit values am and an map to table |
row numbers in technique C tables. |
row | am | an |
0 | 0 | 0 |
1 | 0 | 1 |
2 | 1 | 1 |
3 | 0 | 2 |
4 | 1 | 2 |
5 | 2 | 2 |
Etc. |
-
- am=decimal value of the 5 bits sequence for S4,1 m, (clong,1,1(m)clong,1,1(m+1), clong,1,1(m)clong,1,1(M+2), clong,1,1(m)clong,1,1(m+3), clong,1,1(m)clong,2,1(m), clong,1,1(m)clong,2,1(m+2))
- an=decimal value of the 5 bits sequence for S4,1 n, (clong,1,1(n)clong,1,1(n+1), clong,1,1(n)clong,1,1(n+2), clong,1,1(n)clong,1,1(n+3), clong,1,1(n)clong,2,1(n), clong,1,1(n)clong,2,1(n+2))
The address into the table of technique A would be row=am+an25. As described earlier, the correlation values read out from the table will need to be multiplied by the product of clong,1,1(m) clong,1,1(n).
Claims (28)
C long,n(i)=c long,1,n(i)(1+j(−1)i c long,2,n(2└i/2┘))
C long,n(i)=c long,1,n(i)(1+j(−1)i c long,2,n(2└i/2┘))
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EP1128564A1 (en) * | 2000-02-28 | 2001-08-29 | Lucent Technologies Inc. | Multi-user detection CDMA receivers in mobile telecommunications systems |
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US6891882B1 (en) | 1999-08-27 | 2005-05-10 | Texas Instruments Incorporated | Receiver algorithm for the length 4 CFC |
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