WO2012116488A1

WO2012116488A1 - Clamping voltage and current in an asymmetric half bridge dc/dc converter

Info

Publication number: WO2012116488A1
Application number: PCT/CN2011/071419
Authority: WO
Inventors: Long Yu; Xiaodong Zhan; Wenguang Wang
Original assignee: Intersil Americas Inc.
Priority date: 2011-03-01
Filing date: 2011-03-01
Publication date: 2012-09-07

Abstract

A DC/DC converter is provided. The DC/DC converter includes an input, configured to receive an input DC voltage. The converter further includes first and second switches coupled in series between the input and a second node, wherein the first and second switches are coupled together at a common node. The converter also includes a transformer having a primary winding and a secondary winding. An output circuit of the converter has first and second diodes coupled to the secondary winding of the transformer and an inductor coupled between the first and second diodes and an output node. The converter further includes a clamp circuit coupled between the common node and the primary winding of the transformer wherein the clamp circuit limits a reverse recovery current in the rectifier diodes and limits the voltage on the transformer and rectifier diodes.

Description

CLAMPING VOLTAGE AND CURRENT

IN AN ASYMMETRIC HALF BRIDGE DC/DC CONVERTER

DRAWINGS

[0001] Embodiments of the present invention can be more easily understood and further advantages and uses thereof more readily apparent, when considered in view of the description of the preferred embodiments and the following figures in which:

[0002] Figure 1 is a schematic diagram of a DC/DC converter according to one embodiment of the present invention.

[0003] Figure 2 is a schematic diagram of a DC/DC converter according to another embodiment of the present invention.

[0004] Figure 3 is a schematic diagram of a DC/DC converter according to another embodiment of the present invention.

[0005] Figure 4 is a schematic diagram illustrating the direction of positive current flow in the DC/DC converter of Figure 1 according to one embodiment of the present invention.

[0006] Figures 5A-5M are timing diagrams illustrating one embodiment of a method for operating a DC/DC converter according to the teachings of the present invention.

[0007] Figures 6A-6H are schematic diagrams showing current flow paths in various time frames during the operation of a DC/DC converter according to the teachings of the present invention.

[0008] Fig. 7 is a block diagram of one embodiment of a system including a DC/DC converter according to one embodiment of the present invention.

[0009] In accordance with common practice, the various described features are not drawn to scale but are drawn to emphasize features relevant to the present invention. Reference characters denote like elements throughout figures and text. DETAILED DESCRIPTION

[0010] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of specific illustrative embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense.

[0011] Embodiments of the methods described above can be implemented in a DC/DC converter for telecommunication, computing, automotive and consumer applications. A number of embodiments of the invention defined by the following claims have been described.

Nevertheless, it will be understood that various modifications to the described embodiments may be made without departing from the scope of the claimed invention. Features and aspects of particular embodiments described herein can be combined with or replace features and aspects of other embodiments. Accordingly, other embodiments are within the scope of the following claims.

[0012] Figure 1 is a schematic diagram of a DC/DC converter, indicated generally at 100, and constructed according to one embodiment of the present invention. Converter 100 is an asymmetrical half-bridge voltage converter with a clamp circuit 102 that reduces the impact of ringing found in convention half-bridge converters.

[0013] Converter 100 receives an input DC voltage, V_IN, at input 104 and produces an output DC voltage at node 106. The operation of converter 100 is based on first and second switches Ql and Q2. In one embodiment, transistors Ql and Q2 comprise metal oxide semiconductor field effect transistors (MOS FET) having body diodes. Switches Ql and Q2 are coupled in series between input 104 and second node 107. Specifically, a drain contact of switch Ql is coupled to input 104 and a source contact of switch Ql is coupled to a common node 105.

Further, a drain contact of switch Q2 is coupled to common node 105 and a source contact of switch Q2 is coupled to second node 107. In one embodiment, second node 107 is coupled to ground potential. [0014] Each of switches Ql and Q2 have control gates 108 and 110, respectively. Control gates 108 and 110 are driven by control signals from a controller 1 12. Controller 112 receives feedback on the output of converter 100 at feedback circuit 114 and, based on this information, generates the signals to control switches Ql and Q2.

[0015] Converter 100 also includes an output circuit 116. Output circuit 116 includes diodes D3 and D4 and inductor L2. Diode D3 has an anode coupled to the secondary winding of transformer Tl at terminal 5. Also, D3 has a cathode that is coupled to inductor L2. Diode D4 similarly has an anode that is coupled to the secondary side of transformer Tl at terminal 8 and a cathode that is coupled to inductor L2. Capacitor C2 is coupled between inductor L2 and to the secondary winding of transformer Tl and terminal 6.

[0016] Converter 100 also includes the clamp circuit 102. The clamp circuit 102 includes external inductor LI and diodes Dl and D2. Inductor LI is external to transformer Tl and is coupled between common node 105 and the primary winding of transformer Tl at terminal 1. Advantageously, by including the external inductor LI , transformer Tl can be designed with reduced leakage inductance. The anode of diode Dl and the cathode of diode D2 are also coupled to terminal 1 of the primary winding of transformer Tl . Further, the cathode of diode Dl is also coupled to input 104. Further, the anode of diode D2 is also coupled to second node 107.

[0017] Figures 2 and 3 are schematic diagrams of DC/DC converters of alternative embodiments of the present invention. In Fig. 2, converter 100a is identical to converter 100 but includes a second capacitor, C8, on the primary side of the transformer Tl . This capacitor C8 is coupled between terminal 4 of the primary side of transformer Tl and input 104. In Fig. 3, a damping circuit 302 is included in converter 100b. Damping circuit 302 includes capacitor C3 and resistor Rl . Capacitor C3 is coupled in parallel with Rl between node 300 and terminal 1 of the primary winding of transformer Tl . The anode of diode Dl and the cathode of D2 are coupled together at node 300 in this embodiment. Damping circuit 302 operates to dampen any potential ringing in diodes Dl and D2. In general, the embodiments of converter 100a and 100b of Figures 2 and 3, respectively, function in a similar manner to converter 100 of Figure 1. Thus, the operation of these converters is not described separately here. [0018] The operation of converter 100 is described below with reference to Figures 1 , 4, 5A-5M and 6A-6K. For reference, the direction of positive current flow through various elements in converter 100 is shown by arrows 400. The description of the operation of converter 100 is divided into eight time periods. In operation, the converter repeats these eight time periods as necessary to provide power to a load.

[0019] As mentioned above, converter 100 is an asymmetrical half-bridge DC/DC converter. Input voltage, Vi_N, is received at input 104 and an output DC voltage is provided at output 106. The converter 100 operates by alternating between two half cycles; one in which Ql is switched on and Q2 is switched off and a second in which Q2 is switched on and Ql is switched off. These cycles alternately provide power to output node 106. The two cycles are separated by a dead time in which both switches are tumed off.

Time period tO to tl : Dead time

[0020] At time tO, the converter 100 enters a dead time between cycles. In this dead time, switch Ql is already off as depicted by the low control voltage applied at the gate of Ql in Fig. 5 A before time tO. At time tO, the second switch, Q2, is tumed off as depicted by the drop in voltage applied to the gate terminal 110 of switch Q2 in Fig. 5B.

[0021] Current flow in converter 100 during this time period is as depicted in Fig. 6A. As shown, on the primary side of transformer Tl , current flows is in the negative direction (see Fig. 4 and Figs. 5C and 5D) through the transformer Tl and inductor LI . Prior to tO, the current also passed through switch Q2. During this dead time, the current on the primary side transitions from switch Q2 to switch Ql as the drain to source voltage of Ql drops from an off-mode voltage to an on-mode voltage and the drain to source voltage of Q2 rises from an on-mode voltage level to an off-mode voltage level (Figs. 5K and 5L, respectively). At the time tl , the drain to source voltage of Ql reaches zero voltage and the body diode of Ql turns on to pass current from inductor LI thus providing zero voltage turn on for Ql .

[0022] On the secondary side of the transformer Tl , both diodes D3 and D4 are conducting and provide current to L2 (Figs. 5E and 5F). The secondary side of Tl is shorted (Fig. 51). As depicted in Fig. 5E, the current in D3 increases during this time period while Fig. 5F shows that the current in D4 decreases. At tl , both D3 and D4 still are conducting positive current.

Time Period tl to t2; Reverse Recovery of D4 [0023] The currents in this time period are shown in Fig. 6B. During this time period, the diode D4 experiences the so-called "reverse recovery." As shown in Fig. 5E, the current in diode D3 continues to increase. Meanwhile, the current in diode D4 decreases and passes zero to provide current to secondary winding of transformer Tl which is still shorted (Fig. 51). During this time, the current in D3 is higher than the load current (Fig. 5M) because of the negative current in D4.

[0024] The negative current from D4 passes through the secondary side of transformer Tl from terminal 8 to terminal 5. This current in reflected in the primary side of Tl by a current passing from terminal 1 to terminal 4 of the primary winding of transformer Tl . This current also passes through inductor LI and transistor Ql . Advantageously, inductor LI of clamping circuit 102 limits the current in the secondary winding of transformer Tl and thus limits the reverse recovery current in diode D4.

[0025] At time t2, the current in D4 cuts off and the current in D3 decreases (Figs. 5E and 5F). Further, the transformer Tl is no longer shorted and starts to output power to the load through the LC filter. The current in transformer Tl also drops due to the change in the current in diode D3 and D4. On the primary side, the current in LI does not change at t2 as the current in the inductor cannot change instantaneously (Fig. 5D).

Time Period t2 to t3; Free-wheeling diode Dl

[0026] The direction of current flow in converter 100 for this time period is shown in Fig. 6C. During this time period, the recovery of diode D4 is over and D4 is off (Fig. 5F). On the secondary side, the current in L2 and D3 are the same (Fig. 5E and 5M). The current in L2 also increases during this time because the input voltage, V_IN, is coupled through inductor LI across transformer Tl to provide power to the output.

[0027] On the primary side of transformer Tl , the current in the primary winding of transformer Tl is the reflected current of D3. The current of LI cannot change immediately with the change in the current of D3 (at t2), so diode Dl of the clamping circuit 102 turns on as a freewheeling diode and conducts current (Fig. 5G, Fig. 6C). Thus, the current drop in the primary winding of transformer Tl is shifted to diode Dl (Fig. 5C and 5G). This period ends when the current in Dl decays to zero at t3 (Fig. 5G). Also, advantageously, diode Dl also clamps the voltage potential of the terminal 1 of the primary winding of transformer Tl to V_IN thereby reducing the voltage spike and ringing on D4 caused by the sudden cutting off of its reverse recovery current. Time Period t3 to t4; Steady state

[0028] The state of current flow during this time period is represented in Fig. 6D. In this state, diode Dl is off and current on the primary side of transformer Tl flows through inductor LI and the primary winding of Tl . In this steady state, the current in transformer Tl and inductor LI are the same (Figs. 5C and 5D). This first half cycle of the converter 100 ends at t4 when the control signal applied to the gate terminal of switch Ql is lowered so as to turn off switch Ql . This commences a second dead time in preparation to turn on switch Q2 to drive the second half cycle of converter 100.

Time Period t4 to t5; Dead time

[0029] At time t4, the converter 100 enters the second dead time between cycles. In this dead time, switch Q2 is already off as depicted by the low control voltage applied at the gate of Q2 in Fig. 5B before time t4. At time t4, the first switch, Ql, is turned off as depicted by the drop in voltage applied to the gate terminal 108 of switch Ql in Fig. 5A.

[0030] Current flow in converter 100 during this time period is as depicted in Fig. 6E. As shown, on the primary side of transformer Tl, current flows is in the positive direction (see Fig. 4 and Figs. 5C and 5D) through the transformer Tl and inductor LI . Prior to t4, the current also passed through switch Ql . During this dead time, the current on the primary side transitions from switch Ql to switch Q2 as the drain to source voltage of Q2 drops from an off-mode voltage to an on-mode voltage and the drain to source voltage of Ql rises from an on -mode voltage level to an off-mode voltage level (Figs. 5K and 5L, respectively). At the time t5, the drain to source voltage of Q2 reaches zero voltage and the body diode of Q2 turns on to pass current to inductor LI thus providing zero voltage turn on for Q2. The current in inductor LI and transformer Tl drop toward zero during this time.

[0031] On the secondary side of the transformer Tl, both diodes D3 and D4 are conducting and provide current to L2 (Figs. 5E and 5F). The secondary side of Tl is shorted (Fig. 51). As depicted in Fig. 5F, the current in D4 increases during this time period while Fig. 5E shows that the current in D3 decreases. At t5, both D3 and D4 still are conducting positive current.

Time Period t5 to t6; Reverse Recovery of D3

[0032] The currents in this time period are shown in Fig. 6F. During this time period, the diode D3 experiences the so-called "reverse recovery." As shown in Fig. 5F, the current in diode D4 continues to increase. Meanwhile, the current in diode D3 decreases and passes zero to provide current to secondary winding of transformer Tl which is still shorted (Fig. 51). During this time, the current in D4 is higher than the load current (Fig. 5M) because of the negative current in D3.

[0033] The negative current from D3 passes through the secondary side of transformer Tl from terminal 5 to terminal 8. This current is reflected in the primary side of Tl by a current passing from terminal 4 to terminal 1 of the primary winding of transformer Tl . This current also passes through inductor LI and transistor Ql . Advantageously, inductor LI of clamping circuit 102 limits the current in the secondary winding of transformer Tl and thus limits the reverse recovery current in diode D3.

[0034] At time t6, the current in D3 cuts off and the current in D4 decreases (Figs. 5F and 5E). Further, the transformer Tl is no longer shorted and starts to output power to the load through the LC filter. The current in transformer Tl also rises due to the change in the current in diode D4. On the primary side, the current in LI does not change at t6 as the current in the inductor cannot change instantaneously (Fig. 5D).

Time Period t6 to tl: Free-wheeling diode D2

[0035] The direction of current flow in converter 100 for this time period is shown in Fig. 6G. During this time period, the recovery of diode D3 is over and D3 is off (Fig. 5E). On the secondary side, the current in L2 and D4 are the same (Fig. 5F and 5M).

[0036] On the primary side of transformer Tl , the current in the primary winding of transformer Tl is the reflected current of D4. The current in LI cannot change immediately with the change in the current of D4 (at t6), so diode D2 of the clamping circuit 102 turns on as a freewheeling diode and conducts current (Fig. 5H, Fig. 6G). Thus, the current drop in the primary winding of transformer Tl is shifted to diode D2 (Fig. 5C and 5H). This period ends when the current in D2 decays to zero at t7 (Fig. 5H). Also, advantageously, diode D2 also clamps the voltage on transformer Tl primary winding to the voltage on capacitor CI thereby reducing the voltage spike and ringing on D3 caused by the sudden cutting off of its reverse recovery current..

Time Period tl to t8; Steady State

[0037] The state of current flow during this time period is represented in Fig. 6H. In this state, diode D2 is off and current on the primary side of transformer Tl flows through inductor LI and the primary winding of Tl . In this steady state, the current in transformer Tl and inductor LI are the same (Figs. 5C and 5D). This second half cycle of the converter 100 ends at t8 when the control signal applied to the gate terminal of switch Q2 is again lowered so as to turn off switch Q2. These two half cycles are then repeated as needed for converter 100 to provide power to a load.

[0038] Fig. 7 is a block diagram of one embodiment of a system, indicated generally at 700, and including a DC/DC converter 702 according to one embodiment of the present invention.

Converter 702 comprises an asymmetric half-bridge DC/DC converter with a clamp that limits reverse recovery current and voltage spike and ringing in the rectifier diodes of its output stage. In one embodiment, the converter 702 is constructed as described above with respect to one or more of Figs. 1, 2, 3, 4, 5A-5M and 6A-6H.

[0039] Converter 702 converts a DC voltage provided by power source 706 to a functional circuit 704. In one embodiment, functional circuit 704 comprises any appropriate electronic circuit, e.g., a microprocessor, memory, circuit board, or the like.

[0040] Converter 702 includes a clamp circuit. The clamp circuit includes an inductor that limits the reverse recovery current in the output diodes and at least one diode that clamps the voltage of the transformer.

[0041] Embodiments of the methods described above can be implemented in a DC/DC converter for telecommunication, computing, automotive and consumer applications. A number of embodiments of the invention defined by the following claims have been described.

Claims

What is claimed is:

1. A DC/DC converter, comprising:

an input, configured to receive an input DC voltage;

first and second switches coupled in series between the input and a second node, wherein the first and second switches are coupled together at a common node;

a transformer having a primary winding and a secondary winding;

an output circuit having first and second diodes coupled to the secondary winding of the transformer and an inductor coupled between the first and second diodes and an output node; and a clamp circuit coupled between the common node and the primary winding of the transformer;

wherein the clamp circuit limits a reverse recovery current in the first and second diodes and limits the voltage on the transformer.

2. The DC/DC converter of claim 1 , wherein the clamp circuit comprises:

an inductor coupled between the common node and the primary winding of the transformer;

a third diode coupled between the input and the primary winding of the transformer; and a fourth diode coupled between the second node and the primary winding of the transformer.

3. The DC/DC converter of claim 2, wherein the third and fourth diodes clamp the voltage of the transformer.

4. The DC/DC converter of claim 1 , wherein the clamp circuit includes an inductor that limits the reverse recovery current in the first and second diodes.

5. The DC/DC converter of claim 1 , wherein the clamp circuit includes at least one diode that clamps the voltage of the transformer.

6. The DC/DC converter of claim 1 , and further including a capacitor coupled between the transformer and the second node.

7. The DC/DC converter of claim 6, and further including a second capacitor coupled between the transformer and the input.

8. The DC/DC converter of claim 2, wherein the clamping circuit further includes a damping circuit.

9. The DC/DC converter of claim 8, wherein the damping circuit comprises a parallel combination of a resistor and a capacitor coupled between the third and fourth diodes and the transformer.

10. A method for a half-bridge DC/DC converter, the method comprising:

receiving a DC voltage input;

turning off a first switch to enter a dead time mode of a half bridge converter;

turning on a second switch;

driving the current in an inductor of a clamp on a primary side of a transformer of the converter from a first polarity to a second polarity, wherein the inductor limits the reverse recovery current of an output diode of the half bridge converter; and

when the reverse recovery current of an output diode of the converter cuts off, freewheeling current in a first diode of the clamp to clamp the voltage on the transformer to not exceed the DC voltage input.

11. The method of claim 10, and further comprising:

turning off the second switch to enter a second dead time between half cycles of the half bridge converter;

turning on the first switch;

limiting a reverse recovery current in a second output diode; and freewheeling current in a second diode of the clamp to clamp the voltage on the transformer to not exceed the DC voltage input.

12. The method of claim 10, wherein the freewheeling current in the diode of the clamp decreases to zero over time.

13. The method of claim 12, wherein the current in the primary side of the transformer tracks the current in the inductor of the clamp after the freewheeling current in the diode of the clamp reaches approximately zero.

14. The method of claim 10, wherein tuming on a second switch comprises providing zero voltage tum-on for the second switch.

15. The method of claim 11 , wherein tuming on a first switch comprises providing zero voltage tum-on for the first switch.

16. An electronic system comprising:

a functional circuit; and

an asymmetrical half-bridge DC/DC converter coupled to provide DC power to the functional circuit, the converter comprising:

a transformer having primary and secondary windings;

a pair of switches coupled between an input DC voltage and a reference potential; a clamp, coupled between the pair of switches and the primary side of the

transformer;

an output circuit including first and second diodes, coupled to the secondary side of the transformer;

a feedback and a controller coupled between the output circuit and the pair of switches to provide feedback control of the converter; and wherein the clamp limits reverse recovery current in the first and second diodes of the output circuit and also limits a voltage on the primary winding of the transformer.

17. The system of claim 16, wherein the claim comprises:

an inductor, coupled to a common node of the pair of switches;

a first diode coupled between the inductor and the DC input voltage; and

a second diode coupled between the inductor and the reference potential.

18. The system of claim 16, wherein the controller provides control signals to gates of the pair of switches.

19. The system of claim 17, wherein the inductor of the clamp limits the reverse recovery current of the diodes in the output circuit of the converter.

20. The system of claim 17, wherein the first and second diodes of the clamp clamps the voltage of the transformer of the converter.

21. A method for a half-bridge DC/DC converter, the method comprising:

receiving a DC voltage input;

during a first half cycle of the half-bridge DC/DC converter,

limiting the reverse recovery current of a first output diode of the half-bridge converter with an inductor; and

freewheeling current in a first clamping diode from the inductor to clamp a voltage on a transformer of the half-bridge DC/DC converter to not exceed the DC voltage input.

22. The method of claim 21 , and further comprising:

during a second half cycle of the half-bridge DC/DC converter,

limiting the reverse recovery current of a second output diode of the half-bridge converter with the inductor; and freewheeling current in a second clamping diode from the inductor to clamp a voltage on a transformer of the half-bridge DC/DC converter to not exceed the DC voltage input.