WO2012109932A1 - 带宽调整方法、发送芯片及系统 - Google Patents
带宽调整方法、发送芯片及系统 Download PDFInfo
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- WO2012109932A1 WO2012109932A1 PCT/CN2011/082292 CN2011082292W WO2012109932A1 WO 2012109932 A1 WO2012109932 A1 WO 2012109932A1 CN 2011082292 W CN2011082292 W CN 2011082292W WO 2012109932 A1 WO2012109932 A1 WO 2012109932A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W28/00—Network traffic management; Network resource management
- H04W28/16—Central resource management; Negotiation of resources or communication parameters, e.g. negotiating bandwidth or QoS [Quality of Service]
- H04W28/18—Negotiating wireless communication parameters
- H04W28/20—Negotiating bandwidth
Definitions
- the present invention relates to the field of communications technologies, and in particular, to a bandwidth adjustment method, a transmitting chip, and a system. Background technique
- SERia izer/DES ia izer, SerDes serial-to-serial conversion
- SerDes serial-to-serial conversion
- a bandwidth adjustment method provided in the prior art is: when one or more of the multiple SerDes channels that are transmitted in parallel fail, the faulty SerDes is processed by a central processing unit (Centra l Proces s ing Uni t , CPU ) The channel does not participate in data transmission, reconfiguring the protocol interface for data transmission.
- FIG. 1 a schematic diagram of a transmitting chip transmitting data to a receiving chip through M SerDes channels (channel 1 to channel M ), wherein message 1 is sent through channel 1 and message 2 is sent through channel 2. , and so on. If one of the SerDes channels fails, for example, channel 1, the data verification module on the receiving side can recognize the error and upload the error message to the control CPU.
- the CPU reconfigures the protocol interface and uses the faultless M-1 SerDes channel for data transmission, thereby reducing the SerDes channel participating in data transmission and reducing the data transmission bandwidth.
- An aspect of the present invention provides a bandwidth adjustment method, a transmitting chip, and a system, which can be adaptively adjusted. Bandwidth and avoid data latency.
- a bandwidth adjustment method applied to data transmission between chips including:
- the cached watermark is a ratio of the amount of data stored in the cache to the size of the buffer; If the watermark value is lower than the minimum threshold, the corresponding link is closed according to a preset link reduction rule, where the sending chip includes multiple sending links, and each sending link includes at least one parallel string conversion or string. And converting the SerDe s channel;
- the corresponding link is opened according to a preset link increase rule.
- a transmitting chip includes:
- a monitoring unit configured to monitor whether a watermark value buffered in the sending chip is between a highest threshold and a lowest threshold, wherein the cached watermark is a ratio of the amount of data stored in the cache to the size of the buffer.
- a closing unit configured to: when the watermark value of the cache is lower than a minimum threshold, close a corresponding link according to a preset link reduction rule, where the sending chip includes multiple sending links, and each sending link Containing at least one parallel-serial conversion or serial-to-parallel conversion of the SerDe s channel;
- an opening unit configured to: when the watermark value of the cache is higher than a highest threshold, start a corresponding link according to a preset link increase rule.
- a bandwidth adjustment system includes: a receiving chip and a transmitting chip
- the receiving chip is configured to receive, by using a corresponding receiving link, the data sent by the sending chip by using a sending link, and control the opening and closing of the receiving link according to the synchronization information sent by the sending chip; wherein, the receiving chip
- the receiving link corresponds to the transmitting link of the transmitting chip, and each receiving link includes a corresponding number of parallel-serial conversion or serial-to-serial conversion SerDes channels.
- the bandwidth adjustment method, the sending chip, and the system provided by the embodiment of the present invention increase or decrease the number of links according to the buffered watermark value monitoring result, thereby adjusting the bandwidth, preventing data delay, and avoiding waste of bandwidth, and the CPU is used in the prior art.
- FIG. 1 is a schematic diagram of a transmission link in the background art
- Embodiment 3 is a flowchart of a bandwidth adjustment method according to Embodiment 2 of the present invention.
- FIG. 4 is a schematic diagram of a composition of a transmitting chip according to Embodiment 3 of the present invention.
- FIG. 5 is a schematic structural diagram of another transmitting chip according to Embodiment 3 of the present invention.
- FIG. 6 is a schematic diagram showing another composition of a transmitting chip according to Embodiment 3 of the present invention.
- FIG. 7 is a schematic structural diagram of another transmitting chip according to Embodiment 3 of the present invention.
- FIG. 8 is a schematic structural diagram of a bandwidth adjustment system according to Embodiment 3 of the present invention.
- the embodiment of the invention provides a bandwidth adjustment method, as shown in FIG. 2, including:
- a watermark value buffered in the sending chip is between a highest threshold and a lowest threshold, wherein the cached watermark is a ratio of the amount of data stored in the cache to the size of the buffer.
- the cached watermark value may be based on the relationship between the amount of data in the current cache and the capacity of the cache itself, or may be based on the ratio of the inflow speed and the outflow speed of the data in the cache, or other
- the parameter of the expression form is not limited in this embodiment of the present invention, as long as it can be used to reflect whether the data transmission of the transmitting chip is smooth, and indirectly reflects the congestion degree of the data transmission between the chips.
- the highest threshold and the lowest threshold may be preset according to the performance of the chip, the size of the buffer capacity, the performance of the transmission bandwidth, etc., so that the watermark value is in the predetermined waterline threshold interval, the data transmission between the chips is smooth, and the bandwidth is avoided. Waste of resources; when the watermark value is not in the predetermined waterline threshold interval, the number of transmit and receive links can be adaptively adjusted to adjust the bandwidth.
- the corresponding link is closed according to a preset link reduction rule, where the sending chip includes multiple sending links, and each sending link includes at least A parallel-to-serial conversion or serial-to-serial conversion of the SerDes channel.
- the transmission link When the buffered watermark value is lower than the preset minimum threshold, the transmission link is in a relatively idle state, which can reduce the number of sending links and receiving links, thereby reducing bandwidth and avoiding waste of bandwidth resources.
- both ends of the link responsible for data transmission belong to the transmitting chip and the receiving chip, the part belonging to the transmitting chip is called a transmitting link, and the part belonging to the receiving chip is called a receiving link.
- data transmission between chips has only one link, and the link includes a plurality of parallel SerDes channels.
- the data transmission between chips may have multiple parallel links, and each link may include multiple parallel SerDes channels or only one SerDes channel.
- the transmitting chip transmits data to the receiving chip through the transmitting link.
- the corresponding receiving chip receives the data sent by the transmitting chip through the receiving link.
- the receiving link of the receiving chip is corresponding to and connected to the transmitting link of the transmitting chip, and the SerDes channel included in the receiving link is also corresponding to and connected to the SerDes channel in the corresponding transmitting link.
- the corresponding link is started according to a preset link increase rule.
- the transmission link when the buffered watermark value is higher than a preset maximum threshold, the transmission link is in Relatively crowded, the number of transmit links and receive links can be increased, thereby increasing bandwidth and avoiding data delay or loss.
- the link opening and the road part can be completely implemented by hardware, and the SerDe s processing circuit and protocol in the link are turned on and off according to the water line value signal.
- the processing circuit can be turned on and off by physical circuit signals without CPU or software participating in bandwidth adjustment, thereby preventing the CPU or software from participating in control bandwidth adjustment.
- the protocol processing circuit and the SerDes processing circuit may respectively include a control signal port for controlling the switch of the circuit.
- the control signal port is implemented by a high/low level, capacitor, diode, bias, etc. circuit structure to enable the corresponding circuit to be turned on and off when the water line value is not within the threshold range.
- a high level signal is output, and the high level signal is sent to the corresponding protocol processing circuit and the control signal port of the SerDes processing circuit according to a preset link increase rule.
- the receiving link may also be used to enable/disable the sending link after the receiving link is first turned on/off. This is not limited in the embodiment of the present invention, and may be specifically set according to specific conditions.
- the bandwidth adjustment method provided by the embodiment of the present invention increases or decreases the number of links according to the buffered watermark value monitoring result, thereby adjusting the bandwidth, preventing data delay and avoiding waste of bandwidth, and failing in the SerDe s channel by the CPU in the prior art.
- the method can actively adjust the bandwidth adaptively, and the SerDe s processing circuit and the protocol processing circuit in the link can be turned on and off by the physical circuit signal without using the CPU or the software. Participate in bandwidth adjustment, avoiding data delay caused by CPU or software participating in bandwidth adjustment.
- the embodiment of the invention provides a bandwidth adjustment method, as shown in FIG. 3, including:
- step 201 Monitor whether a watermark value buffered in the sending chip is between a highest threshold and a lowest threshold, where the cached watermark is a ratio of the amount of data stored in the cache to the size of the buffer; If the watermark value of the cache is lower than the lowest threshold, step 202 is performed; if the cached watermark If the value is higher than the highest threshold, step 205 is performed; if the cached watermark value is between the highest threshold and the lowest threshold, step 210 is performed.
- the data to be sent by the sending chip can be temporarily stored in the buffer for transmission, and the data in the buffer is also sent out through the sending link.
- the outflow speed of the data in the buffer is less than the inflow speed of the data, which may result in more data to be sent, which may cause the watermark value to rise, which may cause packet delay or even data loss.
- the traffic of the transmitting chip is small and the transmission bandwidth is high to a certain extent, the outflow speed of the data in the buffer is far greater than the inflow speed of the data, and the data in the buffer is not substantially retained, thereby causing the watermark value to decrease. This causes a waste of bandwidth resources.
- the optimal watermark threshold interval may be preset according to the performance of the chip, the size of the buffer capacity, the performance of the transmission bandwidth, etc., so that the data transmission between the chips is performed when the waterline value is in the predetermined waterline threshold interval. Smooth and avoid wasting bandwidth resources.
- the transmission link when the buffered watermark value is lower than the preset minimum threshold, the transmission link is in a relatively idle state, which can reduce the number of sending links and receiving links, thereby reducing bandwidth and avoiding waste of bandwidth resources.
- the cached watermark value is higher than the preset maximum threshold, it indicates that the transmission link is in a relatively congested state, which can increase the number of transmit links and receive links, thereby increasing the bandwidth and avoiding data delay or loss.
- the cached watermark value is between the highest threshold and the lowest threshold, it indicates that the transmission link is in a state of smooth transmission and does not waste bandwidth resources, and the bandwidth adjustment may not be performed.
- the waterline value can be preset according to performance parameters such as chip and link:
- performance parameters such as chip and link:
- the waterline value is higher than 80%, any one of the currently closed links is turned on.
- the watermark value is lower than 20%, the current Any of the links that are open.
- the watermark value can be continuously monitored. If the waterline value still satisfies the condition of adjusting the bandwidth, the bandwidth is adjusted again until the appropriate bandwidth is adjusted.
- the link reduction rule may be preset according to the number of links between the sending chip and the corresponding receiving chip and the number of SerDes channels in each link, and may be randomly closed from the currently opened link.
- a link can also be selected in a certain order for the link sequence number.
- the link should be closed, and the number of links that can be closed at one time can also be two, three, or other predetermined quantities. For example, when the watermark value is low, closing the 1/2 link halved the bandwidth; if the watermark value is still low, then closing the 1/4 link again halved the bandwidth.
- the service data transmission of the link to be closed may be stopped, and no data may be transmitted.
- the receiving chip determines the link failure when the data cannot be received by detecting the received data. After the transmission link transmits the data, it continues to send invalid data packets (IDLE) to the link to avoid The link is reported incorrectly.
- IDLE invalid data packets
- the method of stopping data transmission, or closing the transmission link, or closing the receiving link may be determining the end of a message, and stopping the sending or receiving of the data message at the boundary of the message to prevent interruption. The message caused the data to be lost.
- the receiving link of the corresponding receiving chip corresponds to the sending link of the sending chip, and each receiving link includes a corresponding number of parallel-serial conversion or serial-to-parallel conversion SerDes channels.
- the closing of the corresponding link includes closing the protocol processing circuit of the corresponding link and the SerDes processing circuit. It can be understood that when the data is transmitted from the chip, the transmission link uses a parallel-serial conversion circuit, and the parallel-to-serial conversion circuit and the protocol processing circuit are correspondingly closed. When the chip receives data, the receiving link uses a serial-to-parallel conversion link, and the serial-to-parallel conversion circuit and the protocol processing circuit are correspondingly closed.
- Inter laken interface, switching network interface, etc.; can also be PCI Expres s interface in the computer field; also can be other protocol interfaces such as Ra p i d 10.
- the embodiments of the present invention can be applied to other scenarios in which the parallel SerDes channel is transmitted.
- the specific protocol processing and the application scenario are not limited in the embodiment of the present invention.
- the receiving chip receives synchronized information sent by the receiving chip, and close the corresponding sending link.
- the receiving chip turns off the corresponding receiving circuit according to the synchronization information in 203, and after the synchronization is completed, feeds the synchronized signal to the corresponding transmitting chip, so that the transmitting chip turns off the corresponding sending link.
- the closing the corresponding link includes closing a protocol processing circuit of the corresponding link and a SerDes processing circuit.
- each parallel link can independently perform data transmission, at least one link can still be in normal operation during the link closing process, so the data transmission is not interrupted, so that the bandwidth adjustment is not performed. Affects the delay of the message.
- the rule for increasing the link may be preset according to the number of links between the sending chip and the corresponding receiving chip and the number of SerDes channels in each link, and may be randomly opened from the currently closed link.
- a link may also select a link to be opened in a certain order for the link sequence number, and the number of links that can be opened at one time may also be two, three, or other predetermined numbers. For example, when the watermark value is high, all closed links are opened, which can quickly achieve bandwidth requirements and prevent link flapping. Or, when the watermark value is high, select the link that should be turned on in order and turn it on; if the watermark value continues to rise, open the link one by one in the predetermined order until the bandwidth is appropriate.
- the specific link addition rule can be adjusted according to the actual situation, which is not limited in the embodiment of the present invention.
- the service data may not be sent immediately, but the synchronization information is first sent to the corresponding receiving chip.
- the receiving link of the corresponding receiving chip corresponds to the transmitting link of the transmitting chip, and each receiving link includes a corresponding number of serial-to-serial conversion or serial-to-parallel conversion SerDes channels.
- the receiving chip After receiving the synchronization information, the receiving chip starts the corresponding receiving link.
- the opening of the corresponding link includes opening a protocol processing circuit and a SerDes processing circuit of the corresponding link.
- the synchronized signal may be fed back to the corresponding transmitting chip, so that the transmitting chip enables the corresponding link to participate in the data transmission.
- the method of step 205 to step 207 may be used to enable the link to increase the bandwidth, or the sequence of each step may be appropriately adjusted.
- the receiving link is first started, and the sending link is started after synchronization.
- the opening of the corresponding link includes opening a protocol processing circuit and a SerDes processing circuit of the corresponding link.
- the transmission link includes multiple transmission links between the chips, the transmission link acquires the transmission link of the data to be transmitted, and the plurality of transmission links are combined into one overall logical transmission link.
- the received data is reassembled on the receiving chip, the data to be sent by the transmitting chip is restored, and multiple receiving links are combined into one whole. Logical receive link.
- the buffered watermark value When the buffered watermark value is between the highest threshold and the lowest threshold, it indicates that the transmission link is in a state of smooth transmission and does not waste bandwidth resources, and the bandwidth adjustment may not be performed.
- the watermark value may be continuously monitored in step 201, and the bandwidth is adjusted again according to the monitoring result of the waterline value until the watermark value is at The right height makes the transmission link neither crowded nor wasted.
- the bandwidth adjustment method provided by the embodiment of the present invention increases or decreases the number of links according to the buffered watermark value monitoring result, thereby adjusting the bandwidth, preventing data delay and avoiding waste of bandwidth, and the prior art fails in the SerDes channel by the CPU.
- Active adaptive adjustment of bandwidth, and the SerDe s processing circuit and protocol processing circuit in the link can be turned on and off by physical circuit signals without CPU or software participating in bandwidth adjustment, avoiding CPU or software participating in bandwidth adjustment. Data delay.
- the receiving link can be prevented from receiving a link and determining a link failure, thereby avoiding link error reporting and improving The stability of the transmission link.
- the embodiment of the present invention provides a transmitting chip, as shown in FIG. 4, including: a monitoring unit 31, a closing unit 32, and an opening unit 33.
- the monitoring unit 31 is configured to monitor whether a watermark value buffered in the sending chip is between a highest threshold and a lowest threshold, where the cached watermark is the amount of data stored in the cache and the size of the cache. ratio.
- the closing unit 32 is configured to: when the monitoring unit 31 detects that the cached watermark value is lower than a minimum threshold, close the corresponding link according to a preset link reduction rule, where the sending chip includes multiple sending Link, each transmission link contains at least one parallel-serial conversion or serial-to-serial conversion SerDe s channel.
- the opening unit 33 is configured to enable the corresponding link according to a preset link addition rule when the monitoring unit 31 detects that the cached watermark value is higher than the highest threshold.
- the closing unit 32 includes: a stopping module 321, a first synchronization module 322, and a shutdown module 323.
- the stopping module 321 is configured to: when the monitoring unit 31 detects that the buffered watermark value is lower than a minimum threshold, determine a link that should be closed according to a preset link reduction rule, and stop to be closed.
- the link transmits data, or sends an invalid data message I DLE to the link that should be closed.
- the first synchronization module 322 is configured to send the synchronization information to the corresponding receiving chip, so that the receiving chip closes the corresponding receiving link according to the synchronization information, where the receiving link of the corresponding receiving chip and the The transmitting link of the transmitting chip - correspondingly, each receiving link contains a corresponding number of parallel-serial conversion or serial-to-serial conversion SerDes channels.
- the closing module 323 is configured to receive the synchronized information sent by the receiving chip, and close the corresponding sending link.
- the opening unit 33 includes: an opening module 331, a second synchronization module 332, and a sending module 333.
- the opening module 331 is configured to: when the monitoring unit detects that the watermark value of the cache is higher than a highest threshold, determine a link that should be opened according to a preset link increase rule, and enable a corresponding sending link.
- the second synchronization module 332 is configured to send the synchronization information to the corresponding receiving chip, so that the receiving chip starts a corresponding receiving link according to the synchronization information, where the receiving link of the corresponding receiving chip and the The transmitting link of the transmitting chip - correspondingly, each receiving link contains a corresponding number of parallel-serial conversion or serial-to-serial conversion SerDes channels.
- the sending module 333 is configured to receive the synchronized information sent by the receiving chip, and use the currently opened link for data transmission.
- the transmitting chip further includes: an allocating unit 34 and a transmitting unit 35.
- the allocating unit 34 is configured to: after the closing unit 32 turns off the corresponding link according to the preset link reduction rule, or after the opening unit 33 starts the corresponding link according to the preset link adding rule, The data to be transmitted is allocated to the currently opened transmission link.
- an allocation unit 34 is added to the front end of the sending link, and each transmitting link is connected, and the data to be sent on the transmitting chip is allocated according to a predetermined rule to a sending chain that is currently in a normal data transmission state.
- the sending unit 35 is configured to send data to the receiving chip through the currently opened sending link, so that the receiving chip collects data and reassembles the data through the currently opened receiving chain.
- a recombining unit is added at the end of the receiving link, and each receiving line is connected, and the data received by the receiving chip is recombined according to the corresponding merge rule, and the transmitting chip is slowly slowed down.
- the data before splitting combines multiple physical receive links into one logical receive link.
- the embodiment of the invention further provides a bandwidth adjustment system, as shown in FIG. 8, comprising: a sending chip 41 and receiving chip 42.
- the receiving chip 42 is configured to receive data sent by the sending chip 41 through the sending link through a corresponding receiving chain, and control the opening and closing of the receiving link according to the synchronization information sent by the sending chip 41.
- the receiving link of the receiving chip 42 corresponds to the transmitting link of the transmitting chip 41, and each receiving link includes a corresponding number of parallel-serial conversion or serial-to-parallel conversion SerDes channels.
- the transmitting chip and the bandwidth adjustment system provided by the embodiments of the present invention increase or decrease the number of links according to the buffered watermark value monitoring result, thereby adjusting the bandwidth, preventing data delay and avoiding waste of bandwidth, and the prior art through the CPU in SerDe
- the technology can adaptively adjust the bandwidth, and the SerDes processing circuit and the protocol processing circuit in the link can be turned on and off by the physical circuit signal without using the CPU.
- the software participates in bandwidth adjustment, avoiding data delay caused by CPU or software participating in bandwidth adjustment.
- the present invention can be implemented by means of software plus necessary general hardware, and of course, by hardware, but in many cases, the former is a better implementation. .
- the technical solution of the present invention which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a readable storage medium, such as a floppy disk of a computer.
- a hard disk or optical disk or the like includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform the methods described in various embodiments of the present invention.
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Description
带宽调整方法、 发送芯片及系统 技术领域
本发明涉及通信技术领域， 尤其涉及一种带宽调整方法、 发送芯片及系 统。 背景技术
为了提高芯片之间的数据传输带宽， 通常会在芯片之间通过多条并串转 换或串并转换 ( SERia l izer/DESer ia l izer , SerDes )通道并行组成一条传输 链路， 用于传输数据。 随着带宽的增大， 如何调整数据传输带宽从而降 低功耗和延长运行寿命， 已成为重要的课题。
现有技术中提供的一种带宽调整方法为： 在多条并行传输的 SerDes通道 中的一条或多条发生故障时， 通过中央处理器（Centra l Proces s ing Uni t , CPU )令故障的 SerDes通道不参与数据传输， 重新配置数据传输的协议接口。 具体的， 如图 1所示， 为一种发送芯片通过 M条 SerDes通道（通道 1至通道 M )向接收芯片发送数据的示意图， 其中报文 1通过通道 1发送， 报文 2通过 通道 2发送， 以此类推。 若其中一条 SerDes通道发生故障， 例如通道 1 , 接 收侧的数据校验模块可以识别该错误， 并将错误信息上传给控制 CPU。 控制 CPU重新配置协议接口， 使用无故障的 M-1条 SerDes通道进行数据传输， 从 而减少参与数据传输的 SerDes通道， 降低数据传输带宽。
在实现上述带宽调整的过程中， 发明人发现现有技术中至少存在如下问 题： 由于在 SerDes通道故障时才能被动地减少 SerDes通道， 从而造成带宽 的下降， 不能主动地自适应地调整带宽， 造成带宽资源的浪费； 并且 CPU参 与带宽调整的控制， 接口的计算及控制信号的传输导致协议接口的配置延迟， 从而造成数据延迟。 发明内容
本发明一方面提供一种带宽调整方法、 发送芯片及系统， 能自适应调整
带宽并避免数据延迟。
为达到上述目的， 本发明的实施例采用如下技术方案：
一种带宽调整方法， 应用于芯片间的数据传输， 包括：
监测发送芯片中緩存的水线值是否在最高阈值与最低阈值之间， 其中所 述緩存的水线值为所述緩存中存储的数据量与所述緩存的容量大小的比值； 若所述緩存的水线值低于最低阈值， 则按照预设的链路减少规则关闭对 应的链路， 其中所述发送芯片包含多条发送链路， 每条发送链路中包含至少 一条并串转换或串并转换 SerDe s通道；
若所述緩存的水线值高于最高阈值， 则按照预设的链路增加规则开启对 应的链路。
一种发送芯片， 包括：
监测单元， 用于监测发送芯片中緩存的水线值是否在最高阈值与最低阈 值之间， 其中所述緩存的水线值为所述緩存中存储的数据量与所述緩存的容 量大小的比值；
关闭单元， 用于在所述緩存的水线值低于最低阈值时， 按照预设的链路 减少规则关闭对应的链路， 其中所述发送芯片包含多条发送链路， 每条发送 链路中包含至少一条并串转换或串并转换 SerDe s通道；
开启单元， 用于在所述緩存的水线值高于最高阈值时， 按照预设的链路 增加规则开启对应的链路。
一种带宽调整系统， 包括： 接收芯片和发送芯片；
所述接收芯片， 用于通过对应的接收链路接收所述发送芯片通过发送链 路发送的数据， 并根据发送芯片发送的同步信息控制接收链路的开启和关闭； 其中 , 所述接收芯片的接收链路与所述发送芯片的发送链路——对应 , 每条 接收链路中包含对应数量的并串转换或串并转换 SerDes通道。
本发明实施例提供的带宽调整方法、 发送芯片及系统， 根据緩存的水线 值监测结果增减链路数量， 从而调整带宽， 防止数据的延迟和避免带宽的浪 费， 与现有技术中通过 CPU在 SerDes通道故障时去除故障通道从而降低带宽
的技术相比， 能够主动的自适应的调整带宽， 并且链路中的 SerDes处理电路 和协议处理电路均可以通过物理的电路信号开启和关闭， 而不用 CPU或软件 参与带宽调整， 避免了 CPU或软件参与带宽调整造成的数据延迟。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面 描述中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附图。
图 1为背景技术中的传输链路示意图；
图 2为本发明实施例 1的带宽调整方法流程图；
图 3为本发明实施例 2的带宽调整方法流程图；
图 4为本发明实施例 3的一种发送芯片组成示意图；
图 5为本发明实施例 3的另一种发送芯片组成示意图；
图 6为本发明实施例 3的另一种发送芯片组成示意图；
图 7为本发明实施例 3的另一种发送芯片组成示意图；
图 8为本发明实施例 3的一种带宽调整系统组成示意图。
具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而 不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有作 出创造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
实施例 1
本发明实施例提供一种带宽调整方法， 如图 2所示， 包括：
1 01、 监测发送芯片中緩存的水线值是否在最高阈值与最低阈值之间， 其 中所述緩存的水线值为所述緩存中存储的数据量与所述緩存的容量大小的比 值。
需要说明的是， 緩存的水线值可以是根据当前緩存中数据量的多少与緩 存本身的容量大小之间的关系， 也可以是根据緩存中数据的流入速度和流出 速度比值， 还可以是其他表现形式的参数， 本发明实施例对此不进行限定， 只要其能用于反映发送芯片的数据发送是否流畅， 并间接体现芯片间业务数 据传输的拥挤程度即可。 最高阈值和最低阈值可以根据芯片的性能、 緩存容 量的大小、 传输带宽的性能等预先设定， 使得水线值在该预定的水线阈值区 间中时， 芯片间的数据传输流畅， 并避免带宽资源浪费； 当水线值不在预定 的水线阈值区间中时， 则可以自适应的调整发送和接收链路的数量， 从而调 整带宽。
102、 若所述緩存的水线值低于最低阈值， 则按照预设的链路减少规则关 闭对应的链路， 其中所述发送芯片包含多条发送链路， 每条发送链路中包含 至少一条并串转换或串并转换 SerDes通道。
其中， 当緩存的水线值低于预先设定的最低阈值时， 说明传输链路处于 相对空闲状态， 可以减少发送链路和接收链路的数量， 从而降低带宽， 避免 带宽资源的浪费。
可以理解的是， 负责数据传输的链路的两端各自属于发送芯片和接收芯 片， 属于发送芯片的部分称为发送链路， 属于接收芯片的部分称为接收链路。 现有技术中芯片间的数据传输只有一条链路， 该链路中包含多条并行的 SerDes通道。 而本实施例中， 芯片间的数据传输可以有多条并行的链路， 每 条链路中可以包含多条并行的 SerDes通道， 也可以仅包含一条 SerDes通道。 如图 8 所示， 发送芯片通过发送链路将数据发送给接收芯片， 相应的， 对应 的接收芯片通过接收链路接收发送芯片发送的数据。 接收芯片的接收链路与 发送芯片的发送链路——对应并相连， 接收链路中包含的 SerDes通道也与对 应的发送链路中的 SerDes通道——对应并相连。
103、 若所述緩存的水线值高于最高阈值， 则按照预设的链路增加规则开 启对应的链路。
其中， 当緩存的水线值高于预先设定的最高阈值时， 说明传输链路处于
相对拥挤状态， 可以增加发送链路和接收链路的数量， 从而提升带宽， 避免 数据的延迟或丟失。
需要说明的是， 为了链路工作的稳定性和更高效的节能， 链路的开启和 路部分可以完全由硬件实现， 根据水线值信号开启和关闭， 链路中的 SerDe s 处理电路和协议处理电路均可以通过物理的电路信号开启和关闭，而不用 CPU 或软件参与带宽调整， 从而避免 CPU或软件参与控制带宽调整。 具体的， 协 议处理电路和 SerDes处理电路可以分别包含一个控制信号端口， 用于控制电 路的开关。 通过高电平 /低电平、 电容、 二极管、 偏置等电路结构实现控制信 号端口， 以便在水线值不在阈值范围内时实现对应的电路开启和关闭。 例如， 当检测到水线值高于最高阈值时， 输出一个高电平信号， 按照预设的链路增 加规则将高电平信号发送到对应的协议处理电路和 SerDes处理电路的控制信 号端口， 从而开启处理电路。 收链路， 也可以为先开启 /关闭接收链路后开启 /关闭发送链路， 本发明实施 例对此不进行限定， 可以根据具体情况具体设置。
本发明实施例提供的带宽调整方法， 根据緩存的水线值监测结果增减链 路数量， 从而调整带宽， 防止数据的延迟和避免带宽的浪费， 与现有技术中 通过 CPU在 SerDe s通道故障时去除故障通道从而降低带宽的方法相比， 能够 主动的自适应的调整带宽， 并且链路中的 SerDe s处理电路和协议处理电路均 可以通过物理的电路信号开启和关闭， 而不用 CPU或软件参与带宽调整， 避 免了 CPU或软件参与带宽调整造成的数据延迟。
实施例 2
本发明实施例提供一种带宽调整方法， 如图 3所示， 包括：
201、 监测发送芯片中緩存的水线值是否在最高阈值与最低阈值之间， 其 中所述緩存的水线值为所述緩存中存储的数据量与所述緩存的容量大小的比 值； 若所述緩存的水线值低于最低阈值， 则执行步骤 202 ; 若所述緩存的水线
值高于最高阈值， 则执行步骤 205 ; 若所述緩存的水线值在最高阈值与最低阈 值之间， 则执行步骤 210。
其中， 发送芯片待发送的数据可以暂时保存在緩存中等待发送， 同时緩 存中的数据也会通过发送链路发送出去。 当发送带宽低到一定程度时， 緩存 中数据的流出速度不及数据的流入速度， 会导致较多待发送数据的滞留， 从 而导致水线值上升， 容易导致报文延迟甚至数据丟失。 相反的， 当发送芯片 的业务量较少而发送带宽高到一定程度时， 緩存中数据的流出速度远远大于 数据的流入速度， 緩存中的数据基本不会滞留， 从而导致水线值下降， 造成 带宽资源的浪费。 因此， 可以根据芯片的性能、 緩存容量的大小、 传输带宽 的性能等， 预先设定最佳的水线阈值区间， 使得水线值在该预定的水线阈值 区间中时， 芯片间的数据传输流畅， 并避免带宽资源浪费。
具体的， 当緩存的水线值低于预先设定的最低阈值时， 说明传输链路处 于相对空闲状态， 可以减少发送链路和接收链路的数量， 从而降低带宽， 避 免带宽资源的浪费。 当緩存的水线值高于预先设定的最高阈值时， 说明传输 链路处于相对拥挤状态， 可以增加发送链路和接收链路的数量， 从而提升带 宽， 避免数据的延迟或丟失。 当緩存的水线值处于最高阈值与最低阈值之间 时， 说明传输链路处于传输流畅并不浪费带宽资源的状态， 可以不对带宽做 相关的调整。 例如， 可以根据芯片和链路等性能参数预先设定： 当水线值高 于 80%时， 开启当前已关闭的链路中的任意一条， 当水线值低于 20%时， 关闭 当前已开启的链路中的任意一条。 另外， 在完成一次带宽调整之后， 可以继 续监测水线值， 若水线值仍满足调整带宽的条件， 则再次对带宽进行调整， 直到调整得到适当的带宽。
202、 根据预设的链路减少规则确定应关闭的链路， 并停止向所述应关闭 的链路发送数据， 或向所述应关闭的链路发送无效数据报文 IDLE。
其中， 链路的减少规则可以是根据发送芯片与对应的接收芯片间链路的 数量以及每条链路中 SerDes通道的数量等预先设定的， 可以为从当前已开启 的链路中随机关闭一条链路， 也可以对链路顺序编号按照一定顺序选取一条
应关闭的链路， 并且一次关闭链路的数量也可以为两条、 三条或其他预定数 量。 例如， 当水线值较低时， 关闭 1/2 的链路使带宽减半； 若水线值仍然较 低， 则再关闭 1/4 的链路使带宽再次减半。 或者， 当水线值较低时， 按顺序 选择一条当前应关闭的链路并关闭它； 若水线值持续走低， 则按照预定顺序 逐一关闭链路， 直至带宽适当。 以此类推， 具体的链路减少规则可以根据实 际情况进行调整， 本发明实施例不做限定。
另外， 根据水线值低于最对阈值的信号指示， 停止所述应关闭的链路的 业务数据发送， 可以为不发送任何数据。 但是， 在一些传输链路中接收芯片 会通过接收数据的检测在无法接收任何数据时判定链路故障， 导致传输链路 发送数据后， 继续向该链路发送无效数据报文（ IDLE ), 避免链路报错。
在本实施例中， 停止数据发送、 或关闭发送链路、 或关闭接收链路的方 法可以为判断一个报文的末尾， 并在报文的边界处停止数据报文的发送或接 收， 防止中断报文导致数据丟失。
203、 将同步信息发送给对应的接收芯片， 使得所述接收芯片根据所述同 步信息关闭对应的接收链路。
其中， 所述对应的接收芯片的接收链路与所述发送芯片的发送链路—— 对应， 每条接收链路中包含对应数量的并串转换或串并转换 SerDes通道。 所 述关闭对应链路， 包括关闭对应链路的协议处理电路和 SerDes处理电路。 可 以理解的是， 当数据从芯片发送出去时， 发送链路采用的是并串转换电路， 则相应的关闭并串转换电路和协议处理电路。 当芯片接收数据时， 接收链路 采用的是串并转换链路， 则相应的关闭串并转换电路和协议处理电路。
Inter laken接口、 交换网接口等； 也可以为计算机领域的 PCI Expres s接口 等； 还可以为 Ra p i d 10等其他协议接口。 本发明实施例可以应用于其他并行 SerDes通道传输的场景，具体的协议处理和应用场景本发明实施例不做限定。
204、 接收所述接收芯片发送的已同步信息， 并关闭对应的发送链路。
其中， 在 203 中接收芯片根据同步信息关闭对应的接收电路， 并完成同 步后， 将已同步的信号反馈给对应的发送芯片， 以便所述发送芯片关闭对应 的发送链路。所述关闭对应链路，包括关闭对应链路的协议处理电路和 SerDes 处理电路。
另外， 由于各个并行链路可以分别独立的进行数据传输， 在链路的关闭 过程中， 仍可以保持至少有一条链路在正常工作， 因此不会中断数据的传输， 从而使得带宽的调整不会影响报文的时延。
205、 根据预设的链路增加规则确定应开启的链路， 并开启对应的发送链 路。
其中， 链路的增加规则可以是根据发送芯片与对应的接收芯片间链路的 数量以及每条链路中 SerDes通道的数量等预先设定的， 可以为从当前已关闭 的链路中随机开启一条链路， 也可以对链路顺序编号按照一定顺序选取一条 应开启的链路， 并且一次开启链路的数量也可以为两条、 三条或其他预定数 量。 例如， 当水线值较高时， 打开全部关闭的链路， 既可以快速达到带宽要 求， 又可以防止链路震荡。 或者， 当水线值较高时， 按顺序选择当前应开启 的链路并开启它； 若水线值持续走高， 则按照预定顺序逐一开启链路， 直至 带宽适当。 以此类推， 具体的链路增加规则可以根据实际情况进行调整， 本 发明实施例不做限定。
206、 将同步信息发送给对应的接收芯片， 使得所述接收芯片根据所述同 步信息开启对应的接收链路。
其中， 在步骤 205开启发送链路之后， 可以不立即进行业务数据的发送， 而先将同步信息发送给对应的接收芯片。 所述对应的接收芯片的接收链路与 所述发送芯片的发送链路——对应， 每条接收链路中包含对应数量的并串转 换或串并转换 SerDes通道。 所述接收芯片接收到同步信息后， 开启对应的接 收链路。 所述开启对应链路， 包括开启对应链路的协议处理电路和 SerDes处 理电路。
207、 接收所述接收芯片发送的已同步信息， 并使用当前已开启的链路进
行数据传输。
其中， 在步骤 206 中接收芯片开启对应的接收链路， 并完成同步之后， 可以将已同步的信号反馈给对应的发送芯片， 以便所述发送芯片启用对应的 链路参与数据传输。
其中， 可以采用步骤 205至步骤 207的方法开启链路增加带宽， 也可以 适当调整各步骤的顺序， 先开启接收链路， 后同步开启发送链路。 所述开启 对应链路， 包括开启对应链路的协议处理电路和 SerDes处理电路。
208、 将待发送的数据分配给当前已开启的发送链路。
其中， 由于芯片间包含多条传输链路， 在发送链路获取待发送的数据之 传输状态的发送链路， 将多条发送链路合并为一个整体的逻辑发送链路。
209、 通过当前已开启的发送链路将数据发送给接收芯片， 以便所述接收 芯片通过当前已开启的接收链路接收数据并重新组合。
对应的， 在接收链路对应接收到拆分的数据后， 最后在所述接收芯片上 将接收到的数据重组， 还原所述发送芯片要发送的数据， 将多条接收链路合 并为一个整体的逻辑接收链路。
21 0、 不进行带宽调整的相关操作。
其中， 当緩存的水线值处于最高阈值与最低阈值之间时， 说明传输链路 处于传输流畅并不浪费带宽资源的状态， 可以不对带宽做相关的调整。
需要说明的是， 在不调整带宽、 或者提高了带宽、 或者降低了带宽之后， 可以继续执行步骤 201 对水线值进行监测， 并根据水线值的监测结果再次调 整带宽， 直至水线值处于恰当高度， 使得传输链路既不拥挤又不浪费。 本发 明实施例中部分步骤的描述可以参考实施例 1 中对应内容， 本发明实施例这 里将不再——贅述。
本发明实施例提供的带宽调整方法， 根据緩存的水线值监测结果增减链 路数量， 从而调整带宽， 防止数据的延迟和避免带宽的浪费， 与现有技术中 通过 CPU在 SerDes通道故障时去除故障通道从而降低带宽的方法相比， 能够
主动的自适应的调整带宽， 并且链路中的 SerDe s处理电路和协议处理电路均 可以通过物理的电路信号开启和关闭， 而不用 CPU或软件参与带宽调整， 避 免了 CPU或软件参与带宽调整造成的数据延迟。
并且， 在确定应关闭的链路之后， 继续向所述应关闭的链路发送无效数 据报文， 可以防止接收链路因接收不到报文而判定链路故障， 从而避免链路 报错， 提高传输链路的稳定性。
实施例 3
本发明实施例提供一种发送芯片， 如图 4所示， 包括： 监测单元 31、 关 闭单元 32、 开启单元 33。
监测单元 31 , 用于监测发送芯片中緩存的水线值是否在最高阈值与最低 阈值之间， 其中所述緩存的水线值为所述緩存中存储的数据量与所述緩存的 容量大小的比值。
关闭单元 32 ,用于在所述监测单元 31监测到所述緩存的水线值低于最低 阈值时， 按照预设的链路减少规则关闭对应的链路， 其中所述发送芯片包含 多条发送链路， 每条发送链路中包含至少一条并串转换或串并转换 SerDe s通 道。
开启单元 33 ,用于在所述监测单元 31监测到所述緩存的水线值高于最高 阈值时， 按照预设的链路增加规则开启对应的链路。
进一步的， 如图 5所示， 所述关闭单元 32包括： 停止模块 321、 第一同 步模块 322、 关闭模块 323。
停止模块 321 , 用于在所述监测单元 31监测到所述緩存的水线值低于最 低阈值时， 根据预设的链路减少规则确定应关闭的链路， 并停止向所述应关 闭的链路发送数据， 或向所述应关闭的链路发送无效数据报文 I DLE。
第一同步模块 322 , 用于将同步信息发送给对应的接收芯片，使得所述接 收芯片根据所述同步信息关闭对应的接收链路； 其中， 所述对应的接收芯片 的接收链路与所述发送芯片的发送链路——对应， 每条接收链路中包含对应 数量的并串转换或串并转换 SerDes通道。
关闭模块 323 , 用于接收所述接收芯片发送的已同步信息， 并关闭对应的 发送链路。
进一步的， 如图 6所示， 所述开启单元 33包括： 开启模块 331、 第二同 步模块 332、 发送模块 333。
开启模块 331 ,用于在所述监测单元监测到所述緩存的水线值高于最高阈 值时， 根据预设的链路增加规则确定应开启的链路， 并开启对应的发送链路。
第二同步模块 332 , 用于将同步信息发送给对应的接收芯片，使得所述接 收芯片根据所述同步信息开启对应的接收链路； 其中， 所述对应的接收芯片 的接收链路与所述发送芯片的发送链路——对应， 每条接收链路中包含对应 数量的并串转换或串并转换 SerDes通道。
发送模块 333 , 用于接收所述接收芯片发送的已同步信息， 并使用当前已 开启的链路进行数据传输。
进一步的， 如图 7所示， 该发送芯片还包括： 分配单元 34、发送单元 35。 分配单元 34 ,用于在所述关闭单元 32按照预设的链路减少规则关闭对应 的链路之后， 或者在所述开启单元 33按照预设的链路增加规则开启对应的链 路之后， 将待发送的数据分配给当前已开启的发送链路。
其中， 在发送芯片上， 发送链路的前端添加一个分配单元 34 , 与每条发 送链路相连， 将所述发送芯片上待发送的数据按照预定规则分配给当前处于 正常数据传输状态的发送链路， 将多条物理发送链路合并为一个逻辑发送链 路。
发送单元 35 , 用于通过当前已开启的发送链路将数据发送给接收芯片， 以便所述接收芯片通过当前已开启的接收链 妻收数据并重新组合。
需要说明的是， 在接收芯片上， 在接收链路的末端添加一个重组单元， 与每接收线路相连， 将所述接收芯片接收的数据按照对应的合并规则重新组 合， 緩緩所述发送芯片上拆分前的数据， 将多条物理接收链路合并为一个逻 辑接收链路。
本发明实施例还提供一种带宽调整系统， 如图 8 所示， 包括： 发送芯片
41和接收芯片 42。
所述接收芯片 42 ,用于通过对应的接收链 妻收所述发送芯片 41通过发 送链路发送的数据， 并根据发送芯片 41发送的同步信息控制接收链路的开启 和关闭。
其中， 所述接收芯片 42的接收链路与所述发送芯片 41 的发送链路—— 对应， 每条接收链路中包含对应数量的并串转换或串并转换 SerDes通道。
需要说明的是， 本发明实施例提供的发送芯片和带宽调整系统中部分功 能模块的描述可以参考实施例 1和实施例 2 中对应内容， 本发明实施例这里 将不再——贅述。
本发明实施例提供的发送芯片及带宽调整系统， 根据緩存的水线值监测 结果增减链路数量， 从而调整带宽， 防止数据的延迟和避免带宽的浪费， 与 现有技术中通过 CPU在 SerDe s通道故障时去除故障通道从而降低带宽的技术 相比， 能够主动的自适应的调整带宽， 并且链路中的 SerDes处理电路和协议 处理电路均可以通过物理的电路信号开启和关闭， 而不用 CPU或软件参与带 宽调整， 避免了 CPU或软件参与带宽调整造成的数据延迟。
通过以上的实施方式的描述， 所属领域的技术人员可以清楚地了解到本 发明可借助软件加必需的通用硬件的方式来实现， 当然也可以通过硬件， 但 很多情况下前者是更佳的实施方式。 基于这样的理解， 本发明的技术方案本 质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来， 该 计算机软件产品存储在可读取的存储介质中， 如计算机的软盘， 硬盘或光盘 等， 包括若干指令用以使得一台计算机设备（可以是个人计算机， 服务器， 或者网络设备等）执行本发明各个实施例所述的方法。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应以所述权利要求的保护范围为准。
Claims
1、 一种带宽调整方法， 应用于芯片间的数据传输， 其特征在于， 包括： 监测发送芯片中緩存的水线值是否在最高阈值与最低阈值之间， 其中所述 緩存的水线值为所述緩存中存储的数据量与所述緩存的容量大小的比值；
若所述緩存的水线值低于最低阈值， 则按照预设的链路减少规则关闭对应 的链路， 其中所述发送芯片包含多条发送链路， 每条发送链路中包含至少一条 并串转换或串并转换 SerDes通道；
若所述緩存的水线值高于最高阈值， 则按照预设的链路增加规则开启对应 的链路。
2、 根据权利要求 1所述的带宽调整方法， 其特征在于， 所述按照预设的链 路减少规则关闭对应的链路包括：
根据预设的链路减少规则确定应关闭的链路， 并停止向所述应关闭的链路 发送数据， 或向所述应关闭的链路发送无效数据报文 IDLE;
将同步信息发送给对应的接收芯片， 使得所述接收芯片根据所述同步信息 关闭对应的接收链路； 其中， 所述对应的接收芯片的接收链路与所述发送芯片 的发送链路——对应， 每条接收链路中包含对应数量的并串转换或串并转换 SerDes通道 ^
接收所述接收芯片发送的已同步信息， 并关闭对应的发送链路。
3、 根据权利要求 1所述的带宽调整方法， 其特征在于， 所述按照预设的链 路增加规则开启对应的链路包括：
根据预设的链路增加规则确定应开启的链路， 并开启对应的发送链路； 将同步信息发送给对应的接收芯片， 使得所述接收芯片根据所述同步信息 开启对应的接收链路； 其中， 所述对应的接收芯片的接收链路与所述发送芯片 的发送链路——对应， 每条接收链路中包含对应数量的并串转换或串并转换 SerDes通道 ^
接收所述接收芯片发送的已同步信息， 并使用当前已开启的链路进行数据 传输。
4、 根据权利要求 1-3中任一项所述的带宽调整方法， 其特征在于， 在所述 按照预设的链路减少规则关闭对应的链路之后， 或者在所述按照预设的链路增 加规则开启对应的链路之后， 还包括：
将待发送的数据分配给当前已开启的发送链路；
通过当前已开启的发送链路将数据发送给接收芯片， 以便所述接收芯片通 过当前已开启的接收链^妻收数据并重新组合。
5、 根据权利要求 4所述的带宽调整方法， 其特征在于，
所述关闭对应链路，包括关闭对应链路的协议处理电路和 SerDes处理电路； 所述开启对应链路，包括开启对应链路的协议处理电路和 SerDes处理电路。
6、 一种发送芯片， 其特征在于， 包括：
监测单元， 用于监测发送芯片中緩存的水线值是否在最高阈值与最低阈值 之间 , 其中所述緩存的水线值为所述緩存中存储的数据量与所述緩存的容量大 小的比值；
关闭单元， 用于在所述监测单元监测到所述緩存的水线值低于最低阈值时， 按照预设的链路减少规则关闭对应的链路， 其中所述发送芯片包含多条发送链 路， 每条发送链路中包含至少一条并串转换或串并转换 SerDes通道；
开启单元， 用于在所述监测单元监测到所述緩存的水线值高于最高阈值时， 按照预设的链路增加规则开启对应的链路。
7、 根据权利要求 6所述的发送芯片， 其特征在于， 所述关闭单元包括： 停止模块， 用于在所述监测单元监测到所述緩存的水线值低于最低阈值时， 根据预设的链路减少规则确定应关闭的链路， 并停止向所述应关闭的链路发送 数据， 或向所述应关闭的链路发送无效数据报文 IDLE;
第一同步模块， 用于将同步信息发送给对应的接收芯片， 使得所述接收芯 片根据所述同步信息关闭对应的接收链路； 其中， 所述对应的接收芯片的接收 链路与所述发送芯片的发送链路——对应， 每条接收链路中包含对应数量的并 串转换或串并转换 SerDes通道；
关闭模块， 用于接收所述接收芯片发送的已同步信息， 并关闭对应的发送 链路。
8、 根据权利要求 6所述的发送芯片， 其特征在于， 所述开启单元包括： 开启模块， 用于在所述监测单元监测到所述緩存的水线值高于最高阈值时， 根据预设的链路增加规则确定应开启的链路， 并开启对应的发送链路；
第二同步模块， 用于将同步信息发送给对应的接收芯片， 使得所述接收芯 片根据所述同步信息开启对应的接收链路； 其中， 所述对应的接收芯片的接收 链路与所述发送芯片的发送链路——对应， 每条接收链路中包含对应数量的并 串转换或串并转换 SerDes通道；
发送模块， 用于接收所述接收芯片发送的已同步信息， 并使用当前已开启 的链路进行数据传输。
9、 根据权利要求 6-8中任一项所述的发送芯片， 其特征在于， 还包括： 分配单元， 用于在所述关闭单元按照预设的链路减少规则关闭对应的链路 之后， 或者在所述开启单元按照预设的链路增加规则开启对应的链路之后， 将 待发送的数据分配给当前已开启的发送链路；
发送单元， 用于通过当前已开启的发送链路将数据发送给接收芯片， 以便 所述接收芯片通过当前已开启的接收链 妻收数据并重新组合。
10、 一种带宽调整系统， 其特征在于， 包括： 接收芯片和如权利要求 6-9 中任一项所述的发送芯片；
所述接收芯片， 用于通过对应的接收链路接收所述发送芯片通过发送链路 发送的数据， 并根据发送芯片发送的同步信息控制接收链路的开启和关闭； 其 中， 所述接收芯片的接收链路与所述发送芯片的发送链路——对应， 每条接收 链路中包含对应数量的并串转换或串并转换 SerDes通道。
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