WO2012109882A1

WO2012109882A1 - Data reading method and ddr controller

Info

Publication number: WO2012109882A1
Application number: PCT/CN2011/078077
Authority: WO
Inventors: 程永波; 贺成洪; 兰可嘉
Original assignee: 华为技术有限公司
Priority date: 2011-08-05
Filing date: 2011-08-05
Publication date: 2012-08-23
Also published as: CN102378971B; CN102378971A

Abstract

Provided are a data reading method and DDR controller. The method comprises: reading a first data corresponding to a first reading request from the DDR and continuing to read the adjacent data with an address neighboring to the address of the first data after receiving the first reading request sent by a central processing unit, the sum of the data volume of the first data and the adjacent data is the cache line capacity of the central processing unit; caching the adjacent data; reading a subsequent reading request of the adjacent data according to the received request, and sending the cached adjacent data to the central processing unit. The technical solution, relating to the field of computer, is mainly applied to computer systems, and capable of reducing the time required for a central processing unit to obtain the data of a complete cache line and improving the data processing efficiency of a computer system.

Description

Data reading method and memory controller

The present invention relates to the field of computers, and in particular, to a data reading method and a memory controller.

Background technique

In a computer system, a central processing unit (CPU) reads data of a memory or writes data to a memory by transmitting a data operation instruction to a memory controller (DDR Controler). The memory controller places the received data manipulation instructions into its own cache queue and reorders them. The ordering principle is: Arrange the data operation instructions of the accessed memory address close to (in the same storage BANK or the same address line), so that the data reading can be performed sequentially, avoiding the time caused by frequent switching of the BANK (storage area) and the address line. delay. The data in the memory is read and loaded into the data response message, which is sent by the memory controller to the CACHE (cache) of the central processing unit for use by the central processing unit.

Typically, the CACHE in the central processor caches the data returned by the memory controller in a CACHE line unit. The capacity of the CHACHE line may be different from the capacity of the data response message. For example, if the CACHE line capacity of the central processing unit is 128 bytes, and the data response message used in the computer system can only return 64 bytes of data, the central processor needs to send two data operation instructions, respectively, requiring reading. Take the first 64 bytes and the last 64 bytes of 128 bytes to correspond to the capacity of the CACHE line.

In the process of implementing the above technical solution, the inventors have found that the prior art has at least the following problems: A plurality of data operation instructions corresponding to the CACHE line capacity require that the memory address for reading data is generally continuous, when reading data from the memory. It is not necessary to switch BANK or address lines frequently. However, in actual applications, when the cache queue of the memory controller is reached, other data operation instructions may be inserted in the plurality of data operation instructions corresponding to the CACHE line capacity, especially In a high-performance computer system consisting of multiple central processing units and multiple memory cascade extensions (as shown in Figure 1), different central processors access different memory times, and the routing schemes are different, so that corresponding to the same CACHE line Inserting other data operation instructions into multiple consecutive data operation instructions is more obvious, which makes the data operation instructions arriving in the multiple data operation instructions corresponding to the same CACHE line cannot enter the buffer queue, and cannot be optimized in timing, thereby making the center The time it takes for the processor to acquire data for a complete CACHE line reduces system processing efficiency.

Summary of the invention

Embodiments of the present invention provide a data reading method and a memory controller that reduce the time taken by the central processing unit to acquire data of a complete CACHE line, and improve the data processing efficiency of the computer system.

In order to achieve the above object, the embodiment of the present invention adopts the following technical solutions:

A method of reading data, including:

After receiving the first read request issued by the central processing unit, reading the first data corresponding to the first read request from the memory, and continuing to read the adjacent adjacent to the first data address Data; a sum of data amounts of the first data and the adjacent data is a capacity of a CHCHE cache line of a central processing unit;

Cache the adjacent data;

The subsequent read request of the adjacent data is read according to the received request, and the cached adjacent data is sent to the central processor.

A memory controller includes:

a data reading unit, configured to: after receiving the first read request issued by the central processing unit, read the first data corresponding to the first read request from the memory, and continue reading with the first Adjacent data adjacent to the data address; a sum of data amounts of the first data and the adjacent data is a capacity of a cache line of the central processing unit;

An adjacent data buffer unit, configured to cache the adjacent data; And a neighboring data sending unit, configured to read the subsequent read request of the adjacent data according to the received request, and send the cached adjacent data to the central processor.

The data reading method and the memory controller provided by the embodiment of the present invention, when reading data from the memory, read out adjacent data and cache, so that when the central processor requests to read adjacent data, it directly The cache is fetched and sent to the central processor, avoiding repeated reads of the memory. Especially in a high-performance computer system consisting of multiple central processing units and multiple memory cascade extensions, consecutive data operation instructions of the same central processing unit may be inserted into data of other central processing units when reaching the memory controller. The instructions are manipulated and cannot enter the cache queue at the same time for timing optimization. In this case, different central processors require that the addresses of the read data are far apart, resulting in frequent switching of BANKs and rows and columns when reading from memory. With the method provided by the embodiment of the present invention, adjacent data can be taken out and cached in advance, the influence of data operation instructions of other central processing units is avoided, and frequent reading of the memory is reduced, so that the same central processing unit acquires a complete CACHE line. The time consumed by data is shortened, and the data processing efficiency of the computer system is improved.

DRAWINGS

Figure 1 is a schematic diagram of a high performance computer system consisting of multiple central processing units and multiple memory cascade extensions;

2 is a flowchart of a method for reading data in Embodiment 1 of the present invention;

3 is a flowchart of a method for reading data in Embodiment 2 of the present invention;

4 is a block diagram of a memory controller in Embodiment 3 of the present invention;

Figure 5 is a block diagram of another memory controller in Embodiment 3 of the present invention;

FIG. 6 is a schematic diagram showing the internal structure of a computer using a cache chip in Embodiment 3 of the present invention. detailed description

The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not An embodiment of the department. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention. Example 1:

An embodiment of the present invention provides a data reading method. As shown in FIG. 2, the method includes the following steps:

After receiving the first read request from the central processing unit, reading the first data corresponding to the first read request from the memory, and continuing to read adjacent to the first data address Adjacent data.

The central processor's data operations on the memory include read operations and write operations. When the central processor is to read the memory, a first read request is issued to the memory controller. The memory controller analyzes and decodes the received first read request, thereby obtaining a BANK address, and a row and column address of the first data corresponding to the first read request in the memory. Afterwards, the memory controller addresses the BANK where the first data is located, activates the row where the first data is located in the BANK where it is located, and determines the first data according to the column address where the first data is located. Positioning, reading the first data while continuing to read adjacent data adjacent to the address of the first data.

1 02. Cache the adjacent data.

The memory controller transmits the read first data to the central processor, and on the other hand, caches the adjacent data.

1 03. Read a subsequent read request of the adjacent data according to the received request, and send the cached adjacent data to the central processor.

The cached adjacent data is sent to the central processor when the memory controller receives a subsequent read request to read the adjacent data.

For example, if the capacity of a CHACHE line of the central processor A is 128 BYTE, and the capacity of the data response message of the memory controller A received by the central processor A is 64 BYTE, the central processor A needs to read the entire CHACHE. The data of the line needs to send two data operation instructions to respectively read the data of 64BYTE, and receive two data response messages in succession. The first data operation instruction issued is the first read request, and the second data operation instruction is the subsequent read request. The data amount of the first data is 64 BYTE, and the first data response message is loaded by the memory controller A after receiving the first read request. , sent to the CHCHE line of central processor A. After the memory controller A reads the first data, it continues to read the adjacent data of the first data (size 64 BYTE) and caches it. After the subsequent read request of the central memory A reaches the memory controller A, if the subsequent read request requires reading the adjacent data of the first data, the memory controller A loads the cached adjacent data into the second data. The response message is sent to the CHCHE line of central processor A. When the central processor A requests to read the adjacent data, the memory controller A has been pre-cached, and it is no longer necessary to enter the memory for the read operation. The sum of the data amounts of the first data and the adjacent data is the capacity of the CHCHE line of the central processor A.

The data reading method provided by the embodiment of the present invention reads out adjacent data and caches when reading data from the memory, so as to be directly taken out from the cache when the central processor requests to read adjacent data. Sent to the central processor, avoiding repeated read operations on the memory. Especially in a high-performance computer system consisting of multiple central processing units and multiple memory cascade extensions, consecutive data operation instructions of the same central processing unit may be inserted into data of other central processing units when reaching the memory controller. The instructions are manipulated and cannot enter the cache queue at the same time for timing optimization. In this case, the addresses of the different central processors that require reading data are far apart, resulting in frequent switching of BANKs and rows and columns when reading from memory. The method provided by the embodiment of the present invention can pre-fetch and cache adjacent data, avoiding the influence of data operation instructions of other central processing units, and reducing frequent reading of the memory, so that the same central processing unit acquires a complete CACHE line. The time consumed by data is shortened, and the data processing efficiency of the computer system is improved.

Example 2:

An embodiment of the present invention provides a data reading method, as shown in FIG. 3, including the following steps:

301. Receive a first read request from a central processing unit.

The memory controller receives a first read request from the central processor. The first read request requires reading the first data.

302. Detect whether the first data is cached.

The memory controller analyzes and decodes the received first read request, and obtains a BANK address, a row and a column address of the first data corresponding to the first read request in the memory, if The data corresponding to the address has been cached in the memory controller, and the first data is directly returned to the central processor; otherwise, the process proceeds to step 303. 303. Read the first data from a memory, and continue to read adjacent data adjacent to the first data address.

The memory controller acquires the first data corresponding to the first read request, after the BANK address in the memory, and the row and column addresses, and addresses the BANK where the first data is located, and activates the location in the BANK where the data is located. Determining a row of the first data, determining a location of the first data according to a column address where the first data is located, reading the first data, and continuing to read an address with the first data Adjacent adjacent data.

304. Cache the adjacent data.

In one aspect, the memory controller transmits the read first data to the central processor and, on the other hand, caches the adjacent data.

305. Read a subsequent read request of the neighboring data according to the received request, and send the cached neighboring data to the central processor.

The following example is used to illustrate the above process. It may be assumed that the capacity of one CHACHE line of the central processing unit B is 128 BYTE, and the capacity of the data response message of the memory controller B received by the central processing unit B is 64 BYTE, then the central processing unit B reads the data of the entire CHACHE line. Two data operation instructions need to be sent to respectively read 64BYTE data, and receive two data response messages in succession. The first data operation instruction issued is the first read request, and the second data operation instruction is the subsequent read request. After receiving the first read request, the memory controller B first detects whether the first data corresponding to the first read request has been cached, and the data amount of the first data is 64 BYTE. In the case where the first data is not cached, the memory controller B reads the first data from the memory and loads it in the first data response message and sends it to the CHACHE line of the central processor B. In addition, after the memory controller B reads the first data, it continues to read the adjacent data of the first data (size 64BYTE) and performs buffering. After the subsequent read request of the central memory B reaches the memory controller B, if the subsequent read request requires reading the adjacent data of the first data, the memory controller B loads the cached adjacent data into the second data. The response message is sent to the CHCHE line of central processor A. Thus, the two data response messages return 128BYTE data, which satisfies the capacity of one CHACHE line. Considering other cases, when the capacity of a CHACHE line of the central processing unit B is 256 BYTE, the central processor B needs to read the data of the entire CHACHE line, and needs to send four data operation instructions to respectively read the 64BYTE. Data, and receives four data response messages in succession. Wherein, the memory controller B reads the first data with a data amount of 64 BYTE, Loaded in the first data response message, sent to the CHCHE line of central processor B. In addition, after the memory controller B reads the first data, it continues to read the adjacent data of the first data (size 1 92BYTE) and caches it. When the subsequent read request of the central memory B reaches the memory controller 8 (the subsequent read request is three read requests, each read request requires 64BYTE to be read), the memory controller B will cache the adjacent The data is loaded into three data response messages and sent to the CHCHE line of central processor A.

Further, in the embodiment of the present invention, a cache chip may be connected between the central processing unit and the memory controller. After receiving the first read request or the subsequent read request sent by the central processing unit, the cache chip detects whether it has cached corresponding data, and sends the self-cached data to the central processing unit. In addition, the cache chip forwards the first read request or the subsequent read request to the memory controller when the data corresponding to the first read request or the subsequent read request is not stored by itself.

After the memory controller receives the first read request forwarded by the cache chip, detecting whether the first data has been cached, and when the first data is not cached, reading the first corresponding to the first read request from the memory The data continues to read adjacent data adjacent to the first data address and transmits the first data and the adjacent data to the cache chip.

In a practical application, the first read request and the subsequent read request mentioned in the embodiment of the present invention may be QP I (Qu i ckPa th I n t e r connec t).

The data reading method provided by the embodiment of the present invention reads out adjacent data and caches when reading data from the memory, so as to be directly taken out from the cache when the central processor requests to read adjacent data. Sent to the central processor, avoiding repeated read operations on the memory. In a high-performance computer system consisting of multiple central processing units and multiple memory cascade extensions, consecutive data operation instructions of the same central processor may arrive at the memory controller due to insertion of data processing instructions of other central processing units. Instead of simultaneously entering the cache queue for timing optimization, in this case different central processors require that the addresses of the read data differ by 4 ,, resulting in frequent switching of BANKs and rows and columns when reading from memory. The method provided by the embodiment of the present invention can pre-fetch and cache adjacent data, avoiding the influence of data operation instructions of other central processing units, and reducing frequent reading of the memory, so that the same central processing unit acquires a complete CACHE line. The time consumed by the data is shortened, and the system processing efficiency is improved.

In addition, in the embodiment of the present invention, a cache chip is connected, which can further reduce data reading. The time spent to improve processing efficiency.

Example 3:

The embodiment of the present invention provides a memory controller. As shown in FIG. 4, the memory controller includes: a data reading unit 41, an adjacent data buffer unit 42, and an adjacent data transmitting unit 43.

The data reading unit 41 is configured to: after receiving the first read request sent by the central processing unit, read the first data corresponding to the first read request from the memory, and continue to read and The adjacent data of the first data address is adjacent.

The sum of the data amounts of the first data and the adjacent data is the capacity of the cache line of the central processing unit.

The adjacent data buffer unit 42 is configured to buffer the adjacent data.

The adjacent data transmitting unit 43 is configured to read the subsequent read request of the adjacent data according to the received request, and send the cached adjacent data to the central processing unit.

Further, as shown in FIG. 5, the memory controller further includes a cache detecting unit 44, configured to read the first data corresponding to the first read request in the memory, and continue to read with the first Before the adjacent data adjacent to the data address, detecting whether the first data has been cached; when detecting that the first data is not cached, reading the first data corresponding to the first read request in the memory .

Further, in the embodiment of the present invention, a cache chip may be connected between the central processing unit and the memory controller. After receiving the first read request or the subsequent read request sent by the central processing unit, the cache chip detects whether it has cached corresponding data, and sends the self-cached data to the central processing unit. In addition, the cache chip forwards the first read request or the subsequent read request to the memory controller when the data corresponding to the first read request or the subsequent read request is not stored by itself. As shown in Figure 6, the cache chip is connected between the central processor and the memory controller, and the memory controller is directly connected to the memory to operate on the data in the memory.

In the case that the memory controller is connected to the cache chip, the data reading unit 41 is further configured to read from the memory and the first read after receiving the first read request forwarded by the cache chip. The corresponding first data is requested and the adjacent data adjacent to the first data address is continuously read. The adjacent data sending unit 43 is further configured to send the first data and the adjacent data to the cache chip. In a practical application, the first read request and the subsequent read request mentioned in the embodiment of the present invention may be a QP I message.

The memory controller provided by the embodiment of the present invention reads out adjacent data and caches when reading data from the memory, so as to be directly taken out from the cache and sent to the central processor when reading the adjacent data. The central processor avoids repeated read operations on the memory. In a high-performance computer system consisting of multiple central processing units and multiple memory cascade extensions, consecutive data operation instructions of the same central processor may arrive at the memory controller due to insertion of data processing instructions of other central processing units. Instead of simultaneously entering the cache queue for timing optimization, in this case different central processors require that the addresses of the read data differ by 4 ,, resulting in frequent switching of BANKs and rows and columns when reading from memory. The method provided by the embodiment of the present invention can pre-fetch and cache adjacent data, avoiding the influence of data operation instructions of other central processing units, and reducing frequent reading of the memory, so that the same central processing unit acquires a complete CACHE line. The time consumed by the data is shortened, and the system processing efficiency is improved.

In addition, in the embodiment of the present invention, the cache chip is connected, which can further reduce the time consumed for data reading and improve processing efficiency.

Through the description of the above embodiments, those skilled in the art can clearly understand that the present invention can be implemented by means of software plus necessary general hardware, and of course, by hardware, but in many cases, the former is a better implementation. . Based on such understanding, the technical solution of the present invention, which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a readable storage medium, such as a floppy disk of a computer. A hard disk or optical disk, etc., includes instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the methods described in various embodiments of the present invention.

The above is only the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention. Therefore, the scope of the invention should be determined by the scope of the claims.

Claims

Claim

A method for reading data, characterized in that it comprises:

Cache the adjacent data;

2. The method according to claim 1, wherein the first data corresponding to the first read request is read in a memory, and reading adjacent to the first data address is continued Before the data, it also includes:

Detecting whether the first data has been cached; when detecting that the first data is not cached, reading first data corresponding to the first read request from the memory.

The method according to claim 1, wherein the first read request and the subsequent read request comprise a QP I fast channel interconnection protocol message.

The method according to claim 1 - 3, wherein a cache chip is connected between the memory controller and the central processor, and the cache chip is configured to receive the central processor After the first read request or the subsequent read request, the self-cached data is sent to the central processing unit; and when the data corresponding to the first read request or the subsequent read request is not stored by itself, the A first read request or a subsequent read request is forwarded to the memory controller.

The method according to claim 4, further comprising: after receiving the first read request or the subsequent read request sent by the memory chip, further comprising:

Reading first data corresponding to the first read request from a memory and continuing to read adjacent data adjacent to the first data address, and transmitting the first data or the adjacent data to The cache chip; or

Reading adjacent data adjacent to the first data address from the memory, and transmitting the first data or the adjacent data to the cache chip.

6. A memory controller, comprising: a data reading unit, configured to: after receiving the first read request issued by the central processing unit, read the first data corresponding to the first read request from the memory, and continue reading with the first Adjacent data adjacent to the data address; a sum of data amounts of the first data and the adjacent data is a capacity of a cache line of the central processing unit;

An adjacent data buffer unit, configured to cache the adjacent data;

And a neighboring data sending unit, configured to read the subsequent read request of the adjacent data according to the received request, and send the cached adjacent data to the central processor.

The memory controller according to claim 6, further comprising: a cache detecting unit, configured to read the first data corresponding to the first read request in the memory, and continue to read and Before the adjacent data of the first data address is adjacent, detecting whether the first data has been cached; when detecting that the first data is not cached, reading in the memory corresponds to the first read request The first data.

The memory controller according to claim 6, wherein the data reading unit uses the QP I fast channel interconnection protocol in performing the first read request and the subsequent read request.

The memory controller according to any one of claims 6-8, further comprising a cache chip, wherein the cache controller is connected to the central processor, and the cache chip is used in After receiving the first read request or the subsequent read request sent by the central processing unit, sending the cached data to the central processing unit; and not storing the first read request or the subsequent read request The corresponding read request or subsequent read request is forwarded to the memory controller.

The memory controller according to claim 9, wherein the data reading unit is further configured to: after receiving the first read request or the subsequent read request forwarded by the cache chip, Reading first data corresponding to the first read request in the memory and continuing to read adjacent data adjacent to the first data address, or reading adjacent to the first data address Data

The adjacent data sending unit is further configured to send the first data and the adjacent data to the cache chip.