WO2012109631A3 - Remote core operations in a multi-core computer - Google Patents
Remote core operations in a multi-core computer Download PDFInfo
- Publication number
- WO2012109631A3 WO2012109631A3 PCT/US2012/024776 US2012024776W WO2012109631A3 WO 2012109631 A3 WO2012109631 A3 WO 2012109631A3 US 2012024776 W US2012024776 W US 2012024776W WO 2012109631 A3 WO2012109631 A3 WO 2012109631A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- core
- destination
- notification
- sending
- data structure
- Prior art date
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
- G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
- G06F12/1483—Protection against unauthorised use of memory or access to memory by checking the subject access rights using an access-table, e.g. matrix or list
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1041—Resource optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1056—Simplification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/657—Virtual address space management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Computer Security & Cryptography (AREA)
- Mathematical Physics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
Abstract
A multi-core processor with a shared physical memory is described. In an embodiment a sending core sends a memory write request to a destination core so that the request may be acted upon by the destination core as if it originated from the destination core. In an example, a data structure is configured in the shared physical memory and mapped to be accessible to the sending and destination cores. In an example, the shared data structure is used as a message channel between the sending and destination cores to carry data using the memory write request. In an embodiment a notification mechanism is enabled using the shared physical memory in order to notify the destination core of events by updating a notification data structure. In an example, the notification mechanism triggers a notification process at the destination core to inform a receiving process of a notification.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP12744863.7A EP2673717A4 (en) | 2011-02-11 | 2012-02-11 | Remote core operations in a multi-core computer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/025,446 US9471532B2 (en) | 2011-02-11 | 2011-02-11 | Remote core operations in a multi-core computer |
US13/025,446 | 2011-02-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2012109631A2 WO2012109631A2 (en) | 2012-08-16 |
WO2012109631A3 true WO2012109631A3 (en) | 2012-10-18 |
Family
ID=46562253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2012/024776 WO2012109631A2 (en) | 2011-02-11 | 2012-02-11 | Remote core operations in a multi-core computer |
Country Status (6)
Country | Link |
---|---|
US (1) | US9471532B2 (en) |
EP (1) | EP2673717A4 (en) |
CN (1) | CN102622329B (en) |
HK (1) | HK1174116A1 (en) |
TW (1) | TWI473013B (en) |
WO (1) | WO2012109631A2 (en) |
Families Citing this family (26)
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US9137340B2 (en) * | 2011-08-02 | 2015-09-15 | Cavium, Inc. | Incremental update |
GB2495959A (en) * | 2011-10-26 | 2013-05-01 | Imagination Tech Ltd | Multi-threaded memory access processor |
US9373182B2 (en) * | 2012-08-17 | 2016-06-21 | Intel Corporation | Memory sharing via a unified memory architecture |
US9582287B2 (en) * | 2012-09-27 | 2017-02-28 | Intel Corporation | Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions |
US20140101405A1 (en) * | 2012-10-05 | 2014-04-10 | Advanced Micro Devices, Inc. | Reducing cold tlb misses in a heterogeneous computing system |
CN103853620B (en) * | 2012-11-30 | 2017-06-09 | 华为技术有限公司 | A kind of method, the apparatus and system of many-core processor process intercommunication |
US9026681B2 (en) | 2013-08-08 | 2015-05-05 | Qualcomm Incorporated | Flexible hardware module assignment for enhanced performance |
US9411745B2 (en) * | 2013-10-04 | 2016-08-09 | Qualcomm Incorporated | Multi-core heterogeneous system translation lookaside buffer coherency |
US9348645B2 (en) * | 2014-05-30 | 2016-05-24 | Apple Inc. | Method and apparatus for inter process priority donation |
US9396089B2 (en) | 2014-05-30 | 2016-07-19 | Apple Inc. | Activity tracing diagnostic systems and methods |
US9600442B2 (en) | 2014-07-18 | 2017-03-21 | Intel Corporation | No-locality hint vector memory access processors, methods, systems, and instructions |
US9424173B2 (en) | 2014-10-23 | 2016-08-23 | GlobalFoundries, Inc. | Performing secure address relocation within a multi-processor system sharing a same physical memory channel to external memory |
US9740617B2 (en) * | 2014-12-23 | 2017-08-22 | Intel Corporation | Hardware apparatuses and methods to control cache line coherence |
FR3061327B1 (en) * | 2016-12-26 | 2019-05-31 | Thales | METHOD FOR CONTROLLING A MULTI-HEART PROCESSOR AND ASSOCIATED CALCULATOR |
CN107038125B (en) * | 2017-04-25 | 2020-11-24 | 上海兆芯集成电路有限公司 | Processor cache with independent pipeline to speed prefetch requests |
US11314865B2 (en) * | 2017-08-01 | 2022-04-26 | The Trustees Of Princeton University | Pluggable trust architecture |
US10824584B1 (en) * | 2018-04-03 | 2020-11-03 | Xilinx, Inc. | Device with data processing engine array that enables partial reconfiguration |
CN110413210B (en) * | 2018-04-28 | 2023-05-30 | 伊姆西Ip控股有限责任公司 | Method, apparatus and computer program product for processing data |
CN108614460B (en) * | 2018-06-20 | 2020-11-06 | 东莞市李群自动化技术有限公司 | Distributed multi-node control system and method |
CN109117291A (en) * | 2018-08-27 | 2019-01-01 | 惠州Tcl移动通信有限公司 | Data dispatch processing method, device and computer equipment based on multi-core processor |
US10860487B2 (en) * | 2019-04-17 | 2020-12-08 | Chengdu Haiguang Integrated Circuit Design Co. Ltd. | Multi-core processing device and method of transferring data between cores thereof |
CN113138711B (en) * | 2020-01-20 | 2023-11-17 | 北京希姆计算科技有限公司 | Storage management device and chip |
CN113515483A (en) * | 2020-04-10 | 2021-10-19 | 华为技术有限公司 | Data transmission method and device |
CN112000608B (en) * | 2020-09-02 | 2021-10-01 | 展讯通信(上海)有限公司 | System-level chip, inter-core communication method thereof and intelligent wearable device |
US11954034B2 (en) * | 2022-03-28 | 2024-04-09 | Woven By Toyota, Inc. | Cache coherency protocol for encoding a cache line with a domain shared state |
CN115658569B (en) * | 2022-12-08 | 2023-04-14 | 井芯微电子技术(天津)有限公司 | Method, system and equipment for interrupting and sharing storage among AMP (amplifier) multi-core processors |
Citations (4)
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US20060075197A1 (en) * | 2003-05-30 | 2006-04-06 | Fujitsu Limited | Multi-processor system |
US20060080513A1 (en) * | 2004-10-08 | 2006-04-13 | International Business Machines Corporation | Low latency coherency protocol for a multi-chip multiprocessor system |
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US20080091884A1 (en) * | 2006-10-17 | 2008-04-17 | Arm Limited | Handling of write access requests to shared memory in a data processing apparatus |
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-
2011
- 2011-02-11 US US13/025,446 patent/US9471532B2/en active Active
-
2012
- 2012-01-11 TW TW101101125A patent/TWI473013B/en not_active IP Right Cessation
- 2012-02-10 CN CN201210030338.2A patent/CN102622329B/en active Active
- 2012-02-11 EP EP12744863.7A patent/EP2673717A4/en not_active Ceased
- 2012-02-11 WO PCT/US2012/024776 patent/WO2012109631A2/en active Application Filing
-
2013
- 2013-01-24 HK HK13101090.2A patent/HK1174116A1/en unknown
Patent Citations (4)
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US20060075197A1 (en) * | 2003-05-30 | 2006-04-06 | Fujitsu Limited | Multi-processor system |
US20060080513A1 (en) * | 2004-10-08 | 2006-04-13 | International Business Machines Corporation | Low latency coherency protocol for a multi-chip multiprocessor system |
US20060259705A1 (en) * | 2005-04-04 | 2006-11-16 | Stmicroelectronics Sa | Cache coherency in a shared-memory multiprocessor system |
US20080091884A1 (en) * | 2006-10-17 | 2008-04-17 | Arm Limited | Handling of write access requests to shared memory in a data processing apparatus |
Non-Patent Citations (1)
Title |
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See also references of EP2673717A4 * |
Also Published As
Publication number | Publication date |
---|---|
TWI473013B (en) | 2015-02-11 |
EP2673717A2 (en) | 2013-12-18 |
CN102622329A (en) | 2012-08-01 |
EP2673717A4 (en) | 2018-01-10 |
CN102622329B (en) | 2015-12-02 |
HK1174116A1 (en) | 2013-05-31 |
WO2012109631A2 (en) | 2012-08-16 |
TW201234264A (en) | 2012-08-16 |
US9471532B2 (en) | 2016-10-18 |
US20120210071A1 (en) | 2012-08-16 |
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