WO2012106967A1 - 桥式电流检测电路 - Google Patents
桥式电流检测电路 Download PDFInfo
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- WO2012106967A1 WO2012106967A1 PCT/CN2011/083245 CN2011083245W WO2012106967A1 WO 2012106967 A1 WO2012106967 A1 WO 2012106967A1 CN 2011083245 W CN2011083245 W CN 2011083245W WO 2012106967 A1 WO2012106967 A1 WO 2012106967A1
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- current
- resistor
- controllable switch
- current detecting
- bridge
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
Definitions
- Fig. 1 is a schematic diagram of a topology of a full bridge plus secondary side synchronous rectification according to the related art.
- a primary current of a current transformer (CURRENT TRANSFORMER, abbreviated as CT) is equal to a primary current of a full bridge transformer.
- the switching tubes Ql and Q4 are turned on, and the CT primary current flows from the CSA to the CSB.
- the energy of the power source is transmitted from the primary side of the transformer to the secondary side, and the entire circuit energy is emitted from the input power source, and the current detected by the current detecting circuit is positive.
- the current is turned on, and the switching transistors Ql, Q4 are turned on, the primary current of the CT flows from the CSB to the CSA, and the circuit topology energy is recharged to the input power source.
- the current detected by the current detecting circuit is the reverse current.
- the switching transistors Q2 and Q3 are turned on, the primary current of the CT flows from the CSB to the CSA, and the current detected by the current detecting circuit is a forward current; otherwise, the switching transistors Q2 and Q3 are turned on, and the primary current of the CT flows from the CSA to the CSB.
- the current detected by the current detecting circuit is the reverse current.
- the reverse current is generated due to the backside energy being reversed to the primary side under various conditions.
- 2 is a schematic diagram of a bridge current detecting circuit according to the related art, as shown in FIG. 2, the CT primary current is from
- the CT secondary induced current first passes through D1, then passes through Rs, and finally returns from D4 to form a loop.
- the voltage is formed on Rs, and the secondary current of CT can be obtained by Ohm's law.
- the primary current of CT is obtained, that is, the current of the main transformer of the full bridge; and the primary current of CT
- the secondary side of the CT induces current through D3, then through Rs, and finally from D2 to form a loop.
- a voltage is formed on Rs, so that the current of the primary side of the CT at this time, that is, the current of the main transformer of the full bridge can be obtained.
- FIG. 3 is a schematic diagram of the overall structure of a current-type full bridge and synchronous rectification according to the related art. As shown in FIG. 3, D1, D2, D3, and D4 functions are a full-wave rectification, and positive and negative AC signals on the CT are passed through Rs.
- the current signal is rectified into a corresponding positive voltage signal, and the voltage signal is filtered by R2 and C2, and then input to the current detecting chip of the current type control chip (CURRENT SENSE, referred to as CS), and the current type control chip adjusts the pulse according to the level of the CS pin.
- PWM PWM
- the wave is in OUTA, OUTB in Figure 3.
- 4 is a schematic diagram of a current detection signal obtained by detecting according to the related art, as shown in FIG.
- a CT current waveform is obtained for one cycle of the Rs resistance (the two bridges of the full bridge are opened for half a cycle), wherein each The half-cycle waveform is further divided into Phase 1 and Phase 2 (identified by 1 and 2 in Figure 4, respectively).
- Phase 1 corresponding to the phase 1 in FIG. 4 is the voltage waveform obtained by rectifying the reverse current.
- the current detecting circuit detects the reverse current to a proportional forward voltage.
- the larger the reverse current is, the larger the corresponding forward voltage is, and the larger the CS signal voltage is.
- the present invention provides a bridge current detecting circuit to at least solve the problem in the related art that the current detecting resistor Rs detects a sink current as a corresponding proportional forward voltage.
- the bridge current detecting circuit comprises: a current transformer, wherein a primary winding of the current transformer is connected in series in a full bridge main circuit, and one end of the secondary winding of the current transformer is connected to one end of the first controllable switch And one end of the second controllable switch, the other end of the secondary winding of the current transformer is connected to one end of the third controllable switch and one end of the fourth controllable switch; a current detecting resistor, wherein one end of the current detecting resistor is connected to The other end of the first controllable switch and the other end of the third controllable switch, the other end of the current detecting resistor is connected to the other end of the second controllable switch and the other end of the fourth controllable switch and grounded, wherein the first The control switch, the second controllable switch, the third controllable switch and the fourth controllable switch are arranged to provide a path for the induced current of the secondary winding of the current transformer to the current detecting resistor under the action of the control
- the bridge current detecting circuit further includes: a reference power supply, configured to provide a fixed forward voltage divider for the current detecting resistor; a bias voltage dividing resistor, wherein one end of the bias voltage dividing resistor is connected to the reference power supply, The other end of the voltage dividing resistor is connected to one end of the current detecting resistor.
- the bridge current detecting circuit further includes: a filter circuit configured to filter a current detected by the current detecting resistor.
- the filter circuit comprises: a resistor, wherein one end of the resistor is connected to one end of the current detecting resistor, and the other end of the resistor outputs the filtered current; the capacitor, wherein one end of the capacitor is connected to the other end of the resistor, and the other end of the capacitor is grounded.
- the bridge current detecting circuit further includes: a diode having a cathode connected to the other end of the resistor and a positive pole grounded.
- the diode is a Schottky diode with a conduction voltage reduced to 0.3V.
- the bridge current detecting circuit further includes: a MOS switch tube having a drain connected to the other end of the resistor and a source connected to the ground.
- the MOS switch tube is configured to be turned on simultaneously with the first controllable switch, the second controllable switch, the third controllable switch, and/or the fourth controllable switch under the action of the control signal.
- the MOS switch transistor is a small signal N-channel MOS transistor.
- the current sense resistor Rs detects the sink current as a corresponding proportional negative voltage. Since the control chip's wave-by-wave current limiting protection action threshold voltage is positive pressure, the negative voltage corresponding to the reverse current does not trigger the chip-by-wave current limiting protection action, that is, the large reverse irrigation can be performed by the technical solution of the present invention.
- the current erroneously triggers the chip-by-wave current limiting protection action to eliminate the hidden danger of the power supply burning, thereby improving the reliability of the power supply.
- FIG. 1 is a schematic diagram of a topology of a full bridge plus secondary side synchronous rectification according to the related art
- FIG. 2 is a schematic diagram of a bridge current detecting circuit according to the related art
- FIG. 3 is a current type according to the related art.
- FIG. 4 is a schematic diagram of a current detecting signal obtained by detecting according to the related art;
- FIG. 5 is a schematic diagram of a bridge current detecting circuit according to an embodiment of the present invention
- FIG. 6 is a schematic diagram of a bridge current detecting circuit according to an embodiment of the present invention
- FIG. 7 is a bridge current according to an embodiment of the present invention.
- a schematic diagram of the current detection signal obtained by the detection circuit detecting is a schematic diagram of a bridge current detecting circuit according to a preferred embodiment of the present invention
- FIG. 9 is a schematic diagram of a bridge current detecting circuit for detecting a current detecting signal according to a preferred embodiment of the present invention
- FIG. 10 is a preferred embodiment of the present invention.
- FIG. 11 is a schematic diagram of the current detection signal detected by the bridge current detecting circuit according to the third preferred embodiment of the present invention.
- DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. The invention will be described in detail below with reference to the drawings in conjunction with the embodiments. Embodiments of the present invention provide a bridge current detecting circuit.
- FIG. 5 is a schematic diagram of a bridge current detecting circuit according to an embodiment of the present invention. As shown in FIG.
- the primary winding of the current transformer is connected in series in the main circuit of the full bridge, and one end of the secondary winding of the current transformer is connected to one end of the first controllable switch S1 and one end of the second controllable switch S2, the secondary side of the current transformer
- the other end of the winding is connected to one end of the third controllable switch S3 and one end of the fourth controllable switch S4;
- one end of the current detecting resistor Rs is connected to the other end of the first controllable switch S1 and the other of the third controllable switch S3
- One end, the other end of the current detecting resistor Rs is connected to the other end of the second controllable switch S2 and the other end of the fourth controllable switch S4, and is grounded, wherein the first controllable switch S1, the second controllable switch S2, and the third The controllable switch S3 and the fourth controllable switch S4 are arranged to provide a path for the induced current of the secondary winding of the current transformer to the current detecting resist
- the current detecting resistor Rs detects the sink current as a corresponding proportional forward voltage.
- the current detecting resistor Rs detects the reverse current as a corresponding proportional negative voltage. Since the control chip's wave-by-wave current limiting protection action threshold voltage is positive pressure, the negative voltage corresponding to the reverse current does not trigger the chip-by-wave current limiting protection action, that is, the large reverse irrigation can be performed by the technical solution of the present invention.
- the current erroneously triggers the chip-by-wave current limiting protection action to eliminate the hidden danger of the power supply burning, thereby improving the reliability of the power supply.
- the input of the bridge current detecting circuit of the present invention is a full bridge primary side AC signal
- the output is a current detecting signal, which is input to the current detecting pin of the current type control chip, so that the PWM signal follows the input current. Change and change.
- the control signal is high level
- the controllable switch is turned on. During the turn-on period, the current can flow through the switch in two directions.
- the control signal is low
- the controllable switch is turned off. During the off period, the switch is removed. In addition to a small leakage current, current in any direction cannot flow.
- FIG. 6 is a timing chart of driving of the controllable switches S l, S2, S3, S4 and the switch tube VT with respect to the full bridge mains Ql, Q2, Q3, Q4 in the current detecting structure according to an embodiment of the present invention, as shown in FIG. It is shown that when Q1 and P Q4 are turned on, S 1 and S4 are turned on.
- the CT secondary current is turned on through S l, S4 and Rs, and the magnitude and direction of the current signal are detected on Rs; when the current flows from CSA to CSB
- the CT secondary current first passes through S l , then through Rs , and finally returns from S4 to form a loop, forming a proportional proportional forward voltage on Rs; and when the current flows from CSB to CSA
- the CT secondary current first passes through S4, then passes through Rs, and finally returns from the SI to form a loop, thereby forming a corresponding proportional negative direction on Rs. Voltage.
- the forward voltage on Rs corresponds to the forward current
- the negative voltage corresponds to the reverse current
- the reverse current is generated in the early stage of the main switch tube opening, mainly due to the secondary current being reversed to the primary side under various conditions.
- the bridge current detecting circuit further comprises: a reference power supply Ur, which is set as a current detecting resistor
- the filter circuit filters the voltage signal input to the filter network to suppress attenuating the amplitude of a portion of the noise.
- the filter circuit comprises: a resistor R2, wherein one end of the resistor R2 is connected to one end of the current detecting resistor Rs, and the other end of the resistor R2 outputs the filtered current; the capacitor C2, wherein one end of the capacitor C2 is connected to the resistor R2 At the other end, the other end of the capacitor C2 is grounded.
- the bridge current detecting circuit further comprises: a diode D having a cathode connected to the other end of the resistor R2 and a positive pole grounded.
- the diode D is a Schottky diode having a conduction voltage reduced by 0.3V.
- the negative voltage of the diode D-clamp control chip current detection signal input pin does not exceed -0.3 V under any conditions, thereby protecting the control chip.
- the bridge current detecting circuit further comprises: a MOS switch tube VT having a drain connected to the other end of the resistor R2 and a source connected to the ground.
- the MOS switch tube VT is set to be simultaneously turned on by the first controllable switch S1, the second controllable switch S2, the third controllable switch S3 and/or the fourth controllable switch S4 under the action of the control signal.
- the on-time of the MOS switch tube VT does not exceed 100 ns.
- the MOS switch VT can clamp the switching noise of the autonomous topology master to the ground level, thereby eliminating the leading current detection signal leading edge switching noise.
- the MOS switch transistor VT is a small signal N-channel MOS transistor having a small on-resistance. The implementation process of the embodiment of the present invention will be described in detail below with reference to examples. 8 is a schematic diagram of a bridge current detecting circuit according to a preferred embodiment of the present invention. As shown in FIG. 8, on the basis of the bridge current detecting circuit shown in FIG. 5, Ur and Rl, R2 and C2 are sequentially added. D and VT.
- FIG. Figure 9 is a diagram showing the detection of a current detection signal obtained by a bridge current detecting circuit in accordance with a preferred embodiment of the present invention. Since a forward bias is added to Rs through Ur and R1, the current detection signal detected by the bridge current detecting circuit superimposes a forward bias on the basis of FIG. 7, thereby making the current detecting signal as a whole. Offward. It should be noted that the magnitude of the forward bias voltage applied to the Rs can be obtained by circuit debugging.
- the present invention tests the steady state of the Rs by changing the load at the output end of the power supply, and performing operations such as no-load, full load, and full load jump.
- the negative pressure, and the negative pressure in which the absolute value is the largest, is determined as the magnitude of the forward bias to be superimposed. Therefore, it can be ensured that the steady-state negative voltage outside the detected noise is converted into the forward voltage during the steady state operation of the circuit.
- Preferred Embodiment 2 The preferred embodiment 2 of the present invention adds Ur, Rl, and the like to the bridge current detecting circuit shown in FIG.
- FIG. 10 is a diagram showing the detection of a current detection signal obtained by a bridge current detecting circuit in accordance with a preferred embodiment 2 of the present invention. Since the current detection signal superimposed with the forward bias voltage is input to the R2, C2 filter network, after filtering (as shown in Fig. 10, it can be seen that the leading edge noise is significantly reduced), the current detection pin of the control chip is input. It should be noted that the selection of R2 and C2 filter parameters can neither be too strong nor too weak. The filtering ability is too strong, and the forward current peak value of each cycle in the current detection waveform will be flattened, and the main current of the full bridge primary current will be maximized.
- the preferred embodiment 3 of the present invention adds Ur, R1, R2, C2, D, and P VT to the bridge current detecting circuit shown in FIG. Figure 11 is a diagram showing the detection of a current detection signal obtained by a bridge current detecting circuit in accordance with a preferred embodiment 3 of the present invention.
- a Schottky diode with a conduction voltage lower than 0.3V must be used.
- the function of this diode is to clamp the negative voltage at the current sense pin of the chip.
- the diode D will be turned on, and the negative voltage at the CS pin of the control chip will be controlled. The level is clamped below 0.3V to protect the chip from damage.
- the small signal MOS transistor VT added to the CS pin of the control chip has a driving signal as shown in FIG.
- the control chip's wave-by-wave current limiting protection action threshold voltage is positive pressure
- the negative voltage corresponding to the reverse current does not trigger the chip-by-wave current limiting protection action, that is, the large reverse irrigation can be performed by the technical solution of the present invention.
- the current erroneously triggers the chip-by-wave current limiting protection action to eliminate the hidden danger of the power supply burning, thereby improving the reliability of the power supply.
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Description
桥式电流检测电路 技术领域 本发明涉及通信领域, 具体而言, 涉及一种桥式电流检测电路。 背景技术 图 1是根据相关技术的全桥加副边同步整流的拓扑结构的示意图, 如图 1所示, 电流互感器 (CURRENT TRANSFORMER, 简称为 CT) 原边电流等于全桥变压器原 边电流。 开关管 Ql、 Q4导通, CT原边电流从 CSA流向 CSB, 此时电源的能量从变压器 原边传到副边, 整个电路能量是从输入电源处发出, 电流检测电路检测出来的电流为 正向电流; 而开关管 Ql、 Q4导通, CT原边电流从 CSB流向 CSA, 电路拓扑能量往 输入电源处回灌, 此时电流检测电路检测出来的电流为反灌电流。 同理, 开关管 Q2、 Q3导通, CT原边电流从 CSB流向 CSA, 电流检测电路检测出来的电流为正向电流; 反之开关管 Q2、 Q3导通, CT原边电流从 CSA流向 CSB, 电流检测电路检测出来的 电流为反灌电流。 反灌电流是由于各种情况下副边能量反灌到原边而产生。 图 2是根据相关技术的桥式电流检测电路的示意图,如图 2所示, CT原边电流从
CSA流向 CSB时, 根据同名端关系, CT副边感应电流先经 Dl, 再经 Rs, 最后从 D4 回来,形成环路。在 Rs上形成电压,通过欧姆定律从而可以得出 CT的副边电流大小, 按照 CT原副边匝比关系, 得到 CT原边电流大小, 也就是全桥主变压器电流大小; 而 CT原边电流从 CSB流向 CSA时, CT副边感应电流先经 D3, 再经 Rs, 最后从 D2回 来形成环路。 在 Rs上形成电压, 从而可以得到此时 CT原边电流大小, 也就是全桥主 变压器电流大小。 不管 Ql、 Q2、 Q3、 Q4如何导通,全桥主电路中的电流是正向电流还是反灌电流, 只要有电流流过 CT原边绕组, 就会在 Rs上形成对应成比例的正向电压。 图 3是根据相关技术的电流型全桥与同步整流的整体结构的示意图,如图 3所示, Dl、 D2、 D3、 D4功能就是一个全波整流, 通过 Rs将 CT上的正负交流信号整流成对 应的正电压信号, 该电压信号经 R2、 C2滤波之后输入到电流型控制芯片的电流检测 弓 I脚 (CURRENT SENSE, 简称为 CS), 电流型控制芯片根据 CS脚电平大小调整脉 冲宽度调制(PULSE WIDTH MODULATION,简称为 PWM)信号的占空比大小, PWM
波如图中 3中的 OUTA、 OUTB。 图 4是根据相关技术的检测获得的电流检测信号的示意图, 如图 4所示, 为 Rs 电阻上采得一个周期 (全桥两组对管各开通半个周期) 的 CT 电流波形, 其中每半个 周期的波形又分为阶段 1和阶段 2 (在图 4中分别用 1和 2标识)。 经分析可知图 4中 阶段 1对应的即为反灌电流整流而得的电压波形。 当副边大反灌电流作用到原边时, 此时该电流检测电路将反灌电流检测成对应成比例的正向电压。 但是, 反灌电流越大, 则对应正向电压越大, CS信号电压越大。 当 CS信号超过 控制芯片内部逐波限流保护阀值电压, 将误触发控制芯片逐波限流保护动作, 从而引 起电源模块烧毁。 发明内容 本发明提供了一种桥式电流检测电路, 以至少解决相关技术中电流检测电阻 Rs 将反灌电流检测成对应成比例的正向电压的问题。 根据本发明的桥式电流检测电路包括: 电流互感器, 其中, 电流互感器的原边绕 组串联在全桥主电路中, 电流互感器的副边绕组的一端连接至第一可控开关的一端和 第二可控开关的一端, 电流互感器的副边绕组的另一端连接至第三可控开关的一端和 第四可控开关的一端; 电流检测电阻, 其中, 电流检测电阻的一端连接至第一可控开 关的另一端和第三可控开关的另一端, 电流检测电阻的另一端连接至第二可控开关的 另一端和第四可控开关的另一端并接地, 其中第一可控开关、 第二可控开关、 第三可 控开关和第四可控开关, 设置为在控制信号的作用下, 为电流互感器的副边绕组的感 应电流到电流检测电阻提供通路。 上述桥式电流检测电路还包括: 基准供电电源, 设置为为电流检测电阻提供一个 固定的正向分压; 偏置分压电阻, 其中, 偏置分压电阻的一端连接至基准供电电源, 偏置分压电阻的另一端连接至电流检测电阻的一端。 上述桥式电流检测电路还包括: 滤波电路, 设置为对电流检测电阻检测的电流进 行滤波。 滤波电路包括: 电阻, 其中, 电阻的一端连接至电流检测电阻的一端, 电阻的另 一端输出滤波后的电流; 电容, 其中, 电容的一端连接至电阻的另一端, 电容的另一 端接地。 上述桥式电流检测电路还包括: 二级管, 其负极连接至电阻的另一端, 正极接地。
二级管为导通压降低于 0.3V的肖特基二极管。 上述桥式电流检测电路还包括: MOS开关管, 其漏极连接至电阻的另一端, 其源 极接地。
MOS开关管设置为在控制信号的作用下, 与第一可控开关、 第二可控开关、 第三 可控开关和 /或第四可控开关同时导通。
MOS开关管的导通时间不超过 100ns。
MOS开关管为小信号 N沟道 MOS管。 通过本发明, 在四个可控开关 Sl、 S2、 S3、 S4的控制下, 电流检测电阻 Rs将反 灌电流检测成对应成比例的负向电压。 由于控制芯片逐波限流保护动作阀值电压为正 压, 因此反灌电流对应的负向电压是不会触发芯片逐波限流保护动作的, 即通过本发 明的技术方案可以将大反灌电流误触发控制芯片逐波限流保护动作而引起电源烧毁的 隐患消除, 从而提高电源的可靠性。 附图说明 此处所说明的附图用来提供对本发明的进一步理解, 构成本申请的一部分, 本发 明的示意性实施例及其说明用于解释本发明, 并不构成对本发明的不当限定。 在附图 中: 图 1是根据相关技术的全桥加副边同步整流的拓扑结构的示意图; 图 2是根据相关技术的桥式电流检测电路的示意图; 图 3是根据相关技术的电流型全桥与同步整流的整体结构的示意图; 图 4是根据相关技术的检测获得的电流检测信号的示意图; 图 5是根据本发明实施例的桥式电流检测电路的示意图; 图 6是根据本发明实施例的电流检测结构中可控开关 Sl、 S2、 S3、 S4, 以及开关 管 VT相对于全桥主管 Ql、 Q2、 Q3、 Q4的驱动时序图; 图 7 是根据本发明实施例的桥式电流检测电路检测获得的电流检测信号的示意 图;
图 8是根据本发明优选实施例的桥式电流检测电路的示意图; 图 9是根据本发明优选实施例一的桥式电流检测电路检测获得的电流检测信号的 示意图; 图 10 是根据本发明优选实施例二的桥式电流检测电路检测获得的电流检测信号 的示意图; 图 11 是根据本发明优选实施例三的桥式电流检测电路检测获得的电流检测信号 的示意图。 具体实施方式 需要说明的是, 在不冲突的情况下, 本申请中的实施例及实施例中的特征可以相 互组合。 下面将参考附图并结合实施例来详细说明本发明。 本发明实施例提供了一种桥式电流检测电路。 图 5是根据本发明实施例的桥式电 流检测电路的示意图, 如图 5所示, 包括电流互感器、 电流检测电阻 Rs、 第一可控开 关 Sl、第二可控开关 S2、第三可控开关 S3和第四可控开关 S4。 下面对其结构进行详 细描述。 电流互感器的原边绕组串联在全桥主电路中, 电流互感器的副边绕组的一端连接 至第一可控开关 S1的一端和第二可控开关 S2的一端, 电流互感器的副边绕组的另一 端连接至第三可控开关 S3的一端和第四可控开关 S4的一端; 电流检测电阻 Rs的一 端连接至第一可控开关 S1 的另一端和第三可控开关 S3 的另一端, 电流检测电阻 Rs 的另一端连接至第二可控开关 S2的另一端和第四可控开关 S4的另一端并接地, 其中 第一可控开关 Sl、第二可控开关 S2、第三可控开关 S3和第四可控开关 S4, 设置为在 控制信号的作用下, 为电流互感器的副边绕组的感应电流到电流检测电阻 Rs提供通 路。 相关技术中, 电流检测电阻 Rs将反灌电流检测成对应成比例的正向电压。本发明 实施例中, 在四个可控开关 Sl、 S2、 S3、 S4的控制下, 电流检测电阻 Rs将反灌电流 检测成对应成比例的负向电压。 由于控制芯片逐波限流保护动作阀值电压为正压, 因 此反灌电流对应的负向电压是不会触发芯片逐波限流保护动作的, 即通过本发明的技 术方案可以将大反灌电流误触发控制芯片逐波限流保护动作而引起电源烧毁的隐患消 除, 从而提高电源的可靠性。
需要说明的是, 本发明的桥式电流检测电路的输入为全桥原边交流信号, 输出为 电流检测信号, 该信号输入到电流型控制芯片的电流检测引脚, 使得 PWM信号跟随 输入电流的变化而变化。 需要说明的是, 当控制信号为高电平时可控开关开通, 在开通期间, 电流可以双 向流过开关; 而当控制信号为低电平时可控开关关断, 在关断期间, 开关上除了很小 的漏电流之外, 不能流过任何方向的电流。 下面对在四个可控开关 S l、 S2、 S3、 S4控制下的电流检测电阻 Rs将反灌电流检 测成对应成比例的负向电压的过程进行详细描述。 需要说明的是, 在本发明实施例中, 当主拓扑结构中开关管 Ql、 Q4导通时, 电 流互感器原边电流从 CSA流向 CSB为正向电流, 反之检测出来的电流为反灌电流; 当主拓扑结构中开关管 Q2、 Q3导通时, 电流互感器原边电流从 CSB流向 CSA为正 向电流, 反之检测出来的电流为反灌电流。 图 6是根据本发明实施例的电流检测结构中可控开关 S l、 S2、 S3、 S4, 以及开关 管 VT相对于全桥主管 Ql、 Q2、 Q3、 Q4的驱动时序图, 如图 6所示, Q1禾 P Q4开通 时, S 1和 S4导通, 此时 CT副边电流通过 S l、 S4和 Rs导通, 在 Rs上检测出电流信 号的大小及方向; 当电流从 CSA流向 CSB时, 主拓扑能量由输入电源发出, CT副边 电流先经 S l, 再经 Rs, 最后从 S4回来形成环路, 在 Rs上形成对应成比例的正向电 压; 而当电流从 CSB流向 CSA时, 主拓扑能量往输入电源送, 即此时电流为反灌电 流, CT副边电流先经 S4, 再经 Rs, 最后从 S I回来形成环路, 从而在 Rs上形成对应 成比例的负向电压。所以 Rs上的正向电压对应为正向电流,负向电压对应为反灌电流。 根据全桥工作的原理, 反灌电流产生在主开关管开通的前期, 主要是由于各种情况下 副边电流反灌到原边而产生。 图 7 是根据本发明实施例的桥式电流检测电路检测获得的电流检测信号的示意 图, 如图 7所示, 该信号是正负的。 优选地, 桥式电流检测电路还包括: 基准供电电源 Ur, 设置为为电流检测电阻
Rs提供一个固定的正向分压; 偏置分压电阻 Rl, 其中, 偏置分压电阻的一端连接至 基准供电电源 Ur, 偏置分压电阻的另一端连接至电流检测电阻 Rs的一端。 本优选实施例中, 电流检测电阻的电压由两部分叠加而成: 1、 电流互感器的副边 绕组感应电流在电流检测电阻上产生的电压信号; 2、偏置电源部分在电流检测电阻上 产生的固定正向偏压。
优选地, 桥式电流检测电路还包括: 滤波电路, 设置为对电流检测电阻 Rs检测的 电流进行滤波。 本优选实施例中, 滤波电路对输入该滤波网络的电压信号进行滤波, 从而抑制减 弱一部分噪声的幅值。 优选地, 滤波电路包括: 电阻 R2, 其中, 电阻 R2的一端连接至电流检测电阻 Rs 的一端, 电阻 R2的另一端输出滤波后的电流; 电容 C2, 其中, 电容 C2的一端连接 至电阻 R2的另一端, 电容 C2的另一端接地。 优选地, 桥式电流检测电路还包括: 二级管 D, 其负极连接至电阻 R2的另一端, 正极接地。 优选地, 二级管 D为导通压降低于 0.3V的肖特基二极管。 本优选实施例中, 二级管 D嵌位控制芯片电流检测信号输入引脚的负向电压在任 何条件下都不超过 -0.3 V, 从而可以保护控制芯片。 优选地, 桥式电流检测电路还包括: MOS开关管 VT, 其漏极连接至电阻 R2的 另一端, 其源极接地。 优选地, MOS开关管 VT设置为在控制信号的作用下, 与第一可控开关 Sl、第二 可控开关 S2、 第三可控开关 S3和 /或第四可控开关 S4同时导通。 优选地, MOS开关管 VT的导通时间不超过 100ns。 本优选实施例中, MOS开关管 VT可以将来自主拓扑主管的开关噪声嵌位到地电 平, 从而将最终的电流检测信号前沿开关噪声消除掉。 优选地, MOS开关管 VT为导通电阻小的小信号 N沟道 MOS管。 下面将结合实例对本发明实施例的实现过程进行详细描述。 图 8是根据本发明优选实施例的桥式电流检测电路的示意图, 如图 8所示, 在图 5所示的桥式电流检测电路的基础上, 依次增加了 Ur和 Rl、 R2和 C2、 D和 VT。 下 面通过优选实施例一至优选实施例三对其进行详细描述。 优选实施例一 本发明优选实施例一在图 5所示的桥式电流检测电路的基础上增加了 Ur和 Rl。
图 9是根据本发明优选实施例一的桥式电流检测电路检测获得的电流检测信号的 示意图。 由于通过 Ur和 R1在 Rs上添加了一个正向偏压, 因此该桥式电流检测电路 检测获得的电流检测信号在图 7的基础上叠加了一个正向的偏压, 从而使电流检测信 号整体往上偏移。 需要说明的是,加在 Rs上的正向偏置电压大小可以通过电路调试来获得,本发明 通过改变电源输出端负载,在空载、满载、空满载跳变等动作来测试 Rs上稳态的负压, 并取其中绝对值最大的负压确定为所要叠加的正向偏压大小。 从而可以保证在电路稳 态工作过程中, 检测到噪声之外的稳态负向电压都被转换成了正向电压。 优选实施例二 本发明优选实施例二在图 5 所示的桥式电流检测电路的基础上增加了 Ur、 Rl、
R2禾口 C2。 图 10 是根据本发明优选实施例二的桥式电流检测电路检测获得的电流检测信号 的示意图。 由于叠加了正向偏置电压的电流检测信号输入 R2、 C2滤波网络, 经滤波 之后 (如图 10所示, 可以看出前沿噪声显著减小), 输入控制芯片的电流检测引脚。 需要注意 R2、 C2滤波参数的选取既不能太强也不能太弱, 滤波能力太强, 会把 电流检测波形中每个周期的正向电流峰值滤平, 把真正表现全桥原边主电流最大值的 峰值点滤除掉了, 这会导致电流环控制不准确, 严重时造成电源模块的烧毁。 而如果 滤波能力太弱, 则在电源带大容载开机瞬间产生的峰值电流会触发控制芯片的逐波限 流动作, 从而使电源开不了机。 所以这个 R2、 C2滤波参数的取值, 需要根据布板的 具体情况, 通过调试来确定。 优选实施例三 本发明优选实施例三在图 5 所示的桥式电流检测电路的基础上增加了 Ur、 Rl、 R2、 C2、 D禾 P VT。 图 11 是根据本发明优选实施例三的桥式电流检测电路检测获得的电流检测信号 的示意图。 由于控制芯片 CS引脚处的二极管 D, 须选用导通压降低于 0.3V的肖特基 二极管。 该二极管的作用是嵌位控制芯片电流检测引脚处的负压。 当电源原边有一个 很大的反灌电流时, 该反灌电流形成的负压通过叠加固定的直流偏置不能完全消除, 此时二极管 D会导通, 将控制芯片 CS脚处的负压电平嵌位到 0.3V以下, 保护芯片不 受损坏。
控制芯片的 CS引脚处增加的小信号 MOS管 VT, 其驱动信号见图 6所示。 VT 在全桥每组对管开通的稍前开通 (这是由于驱动信号的上升沿是同时的, 但由于 VT 是小信号 MOS管, Qg小, 所以能更快的开通), 开通维持时间不超过 100ns, 其作用 是将电流检测信号的前沿噪声嵌位到地 (见图 11 ), 彻底消除前沿噪声误触发控制芯 片逐波限流动作的隐患。 综上所述, 根据本发明的上述实施例, 提供了一种桥式电流检测电路。 通过本发 明, 在四个可控开关 Sl、 S2、 S3、 S4的控制下, 电流检测电阻 Rs将反灌电流检测成 对应成比例的负向电压。 由于控制芯片逐波限流保护动作阀值电压为正压, 因此反灌 电流对应的负向电压是不会触发芯片逐波限流保护动作的, 即通过本发明的技术方案 可以将大反灌电流误触发控制芯片逐波限流保护动作而引起电源烧毁的隐患消除, 从 而提高电源的可靠性。 以上所述仅为本发明的优选实施例而已, 并不用于限制本发明, 对于本领域的技 术人员来说, 本发明可以有各种更改和变化。 凡在本发明的精神和原则之内, 所作的 任何修改、 等同替换、 改进等, 均应包含在本发明的保护范围之内。
Claims
权 利 要 求 书 一种桥式电流检测电路, 包括:
电流互感器, 其中, 所述电流互感器的原边绕组串联在全桥主电路中, 所 述电流互感器的副边绕组的一端连接至第一可控开关 (S1 ) 的一端和第二可控 开关 (S2) 的一端, 所述电流互感器的副边绕组的另一端连接至第三可控开关 ( S3 ) 的一端和第四可控开关 (S4) 的一端;
电流检测电阻 (Rs), 其中, 所述电流检测电阻 (Rs) 的一端连接至所述 第一可控开关 (S1 ) 的另一端和所述第三可控开关 (S3 ) 的另一端, 所述电流 检测电阻 (Rs) 的另一端连接至所述第二可控开关 (S2) 的另一端和所述第四 可控开关 (S4) 的另一端并接地, 其中所述第一可控开关 (Sl )、 所述第二可 控开关 (S2)、 所述第三可控开关 (S3 ) 和所述第四可控开关 (S4), 设置为在 控制信号的作用下, 为所述电流互感器的副边绕组的感应电流到所述电流检测 电阻 (Rs) 提供通路。 根据权利要求 1所述的桥式电流检测电路, 其中, 还包括:
基准供电电源 (Ur), 设置为为所述电流检测电阻 (Rs) 提供一个固定的 正向分压;
偏置分压电阻 (Rl ), 其中, 所述偏置分压电阻的一端连接至所述基准供 电电源 (Ur), 所述偏置分压电阻的另一端连接至所述电流检测电阻 (Rs) 的
1而。 根据权利要求 1所述的桥式电流检测电路, 其中, 还包括: 滤波电路, 设置为对所述电流检测电阻 (Rs) 检测的电流进行滤波。 根据权利要求 3所述的桥式电流检测电路, 其中, 所述滤波电路包括:
电阻(R2), 其中, 所述电阻(R2) 的一端连接至所述电流检测电阻(Rs) 的一端, 所述电阻 (R2) 的另一端输出滤波后的电流;
电容 (C2), 其中, 所述电容 (C2) 的一端连接至所述电阻 (R2) 的另一 端, 所述电容 (C2) 的另一端接地。 根据权利要求 4所述的桥式电流检测电路, 其中, 还包括: 二级管(D), 其负极连接至所述电阻 (R2) 的另一端, 正极接地。
6. 根据权利要求 5 所述的桥式电流检测电路, 其中, 所述二级管 (D) 为 导通压降低于 0.3V的肖特基二极管。
7. 根据权利要求 4所述的桥式电流检测电路, 其中, 还包括: MOS开关管
(VT), 其漏极连接至所述电阻 (R2) 的另一端, 其源极接地。
8. 根据权利要求 7所述的桥式电流检测电路,其中,所述 MOS开关管(VT) 设置为在所述控制信号的作用下, 与所述第一可控开关 (Sl )、 所述第二可控 开关(S2)、 所述第三可控开关(S3 )和 /或所述第四可控开关(S4) 同时导通。
9. 根据权利要求 8所述的桥式电流检测电路,其中,所述 MOS开关管(VT) 的导通时间不超过 100ns。
10. 根据权利要求 7所述的桥式电流检测电路, 其中, 所述 MOS开关管 (VT) 为 小信号 N沟道 MOS管。
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