WO2012104580A2 - Electrical devices with improved fault current handling capabilities - Google Patents

Abstract

An electrical device comprising: first and second windings that are magnetically coupled such that, during normal operation, magnetic fields of the first and second windings interact and currents flow through the first and second windings; and a power controller arranged to control the current in the second winding in a fault situation, so as to reduce or limit the current magnitude flowing in the first winding or the second winding, or to synchronise the magnetic field of the second winding with the magnetic field of the first winding and thereby reduce their interaction; wherein the second winding incorporates a tap changer arrangement operable to reduce the number of turns in the second winding through which the current in the second winding flows, and thereby decrease the mutual inductance between the first and second windings and reduce the voltage magnitude required of the power controller in order to exercise control in the fault situation. Also provided is a method of operating such a device, and a tap changer arrangement that is well suited for use with such a device.

Description

ELECTRICAL DEVICES WITH IMPROVED

FAULT CURRENT HANDLING CAPABILITIES

This invention is in the field of power engineering (i.e. the generation, transmission and distribution of electric power) and relates, in part, to electrical and electromechanical devices which are prone to generating a fault current. The invention is particularly applicable, but by no means limited, to rotary generators, especially when used as distributed generators in a wider power distribution network.

Background to the Invention

Environmental concerns, increasing fuel prices and increasingly stringent building energy rating regulations have led to an increase in requests for grid connection agreements to connect renewable energy sources or combined heat and power (CHP) installations as "distributed generation" within the public power distribution network. Several issues may be at stake in making such agreements but one in particular is of concern here. Each time a new source is added to a network for the supply of power in normal operation, there is also a new source for the supply of current into a short circuit (more generally a low impedance) fault. Faults are "cleared" by opening circuit breakers that are rated for a particular maximum breaking current. Further, cables and transformers are rated to withstand certain fault currents during fault clearance. Once designed for a particular fault current (often known as a fault level), a substation and distribution network is then limited in the capacity of generation that can be added without exceeding the fault current. Adding generation beyond the existing fault level requires reinforcement or rebuilding. Increasing breaker ratings can be prohibitively expensive or simply impossible due to space or construction time constraints. This may discourage or slow the uptake of renewable projects. The problem is generally more prevalent in urban rather i than rural networks where loadings are higher and distances are shorter (and hence the impedance governing the fault current is lower).

In rural or marine areas, the distributed generation is likely to include wind- or wave-powered turbines. In urban areas, the distributed generation is likely to be gas or biomass fed combined heat and power (CHP) plants or perhaps photovoltaic panels rather than the marine or wind in rural areas. CHP generators are likely to be with reciprocating engines or turbines as the prime mover driving a synchronous or asynchronous generator connected to the grid. Direct connection of a synchronous machine to the grid requires that the machine runs at a speed dictated by the grid frequency. Even a normal asynchronous machine would need to run within a few percent of the same speed. Variable speed operation of the prime mover would require some form of speed or frequency converter.

The impact of distributed generation on a conventional substation with radial out-going feeders is illustrated in Figure 2. A generic substation layout is shown, in which two HV incomers feed a number of outgoing feeders via a pair of transformers and through a coupled pair of bus bars. Each MV feeder is equipped with a circuit breaker at the substation (Bl . l and B1.2) and feeds local loads that are interspersed along it. If a fault occurs on a different feeder, e.g. feeder 1, then the associated circuit breaker B2.1 must be capable of interrupting the fault current. Three different sources of fault current have been indicated by lines 5, 6 and 7: two fault current contributions (lines 5 and 6) flow via the incomers and transformers and one (line 7) from the generator on feeder 4. It is apparent that the presence of distributed generation on feeder 4 increases the fault current seen by B2.1 over that which would occur with no local generation present. Typically a number of breakers are placed along the length of a feeder, so that the smallest possible feeder section containing the fault can be disconnected rather than the whole feeder being disconnected by a breaker in the substation. To achieve the selectivity necessary to open the correct breaker, the settings of the relays of these breakers are typically coordinated (or "graded") with one another using over-current trip characteristics with different time and current sensitivities. The presence of distributed generation that contributes additional fault current changes the direction and magnitude of fault currents and can disturb this grading.

Therefore, in a network that is "congested" from a fault level point of view, it is desired to have distributed generators that do not inject fault current into the network (or only contribute a defined small current in the event of a fault), but which stay connected during the fault and are available for power production as soon as possible after the protection system has cleared the fault.

Summary of the Invention

According to a first aspect of the present invention there is provided an electrical device as defined in Claim 1 of the appended claims. Thus there is provided an electrical device comprising: first and second windings that are magnetically coupled such that, during normal operation, magnetic fields of the first and second windings interact and currents flow through the first and second windings; and a power controller arranged to control the current in the second winding in a fault situation, so as to reduce or limit the current magnitude flowing in the first winding or the second winding, or to synchronise the magnetic field of the second winding with the magnetic field of the first winding and thereby reduce their interaction; wherein the second winding incorporates a tap changer arrangement operable to reduce the number of turns in the second winding through which the current in the second winding flows, and thereby decrease the mutual inductance between the first and second windings and reduce the voltage magnitude required of the power controller in order to exercise control in the fault situation. By virtue of the tap changer arrangement incorporated in the second winding, the winding ratio between the first and second windings can be changed during a fault situation. This increases the ability of the power controller to take control of the fault current (particularly if the power controller would otherwise be unable to provide sufficient voltage to do so), and enables the power controller to reduce the fault current produced by the device in the fault situation to zero, or some other low level. During the fault situation, by temporarily reducing the number of turns on the second winding, it is not necessary to increase the voltage applied by the power controller, as the key parameter is the voltage applied per turn of winding. There can be an increase in the current in the second winding immediately after the tap operation but this can be rapidly reduced back down because there is sufficient voltage available to exercise control over the current. Moreover, the device is able to stay connected during the fault, to be available for power production post-fault, and to tolerate a variation in the speed of interaction of the magnetic fields of the first and second windings in normal use and during a fault.

Preferable, optional, features are defined in the dependent claims.

The electrical device may be a rotating machine comprising a stator and a rotor.

In a preferred embodiment, the device is a generator, wherein the current flowing through the first winding is the output current from the generator.

i Preferably the first winding is incorporated in the stator and the second winding is incorporated in the rotor. That is to say, the tap changer arrangement is incorporated in the rotor windings. Particularly preferably the device is a doubly fed induction generator, wherein the power controller comprises a machine side converter. Preferably the machine side converter provides pulse width modulation by dynamically adjusting the pulse width of a fixed frequency voltage pulse train. Preferably the machine side converter is connected to a DC link, the voltage of which is regulated by a grid side converter.

Alternatively the electrical device may be a motor, wherein the current flowing through the first winding is the input current powering the motor. Alternatively the first and second windings may be static relative to each other. In such a case, the first winding may be arranged to couple a first electrical distribution arrangement in series with a second electrical distribution arrangement, for example in an electrical substation, distribution board or transmission line.

In all the above cases, preferably the power controller and tap changer arrangement together comprise semiconductor switching means. These provide the advantage of rapidly controllable switching, faster than mechanical switches can generally achieve, to enable the device to take control of the fault current within a short period of time (ideally within one quarter of the AC cycle).

Preferably the power controller and tap changer arrangement together comprise modulation switches and director switches. Particularly preferably the modulation switches comprise transistors, for example insulated gate bipolar transistors, which are sufficiently fast for this purpose.

Preferably the director switches comprise thyristors. Although the director switches could be formed using other semiconductor devices, such as transistors, for example, forming them using thyristors is advantageous since thyristors automatically enter into a blocking state when the current through them attempts to reverse, whereas transistors do not block reverse current or do so only with a low breakdown voltage. The property of thyristors automatically turning themselves off when the current attempts to reverse also enables a very responsive commutation sequence to be employed during tap- changing operations.

In our presently-preferred embodiment (as shown in Figure 8), in the tap changer arrangement, first and second thyristors (Thyl and Thy 5) are arranged to direct the current in the second winding when a first modulation switch transistor (SI) is switched on and conducting, the first and second thyristors (Thyl and Thy 5) being respectively connected to first and second tap positions on the second winding, the first tap position providing conduction along more of the second winding than the second tap position. Thus Thyl and Thy 5 direct the current to the appropriate tap when SI is turned on and is carrying current.

Also in our presently-preferred embodiment, in the tap changer arrangement, third and fourth thyristors (Thy2 and Thy6) are arranged to direct the current in the second winding when a second modulation switch transistor (S2) is switched on and conducting, the third and fourth thyristors (Thy2 and Thy6) being respectively connected to the said first and second tap positions on the second winding. Thus Thy2 and Thy6 direct the current to the appropriate tap when S2 is turned on and is carrying current. In operation, SI and S2 are switched on and off alternately to effect pulse- width modulation of the voltage applied to the second winding.

Preferably the tap changer arrangement further comprises further semiconductor devices known as freewheel devices, each connected in parallel across a modulation switch transistor and a respective one of the thyristors connected thereto, arranged such as to carry winding current that would flow against the normal conduction direction of the first modulation switch transistor (SI) and the first and second thyristors (Thyl and Thy 5), or the second modulation switch transistor (S2) and the third and fourth thyristors (Thy2 and Thy 6). Thus, the purpose of the freewheel devices is to carry the winding current when it is flowing in the opposite direction to whichever of SI and S2 is switched on.

Preferably the further semiconductor devices comprise: a first freewheel thyristor (Thy3), reverse-connected relative to the director switch thyristors and connected across the first modulation switch transistor (SI) and the first director switch thyristor (Th l) to the first tap position on the second winding; a first freewheel diode (Dl), reverse-connected relative to the director switch thyristors and connected across the first modulation switch transistor (S 1 ) and the second director switch thyristor (Thy5) to the second tap position on the second winding; a second freewheel thyristor (Thy4), reverse-connected relative to the director switch thyristors and connected across the second modulation switch transistor (S2) and the third director switch thyristor (Thy2) to the first tap position on the second winding; and a second freewheel diode (D2), reverse-connected relative to the director switch thyristors and connected across the second modulation switch transistor (S2) and the fourth director switch thyristor (Thy6) to the second tap position on the second winding. The above-mentioned further semiconductor devices provide the advantage of guaranteed current continuity during the tap changing operation, and (by virtue of the use of the reverse-connected thyristors) also enable the device to withstand any high voltages which may be generated across the open-circuited portion of the second winding between the first and second tap positions during partial tap mode.

Preferably the electrical device further comprises a fault detection module arranged to compare the current and/or voltage in the first or second winding to a threshold value and, in the event that the threshold value is exceeded, to initiate operation of the power controller and tap changer arrangement.

According to a second aspect of the invention there is provided a method of operating an electrical device, the device comprising first and second windings that are magnetically coupled such that, during normal operation, magnetic fields of the first and second windings interact and currents flow through the first and second windings; wherein the method comprises, in a fault situation, controlling the current in the second winding, so as to reduce or limit the current magnitude in the first winding or the second winding, or to synchronise the magnetic field of the second winding with the magnetic field of the first winding and thereby reduce their interaction; and operating a tap changer arrangement incorporated in the second winding, to reduce the number of turns in the second winding through which the current in the second winding flows, and thereby decrease the mutual inductance between the first and second windings in the fault situation. In our presently-preferred embodiment, in normal operation, current in the second winding flows via the first tap position; and, in the event of a fault, in order to perform a tap-down operation to cause the current in the second winding to flow via the second tap position and not the first, the method comprises the commutation steps of: (1) opening the first and second modulation switch transistors (SI and S2) such that the current in the second winding flows through the first or second freewheel thyristor (Thy3 or Thy4) depending on whether the current is positive or negative; (2) changing the tap by applying gating signals to the second and fourth thyristors (Thy5 and Thy6) and by removing gating signals from the first and third thyristors (Thyl and Thy2) and the first and second freewheel thyristors (Thy3 and Thy4), with the first or second freewheel thyristor (Thy3 or Thy4) remaining in conduction; (3) closing the second modulation switch transistor (S2) if the winding current is positive (i.e. out of the winding) in order to provide a preferred current path through the first freewheel thyristor (Thy3), or closing the first modulation switch transistor (S I) if the winding current is negative in order to provide a preferred current path through the second freewheel thyristor (Thy4); and (4) allowing the first or second freewheel thyristor (Thy3 or Thy4) to cease conduction as the current through it attempts to reverse, such that the current in the second winding flows via the second tap position (via Thy5 or Thy6) and not the first tap position once normal modulation of the first and second modulation switch transistors (SI and S2) resumes.

Optionally, the method may further comprise an additional commutation step, after step (2) and before step (3), of: briefly switching on the first or second modulation switch transistor (S 1 or S2), depending on whether the current is positive or negative, and then turning it off again. This additional commutation step puts zero volts across the open-circuited portion of the second winding between the first and second tap positions, thereby accelerating the recombination process in the first or third thyristor (Thyl or Thy2 as applicable), and assisting in its turn off. After the fault has cleared, the method preferably further comprises performing a tap-up operation, so as to cause the current in the second winding to flow via the first tap position, the tap-up operation comprising applying gating signals to the first and third thyristors (Thyl and Thy2) and the first and second freewheel thyristors (Thy3 and Thy4), and removing the gating signals from the second and fourth thyristors (Thy5 and Thy6).

Preferably the tap-up operation further comprises: sampling the polarity of the current in the conducting portion of the second winding; if the current in the conducting portion of the second winding is positive, switching the first modulation switch transistor (SI) off and the second modulation switch transistor (S2) on; if the current in the conducting portion of the second winding is negative, switching the first modulation switch transistor (SI) on and the second modulation switch transistor (S2) off; and then the said steps of: applying the gating signals to the first and third thyristors (Thy and Thy2) and the first and second freewheel thyristors (Thy3 and Thy4); and removing the gating signals from the second and fourth thyristors (Thy 5 and Thy6). By switching SI or S2 in this manner during the tap-up operation, this speeds up the current transfer across the newly-available extent of the second winding. In general, the method may also comprise comparing the current and/or voltage in the first or second winding to a threshold value and, in the event that the threshold value is exceeded, controlling the current in the second winding and initiating operation of the tap changer arrangement. According to a third aspect of the invention there is provided a tap changer arrangement on a winding, comprising: first and second director switch thyristors (Thyl and Thy5) arranged to direct current in the winding when a first modulation switch transistor (SI) is switched on and conducting, the first and second thyristors (Thyl and Thy5) being respectively connected to first and second tap positions on the winding, the first tap position providing conduction along more of the winding than the second tap position; and third and fourth director switch thyristors (Thy2 and Thy6) arranged to direct current in the winding when a second modulation switch transistor (S2) is switched on and conducting, the third and fourth thyristors (Thy2 and Thy6) being respectively connected to the said first and second tap positions on the winding; wherein the director switch thyristors are connected to conduct in the same direction as their respective modulation devices; and wherein the tap changer arrangement further comprises: a first freewheel thyristor (Thy3), reverse- connected relative to the director switch thyristors and connected in parallel across the first modulation switch transistor (SI) and the first director switch thyristor (Thyl) to the first tap position on the winding; a first freewheel diode (Dl), reverse-connected relative to the director switch thyristors and connected in parallel across the first modulation switch transistor (SI) and the second director switch thyristor (Thy5) to the second tap position on the winding; a second freewheel thyristor (Thy4), reverse-connected relative to the director switch thyristors and connected in parallel across the second modulation switch transistor (S2) and the third director switch thyristor (Thy2) to the first tap position on the winding; and a second freewheel diode (D2), reverse- connected relative to the director switch thyristors and connected in parallel across the second modulation switch transistor (S2) and the fourth director switch thyristor (Thy6) to the second tap position on the winding.

1 Thus, Thyl and Thy 5 are oriented such that they can carry the winding current if SI is on and the winding current is negative (i.e. into the winding), and Thy2 and Thy6 are oriented such that they can carry the winding current if S2 is on and the winding current is positive (i.e. out of the winding).

According to a fourth aspect of the invention there is provided a method of operating a tap changer arrangement, the tap changer arrangement being in accordance with the third aspect of the invention; wherein, in a first operational state, current in the winding flows via the first tap position; and wherein, in order to perform a tap-down operation to cause the current in the winding to flow via the second tap position and not the first, the method comprises the commutation steps of. (1) opening the first and second modulation switch transistors (SI and S2) such that the current in the winding flows through the first or second freewheel thyristor (Thy3 or Thy4) depending on whether the current is positive or negative; (2) changing the tap by applying gating signals to the second and fourth thyristors (Thy5 and Thy6) and by removing gating signals from the first and third thyristors (Thyl and Thy2) and the first and second freewheel thyristors (Thy3 and Thy4), with the first or second freewheel thyristor (Thy3 or Thy4) remaining in conduction; (3) closing the second modulation switch transistor (S2) if the winding current is positive in order to provide a preferred current path through the first freewheel thyristor (Thy3), or closing the first modulation switch transistor (S I) if the winding current is negative in order to provide a preferred current path through the second freewheel thyristor (Thy4); and (4) allowing the first or second freewheel thyristor (Thy3 or Thy4) to cease conduction as the current through it attempts to reverse, such that the current in the winding flows via the second tap position and not the first tap position once normal modulation of the first and second modulation switch transistors (SI and S2) resumes. Optionally, the method may further comprise an additional commutation step, after step (2) and before step (3), of: briefly switching on the first or second modulation switch transistor (S I or S2), depending on whether the current is positive or negative, and then turning it off again.

The method may further comprise performing a tap-up operation, the tap-up operation comprising applying gating signals to the first and third thyristors (Thyl and Thy2) and the first and second freewheel thyristors (Thy3 and Thy4), and removing the gating signals from the second and fourth thyristors (Thy5 and Thy6).

Preferably the tap-up operation further comprises: sampling the polarity of the current in the conducting portion of the winding; if the current in the conducting portion of the winding is positive, switching the first modulation switch transistor (S I) off and the second modulation switch transistor (S2) on; if the current in the conducting portion of the winding is negative, switching the first modulation switch transistor (SI) on and the second modulation switch transistor (S2) off; and then the said steps of: applying the gating signals to the first and third thyristors (Thyl and Thy2) and the first and second freewheel thyristors (Thy3 and Thy4); and removing the gating signals from the second and fourth thyristors (Thy5 and Thy6).

With all the aspects of the invention, preferable, optional, features are defined in the dependent claims.

Brief Description of the Drawings

Embodiments of the invention will now be described, by way of example only, and with reference to the drawings in which:

Figure 1 is a key to some of the electrical symbols used in the other diagrams;

1 Figure 2 illustrates a fault current contribution of a distributed generator;

Figure 3 illustrates a full converter interface;

Figure 4 illustrates a doubly fed induction generator;

Figure 5 illustrates part of a circuit incorporating a doubly fed induction generator;

Figure 6 illustrates a squirrel cage and doubly fed induction generator fault response for various DC-link voltages;

Figure 7 illustrates an equivalent circuit diagram for an embodiment of the invention (the so-called "ZEFAL" generator);

Figure 8 illustrates a machine side converter tap changer (single phase circuit diagram);

Figure 9 illustrates a tap down commutation sequence for a positive load current;

Figure 10 illustrates a machine side controller structure;

Figure 1 1 illustrates a fault ride through voltage profile (low envelope of profiles required by grid operators);

Figure 12 illustrates a proposed circuit symbol for the ZEFAL generator;

Figure 13 illustrates a ZEFAL power flow controller coupling two bus bars in an electricity substation;

Figure 14 illustrates a ZEFAL power flow controller with a further shunt connected power converter;

Figure 15 illustrates a prototype tap changer/inverter single phase circuit diagram;

Figure 16 illustrates a fault response test set-up;

Figure 17 illustrates some simulation and experimental results for the ZEFAL generator (75% drop in voltage, rotor current control, staggered response, 1440 rpm);

Figure 18 shows some simulation results for the tap changer circuit of Figure 8 (tap down at positive load current); Figure 19 shows some further simulation results for the tap changer circuit of Figure 8 (tap up at positive load current);

Figure 20 illustrates a single phase tap changer/inverter prototype circuit;

Figure 21 shows some measurement results obtained using the circuit of Figure 20 (tap down at positive load current);

Figure 22 shows some further measurement results obtained using the circuit of Figure 20 (tap up at positive load current);

Figure 23 shows some further measurement results obtained using the circuit of Figure 20 (tap down at negative load current);

Figure 24 shows some further measurement results obtained using the circuit of Figure 20 (tap up at negative load current); and

Figure 25 illustrates split inductors, for the split rotor doubly fed induction generator model of Appendix 1. Detailed Description of Preferred Embodiments

The present embodiments represent the best ways known to the applicants of putting the invention into practice. However, they are not the only ways in which this can be achieved. A brief description and comparison of a number of viable alternatives will be given first. Then, a new doubly fed induction generator (DFIG) based generator topology will be introduced. Its operational performance will be verified using simulation results and experimental data from the prototype machine.

7. Further background

Depending on the electrical or mechanical output desired of a distributed generator, various generator and grid interface technologies exist. Prime movers that have a fixed speed are often connected directly to the grid via a conventional generator such as synchronous and asynchronous machines. They are robust and cost competitive. However, they exhibit a high fault current capability which can be hard to mitigate. Reactors and superconducting fault current limiters can be used to limit fault current, and high speed circuit breakers, explosive bolts or back-to-back power converter interfaces can be used to stop the fault current by disconnecting the generator. This is expensive and undesirable because when the grid recovers it needs every healthy generator to aid in re-establishing a stable supply to consumers. Furthermore, conventional generators can only operate in a very narrow speed range which might lead to inefficient operation or sub-optimal energy extraction from some prime movers.

Variable speed operation, fault current limiting and power factor control can all be achieved together by using an inverter to interface to the grid as shown in Figure 3. Energy sources with a DC output such as fuel cells or photovoltaic panels are commonly interfaced through an inverter. However, the technology of inverter grid interfaces is relatively young and still prohibitively expensive in the case of high power interfaces. A useful compromise between the variable speed operation of full converter interface and the cheaper directly connected generator are the doubly fed induction generators (DFIGs) as shown in Figure 4. These became popular in wind turbine design during the 1990s because they offered partial-range variable speed operation using partial rated (and therefore cheaper) power converters. A partial-range variable speed operation still allows for greatly improved energy extraction and the rating of the back-to-back converters is a fraction of the full power rating (with the fraction set by the chosen speed range). For CHP installations it would allow prime movers to run at an optimal efficiency operating point. Moreover, DFIGs enable control of reactive power output which can be used for voltage support.

However, during a fault, these DFIGs still delivered fault current and experienced problems due to fault current being reflected into the rotor circuits and thus endangering the power electronics. A common solution is to insert a crowbar into the rotor circuit to limit the fault current magnitude and to disconnect from the grid. As large wind farms started appearing, this strategy of disconnection threatened to cause instability in the grid and more stringent fault ride-through requirements such as ride-through voltage profiles and grid voltage support were put in place.

We recognised the DFIG concept as an opportunity to design a new type of generator (our so-called "ZEFAL" generator) that is capable of staying connected to the grid during a fault whilst delivering zero fault current and even to some extent engaging in grid support services. To understand the operation of the ZEFAL generator, a basic knowledge of DFIGs is required, which is explained in the next section. This will pave the way for the introduction of the modified DFIG and the associated power electronics. Finally, the introduced concepts will be put to the test by means of computer simulation and experiments.

2. Doubly fed induction generators

Doubly fed induction generators (DFIGs) combine the robust and cheap construction of induction machines with the control flexibility of power electronics. They consist of a wound rotor induction generator (WRIG) whose rotor windings have been made available via a set of slip rings. The stator windings are connected to the grid and the rotor windings are excited through the machine side converter (MSG). The MSC is connected to a DC link the voltage of which in turn is regulated by a grid side converter (GSC). The GSC can be directly connected to the grid or via a transformer. In some cases a three winding transformer is used to supply the stator and GSC with different voltages. The complex power supplied to the grid is the sum of the complex power flowing out of the stator terminals and that flowing out of the GSC, as shown in Figure 5.

2.1 Steady state operation

During normal operation, the GSC is operated as an active rectifier which regulates the DC link voltage and the reactive power output. The MSC is operated as a variable frequency inverter, controlling the rotor currents such as to track torque, speed or stator real and reactive power. Using Clarke and Park transformations, the dynamics of the DFIG can be expressed in the synchronously rotating reference frame as: v_s = -Rj_s -~<P_s + j<o_sv_s (1)

dt v_r = -R _r -~ _t + j(o)_s - G)_r ) _r (2)

dt

where:

p_s = (L_is + y₂ L _s + y₂ L_mI_r (3)

where each vector can be expressed as a complex number x_y = x_dy + jx_qy . Using instantaneous power theory (IPT), setting— = 0 and substituting s =——— dt o)_s the steady state stator and rotor real and reactive power can be calculated with:

P_s = ^v ds + = ~^Rs (d + ) + a>, ^~ y* ) (5)

Qs = ¾ - * = ~^ω< ('!■ ⁺ ) + <o_sL_m (i_dri_qs + ) (7)

Qr = ,r - '* = ~^S0J ('I ⁺ '1 ) ^~ «»A _dri_qs + _Λ ) (8) It can be seen that, neglecting winding resistance, S_r ~ sS i.e. complex power flowing out of the rotor is proportional to negative slip. This means that a DFIG with a back-to-back converter rated at 0.3pu has a speed range of 0.7- 1.3pu.

The electrical torque generated by the machine can be found by considering its electrical power output and shaft rotational speed and can be expressed as:

^A^ -v ⁽⁹⁾

2.2 Fault response

The fault response of a DFIG is governed by the fault response of a conventional induction generator (IG) and by the actions of the DFIG control system which is limited by the GSC ratings.

2.2.1 Induction generator fault response

This subsection will briefly describe the IG fault response which is dominated by the interaction between the stator and rotor magnetic fluxes that exist after the fault. The stator voltage generates a rotating magnetic field in the stator windings. When the stator voltage collapses during the fault, there is no voltage to drive this magnetic field and it will remain at its pre-fault DC magnitude and slowly decay through the fault and winding resistances. In a conventional IG such as a squirrel cage induction generator (SCIG) the rotor windings are shorted and the magnetic field in the windings rotates at an angular frequency equal to the slip speed with respect to the rotor mechanical speed. The slip speed is typically very small for IGs and the magnetic field can be considered to be DC in the time frame of interest. From a stationary point of view, this rotor magnetic field is rotating at the rotor mechanical speed and t therefore cutting the stationary stator flux at the rotor mechanical speed. This effectively results in a large slip speed and hence large stator and rotor currents. This response can be formulated mathematically for one phase as:

/, = [e^~"^r: cos a - (1 - σ)^ '^/r; cos(» + )) (10) where

• is the peak fault current,

<^»A

• e^~'^IT' cos cc is the decaying stator magnetic field contribution and a is the stator voltage phase angle at which the fault occurred, and

• ~ (l ~ a)e^Jta''e^~"^{Tr '} cos(<y_sr + «) is the decaying and oscillating rotor magnetic field contribution.

L_s' and L_r' are the stator and rotor transient inductances, T_s' and T_r' are the stator and rotor time constants, and σ is the leakage factor. The stator fault current can be mitigated by either removing the stator or rotor magnetic fields or by synchronising them to remove any interaction. In a DFIG, the MSC can be used to force the rotor flux to rotate in such a way that it is synchronous and aligned with the stator flux. 2.2.2 Doubly fed induction generator fault response

Figure 6 shows the Matlab Simulink simulation results for the phase A stator current after a 100% voltage dip for a SCIG and a DFIG at varying DC link voltages. The SCIG and the DFIG are both operated at a fixed slip of 0.05. The DFIG is operated with rotor current feedback and the rotor current reference has been set equal to the SCIG steady state rotor current for easy comparison. It can be seen that in both cases, the fault current has an exponentially decaying DC offset and an exponentially decaying envelope. A similar current waveform can be observed in the rotor since it is magnetically coupled to the stator. However, the DFIG control system will attempt to track the rotor current reference. It will be able to do so if the DC link voltage is sufficient as is shown by the black dashed line (V_DC = 700V). A small exponentially decaying DC offset can still be noticed. This is due to the current flowing through the stator leakage inductance which decays very slowly through the stator winding resistance. It can be seen that as the DC link voltage is decreased (black dashed, grey dotted and black dot-dashed lines), the DFIG fault response begins to look more and more like that of a SCIG until the DC link voltage is reduced to 0V (black solid line) and the response is exactly the same. The lower the DC link voltage, the less effective voltage per rotor winding turn, and the slower the rotor current can be controlled. Because the fault current rises faster than the control system can prevent with the limited voltage, a fault current peak can be seen which becomes worse for lower DC link voltages.

3. The new "ZEFAL " generator

The core idea behind our new "ZEFAL" generator is to increase the speed of current control by using a tapchanger to apply the DC link voltage to a portion of the rotor winding and hence decrease the mutual inductance whilst preserving the partial rating of the MSC. This will change the stator-rotor winding ratio and cause the rotor currents to be an increased reflection of the stator current which decreases rapidly as the stator current is regulated to zero. The MSC should be designed to have an i t (i is current; t is time and i t is a measure of the energy passed by a current in a given time) rating such that it can cope with these short-lived over-currents without substantially increasing the steady-state rating. The choice of what number of rotor winding turns to connect to the tap-changer is thus a compromise between speed of response, MSC i²t rating and the MSC voltage blocking rating due to the reflected voltage on the open-circuited rotor winding during fault operation.

The presently-preferred embodiment of the ZEFAL generator comprises a split rotor doubly fed induction generator, a tap-changer/inverter, a control system, a fault detection module, and a prime mover.

3.1 Split rotor doubly fed induction generator

The objective of the ZEFAL generator is to get the stator fault currents under control within a fraction of a grid cycle to limit their peak value with a low DC link voltage whilst avoiding the need for a fully rated back-to-back converter. The only means available to control the stator currents is by using the MSC to impose a rotor voltage such as to regulate the stator currents to zero. This is possible due to the mutual inductance between the stator and the rotor. The speed at which the stator current can then be controlled, neglecting saturation effects, is ultimately determined by the mutual inductance and the maximum applicable rotor volta e (i.e. the DC link voltage) and can be approximated as:

where v_r is the applied rotor voltage vector, T_s is the stator current vector and L_{m sr} is the stator-rotor mutual inductance. The stator-rotor mutual inductance is proportional to the product of the number of turns on the stator and rotor windings and can be approximated by:

S 4

where N_s and N_r are the number of turns on the stator and rotor winding, respectively, r, I and g are the radius, length of the rotor and the width of the air gap, respectively, and μ₀ is the permeability of free space. Thus, keeping the maximum applicable rotor voltage constant, the rate of change in stator current

I can be increased by decreasing the mutual inductance - i.e. reducing the number of turns on the rotor (or stator) and thereby increasing the volts-per- turn.

As mentioned previously, the stator fault current arises from an interaction between the stator and rotor flux and can be mitigated by either completely removing the remaining rotor flux or by bringing it into synchronism with the stator flux. It has been noted that rapid resumption of power export after fault clearance can be achieved by adopting the latter option as the rotor is not demagnetised. It requires knowledge of the flux phase angles.

A single phase equivalent circuit diagram of the ZEFAL generator is depicted in Figure 7 showing the stator winding, the split rotor winding, and the tapchanger S. It can be seen that by changing S, either the full rotor winding is excited or only a section, leaving the remaining winding open-circuit. In order to investigate the viability of this concept, a model of the split rotor winding doubly fed induction generator has been developed for use in simulation programs. The generator parameters are listed in Table 1.

Parameters Symbol Unit

Number of turns on stator winding N_s Turns

Number of turns on first rotor winding N_r/ Turns

Number of turns on second rotor winding Turns

Stator winding resistance Rs Ω

First rotor winding section resistance R_rl Ω

Second rotor winding section resistance R_r2 Ω

Stator winding leakage inductance Lis H

First rotor winding section leakage inductance Ltrl H

Second rotor winding section leakage inductance L[r2 H

Magnetising inductance L_m H

Table 1: ZEFAL generator parameters

Applying Kirchhoffs current law to the circuit in Figure 7 using the generator convention (positive current out), the generator dynamics can be expressed in the stationary reference frame:

(13) at

n - ^d - (14)

where

= LJs + L_{j I}i_rl + h _sr2i_{r 2} (16) r₂'r2 (17) rl'r (18)

Note that all variables are three phase quantities that describe a vector in the three phase plane and thus all parameters are 3x3 matrices. Moreover, due to the mechanical rotation of the rotor, the stator-rotor mutual inductances matrices denoted with L are time-varying. The resistance and inductance matrices are given by equations (27)-(35) in Appendix 1. From Figure 7 and equations (13)-(15) the steady state rotor current and voltage magnitudes can be found by considering the transformer effect between winding 1 and 2 and

N

are shown in Table 2 where n = — , / is the steady state current under y

full tap, and v_r is the maximum applicable rotor voltage, i.e. -^- .

Full Tap Partial Tap

1

Rotor currents n

i_r2 = 0

Rotor voltages \ - n

n

Table 2: Steady state voltage and peak current magnitudes

It can be seen that under partial tap, the reflected voltage on the open circuited part of the rotor winding, rotor 2, can exceed the DC link voltage when n < ½. Moreover, the current in rotor 1 under partial tap operation can be considerably larger than under full tap operation if n is small. At the same time as the tap change, the rotor current reference magnitude is set to zero, so the increased current will exist only briefly, in the form of a spike. The MSC should be designed such that this peak can be easily accommodated in its 1 rating. 3.2 Inverter / tap changer

The MSC is typically a voltage source converter (VSC), i.e. it emulates a desired voltage waveform by dynamically adjusting the pulse width of a fixed frequency voltage pulse train. This is called Pulse Width Modulation (PWM) and is typically achieved by using complementary alternately fired power electronic switches to connect a load to positive and negative supply rails alternately. In the case of a DFIG, this load is the rotor winding. In the case of the ZEFAL generator, the rotor winding is split and it is desirable to be able to select to which point in the winding the pulse width modulated voltage should be applied, as shown in Figure 8. The PWM is generated by modulation switches S 1 and S2 which would typically be implemented as insulated gate bipolar transistors (IGBTs), Single pole double throw (SPDT) director switches S3 and S4 are used to select whether the full rotor winding is excited (winding portions rotor 1 and rotor 2 together) or just a part of the winding (rotor 1 only). This director switch functionality is achieved with inverter grade thyristors Thyl, Thy2, Thy5 and Thy6. In order to guarantee current continuity, "freewheel" thyristors Thy3 and Thy4 and "freewheel" anti-parallel diodes Dl and D2 are added. Thyristors Thy3 and Thy4 cannot be replaced with diodes because during partial tap mode voltages across rotor 2 may exceed the DC link voltage and any diodes would be forward biased, causing rotor 2 to be short-circuited.

When switched on, thyristors appear as a diode and when switched off they appear as an open circuit. They can be switched on by applying a gate current for sufficient time and then keeping the load current above a certain threshold called the holding current. Thyristors can only be switched off by removing the gate current AND by reversing or reducing their load current below the holding current for sufficient time to allow the charge in the junction to recombine. This process can be accelerated by applying a reverse voltage. Fast control of the thyristors is thus made possible as they are positioned in the PW load path where the IGBTs control the current flow rather than having to wait for the rotor current zero crossings which occur at twice the slip frequency. Inverter grade thyristors are required to avoid spurious commutations due to high dv/dt.

Switches S 1 and S2 generate the PWM voltage waveform determined by the control system. To excite the entire rotor winding (i.e. rotor 1 and rotor 2), thyristors Thyl, Thy2, Thy3 and Thy4 are switched ON and thyristors Thy5 and Thy6 are OFF. To apply the PWM waveform to only part of the rotor winding (i.e. rotor 1), thyristors Thyl, Thy2, Thy3 and Thy4 are OFF and thyristors Thy5 and Thy6 are ON. A tap change can be achieved by simply applying and removing the desired gate signals, however, this may lead to overvoltages due to the energy stored in the leakage inductance of rotor 2.

A tap change commutation exists that allows this energy to dissipate into the DC rails in order to prevent any voltage spikes from occurring. This commutation sequence will now be described for a tap change from full to partial tap and for a positive current, with reference to Figure 9. The equivalent components and commutation sequence for when the current is negative are indicated in parentheses.

1. Suspend PWM i.e. open IGBTs SI and S2. The load current continues

y to flow through Thy3 (Thy4) and slowly decays. A voltage of - - y

(- -^ ) is applied across the entire winding, so Dl and D2 are reverse biased and not conducting.

2. Change tap by removing gating signals from thyristors Th l-Thy4 and applying gating signals to thyristors Thy 5 and Thy6. Thy3 (Thy4) will remain in conduction until the current through it attempts to reverse regardless of the voltage across it or the gating signals applied to it. The gating signal from SI and S2 has been removed and because zero current is flowing through Thyl & Thy2 they will slowly turn off by natural recombination.

3. Briefly switch on SI (S2). This will put zero volts across rotor 2 and therefore across Thy2 (Thyl) and Thy6 (Thy 5). This will speed up the recombination process in Thy2 (Thyl) and ensure it is off. During this time, the current through rotor 1 and rotor 2 will decrease and increase proportionally.

4. Switch SI (S2) off again. The load current continues to flow through Thy3 (Thy4) but Thyl, Thy2 and Thy4 (Thy3) are off.

5. Switch on S2 (SI). Because Thy3 (Thy4) is conducting, the full DC link voltage is applied across rotor 2 and opposes the flow of current. The current through the leakage inductance of rotor 2 decreases and as it hits zero, Thy3 (Thy4) drops out of conduction. Simultaneously, the current in rotor 1 increases as it is transferred from rotor 2 through the mutual inductance.

6. Once Thy3 (Thy4) has dropped out of conduction, the tap change is complete and PWM can be resumed. The duration of the process depends on how fast the current through the rotor 2 leakage inductance can be ramped down.

The tap up commutation sequence is more straightforward as no abrupt changes in current can occur and any overvoltages are thus prevented. The commutation can be completed by just applying a gate signal to thyristors Thyl-Thy4 and removing the gate signals from thyristors Thy5 and Thy6. The current will automatically start transferring from winding 1 to winding 2 until the currents in both windings are equal. PWM can be continued. However, switches SI and S2 can be used to apply the DC link voltage across the windings in such a way as to speed up the current transfer as follows:

1. Sample the polarity of the current I₍ in winding 1.

a. If I, > 0 then switch SI OFF and S2 ON.

b. If I, < 0 then switch SI ON and S2 OFF.

2. Remove gating signals from thyristors Thy5 and Thy6 and apply gating signals to thyristors Thy 1 -Thy4. Current will start to transfer at the maximum possible rate until I_t = I₂, where I₂ is the current in winding 2.

3. When I_\ = I₂, depending on the current polarity, either diode D 1 or D2 will cease conduction and PWM modulation can be resumed.

3.3 Control system

The ZEFAL generator model has been implemented in the synchronously rotating reference frame in Matlab Simulink to study its behaviour under fault conditions. The GSC is controlled as an active rectifier using stator voltage oriented unity power factor control in the synchronous reference frame, regulating the DC-link voltage and the reactive output power. The MSC controller structure consists of a fast inner rotor current control loop, and a slow outer speed control loop as shown in Figure 10. The MSC controller is implemented in a rotating reference frame synchronised to the rotor currents i.e. the slip frequency. Although Figure 10 depicts a speed control loop (as used in the prototype version), depending on the application this can be replaced with a torque control loop. The generator synchronisation module aligns the stator voltage with the synchronously rotating reference frame q-axis. This entails that the quadrature rotor current component can be used for speed control. The direct component is set to zero even though it could be used to regulate the reactive power output. During normal operation the generator operates under speed or torque control. When a fault occurs, the fault detection module will send a signal to the tapchanger to change tap and at the same time change the rotor current reference to zero. The MSC will now apply a voltage across a part of the rotor winding so as to reduce the rotor current to zero. This will result in the current in the mutual inductance of the stator being reduced to zero. The current in the stator leakage inductance will slowly dissipate through the winding resistance and is much less than the nominal current.

This control system relies on the fact that fundamental positive sequence variables are transformed to DC values which can be controlled using PI (proportional-integral) controllers. Any unbalance present in the form of negative sequence is transformed to double harmonics and cannot be suppressed completely by the PI controllers, resulting in a non-zero steady- state error. A solution to this problem is the use of decoupled dual reference frame control for both negative and positive sequence components.

3.4 Fault detection and recovery

The decision to change tap and ramp the rotor currents down to zero is taken by the fault detection and recovery module. The ZEFAL generator's success in suppressing any fault current relies on the speed of response of this module. The fault current reaches its peak value in a quarter of a grid cycle (5ms), and thus it is key that the fault is detected before this occurs. A fault is characterised by a drop in the utility voltage positive sequence magnitude. Conversely, the objective of ZEFAL is to limit the generator fault current output. Therefore, two fault detection techniques have been implemented, comparing the stator voltage magnitude and the stator currents to pre-set thresholds. Filters are used to prevent noise on voltage or current measurements from tripping the generator. After the fault has occurred, the generator needs to decide whether to stay online or disconnect from the grid. It does so by continuously sampling the stator voltage magnitude and comparing it to the fault ride through voltage profile that is provided by the relevant distribution network operator as shown in Figure 1 1. As long as the stator voltage is above the line, the generator stays connected. It is even possible to denote regions such as when the voltage magnitude is less than 75% in which the generator can provide a limited form of grid support.

If at any point the stator voltage has recovered above a pre-set threshold for more than a user definable number of grid cycles (5 in the prototype machine), the generator will issue a command to tap up again and resume power export. It is important that some hysteresis exists between the threshold for fault detection and recovery to prevent the system from going into some limit cycle when the voltage magnitude is equal to this threshold. Upon the decision of resuming power export, the power references should be increased gradually to prevent the fault detection from tripping on over-currents. It must be noted that during unbalanced faults, the positive sequence voltage magnitude may recover to such a level that the ZEFAL generator decides to resume power export, even though the fault may still be present. The resulting negative sequence component causes high rotor currents which are capable of tripping the fault detection. Decoupled control of positive and negative sequence rotor currents should prevent this issue from occurring.

3.5 Prime mover

During normal operation, the prime mover and ZEFAL generator will operate in torque and speed control, respectively or vice versa. The generator is operated such that its electrical torque T_E matches the mechanical torque T_M of the prime mover. However, during a fault, the rotor currents are regulated to zero and from equation (9) it follows that the electrical torque collapses. Neglecting friction and shaft stiffness, the speed of the prime mover is given by:

T^~£LT^~~^T ^{= Tm ~ Te (l9)}

Since the prime mover dynamic response is likely to be slow, T_M will be nonzero and the shaft will be speeding up. The rate at which it speeds up depends on its inertia J = JQFIG ⁺ JPM and the magnitude of T_M. At this point speed control can no longer be performed by the ZEFAL generator and relies on external devices. The ZEFAL generator can resume power operation at any speed within the operating speed range determined by the ratings of the MSC. Therefore, if the shaft speed exceeds this upper limit, an over-speed trip will be issued. The prime mover governor should therefore be designed such that it can act fast enough to prevent this from happening. By adding more mechanical inertia in the form of a flywheel, the acceleration can be decreased, or alternatively energy can be dumped in a resistive load. As an option of last resort, a mechanical brake can be fitted to extract some of the energy from the shaft. Any heat generated during a brake action could potentially be recovered for use in heat-integrated CHP installations.

3.6 The complete system

We propose the circuit symbol shown in Figure 12 for use in schematics. It shows a the common DC/AC power converter symbol with two alternative AC power connections representing the two AC tap connections. The DFIG symbol also shows two tap connections on the rotor winding.

I 4. Application to static systems

The ZEFAL principle has been described in terms of limiting fault current from a rotating machine which is of the two- winding (doubly-fed) format. Another application of the same principle applies to power converters coupled into electricity networks via transformers. An example is a power flow controller between two bus bars as illustrated in Figure 13. The DC/AC power converter can be used to create an AC voltage applied to a transformer. The other winding of the transformer is connected in series between two bus bars. Thus a small voltage difference is placed between the bus bars and this can be used to set the real and reactive power transfer between the bus bars (given a particular impedance between the bus bars).

In the event of a fault depressing the voltage of one bus bar a potentially large current would flow between the bus bars. To prevent this, the ZEFAL Power Converter would effect a tap change and apply its voltage at a different turns ratio and thus create a voltage between the bus bars sufficient to control the fault current to zero (or some other value).

In normal operation, the control of real and reactive power between the bus bars may require the ZEFAL Power Converter to provide (or to sink) some real power itself. This is accommodated in the normal way by providing a second power converter with a shunt connected transformer, as illustrated in Figure 14.

5. Simulation and experimental results

In order to verify the concepts introduced in the previous sections, prototype versions were built of the split rotor winding DFIG and a single phase version of the proposed tapchanger/inverter. 5.1 Split rotor doubly fed induction generator

To test the hypothesis of fault current control using a split winding DFIG, an existing DFIG was modified. An extra set of slip rings was fitted to the rotor and taps were inserted in the rotor winding at 20% intervals. An existing six leg inverter was modified with a bidirectional switch to provide the functionality of the tap changer. Build up of excessive voltages across the bidirectional switch due to the leakage inductance is prevented by connecting a varistor in parallel. A single phase circuit diagram is shown in Figure 15. IGBTs S I and S2 are used to apply a PWM voltage waveform in full tap mode in which bidirectional switch Tl is switched on. In order to change tap to partial tap mode, S I and S2 are switched off, bidirectional switch Tl is switched off but remains conducting until the current through it hits zero. This allows the current through the leakage inductance to dissipate through one of SI or S2's anti-parallel body diodes. IGBTs S3 and S4 are used to apply a PWM voltage waveform to a part of the rotor winding.

An experimental set-up to re-create a 'realistic' voltage dip has been built as shown schematically in Figure 16. A synchronous generator is used to create a grid. A series combination of a reactance L2 and a DFIG has been used to recreate a 'fault' . The depth of the fault is determined by L2 and the DFIG can be used to control the duration of the fault and the rate of recovery of the terminal voltage in order to recreate a voltage profile as shown in Figure 1 1. Reactance LI is used to limit the fault current delivered by the synchronous machine. The ZEFAL generator is connected in parallel with the fault so that its fault response can be tested.

The ZEFAL generator is operated at full tap under rotor current control with J_r = (0 + j20)A at a fixed speed of 1440 rpm. At time t=0s, a voltage dip of 75% is applied to the stator terminals. The ZEFAL generator control system is set up in such a way that at t=0.2s a tap change command is issued to switch to the n = y_s tap, and at t=0.4s the rotor current reference magnitude is changed to

|Γ_Γ| = 0 . For comparison, a simulation model has been created in SimPower S stems using parameters of the prototype machine as listed in Table 3.

Parameter Symbol Value Unit

Nominal Complex s_n 7.5 kVA

Power

Nominal Voltage v_n 380 V

Number of pole pairs ⁿpp 2

Stator winding resistance 0.3785 Ω

Rotor winding resistance Rr 0.3873 Ω

Stator leakage Lis 0.0082 H

inductance

Rotor leakage inductance L\_r 0.0070 H

Magnetising inductance 0.0880 H

Shaft moment of inertia JDF/G 0.0900 kg m²

Table 3: Prototype machine parameters The simulation and experimental results have been put side to side in Figure 17 showing the direct rotor current and reference, the quadrature rotor current and reference, direct and quadrature rotor voltages, stator voltage magnitude and the three phase stator currents. The voltage generated by the synchronous generator was slightly unbalanced and distorted. This is not shown in the experimental voltage magnitude plot as it has been filtered in the controller. To show the impact of unbalance on generator operation, the simulation model has been fed with a slightly unbalanced voltage phasor with phase voltage magnitudes of 1, 0.9 and 0.95 pu, respectively. Also, to reflect the fact that the voltage drop in the experimental set-up is not instantaneous, the simulated voltage drop is generated through a 200Hz low pass filter. Moreover, the fault current limiting reactance LI causes a voltage drop such that the ZEFAL generator terminal voltage is less than lpu. This has been replicated in the SimPowerSy stems model.

For illustrative purposes, the occurrence of the fault, the tap change, and the reference change have all been separated by 0.2s intervals. In a real ZEFAL generator, the current reference magnitude would be dropped to zero together at the same time as changing tap as soon as the fault is detected by the fault detection module.

The simulation and experimental results are very similar yet some distinct differences can be noted. Firstly, the stator current can be compared with the 200Vdc plot in Figure 6. It shows an initial rise in fault current as the rotor voltage limits and can't contain the rate of rise in stator current. A corresponding exponentially decaying peak in rotor current can be observed. Gradually, the rotor voltage comes back to within the limits set by the DC link voltage and the controller is capable of controlling the rotor currents again, although the synchronous reference frame controllers are incapable of suppressing the unbalance present in the stator voltage. The stator current magnitude returns to its pre-fault value, although a distinct unbalance can be noted. This is due to the flux remaining in the stator leakage inductance which is stationary (DC) and slowly decays. The decay appears to be faster in the experimental results. This is probably due to the increased resistance in the experimental set-up. At t = 0.2s the generator changes tap. Immediately, the rotor voltage magnitude required to track the rotor current reference drops by 60%. It also shows that the current ripple due to unbalance decreases in magnitude. At the same time, the stator current magnitude drops proportionally due to the transformer effect i.e. the changed stator-rotor turns ratio.

At t = 0.4s the rotor current reference magnitude is dropped to zero. The controller can successfully track the reference without exceeding the DC link voltage for a sustained period of time. Because the voltage drop is less than 100%, a stator current continues to flow in addition to the remaining decaying DC flux in the leakage inductance. To prevent this from coupling into the rotor, the controller needs to continue to apply a rotor voltage. It is possible to apply a rotor voltage such as to reduce the stator currents to zero. This is most easily achieved with stator current feedback instead of rotor current feedback.

The most notable difference between the simulation and experimental results is the absence of a high exponentially decaying rotor fault current and the presence of a large ripple. Possibly the rotor fault current is subdued somewhat by resistance in the sliprings and leads. The oscillations could be caused by a resonance between the ZEFAL generator, synchronous generator and/or fault DFIG or by the unbalance in the stator voltage, a difference in controller parameters and an inability to suppress them. Lower bandwidth controllers are less capable of suppressing this type of ripple. Further simulations will show whether or not the differences between simulation and experimental results can be attributed to experimental set-up parasitics.

It must be noted that these results have been obtained at a small generator slip speed. The larger the slip speed, the higher the voltage magnitude required to change the rotor currents due to the increased rotor reactance. The tap setting should be chosen such that fault current suppression can be performed successfully at either end of the generator speed range.

5.2 Inverter / tap changer simulation results

To verify the operation of the proposed tapchanger, the circuit of Figure 8 has been simulated using SimPower Systems using the parameters detailed in Table 4. A mutual inductor is used to replace the rotor magnetic circuit. The commutation sequence proposed in section 3.2 above is used to ensure that the energy stored in the winding 2 leakage inductance dissipates in the DC link rather than in the parasitic or snubber capacitances where it would lead to overvoltages.

Parameter Symbol Value Unit

DC link voltage VDC 100 V

Winding 1 resistance RJ 0.01 Ω

Winding 2 resistance R₂ 0.03 Ω

Winding 1 inductance 2 mH

Winding 2 inductance 6 mti

Coupling factor K 0.9

Table 4: Single phase tap changer parameters The switches S I and S2 are used to generate a PWM voltage waveform with a switching frequency of 5kHz. The duty cycle of SI and S2 is set to generate a positive current at full tap, i.e. thyristors Thyl-Thy4 are on and thyristors Thy5-Thy6 are off. A tap change sequence is initiated and the voltages across and currents through the separate windings have been shown in Figure 18. The numbers corresponding to the various steps in the proposed commutation sequence have been shown along the time axis for clarity.

I At t = 1, the sequence is started with suspending the PWM by opening SI and S2. Current continues to flow through Thy 3 and applies half the DC link voltage across the entire winding. The winding acts as a potential divider, so the voltage across both windings adds up to 50V.

At t = 2, the appropriate thyristor gating signals are applied to ensure that on the next current zero crossing, Thyl-Thy4 are off and Thy5-Thy6 are on. Since SI and S2 are still off, Dl and D2 remain reverse biased and the current continues to flow.

To ensure that Thyl and Thy 2 are off, S I is switched on at t = 3. This applies 0V across winding 2 since Thy3, Thy5 and S I are conducting. This forward biases Dl, and current starts to be transferred from winding 2 to winding 1. At t = 4, SI is switched off again. The difference in current between both windings now freewheels back into the DC rails until they are equal, at which point Dl drops out of conduction and Thy3 bears all the current.

Having ensured Thyl and Thy2 are off, S2 switches on at t = 5 applying the full DC link voltage negatively across winding 2 whilst applying half the DC link voltage positively across winding 1. This transfers the current from winding 2 to winding 1 in the fastest possible way. The rate of current transfer is only limited by the leakage inductance of winding 2 and the DC link voltage. At t = 6, all current in winding 2 has been transferred to winding 1 and thyristor 3 drops out of conduction. At this point the tap change is complete and PWM is resumed. Figure 19 shows the voltages across and currents through winding 1 and 2, respectively, for a tap change up. At t = 1, the tap change command is received. Because the load current is positive, switch S2 is switched on and SI is switched off, applying half the DC link voltage across winding 1. Because winding 2 is still open-circuited, the voltage across it is a reflection of the voltage across winding 1 and zero current flows through it, The current through winding i flows through D 1.

At t = 2, thyristors Thyl-Thy4 are switched on and thyristors Thy5 and Thy6 are switched off. Thyristor Thy3 now begins to pick up load current and because S2 is on, the full DC link voltage is applied across winding 2. Current is being transferred from winding 1 to winding 2.

At t = 3, the current in winding 1 and 2 are equal and diodes Dl and D2 drop out of conduction. At this point the tap change is complete and PWM can be resumed.

5.3 Inverter / tap changer experimental results

A single phase version of the tap changer/inverter as shown in Figure 20 (single phase tap changer/inverter prototype circuit) was built and tested. RC snubbers have been added to thyristors Thy 3 and Thy4 and to the IGBTs. The IGBT snubbers limit any over voltages due to stray inductance between the IGBT and the winding terminals, whereas the thyristor snubbers limit the overvoltage due to the thyristor reverse recovery current. The semiconductor components used in this experiment are listed in Table 5. Component Manufacturer Part No.

Thyristors 1,2,5 & 6 Semikron S T106B08

Thyristors 3 & 4 ON Semiconductor 2N6509

Diodes Dl & D2 ST Microelectronics STPSC1006D (SiC) IGBTs S l & S2 IXYS IXEN60N120D1

Table 5: Semiconductors used in experimental set-up

Rectifier grade thyristors were used for Th l-Thy6 as no inverter grade thyristors could be found with suitable ratings for a benchtop experimental • setup. The drawback is that rectifier grade thyristors have been designed for line frequency applications and hold a large stored charge when they are on. This translates into a large peak reverse recovery current when they are switched off fast, as is the case due to the high frequency PWM modulation. The thyristor snubbers are required to dissipate the energy stored in the winding leakage inductance due to this reverse recovery current. Without snubbers, this inductive energy would be pushed into stray and junction capacitances and cause potentially damaging over voltages. Furthermore, the experimental results suggest that steps 3 and 4 in the commutation process described in section 3.2, are not strictly necessary as long as a sufficiently long wait exists between steps 2 and 5, to ensure all carriers have been removed from the thyristor junctions by natural recombination. In the experiment, the IGBTs are given a sinusoidal voltage PWM reference, with a switching frequency of 10kHz and a dead time of 1μ$. A DC link voltage of 30V was maintained by a variac feeding a diode rectifier bridge with a total DC link capacitance of 3.8mF. Diodes Dl and D2 were silicon carbide diodes with virtually no reverse recovery current, and hence do not require any snubbers.

Figures 21 to 24 show measurement results for a tap down at positive load current, a tap up at positive load current, a tap down at negative load current, and a tap up at negative load current, respectively. The top plot of each figure shows winding voltages 1 (solid black) and 2 (dashed black) and each bottom plot shows the winding currents 1 (solid black) and 2 (dashed black). It can be seen that the proposed tap changer/inverter can provide voltage synthesis via pulse width modulation and change tap whilst successfully preventing voltage spikes due to any leakage inductance in the windings and reverse recovery currents. The square wave like ripple that can be observed on the current waveforms during partial tap mode is due to the thyristor capacitors charging and discharging. The magnitude of this ripple can be reduced by increasing the thyristor snubber resistance or decreasing its capacitance.

The circuit works well, although it appears that the speed of change of tap is dominated by the turn off time of the thyristors rather than the time it takes to transfer the load current. In future versions, an effort should be made to find inverter grade thyristors or rectifier grade thyristors with low stored charge.

5. Other potential applications

It has been noted that the ZEFAL concept is in essence applicable to any application where an inverter is used to drive a rotating magnetic field. For example, a power flow controller essentially consists of a DC link capacitor, connected to the network via an inverter and a transformer. In this application, too, the ZEFAL concept can be used to achieve fault current limiting. Figure 13 shows a power flow controller coupling two bus bars in a substation. During normal operation it could inject reactive power to assist in voltage control. With the ZEFAL technology, it could prevent any fault current from flowing from one bus bar to the other bus bar with a partially rated inverter in much the same way as in the case of the DFIG application.

The same can be done for a similar layout but now including a shunt transformer to feed the DC link as was shown in Figure 14. This layout allows for the control of both real and reactive power by injecting and absorbing reactive power. It can be inserted in series in a transmission line to improve its capacity or support network stability. Equipped with the ZEFAL technology it is also capable of blocking fault current by creating a series voltage that is identical to the voltage of the healthy feeding part of the network.

6. Conclusion

A modification to doubly fed induction generator design has been proposed to allow for zero fault current fault ride through operation without substantially increasing the DC link steady-state ratings and exploiting its i^'t or pulsed current rating. The fast control of stator current required for zero fault current operation is achieved by using a tap changer to increase the effective rotor volts-per-turn ratio. A figure of merit for the generator would be the peak stator fault current after a fault. In case of the ZEFAL generator this peak fault current relies heavily on the speed of fault detection. After a fault has been detected, the control system changes tap and decreases the rotor (or alternatively stator) current reference to zero. By comparing the stator voltage magnitude with the required fault ride through voltage profile, the control system decides whether to disconnect, or to resume power export. Simulation and experimental results confirm that the system is indeed capable of suppressing the stator fault current with a DC link that has a fraction of the nominal rating by subjecting it to a 3 phase 75% (25% of voltage left during fault) balanced voltage dip of approximately one second.

A thyristor based machine side inverter has been proposed that can achieve the desired tap change and synthesize the desired rotor voltage. Thyristors are robust and typically exhibit high current ratings at comparatively low cost. Prohibitively high voltage ratings are avoided by using a commutation sequence that dissipates the energy stored in the leakage inductance of winding 2 into the DC link rather than into parasitic capacitive elements whilst at the same time guaranteeing the fastest possible current transfer. Simulation results show that the proposed commutation sequence indeed avoids any over voltages and confirms the expected behaviour of current transfer during a tap change. Measurements from an experimental prototype confirm the expected operation of the tap changer.

Although the concept of a split winding magnetic component and a power electronic tap changer / inverter has been introduced here as an enhancement to the already existing DFIG concept, it can be extended to various other technologies such as Unified Power Flow Controllers and Series Compensators.

7. Summary of further features and advantages

The present disclosure provides inter alia the following further features and advantages:

• A tapped winding on a transformer used to couple a partially rated power converter (series element of a Unified Power Flow Controller for instance). These suffer the same basic problem as the DFIM in that the partially rated converter is beneficial in normal use but is unable to control current during a fault situation.

A doubly-fed induction machine (DFIM) with a power converter connected to one winding in which one winding is equipped with taps such that the turns ratio between the rotor and stator windings can be changed such that the voltage supplied by the power converter is sufficient to exercise current control even when the voltage on the other winding is temporarily reduced.

A power converter comprising semiconductor switching means able to connect each phase winding to the negative or positive pole of a DC voltage source (the modulation switches) and several additional semiconductor switching means that are arranged to direct the applied voltage to one or other of the available taps of the tapped winding (the director switches).

A power converter as above, in which the director switches are thyristor devices.

A power converter as above, in which additional semiconductor switching means are provided in parallel with the modulation switches and these additional switches are arranged to provide additional current handling capability.

A power converter as above, in which the additional semiconductor switching means is a device with turn-off commutation ability but chosen for a larger current capability than the modulating switches and low switching frequency. A power converter as above, in which the additional switching means is a gate-turn-off thyristor or an integrated-gate commutated thyristor.

A system comprising a doubly fed induction machine and a power converter as above, and a means of detecting either an over-current or under-voltage event and a controller which can coordinate a tap down operation in the event that fault current needs to be controlled, and thereby apply sufficient voltage to the windings to exercise current control.

A method of operating a doubly-fed induction machine in which the turns ratio between stator and rotor is changed by means of a tap selection mechanism when the voltage on one winding is temporarily reduced such that the voltage available to be imposed on the other winding is sufficient to control the current by overcoming the induced voltage caused by the magnetising flux.

A method of operating a power converter in which the modulating switches, during a tap down operation, are turned off and the director switches are operated in an appropriate sequence to drive the current down to zero in the outgoing winding section (note also the proper handling of stored energy in leakage field).

A method of operating a power converter as above, with an additional semiconductor switch in parallel with the modulating switch, in which the additional switch is switched on in preference to the modulating switching during the tap down operating and is only required to commutate off once during each tap-down operation. Appendix I Split rotor doubly fed induction generator model

To determine how the parameters of the rotor winding parts can be found from the parameters given for the entire winding in Table 3, the effect of splitting an inductor with N turns into two parts with N_\ and N-i turns, respectively, is considered as shown in Figure 25.

A realistic inductor wound on a magnetic core typically exhibits winding resistance V, leakage inductance '£_/' and magnetising inductance ⁴Z,_W\ Its magnetising inductance can be found using equation (12). Now consider the

N

winding to be split into two sections as described above, such that n ¹— .

^{5 y} N, + N₂

Then, since winding resistance varies linearly with winding length and thus number of turns, the winding resistances of the two resulting windings are given as a function of r and n by:

r, = « -r (20) r₂ = (! -«) · r (21)

Since the leakage inductance by definition does not exhibit any magnetic coupling with the coil itself, it is reasonable to assume that it can also be split proportionally to the number of winding turns:

L_{a ^} n -l (22)

L_l2 = (\ - n) - L, (23)

Substituting N = N_l + N₂ - nN + (\ - n)N into equation (12), it can be seen how the magnetising inductance is split:

1 rl π

rl π

R 4 (24)

[n² + 2n(l - n) + (l -

Rearranging, it can be seen that the magnetising inductances are composed of a self inductance and a mutual inductance:

L_mX = [n² ₊ n(\ - n)]L_m (25)

Applying these rules to the three phase model of a doubly fed induction machine described by equations (13)-(15), the three phase resistance and inductance matrices can be found. The resistance matrices are:

Assuming imperfect stator-rotor coupling and perfect rotor-rotor coupling, the self inductance matrices are:

and the mutual inductance matrices are:

I ΗΓ2 - ~

I

Claims

An electrical device comprising:

first and second windings that are magnetically coupled such that, during normal operation, magnetic fields of the first and second windings interact and currents flow through the first and second windings; and

a power controller arranged to control the current in the second winding in a fault situation, so as to reduce or limit the current magnitude flowing in the first winding or the second winding, or to synchronise the magnetic field of the second winding with the magnetic field of the first winding and thereby reduce their interaction;

wherein the second winding incorporates a tap changer arrangement operable to reduce the number of turns in the second winding through which the current in the second winding flows, and thereby decrease the mutual inductance between the first and second windings and reduce the voltage magnitude required of the power controller in order to exercise control in the fault situation.

An electrical device as claimed in Claim 1, being a rotating machine comprising a stator and a rotor.

An electrical device as claimed in Claim 2, being a generator;

wherein the current flowing through the first winding is the output current from the generator.

4. An electrical device as claimed in Claim 3, wherein the first winding is incorporated in the stator and the second winding is incorporated in the rotor. An electrical device as claimed in Claim 4, being a doubly fed induction generator;

wherein the power controller comprises a machine side converter.

An electrical device as claimed in Claim 5, wherein the machine side converter provides pulse width modulation, dynamically adjusting the pulse width of a fixed frequency voltage pulse train and applying the pulses to the second winding.

An electrical device as claimed in Claim 6, wherein the machine side converter is connected to a DC link, the voltage of which is regulated by a grid side converter.

An electrical device as claimed in Claim 2, being a motor;

wherein the current flowing through the first winding is the input current powering the motor.

An electrical device as claimed in Claim 1 , wherein the first and second windings are static relative to each other.

An electrical device as claimed in Claim 9, wherein the first winding is arranged to couple a first electrical distribution arrangement in series with a second electrical distribution arrangement, for example in an electrical substation, distribution board or transmission line. 1. An electrical device as claimed in any preceding claim, wherein the power controller and tap changer arrangement together comprise semiconductor switching means.

12. An electrical device as claimed in Claim 1 1, wherein the power controller and tap changer arrangement together comprise modulation switches and director switches.

13. An electrical device as claimed in Claim 12, wherein the modulation switches comprise transistors, for example insulated gate bipolar transistors.

An electrical device as claimed in Claim 12 or Claim 13, wherein the director switches comprise thyristors.

An electrical device as claimed in Claim 14 wherein, in the tap changer arrangement:

first and second thyristors (Thyl and Thy 5) are arranged to direct the current in the second winding when a first modulation switch transistor (SI) is switched on and conducting, the first and second thyristors (Thyl and Thy5) being respectively connected to first and second tap positions on the second winding, the first tap position providing conduction along more of the second winding than the second tap position; and

third and fourth thyristors (Thy2 and Thy6) are arranged to direct the current in the second winding when a second modulation switch transistor (S2) is switched on and conducting, the third and fourth thyristors (Thy2 and Thy6) being respectively connected to the said first and second tap positions on the second winding.

An electrical device as claimed in Claim 15, wherein the tap changer arrangement further comprises further semiconductor devices each connected in parallel across a modulation switch transistor and a respective one of the thyristors connected thereto, arranged such as to carry winding current that would flow against the normal conduction direction of the first modulation switch transistor (SI) and the first and second thyristors (Thyl and Thy5), or the second modulation switch transistor (S2) and the third and fourth thyristors (Thy 2 and Thy6).

An electrical device as claimed in Claim 16, wherein the further semiconductor devices comprise:

a first freewheel thyristor (Thy3), reverse-connected relative to the director switch thyristors and connected across the first modulation switch transistor (SI) and the first director switch thyristor (Thyl) to the first tap position on the second winding;

a first freewheel diode (Dl), reverse-connected relative to the director switch thyristors and connected across the first modulation switch transistor (SI) and the second director switch thyristor (Thy 5) to the second tap position on the second winding;

a second freewheel thyristor (Thy4), reverse-connected relative to the director switch thyristors and connected across the second modulation switch transistor (S2) and the third director switch thyristor (Thy2) to the first tap position on the second winding; and

a second freewheel diode (D2), reverse-connected relative to the director switch thyristors and connected across the second modulation switch transistor (S2) and the fourth director switch thyristor (Thy6) to the second tap position on the second winding.

An electrical device as claimed in any preceding claim, further comprising a fault detection module arranged to compare the current and/or voltage in the first or second winding to a threshold value and, in the event that the threshold value is exceeded, to initiate operation of the power controller and tap changer arrangement.

A method of operating an electrical device, the device comprising first and second windings that are magnetically coupled such that, during normal operation, magnetic fields of the first and second windings interact and currents flow through the first and second windings;

wherein the method comprises, in a fault situation, controlling the current in the second winding, so as to reduce or limit the current magnitude flowing in the first winding or the second winding, or to synchronise the magnetic field of the second winding with the magnetic field of the first winding and thereby reduce their interaction; and

operating a tap changer arrangement incorporated in the second winding, to reduce the number of turns in the second winding through which the current in the second winding flows, and thereby decrease the mutual inductance between the first and second windings in the fault situation.

A method as claimed in Claim 19, wherein the electrical device is a rotating machine comprising a stator and a rotor.

A method as claimed in Claim 20, wherein the electrical device is a generator;

and wherein the current flowing through the first winding is the output current from the generator.

22. A method as claimed in Claim 20, wherein the electrical device is a motor; and wherein the current flowing through the first winding is the input current powering the motor.

23. A method as claimed in claimed in Claim 19, wherein the first and second windings are static relative to each other.

24. A method as claimed in any of claims 19 to 23, wherein the tap changer arrangement comprises semiconductor switching means. 25. A method as claimed in Claim 24, wherein the tap changer arrangement comprises modulation switches and director switches.

26. A method as claimed in Claim 25, wherein the modulation switches comprise transistors, for example insulated gate bipolar transistors.

27. A method as claimed in Claim 25 or Claim 26, wherein the director switches comprise thyristors.

28. A method as claimed in Claim 27 wherein, in the tap changer arrangement:

first and second thyristors (Thyl and Thy 5) direct the current in the second winding when a first modulation switch transistor (SI) is switched on and conducting, the first and second thyristors (Thyl and Thy5) being respectively connected to first and second tap positions on the second winding, the first tap position providing conduction along more of the second winding than the second tap position; and

third and fourth thyristors (Thy2 and Thy6) direct the current in the second winding when a second modulation switch transistor (S2) is switched on and conducting, the third and fourth thyristors (Thy2 and Thy6) being respectively connected to the said first and second tap positions on the second winding.

A method as claimed in Claim 28, wherein the tap changer arrangement further comprises further semiconductor devices each connected in parallel across a modulation switch transistor and a respective one of the thyristors connected thereto, arranged such as to carry winding current that would flow against the normal conduction direction of the first modulation switch transistor (SI) and the first and second thyristors (Thyl and Thy5), or the second modulation switch transistor (S2) and the third and fourth thyristors (Thy2 and Thy 6).

A method as claimed in Claim 29, wherein the further semiconductor devices comprise:

a first freewheel thyristor (Thy3), reverse-connected relative to the director switch thyristors and connected across the first modulation switch transistor (SI) and the first director switch thyristor (Thyl) to the first tap position on the second winding;

a first freewheel diode (Dl), reverse-connected relative to the director switch thyristors and connected across the first modulation switch transistor (SI) and the second director switch thyristor (Thy5) to the second tap position on the second winding;

a second freewheel thyristor (Thy4), reverse-connected relative to the director switch thyristors and connected across the second modulation switch transistor (S2) and the third director switch thyristor (Thy2) to the first tap position on the second winding; and

a second freewheel diode (D2), reverse-connected relative to the director switch thyristors and connected across the second modulation switch transistor (S2) and the fourth director switch thyristor (Thy6) to the second tap position on the second winding.

A method as claimed in Claim 30 wherein, in normal operation, current in the second winding flows via the first tap position;

and wherein, in the event of a fault, in order to perform a tap- down operation to cause the current in the second winding to flow via the second tap position and not the first, the method comprises the commutation steps of:

(1) opening the first and second modulation switch transistors (SI and S2) such that the current in the second winding flows through the first or second freewheel thyristor (Thy3 or Thy4) depending on whether the current is positive or negative;

(2) changing the tap by applying gating signals to the second and fourth thyristors (Thy5 and Thy6) and by removing gating signals from the first and third thyristors (Thyl and Thy2) and the first and second freewheel thyristors (Thy 3 and Thy4), with the first or second freewheel thyristor (Thy3 or Thy4) remaining in conduction;

(3) closing the second modulation switch transistor (S2) if the winding current is positive in order to provide a preferred current path through the first freewheel thyristor (Thy3), or closing the first modulation switch transistor (S I) if the winding current is negative in order to provide a preferred current path through the second freewheel thyristor (Thy4); and

(4) allowing the first or second freewheel thyristor (Thy3 or Thy4) to cease conduction as the current through it attempts to reverse, such that the current in the second winding flows via the second tap position (via Thy5 or Thy6) and not the first tap position once normal modulation of the first and second modulation switch transistors (SI and S2) resumes. A method as claimed in Claim 31, further comprising an additional commutation step, after step (2) and before step (3), of:

briefly switching on the first or second modulation switch transistor (SI or S2), depending on whether the current is positive or negative, and then turning it off again.

A method as claimed in Claim 31 or Claim 32, further comprising performing a tap-up operation after the fault has cleared, so as to cause the current in the second winding to flow via the first tap position, the tap-up operation comprising applying gating signals to the first and third thyristors (Thyl and Thy2) and the first and second freewheel thyristors (Thy3 and Thy4), and removing the gating signals from the second and fourth thyristors (Thy 5 and Thy 6).

A method as claimed in Claim 33, wherein the tap-up operation further comprises:

sampling the polarity of the current in the conducting portion of the second winding;

if the current in the conducting portion of the second winding is positive, switching the first modulation switch transistor (SI) off and the second modulation switch transistor (S2) on;

if the current in the conducting portion of the second winding is negative, switching the first modulation switch transistor (SI) on and the second modulation switch transistor (S2) off; and then the said steps of: applying the gating signals to the first and third thyristors (Thyl and Thy2) and the first and second freewheel thyristors (Thy3 and Thy4); and removing the gating signals from the second and fourth thyristors (Thy5 and Thy6).

A method as claimed in any of claims 19 to 34, further comprising comparing the current and/or voltage in the first or second winding to a threshold value and, in the event that the threshold value is exceeded, controlling the current in the second winding and initiating operation of the tap changer arrangement.

A tap changer arrangement on a winding, comprising:

first and second director switch thyristors (Thyl and Thy5) arranged to direct current in the winding when a first modulation switch transistor (SI) is switched on and conducting, the first and second thyristors (Thyl and Thy5) being respectively connected to first and second tap positions on the winding, the first tap position providing conduction along more of the winding than the second tap position; and third and fourth director switch thyristors (Thy2 and Thy6) arranged to direct current in the winding when a second modulation switch transistor (S2) is switched on and conducting, the third and fourth thyristors (Thy2 and Thy6) being respectively connected to the said first and second tap positions on the winding;

wherein the director switch thyristors are connected to conduct in the same direction as their respective modulation devices;

and wherein the tap changer arrangement further comprises:

a first freewheel thyristor (Thy3), reverse-connected relative to the director switch thyristors and connected in parallel across the first modulation switch transistor (S I) and the first director switch thyristor (Thyl) to the first tap position on the winding; a first freewheel diode (Dl), reverse-connected relative to the director switch thyristors and connected in parallel across the first modulation switch transistor (SI) and the second director switch thyristor (Thy5) to the second tap position on the winding;

a second freewheel thyristor (Thy4), reverse-connected relative to the director switch thyristors and connected in parallel across the second modulation switch transistor (S2) and the third director switch thyristor (Thy2) to the first tap position on the winding; and

a second freewheel diode (D2), reverse-connected relative to the director switch thyristors and connected in parallel across the second modulation switch transistor (S2) and the fourth director switch thyristor (Thy6) to the second tap position on the winding.

37. A method of operating a tap changer arrangement, the tap changer arrangement being as claimed in Claim 36;

wherein, in a first operational state, current in the winding flows via the first tap position;

and wherein, in order to perform a tap-down operation to cause the current in the winding to flow via the second tap position and not the first, the method comprises the commutation steps of:

(1) opening the first and second modulation switch transistors (SI and S2) such that the current in the winding flows through the first or second freewheel thyristor (Thy3 or Thy4) depending on whether the current is positive or negative;

(2) changing the tap by applying gating signals to the second and fourth thyristors (Thy5 and Thy6) and by removing gating signals from the first and third thyristors (Thyl and Thy2) and the first and second freewheel thyristors (Thy3 and Thy4), with the first or second freewheel thyristor (Thy3 or Thy4) remaining in conduction; (3) closing the second modulation switch transistor (S2) if the winding current is positive in order to provide a preferred current path through the first freewheel thyristor (Thy3), or closing the first modulation switch transistor (S I) if the winding current is negative in order to provide a preferred current path through the second freewheel thyristor (Thy4); and

(4) allowing the first or second freewheel thyristor (Thy3 or Thy4) to cease conduction as the current through it attempts to reverse, such that the current in the winding flows via the second tap position (via Thy5 or Thy6) and not the first tap position once normal modulation of the first and second modulation switch transistors (S I and S2) resumes.

A method as claimed in Claim 37, further comprising an additional commutation step, after step (2) and before step (3), of:

briefly switching on the first or second modulation switch transistor (SI or S2), depending on whether the current is positive or negative, and then turning it off again.

A method as claimed in Claim 37 or Claim 38, further comprising performing a tap-up operation so as to cause the current in the second winding to flow via the first tap position, the tap-up operation comprising applying gating signals to the first and third thyristors (Thyl and Thy2) and the first and second freewheel thyristors (Thy3 and Thy4), and removing the gating signals from the second and fourth thyristors (Thy5 and Thy6).

A method as claimed in Claim 39, wherein the tap-up operation further comprises: sampling the polarity of the current in the conducting portion of the winding;

if the current in the conducting portion of the winding is positive, switching the first modulation switch transistor (S I) off and the second modulation switch transistor (S2) on;

if the current in the conducting portion of the winding is negative, switching the first modulation switch transistor (SI) on and the second modulation switch transistor (S2) off; and then the said steps of:

applying the gating signals to the first and third thyristors (Thyl and Thy2) and the first and second freewheel thyristors (Thy3 and Thy4); and

removing the gating signals from the second and fourth thyristors (Thy5 and Thy6).

An electrical device substantially as herein described with reference to and as illustrated in any combination of the accompanying drawings.

A method of operating an electrical device substantially as herein described with reference to and as illustrated in any combination of the accompanying drawings.

43. A tap changer arrangement on a winding substantially as herein described with reference to and as illustrated in any combination of the accompanying drawings.

44. A method of operating a tap changer arrangement substantially as herein described with reference to and as illustrated in any combination of the accompanying drawings.