WO2012087330A3 - Test, validation, and debug architecture - Google Patents

Test, validation, and debug architecture Download PDF

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Publication number
WO2012087330A3
WO2012087330A3 PCT/US2010/061995 US2010061995W WO2012087330A3 WO 2012087330 A3 WO2012087330 A3 WO 2012087330A3 US 2010061995 W US2010061995 W US 2010061995W WO 2012087330 A3 WO2012087330 A3 WO 2012087330A3
Authority
WO
WIPO (PCT)
Prior art keywords
test
architecture
debug
validation
access
Prior art date
Application number
PCT/US2010/061995
Other languages
French (fr)
Other versions
WO2012087330A2 (en
Inventor
Mark Trobough
Kreshavan TIRUVALLUR
Chinna Prudvi
Christian LOVIN
David Grawrock
Jay Nejedlo
Ashok Kabadi
Travis GOFF
Evan J. HALPRIN
Kapila UDAWATTA
Jiun Long FOO
Wee Hoo Cheah
Vui YONG
Selvakumar Raja GOPAL
Yen Tat LEE
Samie B SAMAAN
Kip KILLPACK
Niel DOBLER
Nagib Z. HAKIM
Michael T. White
Brian Meyer
Bill PENNER
John Baudrexl
Russ Wunderlich
Anthony Kozaczuk
James Grealish
Kyle Markley
Tim STOREY
Loren MCCONNELL
Lyle Cool
Mukesh Kataria
Rahima MOHAMMED
Tieyu Zheng
Amy XIA
Ridvan SAHA
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to US13/997,182 priority Critical patent/US10198333B2/en
Priority to JP2012549998A priority patent/JP5548966B2/en
Priority to CN201080035787.5A priority patent/CN103748562B/en
Priority to DE112010006087.8T priority patent/DE112010006087T5/en
Priority to KR1020137016196A priority patent/KR101581702B1/en
Priority to GB1122290.8A priority patent/GB2493793B/en
Priority to PCT/US2010/061995 priority patent/WO2012087330A2/en
Publication of WO2012087330A2 publication Critical patent/WO2012087330A2/en
Publication of WO2012087330A3 publication Critical patent/WO2012087330A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2733—Test interface between tester and unit under test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3636—Software debugging by tracing the execution of the program
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.
PCT/US2010/061995 2010-12-23 2010-12-23 Test, validation, and debug architecture WO2012087330A2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US13/997,182 US10198333B2 (en) 2010-12-23 2010-12-23 Test, validation, and debug architecture
JP2012549998A JP5548966B2 (en) 2010-12-23 2010-12-23 Test, verification and debug architecture apparatus and system
CN201080035787.5A CN103748562B (en) 2010-12-23 2010-12-23 Test, verifying and debugging framework
DE112010006087.8T DE112010006087T5 (en) 2010-12-23 2010-12-23 Architecture for testing, validation and debugging
KR1020137016196A KR101581702B1 (en) 2010-12-23 2010-12-23 Test, validation, and debug architecture
GB1122290.8A GB2493793B (en) 2010-12-23 2010-12-23 Test, validation, and debug architecture
PCT/US2010/061995 WO2012087330A2 (en) 2010-12-23 2010-12-23 Test, validation, and debug architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2010/061995 WO2012087330A2 (en) 2010-12-23 2010-12-23 Test, validation, and debug architecture

Publications (2)

Publication Number Publication Date
WO2012087330A2 WO2012087330A2 (en) 2012-06-28
WO2012087330A3 true WO2012087330A3 (en) 2013-06-13

Family

ID=45573022

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/061995 WO2012087330A2 (en) 2010-12-23 2010-12-23 Test, validation, and debug architecture

Country Status (7)

Country Link
US (1) US10198333B2 (en)
JP (1) JP5548966B2 (en)
KR (1) KR101581702B1 (en)
CN (1) CN103748562B (en)
DE (1) DE112010006087T5 (en)
GB (1) GB2493793B (en)
WO (1) WO2012087330A2 (en)

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Also Published As

Publication number Publication date
KR20130128424A (en) 2013-11-26
CN103748562A (en) 2014-04-23
KR101581702B1 (en) 2016-01-11
GB2493793B (en) 2020-07-08
WO2012087330A2 (en) 2012-06-28
GB201122290D0 (en) 2012-02-01
JP2013529321A (en) 2013-07-18
DE112010006087T5 (en) 2014-06-26
CN103748562B (en) 2019-03-29
JP5548966B2 (en) 2014-07-16
US10198333B2 (en) 2019-02-05
GB2493793A (en) 2013-02-20
US20150127983A1 (en) 2015-05-07

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