WO2012087106A1

WO2012087106A1 - A configurable multi - modulation baseband modulator of software defined radio using fpga

Info

Publication number: WO2012087106A1
Application number: PCT/MY2011/000091
Authority: WO
Inventors: Mohd Fadzil AIN; Yin Hui CHYE
Original assignee: Universiti Sains Malaysia
Priority date: 2010-12-24
Filing date: 2011-06-13
Publication date: 2012-06-28
Also published as: MY172751A

Abstract

The present invention relates to a configurable multi - modulation baseband modulator hereinafter referred as "MMBM" of software defined radio using FPGA. The present invention further relates to a means to extend single digital modulation. Single digital modulation of baseband modulator is extended to multiple digital amplitude and/or phase modulations that can be configured for various applications of software defined radio. The means comprise of modeling a configurable MMBM in digital signal processing basis, generating first hardware description language hereinafter referred as "HDL", designing second HDL, combining the first and second HDLs, synthesizing the combined HDL, implementing the synthesized HDL into FPGA, and measuring the results obtained in real time.

Description

A CONFIGURABLE MULTI - MODULATION BASEBAND MODULATOR OF

SOFTWARE DEFINED RADIO USING FPGA

FIELD OF THE INVENTION

The present invention relates to a configurable multi - modulation baseband modulator hereinafter also referred as "MMBM" of software defined radio hereinafter also referred as "SDR" using field programmable gate array hereinafter also referred as "FPGA". More particularly the present invention relates to a means to extend single digital modulation scheme of baseband modulator to multiple digital amplitude and/or phase modulation schemes that can be configured to best suited for various applications of SDR.

BACKGROUND OF THE INVENTION

Software radio hereinafter also referred as "SR" is a set of digital signal processing hereinafter also referred as "DSP" primitives, a meta level system for combining the DSP primitives into communications systems functions (transmitter, channel model, receiver) and a set of target processor on which SR is hosted for realtime communications. An ideal SR receiver begins processing of incoming signal right after the antenna. Similarly, an ideal SR transmitter is located just before antenna.

However, SR is not practical due to limitations of bandwidth and dynamic range constrained by analog-to-digital converter hereinafter also referred as "ADC" and digital-to-analog converter hereinafter also referred as "DAC". Therefore, a more practical version of SR called software defined radio or SDR has emerged that performs processing of bit-stream, baseband, and intermediate frequency hereinafter also referred as "IF" with ADC and DAC as closed to radio frequency hereinafter also referred as "RF" conversion as possible. However, the present invention only emphasizes on baseband processing part in SDR transmitter.

The commonly used processor devices for implementation of DSP-based SDR systems are general purpose processors hereinafter also referred as "GPPs", digital signal processors hereinafter also referred as "DSPs", application specific integrated circuits hereinafter also referred as "ASICs", and FPGAs. GPPs function with fully detenninistic execution time that are switched by operating systems hereinafter referred as "OS" using multi-threading concept, thus resulting in low speed, high power consumption, and high cost. Increase in the number of instructions for executing computationally-intensive functions in DSPs causes low data throughput and high power consumption. ASICs suffer from low flexibility, high cost and long design cycle for system upgrades.

All these problematic issues have made GPPs, DSPs, and ASICs difficult to be adapted in multi-function and multi-rate DSP systems. However, the emerging technology of FPGAs solves most of the problems by utilizing dynamically reconfiguration, and parallelism in pipelined structures to build DSP functions (primitives) such as multiply-accumulate hereinafter referred as "MAC", distributed arithmetic hereinafter also referred as "DA", Fast Fourier Transform hereinafter also referred as "FFT", from logic elements, look-up tables hereinafter also referred as "LUTs", multiplexers hereinafter also referred as "MUXs", flip-flops hereinafter also referred as "FFs", Random Access Memories hereinafter also referred as "RAMs", dedicated multipliers, and first-in-first-out hereinafter also referred as "FIFO".

Herein now would be described briefly some related prior art for better understanding of the present invention.

US 5,945,885 describes a digital baseband modulator having a flexible architecture that is readily adaptable to a variety of digital modulation types is provided. A symbol builder maps the input data to a series of modulation states corresponding to data symbols that are represented as state indexes. A pair of digital filters accepts the state indexes being generated by the symbol builder to provide both up-sampling and filtering functions. The digital filters are implemented using random access memory (RAM) to implement blocks of interpolating look-up multipliers which may be readily configured between fast, normal, and long modes. The filtered output data from the digital filters is provided to a resampler that converts the filtered output data to an output sample rate that corresponds to the sample rate of output DACs and corresponding analog low pass filters.

US 5,548,831 describes an FM receiver includes ah RF section, a first mixer stage for converting a desired RF reception signal into a first IF signal having a carrier frequency located on average at a first intermediate frequency, a first IF section for selecting the first IF signal, and a second mixer stage for converting the first IF signal into a second IF signal having a carrier frequency located on average at a second intermediate frequency. The second intermediate frequency is below the first intermediate frequency. A second IF section selects the second IF signal and is coupled to an FM demodulator for demodulating the baseband modulation signal of the desired RF reception signal, followed by a low-pass filter for selecting the baseband modulation signal. In order to enhance the signal processing of the FM receiver and to realize a receiver in a largely integrated form, to provide a substantially fully integrable IF stage which is easily exchangeable with the IF section of substantially all existing FM receivers of the superheterodyne type, and to realize a selectivity considerably greater than that of known IF filters, a third mixer stage is coupled between the second IF section and the FM demodulator for converting the second IF signal to a third IF signal having a carrier frequency located on average at a third intermediate frequency which is above the second intermediate frequency.

US2007/0190994 This prior art teaches a reconfigurable units each include a hardware circuit having one part of a radio procedure function and a reconfigurable circuit having another part of the radio procedure function. An extension interface unit includes a switch circuit having a changeable connection specification to interconnect the reconfigurable units. A memory unit stores logic information for changing logics of the reconfigurable circuits and the connection specification of the switch circuit. A control unit downloads into the memory unit the logic information supplied from outside of the software defined radio. Rewriting the logics of the reconfigurable circuits according to the logic information and switching connection information of the switch circuit makes it possible to realize an optimum logic circuit in compliance with a radio communication to be used. In other words, it is possible to improve the scalability of the radio procedure function of the software defined radio.

The present invention is designed to be implemented for DSP based baseband modulator that can be further configured for various M-ary digital amplitude and/or phase modulation schemes. Further to this the present invention is configured for 4,8,8, and 16 interpolation rates for Raised Cosine filters that can perform multiple pulse shaping of BPSK, 4-PAM, QPSK, and 16-QAM respectively. Further to this, the present invention is capable of configuring M-ary digital amplitude and/or phase modulation schemes that can expand software defined radio applications. The features of the present invention such as able to change or configure multi rate interpolation filters is another advantage feature which appears not to be provided in the prior art.

SUMMARY OF THE INVENTION

The present invention relates to a configurable multi - modulation baseband modulator (or MMBM) of software defined radio (or SDR) using FPGA. The present invention further relates to a means to extend single digital modulation. Single digital modulation of baseband modulator is extended to multiple digital amplitude and/or phase modulations that can be configured for various SDR applications. The means comprise of modeling a configurable MMBM in DSP basis, generating first hardware description language hereinafter referred as "HDL", designing second HDL, combining the first and second HDLs, synthesizing the combined HDL, implementing the synthesized HDL into FPGA, and measuring the results obtained in real time. The first HDL is netlist of configurable MMBM with its test-bench file written in Verilog codes. The second HDL is setup configuration for P240 analog module (containing ADC and DAC) and FPGA on-board clock synthesizer written in Verilog codes. The netlist of configurable MMBM and module of setup configuration are combined into HDL module of integrated design. The delivery of configuration data to ADC and DAC is done prior to the running of configurable MMBM system.

According to the present invention, before executing the final stage of synthesis, FPGA pins are assigned accordingly for I/O ports. The final synthesis would ignore the pin assignment of analog input ports since no analog input is involved in configurable MMBM. The real-time results of configurable MMBM output (from DAC) in analog domain, especially pulse interval or pulse rate and waveform shape are measured.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a diagram illustrating a configurable MMBM design using System Generator/Simulink.

Figure 2 shows a diagram illustrating a PR Bit Generator subsystem. Figure 3 shows a diagram illustrating a Symbol Mapper subsystem. Figure 4 shows a diagram illustrating a l-to-2 Splitter subsystem. Figure 5shows a diagram illustrating a l-to-4 Splitter subsystem.

Figure 6 shows a diagram illustrating an I Map subsystem.

Figure 7 shows a diagram illustrating a Q Map subsystem.

Figure 8 shows a diagram illustrating a Set Zero subsystem.

Figure 9 shows a diagram illustrating an Interpolation Filter subsystem.

Figure 10 shows a diagram illustrating a 2xMA FIR Multi Interpolator subsystem.

Figure 11 shows a diagram illustrating a Control subsystem.

Figure 12 shows a diagram illustrating a Constant Selection subsystem.

Figure 13 shows a diagram illustrating a Count Selection subsystem.

Figure 14 shows a diagram illustrating a Coef Addr Gen subsystem.

Figure 15 shows a diagram illustrating a Data Buffer subsystem.

Figure 16 shows a diagram illustrating a Coef Buffer subsystem. Figure 17 shows a diagram illustrating a 2xMultiply-Add subsystem.

Figure 18 shows a diagram illustrating the simulation results for modulations of (a) BPSK; (b) 4-PAM; (c) QPSK and (d) 16-QAM.

Figure 19 shows a diagram illustrating a HDL simulation result of integrated design for 16-QAM.

Figure 20 shows a diagram illustrating the BPSK baseband modulation results of (a) Real-time and (b) Simulation.

Figure 21 shows a diagram illustrating the 4-PAM baseband modulation result of (a) Real-time and (b) Simulation.

Figure 22 shows a diagram illustrating the QPSK baseband modulation results of (a) Real-time and (b) Simulation.

Figure 23 shows a diagram illustrating the 16-QAM baseband modulation results of (a) Real-time and (b) Simulation.

Figure 24 shows a diagram illustrating a hardware implementation using Virtex-4 MB Board and P240 analog module. DETAILED DESCRIPTION OF THE PRESENT INVENTION

The present invention will now be described in detail with reference made to the accompanied drawings. However, it shall be noted that the scope of the invention is not limited thereto by making reference to the accompanied drawings.

Reference is made to Figure 1 wherein is shown therein a block diagram model of a DSP-based configurable multi-modulation baseband modulator (hereinafter also referred as MMBM) using Xilinx System Generator 9.2i in Simulink (Matlab R2007a) environment. The main system of configurable MMBM comprises of subsystems of PR Bit Generator, Symbol Mapper, and Interpolation Filter. The Simulink blocks are Constant 1, Constant2, and Scope. The Xilinx blocks are System Generator, Reset, Select, Input Bit, I Symbol, Q Symbol, I Signal, and Q Signal.

The System Generator block as illustrated in Figure 1 is used to set Simulink system period: 1 unit and FPGA system clock period: 10 ns (or 100 MSps sample rate). It is also used to generate Verilog HDL netlist of configurable MMBM with its test- bench file. It is convenient to represent 1 sampling period (10 ns) as 1 unit sample time and 1 latency.

As Simulink Source block, the Constantl and Constant2 blocks as illustrated in Figure 1 are the sources generating input signals to the configurable MMBM system. The Constantl block acts as input reset signal ('0' or T) with sample time 4 unit. It is set to Ό' to deactivate the system reset function in this case. While, the Constantl block represents DIP switch [D1:D0] on Virtex-4 FPGA MB Board. Table 1 shows the values to select digital amplitude and/or phase modulation schemes. The digital modulation schemes of BPSK, 4-PAM, QPSK, and 16-QAM are 2-ary phase, 4-ary amplitude, 4- ary phase, and 16-ary amplitude-phase modulations respectively.

Table 1 : Selection Values for Digital Modulation Scheme

As Xilinx Gateway In blocks, the Reset and Select blocks as illustrated in Figure 1 are two top level input ports of configurable MMBM system. The Reset block samples the mcoming signal from Constant! block at 4 units sample time, and yield Boolean output to inputs reset rst of PR Bit Generator and Symbol Mapper subsystems. While, the Select block samples the mcoming signal from Constant2 block at 4 units sample time, and yield 2-bit unsigned integer with fractional length (binary point: 0) to input select sel i of Symbol Mapper subsystem.

The PR Bit Generator subsystem with reference made to Figure 2 uses pseudorandom hereinafter also referred as "PR" concept to generate random bit sequence as input source to configurable MMBM. The sample time is set as 4 units (samples) to represent each generated bit. The initial condition of registers {Register 1-7 blocks) is 1101001. The Assert block re-emphasize output of Logical block as Boolean type at 4 units sample time to input d of Register 7 block. The generated bit rate is 25 Mbps (= 100 MSps/4).

The Symbol Mapper subsystem with reference made to Figure 3 maps the input bit to the corresponding Gray-coded signs and magnitudes of in-phase hereinafter also referred as "I" and/or quadrature hereinafter also referred as "Q" symbols for BPSK, 4- PAM, QPSK, and 16-QAM, using Tables 2, 3, and 4. The symbol mapping for BPSK, 4-PAM, QPSK, and 16-QAM require latency of 0, 8, 8, and 16 respectively.

Table 2: Symbol Mapping for BPSK

Table 3: Symbol Mappings for 4-PAM and QPSK

2-Bit 4-PAM QPSK

Data I I Q

00 -1 -1 -1

01 -0.3333 -1 1

10 1 1 -1

11 0.3333 1 1 Table 4: Symbol Mapping for 16-QAM

The l-to-2 Splitter subsystem with reference made to Figure 4 groups 2-bit data and splits each bit used for 4-PAM and QPSK using serial-to-parallel approach. The input data in Boolean is converted to 1-bit unsigned integer. Each successive 2 bits are grouped into 2-bit unsigned integer for latency: 8 (= 4x2). The most significant bit hereinafter also referred as "MSB" and least significant bit hereinafter also referred as "LSB" of the 2-bit unsigned integer are separated to be outputs of bit l and bit J) respectively.

The l-to-4 Splitter subsystem with reference made to Figure 5 groups 4-bit data and splits each bit used for 16-QAM using serial-to-parallel approach. The input data in Boolean is converted to 1-bit unsigned integer. Each successive 4 bits are grouped into 4-bit unsigned integer for latency: 16 (= 4x4). The bits 3 (MSB), 2, 1, and 0 (LSB) of the 4-bit unsigned integer are separated to be outputs of bit 3, bit 2, bit_l, and bit_0 respectively.

The I Map subsystem with reference made to Figure 6 uses multiplexers to map bit data in Tables 2, 3, and 4 into the corresponding symbols in I channel. Based on the input sel, 1-bit sign (sign bpsk, sign pam, sign qpsk, sign qam) and 1-bit magnitude (mag bpsk, mag pam, mag qpsk, mag qam) are concatenated to be 2-bit unsigned integer that decides sign of either + or - and magnitude of either 1/3 or 1. The I symbol output / symb is set to fixed point: signed 16-bit, binary point: 14. Note: the magnitudes of I symbols for BPSK and QPSK is 1, so mag bpsk and mag qpsk are '0' values mcoming from Constant block illustrated in Figure 3.

The Q Map subsystem with reference made to Figure 7 uses multiplexers to map bit data in Tables 2 and 3 into the corresponding symbols in Q channel. Based on the input sel, 1-bit sign (sign qpsk, sign qam) and 1-bit magnitude (mag qpsk, mag qam) are concatenated to be 2-bit unsigned integer that decides sign of either + or - and magnitude of either 1/3 or 1. The Q symbol output Q symb is set to fixed point: signed 16-bit, binary point: 14. Note: the magnitude of Q symbol for QPSK is 1, so mag qpsk is 'Ο' value incoming from Constant block illustrated in Figure 3.

The Set Zero subsystem with reference made to Figure 8 imposes 0 values to I and Q symbols depending on the following conditions: • Modulation dimension: BPSK and PAM are one-dimensional (1-D) modulation schemes, while QPSK and QAM are 2-D modulation schemes. Thus, Q channel is useless for BPSK and 4-PAM. When MSB of 2-bit input sel is 'Ο', output of AND gate (LogicaU block) is '0' to select 0 as output Q_put. When MSB of 2- bit input sel is Ί ' for QPSK and 16-QAM, the output Q_out will be either 0 or input Q_in depending on the output of AND gate (Logical2 block).

• Initial latency: Depending on the input sel, the normalized (by 4) latency values for BPSK, 4-PAM, QPSK, and 16-QAM are 0, 2, 2, and 4 respectively. If input rst is 'Ο', output of Inverter block is T. The output of AND gate {Logical 1 block) will be ' 1 ' after delay of the normalized latency, which will select inputs IJn and Qjn as outputs of l out and Q_out (for QPSK and 16-QAM) respectively. When input rst is ' 1 ', the outputs of l out and Q_out are 0 values.

The Interpolation Filter subsystem with reference made to Figure 9 is developed as linear phase finite impulse response hereinafter also referred as "FIR" Raised Cosine hereinafter also referred as "RC" filters in interpolation (polyphase) architecture for stability and efficient use of FPGA resources to change the rectangular shape of symbol to smoothed signal. The RC interpolation filters also provide zero crossing ripples of impulse response (time domain) at bit time that would be used for decision making at receiver. There are two configurable multi-rate interpolation filters hereinafter also referred as "MRIFs", each for I and Q channels. The design parameters of MRIF are listed in Table 5. The FDATool block is used to set merely filter design parameters of highest M-ary digital modulation (16-QAM in this case). The delays after MRIFs (with latency: 6) are set to latency of 10 for total latency of 16, equal to the maximum oversampling rate of symbol, for 16-QAM in this case. The outputs of l out and Q out are converted to fixed point: signed 16-bit, binary point: 13 due to DAC limitation.

Table 5: Design Parameters of Multi-Rate Interpolation Filter (MRIF)

The 2xMA FIR Multi Inteprolator subsystem with reference made to Figure 10 utilizes parallelization to perform polyphase decomposition for MRIF. The parallel structure of MRIF is more efficient than conventional interpolator (upsampler and FIR filter) due to fewer multiply-add hereinafter also referred as "MA" operations and lower multiplication and addition rates. The design parameters for polyphase decomposition of MRIF along with optimization are listed in Table 6. The phase taps is number of taps per phase, whereby over phase taps (O) is number of extra taps as compared to integer multiple of interpolation rate (L). 0 = 1 means that only first phase component (phase 1) has extra 1 tap and requires 1 extra MA operation. Thus, for optimization, MA operation of phase 1 is designed to work separately, in order to eliminate extra 0-value coefficients and multipliers used in the successive phase components for fully standardized MA operation. The sampling period is 10 ns (1 unit sample time). The total latency is 6 for all the modulation schemes of BPSK, 4-PAM, QPSK, and 16-QAM.

Table 6: Design Parameters for Polyphase Decomposition of MRIF

The Control subsystem with reference made to Figure 11 generates control signals for Data Buffer and Coef Buffer subsystems. The output data addr is always 0. For consistency of sampling period (1 unit sample time), input sel is upsampled by 4. The Counter block counts up from 0 to 15 periodically with step of 1, for total steps of 16 i.e. the maximum interpolation rate (for 16-QAM). However, the total steps of 4 (for BPSK) and 8 (for 4-PAM and QPSK) equivalent to count-ups of 0-to-3 and O-to-7 can be obtained by O-to-15 modulo 4 and O-to-15 modulo 2 respectively in Count Selection subsystem. When the output out of Counter block (in 4-bit unsigned integer) reaches the upper limits of 3 (for BPSK), 7 (for 4-PAM and QPSK), and 15 (for 16-QAM) i.e. outputs of Constant Selection subsystem, the output shift en is Ί ' for addressable shift registers (ASR1 and ASR2 blocks illustrated in Figure 15) in Data Buffer subsystem to capture and shift data. The initial value of Counter block is set to 15 for ASR1 to capture initial input data. When the output out of Counter block is 0, the flag of first phase component or the output phase 1 is triggered as 1 (in 1-bit unsigned integer). Depending on the input sel and output out of Counter block, Coef Addr Gen subsystem generates address as output coef addr for memories (ROM1 and ROM2 blocks illustrated in Figure 16) that store filter coefficients in Coef Buffer subsystem.

The Constant Selection subsystem with reference made to Figure 12 uses bit slicing to converts 15 in 4-bit unsigned integer to 3 and 7 in 2-bit and 3-bit unsigned integers respectively. However, Mux block imposes zero-padding for consistency of 4- bit unsigned integer. Depending on the input sel, the output const (in 4-bit unsigned integer) is either 3 (for BPSK), 7 (for 4-PAM and QPSK), or 15 (for 16-QAM).

The Count Selection subsystem with reference made to Figure 13 uses bit slicing to converts the input count J in 4-bit unsigned integer to 2-bit and 3-bit unsigned integers. However, Mux block imposes zero-padding for consistency of 4-bit unsigned integer. Depending on the input sel, the output count o (in 4-bit unsigned integer) is either 0-to-3 (for BPSK), 0-to-7 (for 4-PAM and QPSK), or 0-to-15 (for 16-QAM). The CoefAddr Gen subsystem with reference made to Figure 14 uses bit shifting to multiply the input count by 4 (2-bit left shift) and 2 (1-bit left shift) then yields 4-bit unsigned integers. Depending on the input sel, the output addr (in 4-bit unsigned integer) is either 0-4-8-12 (for BPSK), 0-2-4-6-8-12-14 (for 4-PAM and QPSK), or 0- to-15 (for 16-QAM).

The Data Buffer subsystem with reference made to Figure 15 uses registers to control data flow in phase components of MRIF. From Table 6, optimized phase taps (q) is 2, meaning that phase component requires only 1 shift register in which each of the 2 taps is at input and output of the shift register. However, ASR1 block acts as register for initial data capturing (resulting latency: 1) while ASR2 block is the only register for data shifting. The Delay block with latency of 2 (1 for initial data capturing) is a shift register yielding data at tap 2 that is used only for first phase component, while data at taps 1 and 3 are yielded from ASR1 and ASR2 blocks respectively.

The input din is upsampled by 4 to achieve the sampling period of 1 unit sample time because Symbol Mapper subsystem always operates at the minimum sampling period (4 unit sample time), even though l-to-2 Splitter and l-to-4 Splitter subsystems yield outputs at 8 unit (for 4-PAM and QPSK), and 16 unit (for 16-QAM) sample times respectively. The input addr (in 2-bit unsigned integer) is always 0. For first phase component (input phase 1 = 1), the inputs addr (in 2-bit unsigned integer) of ASR1 and ASR2 blocks are 0 and 1 selecting outputs of first and second shift registers respectively, thus the outputs of doutl, dout2 and dout3 are data at taps 1, 3, and 2 respectively. For successive phase components (input phasel = 0), the inputs addr of ASR1 and ASR2 blocks are 0 selecting outputs of first register for both, thus the outputs of doutl and dout2 are data at taps 1 and 2 respectively while the output dout3 is 0. The Register 1, Register 2, and Register 3 blocks yield 1 sample delay (latency: 1) for the outputs of doutl, dout2 and dout3 (in fixed point: 16-bit, binary point: 14) in order to match the latency of 1 caused by ROM1 and ROM2 blocks in Coef Buffer subsystem (as illustrated in Figure 16), for synchronization purpose. So, the total latency is 2.

The Coef Buffer subsystem with reference made to Figure 16 uses look-up table (LUT) method to generate optimized filter coefficients with the highest number of coefficients (32 for 16-QAM). The optimized filter coefficients with numbers of 8 (for BPSK) and 16 (for 4-PAM and QPSK) can be obtained by 4-step and 2-step jumps respectively upon the input addr as performed by Coef Addr Gen subsystem. The filter coefficient for index of 17 is 1. It is not stored in any Read-Only Memory hereinafter also referred as "ROM" block because its multiplication with data will result in no changes in 2xMultiply-Add subsystem, as illustrated in Figure 17.

The first element of ROM2 stores filter coefficient for index of 33 in order to be compatible to data at tap 3 for first phase component in Data Buffer subsystem (as illustrated in Figure 15). The filter coefficients stored in ROM1 and ROM2 blocks are indices of l-to-16 and 33-18-to-32 respectively. The filter coefficients for interpolation rates of 4 (for BPSK), 8 (for 4-PAM and QPSK), and 16 (for 16-QAM) are listed in Table 7. The outputs of coefl and coefl are set to fixed point: signed 16-bit, binary point: 14. The total latency is 1. Table 7: Filter Coefficients used in MRIF

Notes: All: BPSK, 4-PAM, QPSK, 16-QAM. The 2xMultiply-Add subsystem with reference made to Figure 17 performs multiplication of data at taps 1, 2, and 3 with the corresponding filter coefficients, and additions of each of the product outputs. As the filter coefficient for index of 17 is 1, its multiplication with input din3 still yields the same value as din3, thus multiplier is replaced by Delay block with latency: 3 for simplicity. As all multipliers and adders are set to full precision, so the output dout is set to fixed point: signed 34-bit, binary point: 28. The total latency is 4.

As Xilinx Gateway Out blocks, the Input Bit, I Symbol, Q Symbol, I Signal, and Q Signal blocks translate the incoming fixed-point values to floating point double precision values. However, only / Signal and Q Signal blocks would be used as top level output ports of configurable MMBM system; while Input Bit, I Symbol, and Q Symbol blocks are simply used to validate the data flow in the processes of input bit generation and symbol mapping.

As Simulink Sink block, the Scope block acts as a virtual oscilloscope to display the simulation results of input bit, IQ symbols, and IQ baseband modulated signals for BPSK, 4-PAM, QPSK, and 16-QAM, as illustrated in Figure 18.

To design configurations of ADC and DAC contained in P240 analog module, the timing characteristics for two Texas Instrument hereinafter also referred as "TI" ADS5500 (14-bit, 125 MSps) ADCs and one TI DAC5687 (16-bit, 500 MSps, 2x-8x interpolation) dual-channel DAC using Serial Programming Interface hereinafter also referred as "SPI" have to be satisfied, which are shown as inequality expressions in parentheses in Table 8. The required pins of ADS5500 ADC and DAC5687 DAC for interfacing with Virtex-4 FPGA MB Board are listed in Tables 9 and 10.

Table 8 : SPI Timing Characteristics for ADS5500 and DAC5687

SPI Timing Descriptions

ADC SPI Delay from ADC RESET disabled to ADC SEN active, Register Write t₃ = 2 .075 μβ (> 2 s)

ADC SPI Clock ADC_SCLK period, tsci = 100 ns (> 50 ns)

ADC_SCLK duty cycle: t_WCL = 50% (25% < t_WCL < 75%)

ADC SPI ADC SEN to ADC_SCLK setup time, ISLOADS = 100 ns (> 8 ns) Loading ADC_SCLK to ADC SEN hold time, t_SL0ADH = 50 ns (> 6 ns)

ADC SPI Data ADC SDATA hold time, t_DH = 50 ns (> 6 ns)

ADC SDATA setup time, t_DS = 50 ns (> 8 ns)

DAC SPI Clock DAC_SCLK period, t_SCLK = 100 ns (> 100 ns)

DAC_SCLK high time, t_SCLKH = 50 ns (> 40 ns)

DAC_SCLK low time, t_SCLKL = 50 ns (> 40 ns)

DAC SPI DAC SDENB to DAC_SCLK setup time,

Loading ts(SDENB) = 100 ns (> 20 ns)

DAC SPI Data DAC_SDIO hold time, t_H(SDio) = 50 ns (> 5 ns)

DAC_SDIO setup time t_S(SDio) = 50 ns (> 10 ns) Table 9: Required Pins of ADS5500 ADC

Notes: 1 : Pins used in Serial Programming Interface (SPI) process.

Table 10: Required Pins of DAC5687 DAC

Notes: 1 : Pins used in Serial Programming Interface (SPI) process. In order to synchronize ADC_SCLK and DAC_SCLK, clock for both SPI processes must not exceed 20 MHz (within 40-60% duty cycle). Thus, 100 MHz clock signal from FPGA on-board low voltage transistor-transistor logic hereinafter also referred as "LVTTL" oscillator is divided by 5 by f equency divider (written in Verilog codes) to generate 20 MHz (50% duty cycle) clock signal. Then, the 20 MHz clock signal is further divided by 2 to become 10 MHz (50% duty cycle) which equals to the values of ADC SPI Clock and DAC SPI Clock as listed in Table 8.

The 2-byte (or 16 bits) SPI codes designed for ADS5500 ADC configuration are listed in Table 11. The 2-byte (or 16 bits) SPI codes designed for DAC5687 DAC configuration are listed in Table 12. For DAC5687 DAC, the SPI code consists of 1- byte instruction code and 1-byte data code. The instruction code (first byte of SPI code) is set to transfer 1 byte data code (setting bit 6-5 of first byte) to certain register address (setting bit 4-0 of first byte) for each write operation (setting bit 7 of first byte).

Table 11 : SPI Codes for ADS5500 ADC

Name SPI Code Descriptions

Clock DLL 1101 0000 0000 0000 Internal delay locked loop (DLL): on,

for 60-125 MSps clock.

Test Mode 1110 0000 0000 0000 Test Mode: off, for normal operation.

Power Down 1111 0000 0000 0000 Power Down: off, for normal operation. Table 12: SPI Codes for DAC5687 DAC

Name SPI Code Descriptions

CONFIG2 0000 0011 0000 0000 Numerically-controlled oscillator (NCO): off.

NCO gain x2: off.

Quadrature modulator correction (QMC) for gain and phase: off.

Coarse Mixer: off.

Inverse sine compensation filter: off.

CONFIG1 0000 0010 0011 0000 qflag: off, for input data enable as TXENABLE pin.

Input data interleaving: off.

Dual Clock Mode: on, for CLKl/C from FPGA as input data rate; CLK2/C from CDCP1803 clock buffer as DAC sample rate.

Input data interpretation: 2's complement.

Input data reverse: off.

All interpolation filters bypass: off.

All filters, NCO, and QMC bypass: off.

CONFIG0 0000 0001 0000 0110 Phase locked loop (PLL): off.

FIR interpolation: *4, for interpolation rate: 4. FIFO (First In First Out): on, synchronized by TXENABLE pin. The configuration of FPGA on-board ICS8442 clock synthesizer is set to parallel mode, and it is simpler than P240 analog module. The required pins of ICS8442 clock synthesizer for interfacing with Virtex-4 FPGA MB Board are listed in Tables 13. The ICS 8442 differential output clocks {FOUTY) are generated based on formula:

FOUTl = 25 x M IN (MHz) (1)

The 9-bit M (within 8 < M< 28) and 2-bit JV (as 1, 2, 4, or 8) are set via two FPGA onboard DIP switches.

Table 13: Required Pins of ICS8442 Clock Synthesizer

The ICS8442 clock synthesizer is always active (SYNTH RESET: Ό') because it provides the main system clock for the processing of Virtex-4 FPGA, ADC, and DAC. The clock source is set to FPGA on-board 25 MHz crystal (SYNTH XTALSEL: T), thus SYNTH TEST is unused. The internal PLL is enabled (SYNTH_VCOSEL: ' 1 '). For synchronization purpose, SYNTH_PLOAD is set as DAC RESETB or inverse of ADC RESET. The HDL module (written in Verilog codes) of setup configuration developed in ModelSim environment should include all the aforementioned configurations of ADC, DAC, and ICS8442 clock synthesizer.

Considering real-time implementation of integrated design of netlist of configurable MMBM and setup configuration using FPGA and P240 analog module, the ADC and DAC contained in P240 should be configured first prior to the running of configurable MMBM system, in order to avoid instability of ADC and DAC that can cause data losses before and after processing of FPGA during process of configuring ADC and DAC. Thus, clock enable (ce) of configurable MMBM system is disabled during the transfer of SPI codes to ADC and DAC in P240. Controlling the main ce would be easier rather than clock enable clear (ce clr) which requires additional logics to adjust sampling phase of all the multi-sampled data when it is de-asserted. The HDL simulation result of integrated design (for 16-QAM) is shown in Figure 19.

The present inventors have previously described the design of Interpolation Filter I and 2 in RC Filter subsystem. These Interpolation Filters are ready-made blocks by Xilinx, Inc., that use 4*MA (Multiply- Add) and Accumulator hereinafter also referred as "MAC" operation. Due to the 33 (odd number) filter coefficients (or taps), this MAC operation requires 31 more taps with 0-value coefficients, in order to balance the number evenly to become 64 taps (or coefficients). However, the additional 31 useless 0-value coefficients have wasted memory storage (ROM1 and ROM2 blocks illustrated in Figure 16) for filter coefficients. Moreover, only one Interpolation Filter subsystem with interpolation rate of 8 is used in both I and Q channels. Although the resulting pulse-shaped signals are still acceptable, but there are still some non-zero spectral components over the frequency extended to ±∞ in Magnitude Response. The non-zero spectral components would potentially become interference source in band- limited signal transmission in wireless communications.

Therefore, the configurable multi-rate interpolation (MRIF) is designed in order to dirninish the out-of-band spectral components to miriimize the effect of infinite bandwidth. In addition, the optimized structure of MRIF in Interpolation Filter subsystem saves considerably amount of FPGA logic resources as listed in Table 14. The FPGA logic resources consist of slices, flip-flops (FFs), block random access memories (BRAMs), look-up tables (LUTs), and embedded multipliers hereinafter also referred as "EMults". Notice that configurable MRIF utilizes each type of FPGA logic resources nearly closed to pair of interpolation filters, and closely 1/3 of group of interpolation filters called interpolation filter bank hereinafter also referred as "IFB".

The overall FPGA logic utilization of different types of baseband modulator hereinafter also referred as "BM" with interpolation filter is listed in Table 15. Notice that each type of FPGA logic utilization of configurable MMBM with MRTF is closed to single 16-QAM BM. Also, for configurable MMBM with MRIF: the amounts of BRAMs and EMults are 1/3 of configurable BM with IFB; while the amounts of slices, FFs and LUTs are almost 40% of configurable BM with IFB. Table 14: Estimated FPGA Logic Utilization of Interpolation Filter Subsystem

Table 15 : Estimated FPGA Logic Utilization of Baseband Modulator (BM)

Notes: Config: Configurable. All: BPSK, 4-PAM, QPSK, 16-QAM. CH: Channel. Timing constraints are validated properly for optimum performance of FPGA processing before program download to FPGA hardware. The system clock ports for processing of ADC/DAC SPI and DSP-based configurable MMBM are CLK_100 and LIO_CLKIN_l from output of 100 MHz LVTTL oscillator and ADC_CLKOUT respectively. For convenience, both system clocks are set to 100 MHz. As shown in post PAR (Place and Route) static timing report in Table 16, positive worst case slacks (constrained period - best case required period) fulfill the timing requirement. The maximum allowable system sample rate for configurable MMBM used in Virtex-4 xc4vsx35-10ff668 FPGA is 205.7190 MSps (=1/4.861 ns). Due to limitation of ADS5500 ADC with maximum sample rate of 125 MSps, the maximum sample rate of configurable MMBM is 125 MSps practically. However, the system sample rate in the present invention is set to 100 MSps for purpose of illustrating the functionality of configurable MMBM. Nevertheless, the system sample rate can be changeable by configuring ICS 8442 clock synthesizer. This configurability of system sample rate would be useful for designing multi-rate processing of SDR compatible to multi- standard multi-band communications systems as well as testing and measurements.

Table 16: Post PAR (Place and Route) Static Timing Report

Frequency Period Worst Case Best Case Timing

Constraint (MHz) (ns) Slack (ns) Required Error

Setup Hold Period (ns)

CLKJ00 100 10 5.545 0.542 4.455 0

LIO_CLKTN_l 100 10 5.139 0.419 4.861 0 The real-time and simulation results of baseband modulated signals for BPSK, 4-PAM, QPSK, and 16-QAM are illustrated in Figures 20, 21, 22, and 23 respectively. The measured time difference within 4 peaks (At) represents 3 times pulse interval for BPSK, 4-PAM, QPSK, and 16-QAM as shown in Figures 20 (a), 21 (a), 22 (a), and 23 (a) respectively. From Table 17, the measured time difference divided by 3 is equal to the simulated pulse interval for all BPSK, 4-PAM, QPSK, and 16-QAM. The minor differences between modulus of peaks at cursors 1 and 2 and simulation results are because of limitation of 50-ohm coupled transformer (illustrated in Figure 24) after DAC in P240 analog module. However, comparison of the real-time and simulated results of baseband modulated signals for BPSK, 4-PAM, QPSK, and 16-QAM has shown equivalence in time domain, significant phase changes of 180° (π radian) as positive and negative signs, and significant amplitude changes between values of 1/3 and 1 (for 4-PAM and 16-QAM).

Table 17: Comparisons of Real-time and Simulation Results

Results Characteristics BPSK 4-PAM QPSK 16-QAM

3xPulse Interval, At (ns) 120 240 240 480

Pulse Interval, At 3(ns) 40 80 80 160

Real-time

Modulus of Lower Peak (V) 1.00 0.34 1.00 0.36

Modulus of Higher Peak (V) 1.12 1.04 1.04 1.04

Pulse Interval (ns) 40 80 80 160

Simulation Modulus of Lower Peak 1.00 0.33 1.00 0.33

Modulus of Higher Peak 1.00 1.00 1.00 1.00 The following paragraphs describe operations run in hardware implementation of configurable MMBM using Virtex-4 MB Board and P240 analog module with reference made to Figure 24.

The Virtex-4 FPGA on-board DIP switches are set to M 8:0] = 000110000 and N[1 :0] = 00, according to equation (1). After completely downloading the program of integrated design into Xilinx Virtex-4 FPGA, the setup configuration module will run first. The ICS 8442 clock synthesizer is triggered for loading M and N values in order to generate 400 MHz clock to CDCP1803 clock buffer. In the same time, two ADS5500 ADCs and DAC5687 DAC are configured using SPI (Serial Programming Interface) codes as listed in Tables 11 and 12. The sample rates of two ADS5500 ADCs and DAC5687 DAC (at CLK2/C pins) coming from CDCP1803 are 100 (=400/4) and 400 MSps respectively.

Since no analog input is used in the present invention, the final synthesis for the integrated design would ignore the pin assignment of Data In 1 and 2 connecting to ADC_IN [13:0] pins (shown in Table 9) of two ADS5500 ADCs. Also, two sets of THS4509 WB differential amplifier and low-pass 7th order RLC anti-alias filter are not used as well. However, both ADS5500 ADCs will yield 100 MHz sampling clock signals from ADC_CLKOUT pins to Clock 1 and 2 (after single-ended clock buffers). In the present invention, only Clock 1 or LIO CLKTN l pin is used as a source of system sample rate for DSP design of configurable MMBM. After completing setup configuration module, the DSP design of configurable MMBM starts running from now on with 100 MSps sample rate. Depending on the input Select as illustrated in Figure 1 (setting manually using FPGA on-board DIP switch), the DSP-based configurable MMBM will yield baseband modulated signals for either BPSK, 4-PAM, QPSK, or 16-QAM.

The in-phase (I) and quadrature (Q) baseband modulated signals will be sending to DAC_DA[15:0] and DAC_DB[15:0] pins (shown in Table 10) of DAC_5687 DAC respectively. For DAC 5687 DAC, 100 MHz differential clock signal (after differential- ended clock buffer) at CLK1/C pins is used as input data capturing rate, while 400 MHz differential clock signal at CLK2/C pins is used as DAC sample rate, thus resulting in interpolation rate of 4, for both DAC Channel A and B (referring to Table 12).

Eventually, the digital in-phase and quadrature baseband modulated signals will be converted by 2 sets of low-pass 5th order RLC reconstruction filters, and 50-ohm coupled transformers to become analog output signals. The analog outputs are connected to oscilloscope in order to display the real-time results in analog domain for testing and measurements.

Claims

1. A configurable multi - modulation baseband modulator of software defined radio using field programmable gate array wherein the means relates to extend single digital modulation characterized in that wherein single digital modulation of baseband modulator is extended to multiple digital amplitude and/or phase modulations that is configured for various applications of software defined radio wherein the means comprises of modeling a configurable multi - modulation baseband modulator in digital signal processing basis, generating a first hardware description language, designing a second hardware description language, combining the first and second hardware description languages, synthesizing the combined hardware description language, implementing the synthesized hardware description language into field programmable gate array and measuring the results obtained in real time.

2. A configurable multi - modulation baseband modulator of software defined radio using field programmable gate array as claimed in Claim 1 wherein the first hardware description language consists of netlist of configurable multi - modulation baseband modulator with its test-bench file written in Verilog codes.

3. A configurable multi - modulation baseband modulator of software defined radio using field programmable gate array as claimed in Claim 1 wherein the second hardware description language is setup configuration for P240 analog module containing analog-to-digital converter and digital-to-analog converter and field programmable gate array on-board clock synthesizer written in Verilog codes.

4. A configurable multi - modulation baseband modulator of software defined radio using field programmable gate array as claimed in Claim 1 wherein the netlist of configurable multi - modulation baseband modulator and module of setup configuration are combined into hardware description language module of integrated design.

5. A configurable multi - modulation baseband modulator of software defined radio using field programmable gate array as claimed in Claims 1 and 4 wherein the delivery of configuration data to analog-to-digital converter and digital-to- analog converter is done prior to the running of configurable multi - modulation baseband modulator system.

6. A configurable multi - modulation baseband modulator of software defined radio using field programmable gate array as claimed in Claims 1 and 4 wherein before executing the final stage of synthesis, field programmable gate array pins are assigned accordingly for I/O ports and wherein the final synthesis would ignore the pin assignment of analog input ports since no analog input is involved in configurable multi - modulation baseband modulator system.

7. A configurable multi - modulation baseband modulator of software defined radio using field programmable gate array as claimed in Claims 1 wherein the real-time results of configurable multi - modulation baseband modulator system output from digital-to-analog converter in analog domain, especially pulse interval or pulse rate and waveform shape are measured.