WO2012082880A1 - Procédés et systèmes de stockage à faible puissance - Google Patents
Procédés et systèmes de stockage à faible puissance Download PDFInfo
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- WO2012082880A1 WO2012082880A1 PCT/US2011/064880 US2011064880W WO2012082880A1 WO 2012082880 A1 WO2012082880 A1 WO 2012082880A1 US 2011064880 W US2011064880 W US 2011064880W WO 2012082880 A1 WO2012082880 A1 WO 2012082880A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
Definitions
- teachings relate to methods for reducing power consumption of energy-limited devices containing non-volatile memory.
- teachings relate to methods for reducing power consumption of devices whose flash memory shares the same power rail as their central processing unit (CPU),
- CPU central processing unit
- microcontrollers typically include 128 bytes to 10 Kbytes of on-chip flash memory.
- writing to flash memory is an energy-intensive operation because of the fundamental behavior of floating gate transistors.
- An ideal microcontroller would consume energy that varies linearly with the number of flash writes within a workload.
- ultra low-power microcontrollers of this variety require the entire chip to operate on a supply voltage that is significantly higher than what the CPU portion of the microcontroller requires— essentially a large safety margin to eliminate all errors with high probability. The large safety margins result in wasted energy.
- a system can choose a minimum- voltage threshold sufficiently high that flash memory is guaranteed to function reliably. This is the most common choice for embedded systems with on-chip flash memory, but it sacrifices energy for correctness. For example, the TI MSP430F2131 microcontroller consumes up to 50% less power in active mode when operating at 1.8 V instead of its onboard flash memory's specified minimum of 2.2 V.
- a system can choose an operating voltage below the flash memory's minimum specified voltage, resulting in a longer lifetime for a fixed amount of energy by avoiding flash memory usage. This choice forces the system to outsource storage (e.g., via a network interface such as wireless radio) if it demands reliable non- volatile memory. Such an approach, however, raises privacy as well as performance concerns.
- An example of a system that takes this route is the Intel WISP, a batteryless radio frequency identification (RFID) tag that sets its operating voltage to 1.8 V— below its onboard flash memory's 2.2V specified minimum— to save power.
- RFID radio frequency identification
- the microcontroller documentation states that writes to the flash memory will be unpredictable at this low voltage.
- Intel was unable to make the WISP tag write to flash memory at all when the tag relies on harvested energy.
- Most of the flash error correction codes are designed for NA D flash memories. The previously developed techniques neither consider the asymmetry of errors in low voltage flash memories nor consider the resource limitations of low power embedded devices.
- Yet another conventional application detects (but does not correct) 2-bit errors and can detect and correct 1-bit errors for each 256 bytes and targets NAND flash memory.
- a further conventional application provides results specific to Multi-Bit per Cell (or multi-level cells).
- the technology allows a chip to operate at voltages where the hardware was not designed to guarantee reliability of the nonvolatile memory.
- the reliability of storage in on-chip flash memories at operationally unreliable voltages can be improved by running one or more various software-based algorithms, including but not limited to, algorithms related to in- place writes, multiple-place writes, and slow writes.
- a method for improving the reliability of storage in non- volatile memories at operationally unreliable voltages includes supplying an operating voltage below a recommended minimum voltage to the computing device having an on-chip memory, and executing an improved reliability algorithm that repeatedly writes a data value in the on-chip memory.
- the data value is repeatedly written at a particular memory location in the flash memory up to a predetermined number of writing operations.
- the data value is written to a number of predetermined locations in the memory. The written data values are then read as corresponding readback values, and a bitwise logical operation is performed on the readback values to determine a final readback value, which is then read as the final readback value.
- a system comprises a processor, a non-volatile memory, and a computer readable medium having computer executable instructions stored thereon, which when executed by the processor, cause the processor to repeatedly write a data value in the non- volatile memory.
- a computer-readable storage medium having computer- executable instructions, which when executed by a computer, cause the computer to repeatedly write a data value at a particular memory location in a non-volatile memory up to a
- Embodiments of the system of these teachings include a processor and a computer usable medium having computer readable code embodied therein that causes the processor to execute the embodiments of the present disclosure.
- Fig. 1 is a graphical representation illustrating normal operating voltage requirements for a conventional computing device and reduced voltage requirements of the computing device for reducing the energy consumption by the computing device according to embodiments of the present disclosure
- Fig. 2 is a graphical representation of flash- write error rates as a function of voltage according to embodiments of the present disclosure
- Figs. 3A-3C are graphical representations of voltage versus time during write operations at various operating voltages according to embodiments of the present disclosure
- Fig. 4 is a graphical representation of error rates indicating that as the Hamming weight (number of Is in the binary representation) of a number increases, the error rate of low- voltage flash write diminishes;
- Figs. 5A - 5C are flowchart representations illustrating an in-place writes process of improving the reliability of storage in flash memories at low voltages according to embodiments of the present disclosure
- Figs. 6A - 6B are flowchart representations illustrating a multiple-place process of improving the reliability of storage in flash memories at low voltages according to embodiments of the present disclosure
- Figs. 6C - 6D are flowchart representations illustrating the decode method for the process shown in Figs. 6 A - 6B according to embodiments of the present disclosure
- Fig, 7 is a block diagram representation of a system utilizing the process shown in Figs. 5A-C and 6A-D according to embodiments of the present disclosure
- Fig. 8 is a graphical representation illustrating reliability improvement using in-place writes over five different voltages
- Fig. 9 is a graphical representation illustrating reliability improvement using multiple- place writes over five different voltages
- Fig. 10 shows the error rate of slow writes based on the voltage level and the speed of the writes
- Fig. 11 is a graphical representation illustrating ECG data stored in flash memory at 1.89 V improved by using a sign bit.
- Figs. 12A - 12B are flowchart representations illustrating the encoding and decoding methods for the slow- write method.
- the technology allows a chip to operate at voltages where the hardware was not designed to guarantee reliability of the nonvolatile memory.
- the reliability of storage in on-chip flash memories at operationally unreliable voltages can be improved by running one or more various software-based algorithms, including but not limited to, algorithms related to in- place writes, multiple-place writes, and slow writes.
- microcontrollers used in embedded devices are their high energy consumption, which is due to their high operational voltage requirements.
- an energy-limited embedded device can decrease its power consumption and therefore extend its lifetime on a finite energy supply.
- the minimum operating voltage of embedded devices that use nonvolatile on-chip storage is usually determined by the requirements of the non- volatile memory, such as flash memory. Therefore, by reducing the minimum voltage requirements of the non-volatile memory, the energy-limited embedded device can reduce its operational voltage requirements, and as a result, its power consumption.
- Flash memory refers to memory based on memory technologies that utilize a higher voltage than other system components in order for the hardware to perform reliably.
- Fig. 1 is a graphical representation illustrating normal operating voltage requirements for a conventional computing device and reduced voltage requirements of the computing device when implementing power consumption reducing algorithms in accordance with embodiments of the present disclosure.
- a computing device including but not limited to, a microprocessor or a microcontroller, such as, a TI MSP430 microcontroller has a nominal minimum voltage of 2.2V for flash writing and erasure. However, the microcontroller may still operate at lower voltages, such as 1.8V.
- Fig. 2 is a graphical representation of flash- write error rates as a function of voltage according to embodiments of the present disclosure. It has been determined that flash writes may not be error free at low voltages and that there exist voltage levels below the minimum recommended voltage at which flash writes function correctly. However, not all flash writes at voltages lower than the nominal minimum voltage are guaranteed to be successful. Fig. 2 further shows that for different chips of exactly the same type, the error rate can be different even under equivalent voltage.
- Figs. 3 A-3C are graphical representations of voltage versus time during write operations at various operating voltages, show that not all flash writes fail at low voltages. On the contrary, most of the writes (95.24% at 1.9 V and 89.88% at 1.8 V) succeed.
- Fig. 3A shows an original ECG signal correctly stored at 2.0V despite operating below the recommended threshold.
- erroneous writes represented by light colored spikes of varying heights according to the magnitude of the error become more common.
- the black line shows the reconstructed signal that includes the errors.
- Each flash memory cell is a floating-gate (FG) transistor made up of a source, drain, control gate, and floating gate.
- the floating gate is separated from the source and drain by an insulating oxide that makes it difficult for electrons to travel into or out of the gate. Flash cells rely on this oxide to maintain logical state in the absence of power, making the memory non-volatile.
- the control circuitry applies a high field to the source.
- the application of this field greatly increases the probability that electrons in the floating gate will tunnel to the source. If a sufficient number of electrons tunnel to the source, the cell is subsequently read as a 0.
- the control circuitry applies a high field to both the source and drain. This field energizes the electrons currently stored near the source, allowing them to jump the oxide barrier to the floating gate where they are once again trapped.
- the present disclosure provides techniques for improving the reliability of storage in nonvolatile memory while operating a computing device under operationally unreliable conditions, such as operational voltages lower than recommended minimum operational voltages, to acceptable error rates, while reducing energy consumption by the computing device.
- operationally unreliable conditions such as operational voltages lower than recommended minimum operational voltages
- several factors are taken into consideration, including but not limited to the increased error rate, the reduced energy consumption of the computing device, and the increased execution time to store the same data at a low voltage compared to a higher voltage. It should be appreciated that the energy consumed to achieve an acceptably low error rate should not exceed the expected energy savings gained by running at a lower voltage. It should further be appreciated that some of the factors that affect error rates are memory location and the Hamming weight of the data to be stored.
- test platform was setup to run a program that writes numbers ⁇ 0, ..., 255 ⁇ to flash memory, then sends the contents of its flash memory to the monitoring platform via GPIO pins.
- Table II compares the written data and the intended data for cases in which errors occurred. Table II demonstrates that, when both the written data and the intended data are represented as integers, the absolute value of the stored data is always greater than or equal to the absolute value of the intended data.
- Hamming weight of the data With reference to Hamming weight of the data, it has been determined that the lower the Hamming weight (number of Is in the binary representation) of a number, the higher the probability of error when writing that number to flash at low voltage. This can be explained by understanding that in an erased (i.e., having value 1) flash cell, writing a 1 is always error free because no change to the cell is necessary. However, setting a cell to 0 might fail if there is not enough charge accumulated in that cell. Based on per-byte Hamming weight, there are nine equivalence classes of integers that can be represented in one byte. The weight-8 equivalence class has only one member, 255, which can always be written to an erased flash cell without error.
- flash memory has a limited lifetime (about 10 cycles of erasures) after which the erase operations fail to reset the bits to 1.
- Wear-out history affects error rate, so storing data in more than one location might help decrease the error rate, especially if those locations are in different blocks of memory.
- a method for improving the reliability of storage in flash memories at low voltages includes repeatedly writing data at the same memory location for up to a predetermined number of writing operations.
- This embodiment also referred to as in-place writes, makes attempts at write time to store a value correctly in the given memory address.
- the in-place writes method repeatedly writes data to the same memory address.
- FIGs. 5 A - 5C are flowchart representations illustrating an in-place writes process of improving the reliability of storage in flash memories at low voltages according to embodiments of the present disclosure.
- the data is written to flash memory at a given location (step 10), the number of write operations (initially set to zero) is incremented (step 20) and compared to a predetermined threshold (step 30). If the number of write operations is less than the
- Fig. 5B shows the same method, with more detail, but including the step of reading the flash memory at the given location and comparing to data being written. If the output of the read operation is substantially equal to the data being written, the method ends.
- Fig. 5C shows the flowchart of the read operation. Since the transition of a 1 to a 0 in a NOR flash memory at low voltage is stochastic rather than guaranteed, the in-place writes method repeats the write of each byte (to the same memory location) more than once if necessary, up to a threshold number of attempts. Algorithm 1 gives the details for ENCODE and DECODE procedures for in- place writes.
- Algorithm 1 The encoding and decoding algorithms for
- in-place writes method to store data to address by repeating the writes up to threshold number of attempts if
- the processor performs the following steps during writing the data value at a particular memory location in the flash memory. First, the processor writes the data value at the particular memory location and then reads the written data value from the same memory location. A write operation count (repeat) is then incremented. The processor determines if the read data value is not equal to the data value to be written and if the write operation count is less than a predetermined number of writing operations (threshold).
- the steps of writing the data value at the same memory location, reading a corresponding readback value from the same memory location, and incrementing the write operation count are repeated until the processor determines that the write operation count is not less than a predetermined number of writing operations or the data value is equal to the readback value, at which point, the processor ceases to write the data value at the same memory location. It should be appreciated that by determining to see if the readback value is equal to the data value to be written prior to each iteration, and prior to the threshold being reached, the processor may be able to reduce its energy consumption when compared to writing the data value a threshold number of times.
- the processor can prevent itself from consuming additional energy in repeatedly writing the data value a predetermined number of times.
- the method for improving the reliability of storage in flash memories at low voltages includes writing a value to a number of
- predetermined locations in the flash memory reading the written data from each one of the number of predetermined locations, the results of their reading constituting a number of readback values for a datum, and performing a bitwise logical operation on the number of readback values for the datum, with the result of the bitwise logical operation being the final readback value.
- Figs. 6a and 6b are flowchart representations illustrating a multiple-place writes process of improving the reliability of storage in flash memories at low voltages according to embodiments of the present disclosure.
- the address of the location in the flash memory at which data is to be written is initially a predetermined start address and the number of addresses is initially zero. Data is written at the location for which the address is known (step 40), the number of addresses is incremented (step 50) and compared to a
- Figs 6B and 6D are flowchart representations of the read back or decoding portion of the above described method. Referring to Fig. 6C, the address is initially set to the initial or start address and the address number is set initially to 1. The flash memory is read at the initial address (step 110) and the outcome of reading is set equal to the result (step 120).
- the address number is incremented (step 130), the address of the location being read is set to the next address (step 140), the flash memory is read at the location corresponding to the address (step 150), the result is obtained by a logical operation between the outcome of the read process (step 160) and the previous value of the result and the address number is compared to a predetermined threshold (step 170). If the address number is less than the predetermined threshold and the result is not equal to the data, steps 130 through 170 are repeated. If the address number is not less than the predetermined threshold or the result is equal to the data, the method ends.
- the processor may be able to reduce its energy consumption when compared to writing the data value to a threshold number of locations. This is because the amount of energy consumed in reading a data value and comparing it to the data value to be written is less than the energy consumed in writing the data value. As such, if the data value is written correctly in the first attempt, the processor can prevent itself from consuming additional energy in repeatedly writing the data value to a predetermined number of locations.
- Fig. 6D is a more detailed flow chart for the embodiment in which the logical operation is an AND operation.
- Algorithm 2 details ENCODE and DECODE procedures of the multiple-place writes method. Writing a value to more than one memory location increases the probability of storing it successfully in the flash memory.
- Algorithm 2 The encoding and decoding algorithms for
- the method for improving the reliability of storage in flash memories at low voltages includes slowing down the speed of flash writes to allow more charge to be stored in a cell in an attempt to decrease the probability of error.
- This embodiment is referred to as slow writes and tries to decrease the probability of error by allow more charge to be stored in a cell at the time of writing.
- Figs 12A and 12B are flowchart representations of the read back or decoding portion of the above described method.
- This method is similar to in-place writes in that it tries to accumulate enough charge in a cell to present a zero bit. However, instead of writing a bit multiple times, this method writes a bit once but slowly. The extra time allows for more charge to get stored in a cell.
- Algorithm 4 details the simple ENCODE and DECODE procedures.
- One way to improve the slow writes is to choose a frequency level based on the operating voltage as well as the temperature and then try to adjust the frequency based on the error rate. If the error rate is too high, the frequency has to be set to a smaller number to reduce the speed.
- Algorithm 4 The encoding and decoding algorithms for the slow writes method to store data to address by slowing the write threshold times than, a normal write.
- Fig. 7 is a block diagram of an embodiment of the system of these teachings.
- the system includes a processor 180, one or more computer usable media having computer readable code embodied therein for implementing an embodiment of the method of these teachings 185 and a non- volatile memory 190, such as a flash memory.
- a non- volatile memory 190 such as a flash memory.
- the processor 180, the one or more computer readable media 185 and the non- volatile memory 190 are operatively connected by an interconnection component 175.
- the workload used to measure the performance of each of the embodiments is the storage of accelerometer traces— generated using the Intel WISP 4. l 's 10-bit ADC sensor— to flash memory.
- the input trace is a series of three-dimensional 16-bit samples containing 10 bits of information.
- a simple ad-hoc data compression method was utilized to store more data in the available flash memory. The compression method involved reading 4 samples of data, preparing the first byte of each sample to be stored in flash memory, then combining the remaining 2 bits of each sample into one byte of data. Using this compression scheme, every four samples (8 bytes) and were reduced to 5 bytes.
- the in-place writes method slightly outperforms the multiple-place writes method at both voltage levels because its decoding procedure is less CPU intensive. In-place writes method has a better Error Correction Rate (ECR in Table 2) than multiple-place writes. The multiple-place writes method seems to be the most suitable when there are some memory cells that are hard to program and therefore rewriting in those cells is not helpful.
- ECR in Table 2 Error Correction Rate
- ECR Error Correction Rate
- Fig. 8 and Fig. 9 show that flash storage reliability improves as the number of repeated writes/ places at five different voltage levels is increased (all below the nominal minimum voltage for flash writes).
- Fig. 10 shows the error rate of slow writes based on the voltage level and the speed of the writes.
- the speed of the writes has been adjusted by tuning the frequency of the flash memory. For an operating voltage as low as 1.8V, the average error rate eventually drops to about zero percent if the speed is slowed down enough (In the case of this particular chip when the frequency is set to 285 KHz). Since low-power embedded devices have a limited amount of energy available, saving power is usually a higher priority than reducing the delay. Slow writes follows this principle and reduces the speed of the writes in order to save the power consumption of the device. Slow writes would be beneficial especially for CPU-intensive applications that their often use of CPU would cost less power while their rare flash memory use will be slower.
- a TI MSP430F2131 microcontroller runs a program that writes zeros to the data segment of its flash memory (192 bytes).
- the microcontroller's operating voltage was increased in 10-mV steps and the frequency of flash writes was increased from 260 KHz to 1104 KHz.
- the monitoring platform was used to compute the byte error rates over 50 runs.
- the Hamming weight of a number is the Hamming weight of a number.
- One way to improve the performance of the low- voltage storage methods is to store numbers with greater Hamming weights (weight > 4) in flash memory. If a number is lightweight (weight ⁇ 4), the complement of the number would be stored and a sign bit would be set for future data access. An array of sign bits can be stored separately from the data to avoid disturbing data structure layouts. Similar techniques have been applied to multi- level cell (MLC) flash memories with four levels; those techniques result in a significant decrease of energy consumption. Fig. 11 shows that using the sign bit scheme decreases the error rate at low voltage for the same ECG data used herein above.
- MLC multi- level cell
- Fig. 11 shows ECG data stored in flash memory at 1.89 V improved by using a sign bit.
- the light-colored bars show the difference between the ECG stored at low voltage and the original ECG data.
- Another technique for exploiting the fact that numbers with greater Hamming weights have a lower probability of error is to map the most frequently used numbers in the user's data to the heavier numbers.
- One embodiment preprocesses the data to sort numbers based on their frequency of use.
- a simple memory mapping table would map the most frequent numbers to the heaviest numbers. Such a table could be preloaded in flash memory so that storing the table does not consume energy at run time. Use of a memory mapping table would only increase the number of Is and does not increase the number of writes. Therefore, the energy consumption overhead and the delay should be smaller than the sign bit method.
- teachings have been described with respect to various embodiments, it should be realized these teachings are also capable of a wide variety of further and other embodiments within the spirit and scope of the appended claims.
- the present disclosure describes embodiments related to flash memories, the present disclosure may be applied to other types of memory technologies that utilize a higher voltage than other system components in order for the hardware to perform reliably.
- the teachings disclosed in the present disclosure can be applied to other memory technologies, including but not limited to, memsistors, FRAM, spintronic memory, phase-change memory, and the like.
- teachings disclosed herein relate to software algorithms for improving the reliability of storage in a computing device with an on-chip memory at voltages below recommended minimum operating voltages.
- the scope of the present disclosure is not intended to be limited to such applications, but rather, includes applications that may utilize the software algorithm methods of in-place writes, multiple-place writes, and slow writes, or any combination thereof, to improve the reliability of storage in a computing device with an on-chip memory operating in physically unreliable or operationally unreliable conditions. Such conditions may arise from operating at physically unreliable or operationally unreliable voltages. However, other conditions other than operating at
- operationally unreliable voltages may cause the storage in a non- volatile memory to be unreliable.
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Abstract
L'invention concerne des technologies permettant d'améliorer la fiabilité de stockage dans des mémoires non volatiles à des tensions de fonctionnement non fiables. Un procédé consiste à appliquer une tension de fonctionnement inférieure à une tension minimale recommandée à un dispositif de calcul comportant une mémoire flash sur puce, et exécuter un algorithme basé sur un logiciel de fiabilité améliorée qui écrit de façon répétée une valeur de donnée dans la mémoire non volatile sur puce. Selon un aspect, la valeur de donnée est écrite de façon répétée à un endroit particulier de la mémoire flash jusqu'à ce qu'un nombre prédéterminé d'opérations d'écriture soit atteint. Selon un autre aspect, la valeur de donnée est écrite à un certain nombre d'endroits prédéterminés dans la mémoire non volatile. Les valeurs de données écrites sont ensuite lues comme des valeurs de relecture correspondantes, et une opération logique de manipulation de bits est effectuée sur les valeurs de relecture pour déterminer une valeur de relecture finale, qui est alors lue comme la valeur de relecture finale.
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US10303622B2 (en) | 2015-03-06 | 2019-05-28 | Hewlett Packard Enterprise Development Lp | Data write to subset of memory devices |
US10620861B2 (en) | 2015-04-30 | 2020-04-14 | Hewlett Packard Enterprise Development Lp | Retrieve data block from determined devices |
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US10303622B2 (en) | 2015-03-06 | 2019-05-28 | Hewlett Packard Enterprise Development Lp | Data write to subset of memory devices |
US10620861B2 (en) | 2015-04-30 | 2020-04-14 | Hewlett Packard Enterprise Development Lp | Retrieve data block from determined devices |
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