Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/46—Multiprogramming arrangements
  • G06F9/54—Interprogram communication
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/46—Multiprogramming arrangements
  • G06F9/54—Interprogram communication
  • G06F9/544—Buffers; Shared memory; Pipes
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/46—Multiprogramming arrangements
  • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
  • G06F9/522—Barrier synchronisation
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/46—Multiprogramming arrangements
  • G06F9/54—Interprogram communication
  • G06F9/546—Message passing systems or structures, e.g. queues
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
  • G06T1/00—General purpose image data processing
  • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2209/00—Indexing scheme relating to G06F9/00
  • G06F2209/50—Indexing scheme relating to G06F9/50
  • G06F2209/509—Offload

Definitions

• the present invention is generally directed to computing systems. More particularly, the present invention is directed to an architecture for unifying the computational components within a computing system.
• GPU graphics processing unit
• CPU central processing unit
• GPUs have traditionally operated in a constrained programming environment, available only for the acceleration of graphics. These constraints arose from the fact that GPUs did not have as rich a programming ecosystem as CPUs. Their use, therefore, has been mostly limited to two dimensional (2D) and three dimensional (3D) graphics and a few leading edge multimedia applications, which are already accustomed to dealing with graphics and video application programming interfaces (APIs).
• 2D two dimensional
• 3D three dimensional
• the discrete chip arrangement forces system and software architects to utilize chip to chip interfaces for each processor to access memory. While these external interfaces (e.g., chip to chip) negatively affect memory latency and power consumption for cooperating heterogeneous processors, the separate memory systems (i.e., separate address spaces) and driver managed shared memory create overhead that becomes unacceptable for fine grain offload.
• a GPU cannot effectively execute commands which involve an operating system ("OS") such as, for example, instructions that allocate memory or printing data to a computer screen can only be processed using a CPU. Because the GPU cannot perform these tasks, the GPU makes a request to the CPU to perform those tasks. These requests are known as system calls (syscalls).
• OS operating system
• system calls system calls
• Syscalls are expensive for the CPU to process. Often, syscalls are high-priority commands that require CPU's immediate attention. Each time the CPU receives a syscall request, the CPU stops processing its current processes, invokes the OS, processes the syscall, and then returns to processing its work.
• each work item can require a syscall for memory allocation or other instructions that the GPU cannot process (or cannot process readily).
• a GPU makes a separate syscall request to the CPU for each work item. Because the work items execute in parallel, each work item makes the same syscall request to the CPU.
• APD accelerated processing device
• Embodiments of the present invention include a system, method and article of manufacture for optimizing communication for system calls.
• the method includes storing a system call for each work item in a wavefront and transmitting said stored system calls to a processor for execution.
• the method also includes responsive to said transmitting, receiving a result to each work item in the wavefront.
• FIG. 1 A is an illustrative block diagram of a processing system in accordance with embodiments of the present invention.
• FIG. I B is an illustrative block diagram illustration of the APD illustrated in FIG.
• FIG. 2 is an illustrative block diagram illustration 200 of the optimized communication processing between a CPU and an APD.
• FIG. 3 is an illustrative flowchart 300 of an APD using a single instruction multiple data (SIMD) vector to communicate syscall requests to a CPU.
• SIMD single instruction multiple data
• references to "one embodiment,” “an embodiment,” “an example embodiment,” etc. indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
• FIG. 1 A is an exemplary illustration of a unified computing system 100 including a CPU 102 and an APD 104.
• CPU 102 can include one or more single or multi core CPUs.
• the system 100 is formed on a single silicon die or package, combining CPU 102 and APD 104 to provide a unified programming and execution environment. This environment enables the APD 104 to be used as fluidly as the CPU 102 for some programming tasks.
• the CPU 102 and APD 104 be formed on a single silicon die. In some embodiments, it is possible for them to be formed separately and mounted on the same or different substrates.
• system 100 also includes a memory 106, an operating system
• the operating system 108 and the communication infrastructure 109 are discussed in greater detail below.
• the system 100 also includes a kernel mode driver (KMD) 1 10, a software scheduler (SWS) 1 12, and a memory management unit 1 16, such as input/output memory management unit (IOMMU).
• KMD kernel mode driver
• SWS software scheduler
• IOMMU input/output memory management unit
• Components of system 100 can be implemented as hardware, firmware, software, or any combination thereof.
• system 100 may include one or more software, hardware, and firmware components in addition to, or different from, that shown in the embodiment shown in FIG. 1 A.
• a driver such as KMD 110
• KMD 110 typically communicates with a device through a computer bus or communications subsystem to which the hardware connects.
• a calling program invokes a routine in the driver
• the driver issues commands to the device.
• the driver may invoke routines in the original calling program.
• drivers are hardware-dependent and operating-system-specific. They usually provide the interrupt handling required for any necessary asynchronous time-dependent hardware interface.
• Device drivers particularly on modern Windows platforms, can run in kernel-mode (Ring 0) or in user-mode (Ring 3).
• a benefit of running a driver in user mode is improved stability, since a poorly written user mode device driver cannot crash the system by overwriting kernel memory.
• user/kernel-mode transitions usually impose a considerable performance overhead, thereby prohibiting user mode-drivers for Sow latency and high throughput requirements.
• Kernel space can be accessed by user modules only through the use of system calls. End user programs like the UNIX shell or other GUI based applications are part of the user space. These applications interact with hardware through kernel supported functions.
• CPU 102 can include (not shown) one or more of a control processor, field programmable gate array (FPGA), application specific integrated circuit (ASIC), or digital signal processor (DSP).
• CPU 102 executes the control logic, including the operating system 108, KMD 1 10, SWS 1 12, and applications 1 1 1, that control the operation of computing system 100.
• CPU 102 executes and controls the execution of applications 1 1 1 by, for example, distributing the processing associated with that application across the CPU 102 and other processing resources, such as the APD 104.
• APD 104 executes commands and programs for selected functions, such as graphics operations and other operations that may be, for example, particularly suited for parallel processing.
• APD 104 can be frequently used for executing graphics pipeline operations, such as pixel operations, geometric computations, and rendering an image to a display.
• graphics pipeline operations such as pixel operations, geometric computations, and rendering an image to a display.
• APD 104 can also execute compute processing operations, based on commands or instructions received from CPU 102.
• commands can be considered a special instruction that is not defined in the ISA and usually accomplished by a set of instructions from a given ISA or a unique piece of hardware.
• a command may be executed by a special processor such as a dispatch processor, command processor, or network controller.
• instructions can be considered, e.g., a single operation of a processor within a computer architecture.
• some instructions are used to execute x86 programs and some instructions are used to execute kernels on APD/GPU compute unit.
• CPU 102 transmits selected commands to APD
• APD 104 can include its own compute units (not shown), such as, but not limited to, one or more single instruction multiple data (SIMD) processing cores.
• SIMD single instruction multiple data
• a SIMD is a math pipeline, or programming model, where a kernel is executed concurrently on multiple processing elements each with its own data and a shared program counter. All processing elements execute a strictly identical set of instructions. The use of predication enables work-items to participate or not for each issued command.
• each APD 104 compute unit can include one or more scalar and/or vector floating-point units and/or arithmetic and logic units (ALUs).
• the APD compute unit can also include special purpose processing units (not shown), such as inverse-square root units and sine/cosine units.
• the APD compute units are referred to herein collectively as shader core 122.
• SIMD 104 Having one or more SIMDs, in general, makes APD 104 ideally suited for execution of data-parallel tasks such as are common in graphics processing.
• a compute kernel is a function containing instructions declared in a program and executed on an APD/GPU compute unit. This function is also referred to as a kernel, a shader, a shader program, or a program.
• each compute unit e.g., SIMD processing core
• a work-item is one of a collection of parallel executions of a kernel invoked on a device by a command.
• a work-item can be executed by one or more processing elements as part of a work-group executing on a compute unit.
• a work-item is distinguished from other executions within the collection by its global ID and local ID.
• a subset of work-items in a workgroup that execute simultaneously together on a single SIMD engine can be referred to as a wavefront 136.
• the width of a wavefront is a characteristic of the hardware SIMD engine.
• a workgroup is a collection of related work-items that execute on a single compute unit. The work-items in the group execute the same kernel and share local memory and work-group barriers.
• Wavefronts Instructions across a wavefront are issued one at a time, and when all work-items follow the same control flow, each work-item executes the same program.
• An execution mask and work-item predication are used to enable divergent control flow within a wavefront, where each individual work-item can actually take a unique code path through the kernel.
• Partially populated wavefronts can be processed when a full set of work-items is not available at wavefront start time. Wavefronts can also be referred to as warps, vectors, or threads.
• Commands can be issued one at a time for the wavefront.
• each work-item can execute the same program.
• an execution mask and work-item predication are used to enable divergent control flow where each individual work-item can actually take a unique code path through a kernel driver.
• Partial wavefronts can be processed when a full set of work-items is not available at start time.
• shader core 122 can simultaneously execute a predetermined number of wavefronts 136, each wavefront 136 comprising a predetermined number of work- items.
• APD 104 includes its own memory, such as graphics memory 130. Graphics memory 130 provides a local memory for use during computations in APD 104. Individual compute units (not shown) within shader core 122 can have their own local data store (not shown). In one embodiment, APD 104 includes access to local graphics memory 130, as well as access to the memory 106. In another embodiment, APD 104 can include access to dynamic random access memory (DRAM) or other such memories (not shown) attached directly to the APD 104 and separately from memory 106.
• DRAM dynamic random access memory
• APD 104 also includes one or (n) number of command processors (CPs) 124.
• CP 124 controls the processing within APD 104.
• CP 124 also retrieves commands to be executed from command buffers 125 in memory 106 and coordinates the execution of those commands on APD 104.
• CPU 102 inputs commands based on applications 111 into appropriate command buffers 125.
• an application is the combination of the program parts that will execute on the compute units within the CPU and APD.
• a plurality of command buffers 125 can be maintained with each process scheduled for execution on the APD 104.
• CP 124 can be implemented in hardware, firmware, or software, or a combination thereof.
• CP 124 is implemented as a reduced instruction set computer (RISC) engine with microcode for implementing logic including scheduling logic.
• RISC reduced instruction set computer
• APD 104 also includes one or (n) number of dispatch controllers (DCs) 126.
• DCs refers to a command executed by a dispatch controller that uses the context state to initiate the start of the execution of a kernel for a set of workgroups on a set of compute units.
• DC 126 includes logic to initiate workgroups in the shader core 122. In some embodiments, DC 126 can be implemented as part of CP 124.
• System 100 also includes a hardware scheduler (HWS) 128 for selecting a process from a run list 150 for execution on APD 104.
• HWS 128 can select processes from run list 150 using round robin methodology, priority level, or based on other scheduling policies. The priority level, for example, can be dynamically determined.
• HWS 128 can also include functionality to manage the run list 150, for example, by adding new processes and by deleting existing processes from run-list 150.
• the run list management logic of HWS 128 is sometimes referred to as a run list controller (RLC).
• RLC run list controller
• CP 124 when HWS 128 initiates the execution of a process from RLC 150, CP 124 begins retrieving and executing commands from the corresponding command buffer 125. In some instances, CP 124 can generate one or more commands to be executed within APD 104, which correspond with commands received from CPU 102. In one embodiment, CP 124, together with other components, implements a prioritizing and scheduling of commands on APD 104 in a manner that improves or maximizes the utilization of the resources of APD 104 and/or system 100.
• APD 104 can have access to, or may include, an interrupt generator 146.
• Interrupt generator 146 can be configured by APD 104 to interrupt the operating system 108 when interrupt events, such as page faults, are encountered by APD 104.
• APD 104 can rely on interrupt generation logic within IOMMU 1 16 to create the page fault interrupts noted above.
• APD 104 can also include preemption and context switch logic 120 for preempting a process currently running within shader core 122.
• Context switch logic 120 includes functionality to stop the process and save its current state (e.g., shader core 122 state, and CP 124 state).
• the term state can include an initial state, an intermediate state, and a final state.
• An initial state is a starting point for a machine to process an input data set according to a program in order to create an output set of data.
• An intermediate state for example, that needs to be stored at several points to enable the processing to make forward progress. This intermediate state is sometimes stored to allow a continuation of execution at a later time when interrupted by some other process.
• final state that can be recorded as part of the output data set
• Preemption and context switch logic 120 can also include logic to context switch another process into the APD 104.
• the functionality to context switch another process into running on the APD 104 may include instantiating the process, for example, through the CP 124 and DC 126 to run on APD 104, restoring any previously saved state for that process, and starting its execution.
• Memory 106 can include non-persistent memory such as DRAM (not shown).
• Memory 106 can store, e.g., processing logic instructions, constant values, and variable values during execution of portions of applications or other processing logic.
• processing logic or “logic,” as used herein, refers to control flow commands, commands for performing computations, and commands for associated access to resources.
• memory 106 includes command buffers 125 that are used by CPU
• Memory 106 also contains process lists and process information (e.g., active list 152 and process control blocks 154). These lists, as well as the information, are used by scheduling software executing on CPU 102 to communicate scheduling information to APD 104 and/or related scheduling hardware. Access to memory 106 can be managed by a memory controller 140, which is coupled to memory 106. For example, requests from CPU 102, or from other devices, for reading from or for writing to memory 106 are managed by the memory controller 140.
• IOMMU 1 16 is a multi-context memory management unit.
• context can be considered the environment within which the kernels execute and the domain in which synchronization and memory management is defined.
• the context includes a set of devices, the memory accessible to those devices, the corresponding memory properties and one or more command-queues used to schedule execution of a kernel(s) or operations on memory objects.
• process can be considered the execution of a program for an application will create a process that runs on a computer.
• the operating system can create data records and virtual memory address spaces for the program to execute.
• the memory and current state of the execution of the program can be called a process.
• the operating system will schedule tasks for the process to operate on the memory from an initial to final state.
• IOMMU 1 16 includes logic to perform virtual to physical address translation for memory page access for devices including APD 104. IOMMU 1 16 may also include logic to generate interrupts, for example, when a page access by a device such as APD 104 results in a page fault. IOMMU 1 16 may also include, or have access to, a translation lookaside buffer (TLB) 1 18. TLB 1 18, as an example, can be implemented in a content addressable memory (CAM) to accelerate translation of logical (i.e., virtual) memory addresses to physical memory addresses for requests made by APD 104 for data in memory 106.
• CAM content addressable memory
• communication infrastructure 109 interconnects the components of system 100 as needed.
• Communication infrastructure 109 can include (not shown) one or more of a peripheral component interconnect (PCI) bus, extended PCI (PCI-E) bus, advanced microcontroller bus architecture (AMBA) bus, accelerated graphics port (AGP), or such communication infrastructure.
• Communications infrastructure 109 can also include an Ethernet, or similar network, or any suitable physical communications infrastructure that satisfies an application's data transfer rate requirements.
• Communication infrastructure 109 includes the functionality to interconnect components including components of computing system 100.
• operating system 108 includes functionality to manage the hardware components of system 100 and to provide common services.
• operating system 108 can execute on CPU 102 and provide common services. These common services can include, for example, scheduling applications for execution within CPU 102, fault management, interrupt service, as well as processing the input and output of other applications.
• operating system 108 based on interrupts generated by an interrupt controller, such as interrupt controller 148, invokes an appropriate interrupt handling routine. For example, upon detecting a page fault interrupt, operating system 108 may invoke an interrupt handler to initiate loading of the relevant page into memory 106 and to update corresponding page tables.
• Operating system 108 may also include functionality to protect system 100 by ensuring that access to hardware components is mediated through operating system managed kernel functionality. In effect, operating system 108 ensures that applications, such as applications 1 1 1 , run on CPU 102 in user space. Operating system 108 also ensures that applications 1 1 1 invoke kernel functionality provided by the operating system to access hardware and/or input/output functionality.
• applications 1 1 1 include various programs or commands to perform user computations that are also executed on CPU 102.
• the unification concepts can allow CPU 102 to seamlessly send selected commands for processing on the APD 104.
• input/output requests from applications 1 1 1 will be processed through corresponding operating system functionality.
• KMD 1 10 implements an application program interface (API) through which CPU 102, or applications executing on CPU 102 or other logic, can invoke APD 104 functionality.
• API application program interface
• KMD 1 10 can enqueue commands from CPU 102 to command buffers 125 from which APD 104 will subsequently retrieve the commands.
• KMD 1 10 can, together with SWS 1 12, perform scheduling of processes to be executed on APD 104.
• SWS 1 12, for example, can include logic to maintain a prioritized list of processes to be executed on the APD.
• SWS 1 12 maintains an active list 152 in memory 106 of processes to be executed on APD 104.
• SWS 112 also selects a subset of the processes in active list 152 to be managed by HWS 128 in the hardware.
• Information relevant for running each process on APD 104 is communicated from CPU 102 to APD 104 through process control blocks (PCB) 154.
• PCB process control blocks
• Processing logic for applications, operating system, and system software can include commands specified in a programming language such as C and/or in a hardware description language such as Verilog, RTL, or netlists, to enable ultimately configuring a manufacturing process through the generation of maskworks/photomasks to generate a hardware device embodying aspects of the invention described herein.
• a programming language such as C
• a hardware description language such as Verilog, RTL, or netlists
• computing system 100 can include more or fewer components than shown in FIG. 1A.
• computing system 100 can include one or more input interfaces, nonvolatile storage, one or more output interfaces, network interfaces, and one or more displays or display interfaces.
• FIG. IB is an embodiment showing a more detailed illustration of APD 104 shown in FIG. 1A.
• CP 124 can include CP pipelines 124a, 124b, and 124c.
• CP 124 can be configured to process the command lists that are provided as inputs from command buffers 125, shown in FIG. 1A.
• CP input 0 (124a) is responsible for driving commands into a graphics pipeline 162.
• CP inputs 1 and 2 (124b and 124c) forward commands to a compute pipeline 160.
• controller mechanism 166 for controlling operation of HWS 128.
• graphics pipeline 162 can include a set of blocks, referred to herein as ordered pipeline 164.
• ordered pipeline 164 includes a vertex group translator (VGT) 164a, a primitive assembler (PA) 164b, a scan converter (SC) 164c, and a shader-export, render-back unit (SX/RB) 176.
• VCT vertex group translator
• PA primitive assembler
• SC scan converter
• SX/RB shader-export, render-back unit
• Each block within ordered pipeline 164 may represent a different stage of graphics processing within graphics pipeline 162.
• Ordered pipeline 164 can be a fixed function hardware pipeline.
• Graphics pipeline 162 also includes DC 166 for counting through ranges within work-item groups received from CP pipeline 124a. Compute work submitted through DC 166 is semi-synchronous with graphics pipeline 162.
• Compute pipeline 160 includes shader DCs 168 and 170. Each of the DCs is configured to count through compute ranges within work groups received from CP pipelines 124b and 124c.
• the DCs 166, 168, and 170, illustrated in FIG. IB receive the input ranges, break the ranges down into workgroups, and then forward the workgroups to shader core 122.
• graphics pipeline 162 is generally a fixed function pipeline, it is difficult to save and restore its state, and as a result, the graphics pipeline 162 is difficult to context switch. Therefore, in most cases context switching, as discussed herein, does not pertain to context switching among graphics processes. The exception is for graphics work in shader core 122, which can be context switched.
• Shader core 122 can be shared by graphics pipeline 162 and compute pipeline
• Shader core 122 can be a general processor configured to run wavefronts.
• shader core 122 runs programmable software code and includes various forms of data, such as state data.
• Compute pipeline 160 does not send work to graphics pipeline 162 for processing.
• the completed work is processed through a render back unit 176, which does depth and color calculations, and then writes its final results to graphics memory 130.
• simulation, synthesis and/or manufacture of the various embodiments of this invention may be accomplished, in part, through the use of computer-readable code (as noted above), including general programming languages (such as C or C++), hardware description languages (HDL) including Verilog HDL, VHDL, Altera HDL (AHDL) and so on, or other available programming and/or schematic capture tools (such as circuit capture tools).
• general programming languages such as C or C++
• HDL hardware description languages
• AHDL Altera HDL
• circuit capture tools such as circuit capture tools
• This computer-readable code can be disposed in any known computer usable medium including semiconductor, magnetic disk, optical disk (such as CD-ROM, DVD- ROM) and as a computer data signal embodied in a computer-usable (e.g., readable) transmission medium (such as a carrier wave or any other medium including digital, optical, or analog-based medium).
• a computer-usable (e.g., readable) transmission medium such as a carrier wave or any other medium including digital, optical, or analog-based medium.
• the code can be transmitted over communication networks including the
• Embodiments of the present invention allow programmers to write applications that seamlessly transition processing of data between CPUs and APDs, benefiting from the best attributes each has to offer.
• a unified single programming platform can provide a strong foundation for development in languages, frameworks, and applications that exploit parallelism.
• the embodiments of the present invention allow programmers to write applications that seamlessly transition processing of data between CPUs and APDs, benefiting from the best attributes each has to offer.
• a unified single programming platform can provide a strong foundation for development in languages, frameworks, and applications that exploit parallelism.
• FIG. 2 is an illustrative block diagram 200 of an optimized communication process between an APD and a CPU for syscall requests.
• Block diagram 200 includes a wavefront 136, a SIMD vector 208, and a queue 210.
• Wavefronts 136 are processed sequentially by shader cores 122. Each wavefront includes multiple work items 204. Each work item 204 is assigned a task or a portion of a task to process. Shader core 122 processes work items 204 in wavefront 136 in parallel and with the same set of instructions. As a result, each work item 204 in wavefront 136 may issue a syscall to CPU 102 at the same time.
• SIMD vector 206 includes SIMD elements 208.
• Each SIMD elements includes a syscall data structure.
• the syscall data structure includes a function selector parameter (a particular syscall request), a list of arguments, and a memory space to return a result of the syscall request to APD 104.
• function selector parameter a particular syscall request
• list of arguments a list of arguments
• a memory space to return a result of the syscall request to APD 104.
• APD 104 stores a syscall request from each work item 204 in a corresponding SIMD element 208.
• work item WI1 stores syscall SCI in SIMD element 208
• work item WI 1 stores syscall SC2 in another SIMD element 208
• APD 104 saves the type of the syscall request from each work item 204 into the function selector parameter.
• APD 104 can also insert a list of arguments in the argument list section, if needed.
• APD 104 can also store syscalls from work items from multiple wavefronts 136 in one SIMD vector 206.
• Queue 210 is a high-priority public memory queue.
• a queue operates according to the fnst-in, first-out ("FIFO") principle.
• a public queue is a queue visible to CPU 102 and APD 104 processors. Namely, the workload that are first enqueued onto a queue, is the workload that are first dequeued from a queue.
• FIFO fnst-in, first-out
• APD 104 enqueues queue 210 with SIMD vector 206. After APD 104 enqueues
• SIMD vector 206 in one embodiment APD stalls and waits for CPU 102 to process SIMD vector 206 (i.e., receive the SIMD vector 206, process the syscalls stored therein and transmit the results of each syscall to APD 104). In another embodiment, after APD 104 enqueues queue 210, APD 104 saves the state of the wavefront in memory 106 and begins to process another wavefront. When APD 104 receives a signal from CPU 102 that the processing is complete, APD 104 retrieves the original wavefront 136 from memory 106 and reinstates the processing.
• CPU 102 processes tasks received form a high-priority queue ahead of its other processes.
• CPU 102 receives a request from a high-priority queue, such as queue 210, it saves its current process and processes the received request.
• a high-priority queue such as queue 210
• the example using a high-priority public queue described herein is given by way of example, and not limitation, and a person skilled in the art will appreciate that other memory storage structures can be used.
• CPU 102 dequeues SIMD vector 206 from queue 210 and begins to processes
• CPU 102 invokes an OS and begins to processes the syscall requests stored in the function selector parameter in each SIMD element 208.
• CPU 102 also reads the argument list stored in SIMD element 208, if required. After CPU 102 completes each syscall request, CPU 102 writes the result into a memory address allocated in each SIMD element 208.
• CPU 102 After CPU 102 completes processing all SIMD elements 208, in one embodiment, it enqueues SIMD vector 206 onto a queue 210 and returns SIMD vector 206 to APD 104. Typically, CPU 102 enqueues SIMD vector 206 onto a memory queue 210 that is visible to APD 104.
• CPU 102 when CPU 102 completes processing SIMD vector 206, it sends a signal to APD 104 using a semaphore mechanism.
• a semaphore mechanism ensures that APD 104 does not process other wavefronts while it waits for CPU 102 to complete processing requested syscalls.
• APD 104 After APD 104 dequeues SIMD vector 206 or receives a signal from CPU 102 that syscalls were processed, APD 104 begins to process the wavefront 136 using the results of the requested syscall. In an embodiment where APD 104 can process another wavefront while waiting for CPU to process SIMD vector 206, APD 104 retrieves wavefront 136 from APD memory 130, prior to continuing processing.
• a syscall can be a request for memory, such as a malloc() function.
• a malloc() request allocates memory for a particular process or function in system memory 106.
• APD 104 cannot process a malloc() request because APD 104 does not have access to an OS.
• APD 104 therefore, sends a syscall for a malloc() request to CPU 102.
• APD 104 makes a malloc() request when work item 204 in wavefront 136 requests memory.
• APD 104 sends one SIMD vector 206 to CPU 102 that includes a malloc() request for each working item 204 in wavefront 136.
• APD 104 stores information necessary for a malloc() request for each work item in a corresponding SIMD element 208.
• the necessary information includes a function selector, which is a memory address to the malloc() function, a list of arguments, which includes a memory size that CPU 102 needs to allocate to each work item 204, and an empty parameter where CPU 102 stores the address of the allocated space.
• APD 104 enqueues SIMD vector 206 onto queue 210 as described herein.
• CPU 102 retrieves SIMD vector 206 from queue 210, and begins to process SIMD elements 208.
• CPU 102 processes the mallocQ requests in SIMD vector 206, CPU 102 makes one call to the OS.
• CPU 102 then proceeds to allocate memory for each work item 204 in the call to OS. Subsequently, CPU 102, stores the address to the memory space allocated for each work item 204 in SIMD element 208. After CPU 102 completes all syscall requests, CPU 102 returns the SIMD vector 206 to APD 104.
• SIMD elements 208 include multiple structures for passing syscalls to CPU 102.
• each SIMD element 208 can include a data structure for storing the function selector parameter, the argument list, and the result of the syscall.
• an exemplary data structure is described as:
• myCPUCodePtr pointer to code (e.g., x86 binary format)
• myAPDCodePtr pointer to code (e.g., x86 binary format)
• the MyTask structure includes a MyPtr myAPDCodePtr pointer for processing instructions on APD 104, a MyPtr myCPUCodePtr pointer for processing instructions on CPU 102, and a data pointer myPtr myDataPtr.
• work item 204 requests a syscall from CPU 102
• the myAPDCodePtr and myCPUCodePtr pointers point to the memory address of a particular syscall function.
• the mtDataPtr pointer includes parameters for the argument list and a pointer to the memory address in main memory 106 that contains the result of each syscall.
• the MyTask structure includes an MyNotification mechanism.
• APD MyNotification mechanism
• CPU 104 uses the notification mechanism to notify CPU 102 that MyTask exists in queue 1 10 that requires processing. Similarly, CPU 102, uses the MyNotification to notify APD 104 that CPU 102 completed processing the syscall.
• FIG. 3 is an illustrative flowchart 200 of system 100 processing a syscall request using SIMD vector 206.
• APD 104 initializes SIMD vector 206 when work items 204 in wavefront 136 request a syscall that requires processing using CPU 102.
• each work item 204 stores information necessary for processing a syscall request into a corresponding SIMD element 208 as described herein.
• APD 104 enqueues SIMD vector 206 onto queue 210.
• CPU 102 dequeues SIMD vector 206 from queue 210.
• CPU 102 After CPU 102 dequeues SIMD vector 206, CPU 102 invokes the OS and begins to process a syscall in each SIMD element 208. [0098] At step 310, CPU 102 writes the result of each syscall into SIMD element 208. A person skilled in the art will appreciate that step 310 may be performed with step 308. At step 312, CPU 102 notifies APD 104 that syscalls have been processed. In one embodiment, CPU 102 sends the SIMD vector 206 back to APD 104, using queue 210 visible to APD 104. In another embodiment, CPU 102 signals APD 104 using a semaphore. At step 314, APD 104 dequeues SIMD vector 206 from queue 210 and continues to process wavefront 136.
• FIG. 3 Various aspects of the present invention can be implemented by software, firmware, hardware, or a combination thereof.
• the methods illustrated by flowchart 300 of FIG. 3 can be implemented in unified computing system 100 of FIG. 1.
• Various embodiment of the invention are described in terms of this example unified computing system 100. It would be apparent to a person skilled in the relevant art how to implement the invention using other computer systems and/or computer architectures.
• Computer program medium and “computer-usable medium” are used to generally refer to media such as a removable storage unit or a hard disk drive.
• Computer program medium and computer-usable medium can also refer to memories, such as system memory 106 and graphics memory 130, which can be memory semiconductors (e.g., DRAMs, etc.).
• system memory 106 and graphics memory 130 can be memory semiconductors (e.g., DRAMs, etc.).
• the invention is also directed to computer program products comprising software stored on any computer-usable medium.
• Such software when executed in one or more data processing devices, causes a data processing device(s) to operate as described herein or, as noted above, allows for the synthesis and/or manufacture of computing devices (e.g., ASICs, or processors) to perform embodiments of the present invention described herein.
• Embodiments of the invention employ any computer-usable or -readable medium, known now or in the future.
• Examples of computer-usable mediums include, but are not limited to, primary storage devices (e.g., any type of random access memory), secondary storage devices (e.g., hard drives, floppy disks, CD ROMS, ZIP disks, tapes, magnetic storage devices, optical storage devices, MEMS, nanotechnological storage devices, etc.), and communication mediums (e.g., wired and wireless communications networks, local area networks, wide area networks, intranets, etc.).
• primary storage devices e.g., any type of random access memory
• secondary storage devices e.g., hard drives, floppy disks, CD ROMS, ZIP disks, tapes, magnetic storage devices, optical storage devices, MEMS, nanotechnological storage devices, etc.
• communication mediums e.g., wired and wireless communications networks, local area networks, wide area networks, intranets, etc.

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