WO2012082360A2 - Iddq testing of cmos devices - Google Patents
Iddq testing of cmos devices Download PDFInfo
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- WO2012082360A2 WO2012082360A2 PCT/US2011/062435 US2011062435W WO2012082360A2 WO 2012082360 A2 WO2012082360 A2 WO 2012082360A2 US 2011062435 W US2011062435 W US 2011062435W WO 2012082360 A2 WO2012082360 A2 WO 2012082360A2
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. by varying supply voltage
- G01R31/3004—Current or voltage test
- G01R31/3008—Quiescent current [IDDQ] test or leakage current test
Definitions
- Embodiments of the invention generally relate to the field of testing of semiconductor devices and, more particularly, to a method, apparatus, and system for IDDQ testing of CMOS devices.
- testing has practical limitations. If a manufacturer or lab cannot test semiconductor devices quickly, accurately, and at reasonable cost, then the testing will not be possible.
- IDDQ testing is a current-based test method and is known to be effective for detecting faults that can be missed by commonly used structural tests such as stuck- at and delay tests. Such testing measures the supply current (Idd) in a quiescent state via various processes. IDDQ testing may be effective for larger scale devices, such as 0.18 ⁇ or larger CMOS, where the leakage current is significantly smaller than the modeled defect current.
- nanometer process tend to increase because of required test complexity.
- the nanometer process offers performance improvement and a greater number of transistors to be implemented on each die, but also introduces new failure mechanisms that require testing. In order to cope with increasing test cost, less expensive test alternatives are very useful.
- the effectiveness of IDDQ testing of nanometer devices is made difficult by increased leakage currents and their variations across wafers.
- a method and apparatus are provided for IDDQ testing of CMOS devices.
- an embodiment of a method includes applying a test pattern of inputs to a device, the device including one or more CMOS
- each of the current measurements being a measurement of a current after applying an input of the test pattern to the device.
- a filter function is applied to the current
- the filter function including separating defect current values from the current measurements, and a determination is made whether a defect is present in the device based at least in part on a comparison of the defect current values with a threshold value.
- an embodiment of a test apparatus includes an interface for a device under test, the interface being used to apply a set of inputs to a device containing one or more CMOS devices, and logic to apply a test pattern of inputs to the device under test.
- the apparatus further includes a current measurement unit to measure a current of the device for each input of the set of inputs, logic to separate defect current from the measured currents including application of a noise filter function to the current measurements, and logic to determine existence of a defect in the device under test based at least in part on the defect current.
- Figure 1 is an illustration of a non-defective CMOS inverter circuit
- Figure 2 is an illustration of a defective CMOS inverter circuit for detection by an embodiment of a fault detection method, apparatus, or system;
- Figure 3 is a flowchart to illustrate an embodiment of a process for IDDQ testing of advanced devices
- Figure 4 is an illustration of the application of a filter function in an embodiment of a determination of a current
- Figure 5A and 5B illustrate noise filter functions utilized in an embodiment of a defect current detection process, apparatus, or system;
- Figures 6A and 6B illustrate a measured current function and filter function in an embodiment of a process for extraction of a defect current;
- Figure 7 illustrates an embodiment of convolution in a method to recover or extract defect current
- Figure 8 illustrates multiple filter functions applied in series in an
- Figure 9 is an illustration of defect and noise currents addressed in an embodiment of defect current detection
- Figure 10 is an illustration of an embodiment of a method for application of filtering to current measurements
- Figures 11A and 11B illustrate random filter function generation in an embodiment of defect current detection
- Figure 12 illustrates a recurrence equation for an embodiment of a method, apparatus, or system providing defect current detection
- Figure 13 illustrates a filter function for higher order k defined using convolution for an embodiment of a method, apparatus, or system providing defect current detection
- Figure 14 illustrates calculation of coefficients in an embodiment of a process for defect current detection
- Figure 15 illustrates a filter function for an embodiment of detection of defect currents
- Figure 16 illustrates an embodiment of an apparatus or system for the detection of defective components utilizing IDDQ measurements.
- Embodiments of the invention are generally directed to IDDQ testing of CMOS devices.
- IDDQ means testing of semiconductor devices including the measurement of leakage current (I DD ) in a quiescent state.
- an apparatus, system, and method provide for IDDQ testing of semiconductor devices in which testing includes separation of leakage current from intended IDDQ current.
- a novel IDDQ test method is provided for nanometer IC designs.
- an IDDQ test method may be utilized to mitigate the difficulty of testing in presence of large leakage current and its significant variation across wafers.
- an IDDQ test method is provided for IC devices fabricated in advanced manufacturing processes, in which there may be increased leakage current and process variation.
- an IDDQ test system is implemented to mitigate difficulties in IDDQ testing in the presence of high leakage current and significant variation between devices.
- a testing process includes removal of common leakage currents from measured values, while detected defect currents are amplified.
- the amplified defect current may then be further amplified by current aggregation to assist in separating good circuits from defective circuits.
- an IDDQ testing method is provided to increase the observability of a defect current that is captured in a small set of IDDQ current measurements, without requiring the measurement of additional currents using the current test or automatic test equipment (ATE).
- a testing method and system applies signal and system theory to an IDDQ test.
- An embodiment of a testing method considers measured currents as input signals and the leakage current reduction function as a system. When the input signals are applied to the system, output of system can be described by convolution of input signals and the leakage reduction function.
- a method reduces the leakage effect and amplifies the defect current buried in the measured current by the reduction function via the convolution, where the defect current may be further amplified by aggregation of amplified defect current resulting from convolution, the convolution involving a sum of products of signal components that constitute input signals and the reduction function.
- a current may be measured by ATE (Automatic Test Equipment) or other apparatus or system by sensing an IDDQ current at a steady state after a test pattern is applied.
- ATE Automatic Test Equipment
- the test time that is expended for IDDQ testing is dominated by the time required for current measurement at the tester or ATE.
- the time that is required to compute convolution and aggregation generally will be insignificant compared to the IDDQ current measurement time, and thus the value determinations may be carried out concurrently with the current measurements.
- the measured IDDQ current may be considered to be a composite electrical quantity whose components are interpreted as a "signal component” and a "noise component".
- the signal component denotes the wanted component of the current, and the noise component the unwanted component.
- the leakage current constitutes the noise component and the defect current constitutes the signal component.
- a set of non-zero signal and noise components may be defined as a function by assuming zero everywhere else, which may be expressed with the notation f(k).
- the measured current and the noise current can similarly be denoted as I m (k) and I c (k), respectively.
- an IDDQ method is provided to target the defect currents caused by manufacturing defects, such as shorts and opens on transistors, in advanced process devices. Catastrophic failures that occur in such devices, such as power and ground short defects, can immediately be detected from any current measurement, but other defect currents are more subtle and may be lost in the current variation of such devices.
- FIG. 1 is an illustration of a non-defective CMOS inverter circuit 102.
- Figure 2 is an illustration of a defective CMOS inverter circuit 202 for detection by an embodiment of a fault detection method, apparatus, or system.
- input voltage 104 in Figure 1 and 204 in Figure 2
- the NFET N-type field effect transistor
- the PFET P-type field effect transistor
- CMOS circuit If the input voltage (104, 204) is biased to ⁇ ', however, the PFET (108, 208) and NFET (106, 206) are turned on and off respectively, producing a logical T at the output (116, 216).
- An ideal current characteristic of a CMOS circuit would theoretically allow current to flow during output transition, for example, from logical T to ' ⁇ ', with no current flowing when the output reaches steady state. In actual operation, however, a small current flows through a CMOS transistor at steady state. This small current is the "leakage current", and the amount of the leakage current depends on the resistance of the transistors that are turned on and off.
- the leakage current (leakage) 112 of a device under test (DUT) may be obtained by adding the currents from all leakage paths in the DUT.
- SOC system-on-chip
- Each logic gate may, for example, be considered to be an independent leakage path. For this reason, the total leakage current of a circuit with potentially millions of gates can be substantially large.
- an implementation of an IDDQ test may target faults in the turned-off transistors of a device under test.
- a set of input stimuli referred to as a test pattern, may be employed to turn on and off different subsets of transistors in the circuit.
- the resistance R Q ff then will act to reduce current flow during a steady state.
- the IDDQ defect can change resistance at steady state, and allow a significantly larger current than would be expected to flow from power source (V DD ) (110, 210) to ground.
- a short defect 220 is present in the PFET 206 as shown in Figure 2, the PFET 206 is turned on permanently and the resistance is changed permanently to R on .
- other defects such as gates that remain open, can cause transistors to be partially turned on.
- the resistance of partially turned on transistors can be larger than R on but still significantly smaller than R Q ff.
- the NFET 208 is turned on by forcing input stimulus Vin- ⁇ , a large current can flow from V DD 210 to ground at steady state.
- Such defect currents (Idefect) 222 can similarly be estimated with, for example, Idefect being estimated as V DD divided by twice R on , as shown in Figure 2.
- Figure 2 also illustrates the currents graphically.
- Vj n is a logical T value 230 and V ou t 232 thus is ' ⁇ '
- the steady state IDDQ current for a defect-free device will drop to, for example, a steady state current level 236.
- the steady state current will remain high, such as illustrated by current level 234.
- FIG. 3 is a flowchart to illustrate an embodiment of a process for IDDQ testing of advanced devices.
- a semiconductor device is connected to a testing apparatus or system as the device under test (DUT) 302.
- DUT device under test
- a current test is applied to the DUT, but other testing may be provided together with such current testing.
- a determination is made regarding a noise filter function to apply to current measurements 304, where such determination may be made in the design of the testing apparatus or system.
- a test pattern for current testing of the DUT is generated and applied to the DUT 306. As a result of such test pattern, currents at steady state are measured from the DUT 308.
- the chosen filter is applied to the current measurements 310, where such application results in the convolution of the current measurements 312 and the aggregation of defect current measurements 314, resulting in separating the defect current measurements from leakage current measurements 316.
- the defect current is then compared to a threshold value 318. If the defect current is greater than the threshold value 320, then the DUT may be determined to be defective and rejected 322. If the defect current is not greater than the threshold value 320, then there is no determination of defectiveness of the DUT, and testing of the DUT may continue with any additional testing planned for the device 324.
- the measured current for test pattern k at steady state may include a defect current and a total leakage current I c (k) contributed from all leakage current paths in the circuit.
- the I m (k) can be obtained by measuring IDDQ current after applying the k th test pattern.
- the increased IDDQ current that is due to defects can be defined as a(k) I sat , where a(k)e R denotes a current contribution factor from defects.
- the defect current is modeled with a PFET (or NFET) saturation current, and is measured in units of the same saturation current.
- the I c (k) may be estimated by adding leakage currents from all leakage paths in the DUT.
- a process is implemented to reduce the effect of I c (k) so that defect current is more observable.
- a common noise filter function is provided to reduce the effect of I c (k) and to amplify defect currents to provide improved observability.
- An embodiment of a process further improves observability by aggregation of amplified defect currents.
- FIG 4 is an illustration of the application of a filter function in an embodiment of a determination of a current.
- the response of the filter function may be described by the convolution 430 as shown in Figure 4.
- a weighted summation may be employed instead of convolution.
- the weighted summation may be viewed as a moving average without division.
- the summation window size may be determined by the non-zero components of the filter function.
- the magnitude of the non-zero components of the filter function may be considered as weight values to be assigned to the current measurements for summation.
- the convolution may also be viewed as a weighted summation with the weight f(n-k) for c(k).
- Figure 5A and 5B illustrate noise filter functions utilized in an embodiment of a defect current detection process, apparatus, or system. As illustrated, only non-zero signal components are shown, and zeros may be assumed elsewhere. It can be shown that the filter functions 510 and 520 are possible solutions to the convolution equation 430 illustrated in Figure 4, and thus that these filter functions satisfy the filter function criteria.
- the noise current effect may be reduced as the number of current measurements involved in a convolution increases or as non-zero components in f(k) increases.
- the increased number of f(k) components may operate to cancel out more noise components during convolution operations.
- Figure 6 and Figure 7 illustrate an embodiment of a process for extraction of a defect current.
- Figures 6A and 6B illustrate a measured current function I m (k) 610 and filter function f(k) 620 in an embodiment of a process for extraction of a defect current.
- F 0 denotes the number of non-zero components in the filter function.
- the F 0 of filter function f(k) 620 for example, is 3.
- the measured current signal I m (k) in Figure 6 may be constructed as follows:
- I m (0) is assigned to I m (k) for k ⁇ 0.
- I m (k) is assigned to I m (k) for k ⁇ 0.
- Figures 7 illustrates an embodiment of convolution in a method to recover or extract defect current.
- an extracted defect current may be compared with a test limit or threshold to determine whether the DUT is deemed to be defective.
- a process includes performing a convolution operation of I m (k) with f(k) to observe defect current. In this example, convolution is performed in a range of
- common noises are removed by f(k) and the defect current I sat is amplified.
- An absolute value of a convolution is taken in order to recover a magnitude of a defect current.
- convolution with the filter function is employed to amplify the defect currents and to remove common noise current.
- the common noise current is not zero.
- a filter function may be utilized to indicate a validity condition of defect current extraction. For example, if the noise current of the left and right neighbor points are closer to twice of the middle, then more defect current may be observed.
- the noise effect II C (4) -2I C (5) +I C (6)I can be significantly smaller than 2*I sat . If the validity condition does not hold, the f(k) may include a larger number of non-zero
- Figure 8 illustrates multiple filter functions applied in series in an
- the filter functions f(k) and g(k) in system 810 may include the functions illustrated in Figure 5, which may be utilized with an assumption that q > 1 and r > 1.
- the filter functions f(k) and g(k) may be the same or different function, or may be any number of other filter functions.
- I(j) an intermediate current function that can be obtained from convolution of I m (k) with f(k)
- the example depicted in example (a) 710 may be applied.
- the filter function g j) may be applied to further amplify the amplified current in I(n) 820.
- defect current can further be amplified by aggregating amplified currents whose amplitude is above a certain threshold denoted as 5I sat , where ⁇ is a real number.
- the aggregated current may be denoted as I A and can also be measured in units of I sat , i.e. lsat units.
- the lsat measures how many saturation currents there are in I A .
- I A [0057]
- the calculation of I A involves conditional summation of l(I m *f)(n)l for all n.
- the amplified currents larger than the threshold 5I sat are added to I A .
- a single defect current in the I m (k) presented in Figure 6, element 610 is amplified 12 times by the convolution and aggregation.
- unfiltered noise currents included in the amplified currents with amplitudes that are either below or above threshold amounts are removed or and the remaining noise currents are averaged out respectively during aggregation.
- Figure 9 is an illustration of defect and noise currents addressed in an embodiment of defect current detection. If a noise current can be reduced, the difference between defect current and noise current increases as increased numbers of current
- a process may be implemented to increase n without measuring additional currents. Measuring current can be an expensive operation in terms of test time, which can greatly increase total test costs.
- the increase in n may be achieved by one or more of the following approaches: permutation of measured current function; and employment of multiple filter functions. Such approaches are based on the observation that the result of a convolution operation is order sensitive. If components of the original measured current function were reordered, convolution operated on the reordered measured currents can produce a different result.
- the function I m (k) thus may be extended by concatenating the original current measurements with the reordered or permutated ones. If a defect current was captured in the original current measurements, it can be amplified more in the extended measured current function I m (k).
- convolution l(I m *f)(n)l can be operated on 40 current measurements instead of 10.
- concatenation of permutations may be utilized to significantly increase the I A , and assist to differentiate defective parts from defect-free parts, as illustrated in Figure 9.
- amplification by convolution on reordered current measurements using the same filter function may similarly be achieved by convolution on the original current function using multiple filter functions.
- multiple filter functions operated in parallel may be employed to mimic the role of different permutations.
- a set of different filter functions may similarly be obtained from permutation of original filter function.
- Figure 10 is an illustration of an embodiment of a method for application of filtering to current measurements.
- a set of filter functions may convolute with the original measured current function in parallel, such as shown in element 1010 in Figure 10.
- the aggregation method is as illustrated in Figure 8, with filter function f x (k) denoted as I A,x .
- Each aggregated current can be added 1020 to produce the total aggregated current I A 1030.
- the aggregated currents can also be combined using other operations instead of summation.
- an advantage of employing multiple filter functions may be that both convolution and aggregation can concur with current measurement at automatic test equipment (ATE).
- ATE automatic test equipment
- both convolution and aggregation may simultaneously be performed.
- amplified defect currents by different filter functions may, for example, be tested for defect at every step of convolution. Further, at the end of convolution, the I A value can immediately be available. In some embodiments, if the current I A is significantly larger than expected, the DUT may be determined to be defective.
- noise current reduction is dependent upon the filter function that is utilized.
- embodiments are not limited to a certain filter function or approach to generating such filter function. Numerous qualified filter functions satisfy the criteria illustrated in Figure 4, and multiple different approaches to generate filter functions that satisfy such criteria.
- filter function generation may be based on random number generation and an n-th order ⁇ recurrence equation.
- a filter function obtained from random numbers referred to as random filter function, may be utilized to reduce or smooth out noise currents while amplifying the defect current.
- a filter function that is based on an n-th order recurrence equation can reduce noise current and amplify the defect current through the higher order difference operations.
- the recurrent filter function may be utilized to amplify the defect current by more than 2 k times.
- filter functions obtained from two different approaches may be applied one after another, as illustrated in Figure 8, in order to amplify defect currents.
- the random filter function can be applied to the current measurements to amplify the defect current and to smooth out noise currents.
- the recurrent filter function can be applied to the amplified current signal that results from convolution of measured current with the random filter function. For example: Input: array H(N 0 ) (H(n) > Ofor 0 ⁇ n ⁇ N 0 ) [5]
- Figures 11A and 11B illustrate random filter function generation in an embodiment of defect current detection.
- the generation of a random filter function accepts an input of a one-dimensional array H(No) of size No and produces the function f(k).
- each element of an array of H(n) can provide the 2H(n) number of non-zero f(k) components.
- an amplification factor denoted as A
- rand a random number generation function
- the amplification factor may be assigned to f(h) and to f(h+H(n)) with the sign of the amplification factor inverted.
- the obtained filter functions can amplify defect currents during convolution while reducing noise currents buried in the measured currents.
- selection of filter function may improve amplification in I A and observability of defect currents. Further, inclusion of both even and odd number in H(No) can increase observability of defect currents if amplification is uniform.
- amplification is uniform if the same magnitude of amplification factor is used in the f(k).
- the magnitude of amplification factor may be defined as an absolute value of the amplification factor A, denoted as IAI. If both even and odd numbers were included in the H(N 0 ), the defect currents may be observed regardless of whether they are odd or even number of measurements apart. Thus, such currents can be observed more often and amplified in aggregation. For example, when defect currents are captured in the measured currents I m (j) and I m (j+D) where D is odd, those defect currents may not be observed if the filter function 1110 shown in, for example, Figure 11 A is employed. The same defect currents, however, may not be masked if the amplification in the filter function 1110 shown in Figure 11A is non-uniform, or if the filter function 1120 shown in Figure 11B is employed.
- a process can generate the filter functions with both uniform and non-uniform amplifications by providing min and max to the function rand(min, max, -0).
- the filter function f(k) can also be generated using an n-th order ⁇ recurrence equation. Generation of the f(k) using n-th order ⁇ recurrence equation is illustrated in Figure 12 , Figure 13, and Figure 14. In some embodiments, the n-th delta recurrence equation amplifies defect current through the higher order of recurrence relations, while reducing noise current effect from the satisfied filter function criteria.
- Figure 12 illustrates a recurrence equation for an embodiment of a method, apparatus, or system providing defect current detection.
- ⁇ ⁇ ( ⁇ ( ⁇ )) is expressed recursively as ⁇ ⁇ _1 ( ⁇ ( ⁇ )) - ⁇ ⁇ _1 ( ⁇ ( ⁇ -1)).
- the resulting filter function may be a finite difference equation with coefficients 1, -2, 1.
- Figure 6B illustrates the resulting filter function.
- all common noise current components are removed while the defect current is amplified by factor of 2.
- Such amplification is due to the fact that the proposed recurrence equation can extract defect current with respect to both left and right side neighbor signal components. If the amplification factor were larger, the amplified defect current would then be higher. In such calculation, a constraint is that the noise current is required to be reduced simultaneously.
- Figure 13 illustrates a filter function for higher order k defined using convolution for an embodiment of a method, apparatus, or system providing defect current detection.
- the filter function fi may be used to generate n-th order filter function by convoluting fi with f n-1 .
- fi combined with convolution may be considered as an increment operator denoted as inc.
- the filter function fi may be referred to as an operator function.
- the operator increments the filter function order.
- the filter function f n may be obtained by applying the operator n times.
- Figure 14 illustrates calculation of coefficients in an embodiment of a process for defect current detection. From an operator function point of view, as shown in Figure 14, calculation 1410 of coefficients for the n-th order ⁇ recurrence equation (illustrated as Delta recurrence equation 1420) is identical to that of Pascal's triangle 1430 to find coefficients in the binomial expansion of (-x+y) n .
- Pascal's triangle may also be also be generated by convolution as provided in Figure 13 or by the inc operator with operator function as provided in Figure 13.
- Pascal's triangle is a geometrical arrangement of the binomial coefficients in a triangle and is often generated from binomial expansion using combination, which involves a factorial.
- the convolution approach for generation of coefficients may be more efficient and provide a more intuitive operation from a computational point of view.
- I m (n) measure current from ATE
- the IDDQ test procedure allows convolution and aggregation to be concurrent with current measurement at ATE.
- Each current measurement is tested for power short catastrophic defect.
- defect current caused by a power short can be very significant and noticeable immediately. If the device under test (DUT) is free of catastrophic power defects, each measured current at the tester can be used to construct measured current function I m (n).
- the IDDQ test procedure assumes Mo number of current measurements and M 0 > F 0 . If (F 0 -2)-th current measurement are available, the current measurements from 0-th to (F 0 -2)-th (denoted as I m [0:F 0 -2]) or its permutation may be copied to the I m [M 0 :Mo+F 0 -2].
- the I m (Mo+Fo-2) can be assigned to the I m (n) for all n ⁇ Mo+Fo-2, if needed.
- Figure 15 illustrates a filter function for an embodiment of detection of defect currents.
- convolution and aggregation on the appended current measurements I m [Mo:Mo+Fo-2] may be carried out in advance so that both convolution and aggregation can be completed when the last current measurement I m (Mo-l) is available.
- the filter function is known, such as the example illustrated in Figure 15, partial convolution and aggregation may be performed in advance for I m [M 0 :Mo+F 0 -2] and completed when the needed current measurements are available.
- the f(0) and I m (5) which is I m (0) can be multiplied in advance and wait for I m (4]) x f(l) and I m (3) x f(2) to complete convolution and aggregation. In this manner, the required multiplication and addition may be carried out as soon as the measured current is available from the tester.
- the sum of two products I m (5) x f(l) and I m (6) x f(0) may be calculated when I m (0) and I m (l) are available and convolution can be completed when the final current I m (Mo-l) is measured.
- the IDDQ procedure may be extended to accommodate multiple filter functions, such as, for example, functions illustrated in Figures 8 and 11.
- the same IDDQ test procedure can recursively be applied to I(n) as if it were I m (n) until all filter functions are applied.
- the IDDQ procedure can be applied to f(k) and I m [0:M o -l] in order to obtain I(n) which can be considered as I m [0:Mo'-l].
- the IDDQ procedure may again be applied to I(n) and g(j) in order to obtain a test result.
- step 2.2 of Equation [8] may be duplicated for multiple filter functions.
- each aggregated current may be summed up before proceeding to step 3 of Equation [6] .
- step 3 may be duplicated to check the test limit for each individual aggregated current I A,X separately before the currents are summed up to produce the total aggregate current I A .
- FIG. 16 illustrates an embodiment of an apparatus or system for the detection of defective components utilizing IDDQ measurements.
- a testing apparatus or system 1600 is couple with a device under test (DUT) 1650.
- the DUT 1650 may include a semiconductor device generated using advanced manufacturing processes, such as such a 0.13 ⁇ or smaller device, but embodiments are not limited to the testing of any particular device.
- the testing apparatus or system 1600 includes logic to create test patterns 1610 for the testing of the DUT 1650.
- the generated test patterns may include patterns to apply quiescent current in order to measure currents in paths though transistor devices in the DUT 1650.
- the testing apparatus or system 1600 further includes an input interface 1620 to provide the generated test patterns to the DUT 1650.
- the testing apparatus or system 1600 further includes a module or unit for measurement of currents 1630 for the DUT 1650.
- the current measurements are used by a logic for current defect detection 1640.
- the module operates to remove common leakage currents from measured values, while amplifying detected defect currents, including use of current aggregation.
- the apparatus or system 1600 utilizes the detection of defect currents to make a determination whether or not the DUT 1650 is defective.
- Various embodiments of the present invention may include various processes. These processes may be performed by hardware components or may be embodied in computer program or computer-executable instructions, which may be used to cause a general-purpose or special-purpose processor or logic circuits programmed with the instructions to perform the processes. Alternatively, the processes may be performed by a combination of hardware and software.
- Portions of various embodiments of the present invention may be provided as a computer program product, which may include a non-transitory computer-readable storage medium having stored thereon computer program instructions, which may be used to program a computer (or other electronic devices) to perform a process according to the embodiments of the present invention.
- the computer-readable medium may include, but is not limited to, floppy diskettes, optical disks, compact disk read-only memory (CD-ROM), and magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically-erasable programmable read-only memory (EEPROM), magnet or optical cards, flash memory, or other type of computer-readable storage medium suitable for storing electronic instructions.
- the present invention may also be downloaded as a computer program product, wherein the program may be transferred from a remote computer to a requesting computer.
- element A may be directly coupled to element B or be indirectly coupled through, for example, element C.
- a component, feature, structure, process, or characteristic A “causes” a component, feature, structure, process, or characteristic B, it means that "A” is at least a partial cause of "B” but that there may also be at least one other component, feature, structure, process, or characteristic that assists in causing "B.”
- the specification indicates that a component, feature, structure, process, or characteristic "may”, “might”, or “could” be included, that particular component, feature, structure, process, or characteristic is not required to be included. If the specification or claim refers to "a” or “an” element, this does not mean there is only one of the described elements.
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Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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CN201180060400.6A CN103261902B (en) | 2010-12-17 | 2011-11-29 | The iddq test of cmos device |
JP2013544516A JP2014502721A (en) | 2010-12-17 | 2011-11-29 | IDDQ testing of CMOS devices |
KR1020137018838A KR20140018217A (en) | 2010-12-17 | 2011-11-29 | Iddq testing of cmos devices |
EP11848582.0A EP2652515A4 (en) | 2010-12-17 | 2011-11-29 | Iddq testing of cmos devices |
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US201061424572P | 2010-12-17 | 2010-12-17 | |
US61/424,572 | 2010-12-17 | ||
US13/298,001 US20120158346A1 (en) | 2010-12-17 | 2011-11-16 | Iddq testing of cmos devices |
US13/298,001 | 2011-11-16 |
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US9336343B2 (en) * | 2014-02-28 | 2016-05-10 | International Business Machines Corporation | Calculating circuit-level leakage using three dimensional technology computer aided design and a reduced number of transistors |
CN103954901A (en) * | 2014-04-12 | 2014-07-30 | 徐云鹏 | Device for detecting faults of CMOS integrated circuit of handheld device |
US10120000B2 (en) * | 2015-07-15 | 2018-11-06 | Oracle International Corporation | On-chip current sensing employing power distribution network voltage de-convolution |
KR102504912B1 (en) * | 2018-04-30 | 2023-02-28 | 에스케이하이닉스 주식회사 | Leakage distribution estimating system of semiconductor and analysis method of the same |
CN108776296A (en) * | 2018-06-26 | 2018-11-09 | 北京中电华大电子设计有限责任公司 | A method of judging iddq test with current differential |
CN113625146B (en) * | 2021-08-16 | 2022-09-30 | 长春理工大学 | Semiconductor device 1/f noise S alpha S model parameter estimation method |
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US20060167639A1 (en) | 2005-01-21 | 2006-07-27 | Nec Electronics Corporation | Error detection apparatus and method and signal extractor |
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JPH09113575A (en) * | 1995-10-16 | 1997-05-02 | Hitachi Ltd | Iddq diagnostic system |
JP2783243B2 (en) * | 1996-02-06 | 1998-08-06 | 日本電気株式会社 | Method and apparatus for detecting failure of CMOS integrated circuit |
US5742177A (en) * | 1996-09-27 | 1998-04-21 | Intel Corporation | Method for testing a semiconductor device by measuring quiescent currents (IDDQ) at two different temperatures |
JP3092590B2 (en) * | 1997-09-03 | 2000-09-25 | 日本電気株式会社 | Integrated circuit failure detection device, detection method therefor, and recording medium recording the detection control program therefor |
US20010055282A1 (en) * | 1997-12-15 | 2001-12-27 | Douglas Knisely | Reducing peak to average ratio of transmit signal by intentional phase rotating among composed signals |
US6239609B1 (en) * | 1998-02-11 | 2001-05-29 | Lsi Logic Corporation | Reduced voltage quiescent current test methodology for integrated circuits |
US6239605B1 (en) * | 1998-09-29 | 2001-05-29 | Intel Corporation | Method to perform IDDQ testing in the presence of high background leakage current |
US6389404B1 (en) * | 1998-12-30 | 2002-05-14 | Irvine Sensors Corporation | Neural processing module with input architectures that make maximal use of a weighted synapse array |
JP4507379B2 (en) * | 2000-10-02 | 2010-07-21 | ソニー株式会社 | Non-defective product judgment method for CMOS integrated circuit |
CN1242273C (en) * | 2001-05-30 | 2006-02-15 | 株式会社萌利克 | Method and device for detecting semiconductor circuit |
US6812724B2 (en) * | 2002-02-22 | 2004-11-02 | Lan Rao | Method and system for graphical evaluation of IDDQ measurements |
KR20050044921A (en) * | 2002-09-16 | 2005-05-13 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | Apparatus and method for measuring iddq |
US6897665B2 (en) * | 2003-09-06 | 2005-05-24 | Taiwan Semiconductor Manufacturing Co., Ltd | In-situ electron beam induced current detection |
KR100583960B1 (en) * | 2004-01-20 | 2006-05-26 | 삼성전자주식회사 | test pattern of semiconductor device and test method using the same |
US8159255B2 (en) * | 2008-02-15 | 2012-04-17 | Qualcomm, Incorporated | Methodologies and tool set for IDDQ verification, debugging and failure diagnosis |
US20100079163A1 (en) * | 2008-09-26 | 2010-04-01 | Advantest Corporation | Measurement equipment, test system, and measurement method |
US8185336B2 (en) * | 2008-10-30 | 2012-05-22 | Advantest Corporation | Test apparatus, test method, program, and recording medium reducing the influence of variations |
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US20060167639A1 (en) | 2005-01-21 | 2006-07-27 | Nec Electronics Corporation | Error detection apparatus and method and signal extractor |
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US20120158346A1 (en) | 2012-06-21 |
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CN103261902A (en) | 2013-08-21 |
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EP2652515A4 (en) | 2016-10-19 |
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