WO2012078163A1 - Hydrogen passivation of integrated circuits - Google Patents

Hydrogen passivation of integrated circuits Download PDF

Info

Publication number
WO2012078163A1
WO2012078163A1 PCT/US2010/059722 US2010059722W WO2012078163A1 WO 2012078163 A1 WO2012078163 A1 WO 2012078163A1 US 2010059722 W US2010059722 W US 2010059722W WO 2012078163 A1 WO2012078163 A1 WO 2012078163A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
integrated circuit
hydrogen
passivation
transistor
Prior art date
Application number
PCT/US2010/059722
Other languages
French (fr)
Inventor
Gul Bahar Basim
Scott R. Summerfelt
Ted S. Moise
Original Assignee
Texas Instruments Incorporated
Texas Instruments Japan Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Incorporated, Texas Instruments Japan Limited filed Critical Texas Instruments Incorporated
Priority to JP2013543143A priority Critical patent/JP2014501045A/en
Priority to CN2010800706081A priority patent/CN103262223A/en
Priority to PCT/US2010/059722 priority patent/WO2012078163A1/en
Publication of WO2012078163A1 publication Critical patent/WO2012078163A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Definitions

  • This relates to the field of integrated circuits; and, more particularly, to the hydrogen passivation of integrated circuits.
  • FIG. 1 is a flow diagram of process steps for forming an integrated circuit according to an embodiment.
  • FIG. 2A-2E illustrate steps in an integrated circuit process flow according to another embodiment.
  • FIGS. 3A-3B illustrate an integrated circuit according to other embodiments.
  • FIGS. 4A-4C illustrate an integrated circuit according to alternative embodiments.
  • FIG. 5 compares the transistor threshold voltage (V t ) of transistors that are formed according to an example embodiment to the V t of transistors that are not formed according to the example embodiment.
  • the threshold voltage (“V t ”) of a transistor is generally defined as the gate voltage where an inversion layer forms at the interface between the substrate (body) and the gate dielectric.
  • interface states located between the substrate and gate dielectric will generate an interface charge (“Qj t ”) that contributes to the transistor threshold voltage. Therefore, variations in Qj t may cause variations in V t .
  • One method for passivating this interface charge is anneal at a temperature of approximately 400° C in a hydrogen ambient that is usually one of the last steps in an integrated circuit process flow.
  • An earlier step in an integrated circuit process flow is the formation of the gate dielectric of a CMOS transistor.
  • This step typically begins with an oxidation of the single crystal silicon surface of the substrate. As the oxide is grown on the silicon surface, silicon atoms are removed from the single crystal silicon surface to form an amorphous layer of silicon dioxide. When the oxidation is stopped, some ionic silicon and some incomplete silicon bonds remain at the interface region, thereby forming a sheet of positive charge called interface trap charge or Qj t .
  • the gate dielectric (may be composed of pure silicon dioxide, nitrided silicon dioxide, or a high-k dielectric) is deposited on the thin silicon dioxide layer.
  • integrated circuit manufacturing processes may also cause crystal defects to occur near the substrate surface.
  • a crystal defect in the depletion region of a transistor's PN junction may cause increased diode leakage.
  • a forming gas H 2 + N 2
  • the hydrogen may react with the silicon ions and incomplete silicon bonds to form Si-H bonds, thus reducing and stabilizing the interface charge.
  • the spread of a transistor's V t distribution is typically tightened with the passivation of the interface states, plus the stability of the V t distribution versus time may be significantly increased.
  • diode leakage and integrated circuit standby current may be reduced when the hydrogen reacts with incomplete silicon bonds along a crystal defect to form silicon-hydrogen bonds.
  • some materials being used in advanced process flows may be degraded by a hydrogen anneal at 400° C for an hour or more. While some digital integrated circuits may be able to still function with the increased transistor variation if the forming gas anneal is omitted, it may not be possible to omit the anneal from analog process flows (that may require tightly controlled transistor and component matching).
  • passivation refers to the reduction in Qj t and the reduction in diode leakage that may occur during an anneal containing hydrogen or deuterium.
  • a chemical reaction of hydrogen or deuterium with incomplete silicon bonds and silicon ions may occur at the interface between the single crystal silicon substrate and the amorphous layer silicon dioxide and also occur in the crystal defects near the substrate surface to form silicon-hydrogen ("Si-H”) or silicon-deuterium (“Si-D”) bonds, thereby reducing and stabilizing the interface charge.
  • Si-H silicon-hydrogen
  • Si-D silicon-deuterium
  • the Qj t density may be reduced to the low 10 10 cm “2 eV "1 range.
  • the deuterium isotope of hydrogen may be used instead of hydrogen for passivation to form Si-D bonds (that may be more stable than Si-H bonds).
  • FIG. 1 is a flow diagram of process steps for forming an integrated circuit according to an embodiment.
  • the integrated circuit is passivated with an anneal 1002 and then a passivation trapping layer is deposited 1004.
  • the trapping layer generally prevents the hydrogen or deuterium passivation from diffusing away from the transistors and interface region during subsequent thermal processing steps.
  • An optional capping layer may then be deposited 1006 on top of the passivation trapping layer.
  • a silicon nitride passivation trapping layer (formed with NH 3 ) is deposited on top of a substrate (containing transistors). Then an oxide capping layer is deposited on top of the silicon nitride passivation trapping layer.
  • the silicon nitride passivation trapping layer and the oxide capping layer may prevent NH 3 from poisoning the photoresist that is used for a subsequent photoresist patterning step (such as the etch of pre-metal dielectric layer located over the transistors). Further processing 1008 - such as forming contacts to the transistors and the back-end steps of forming the metal interconnect layers - then completes the integrated circuit.
  • the passivation step 1002 may be performed after silicidation of the transistor gates, sources, and drains but prior to any back-end (post contact formation) processing steps that may be aversely affected by hydrogen.
  • a ferroelectric capacitor (“FeCap”)
  • the passivation step and passivation trapping layer may be formed after contact formation and prior to FeCap formation.
  • the passivation step and passivation trapping layer may be formed on top of the first interconnect layer prior to FeCap formation.
  • the passivation step 1002 of an example embodiment may be a hydrogen or deuterium anneal performed at 350° C or higher with a high density plasma containing hydrogen or deuterium, or the passivation step 1002 may be accomplished by depositing a hydrogen or deuterium releasing film.
  • the hydrogen releasing film may be a silicon nitride film, for example, with a high concentration of silicon-hydrogen bonds.
  • the passivation trapping layer formed in step 1004 may be a film such as AlOx, AlONx, SiNx, SiNxHy, A1N, or BN.
  • the passivation trapping layer formed in step 1004 may be a silicon nitride film with a low concentration of Si-H bonds.
  • the silicon nitride passivation trapping layer may contain a significant concentration of N-H bonds.
  • FIGS. 2A-2E illustrate the major processing steps of another embodiment.
  • deuterium passivation may instead be used
  • FIG. 2A shows an integrated circuit 2000 that has been partially processed up to, but not including, contact photoresist patterning.
  • the integrated circuit is formed on substrate 2002 and it includes shallow trench isolation regions 2004, transistors 2010 (having a transistor gate dielectric 2006 and a transistor gate 2008), and pre-metal dielectric ("PMD") 2012.
  • a hydrogen releasing layer 2014 has also been deposited over the integrated circuit for the passivation step of the example embodiment.
  • the hydrogen releasing film is a SiNxHy film with a high concentration of Si-H bonds that is formed using a high density plasma (“HDP") process (although such a film may also be formed using a low density plasma).
  • SiNxHy films typically contain hydrogen in the form of Si-H and N-H bonds.
  • Si-H bonds are of lower bond energy (e.g., about 3.34 eV) than N-H bonds (e.g., about 4.05 eV).
  • the hydrogen in high Si-H bond containing SiNxHy films may dissociate during back-end (e.g., post contact formation) thermal processing steps (such as copper anneals) and thereafter become available for passivation.
  • An example 8-inch HDP process for forming a SiNxHy hydrogen releasing film is given in Table 1 infra. Those skilled in the art may prepare an equivalent hydrogen releasing film using a different process such as PECVD.
  • a hydrogen diffusion barrier layer 2116 is formed on top of the hydrogen releasing layer 2014 of the integrated circuit 2100 to function as a passivation trapping layer. More specifically, the hydrogen diffusion barrier layer 2116 generally prevents hydrogen from diffusing away from the interface and silicon crystal defects during subsequent thermal processing (resulting in degassification). The hydrogen diffusion barrier layer 2116 aids the retention of a high hydrogen concentration in close proximity to the transistor 2010 where it may passivate the interface states and crystal defects.
  • the hydrogen barrier layer may be formed of one or more dielectric thin films, such as AlOx, AlONx, SiNx, SiNxHy, A1N, or BN.
  • the hydrogen barrier layer is an SiNxHy film with most of the hydrogen in the form of N-H bonds.
  • An example process for forming such a SiNxHy hydrogen barrier film using an 8- inch plasma enhanced chemical vapor deposition (PECVD) process is given in Table 2 infra.
  • SiNxHy hydrogen barrier films may alternatively be prepared by one skilled in the art using other processes such as HDP.
  • the optional capping layer of an oxide film 2218 is formed on the integrated circuit 2200.
  • a contact photoresist pattern 2217 is formed on top of the oxide film 2218.
  • the oxide film 2218 may prevent an adverse reaction (e.g., resist poisoning) between the residual N3 ⁇ 4 that may be present in the PECVD SiNxHy hydrogen barrier film 2116 and the contact photoresist pattern 2217.
  • the adverse reaction may interfere with the patterning and development of the photoresist and it may also interfere with the photoresist removal process.
  • FIG. 2D shows the integrated circuit 2300 after contacts 2320 have been formed using conventional processing. Note that the contact etch may be modified to etch the hydrogen releasing 2014 and the hydrogen barrier 2116 SiNxHy films.
  • Additional back-end processing may be performed, as shown in FIG. 2E, to add first level interconnects 2424.
  • a first intermetal dielectric layer (“IMD-1") 2422 electrically insulates the first level interconnects ("metal- 1") 2424.
  • IMD-1 2422 may be any suitable dielectric such as a PECVD oxide or a low-k dielectric.
  • the first level interconnects 2424 may be a metal such as copper or an aluminum-copper alloy. Additional processing steps to add additional levels of dielectric and interconnects may be performed to complete the integrated circuit. With this example embodiment, the back-end passivation anneal that is currently commonly used as one of the final processing steps in CMOS process flows may be omitted.
  • transistors were shown in FIGS. 2A-2E to illustrate the embodiment, other components such as memory cells (SRAM, DRAM, FLASH, FRAM, etc.), resistors, capacitors, analog components, and high voltage components may also benefit using this embodiment.
  • the substrate 2002 of the example embodiment is bulk silicon substrate, but other substrates such as silicon-on- insulator may alternatively be used.
  • the example embodiment described supra with reference to FIGS. 2A-2E utilizes a hydrogen releasing film 2014.
  • the hydrogen releasing film is omitted, but a hydrogen or deuterium anneal, or a forming gas anneal containing hydrogen or deuterium, is used to passivate the integrated circuit prior to the deposition of the passivation trapping layer 2116.
  • the passivation anneal that is currently commonly used as one of the final processing steps in CMOS process flows may be omitted.
  • the hydrogen releasing film is deposited over the planarized PMD dielectric layer subsequent to transistor formation and prior to contact photoresist patterning.
  • the passivation step and the deposition of the optional overlying hydrogen barrier film may occur at other points in the process flow, as illustrated in FIGS. 3A and 3B.
  • the hydrogen releasing film 3014 and the hydrogen barrier film 3016 are deposited over the integrated circuit 3000 after the contacts 3020 have been formed.
  • the (passivating) hydrogen releasing film 3014 and the (passivation trapping) hydrogen barrier film 3016 also may function as etch stop layers for the metal- 1 3024 etch process.
  • the metal- 1 dielectric material 3022 may also be a hydrogen barrier material, such as TiN or TaN. Even though openings for metal- 1 interconnections 3024 have been etched through the hydrogen barrier layer 3016 to enable metal- 1 3024 to make the desired electrical connection to the contacts 3020, the combination of the metal- 1 dielectric material 3022 and the hydrogen barrier layer 3016 may still function as a substantially continuous hydrogen barrier over the integrated circuit 3000.
  • the hydrogen releasing layer 3114 is deposited over the integrated circuit 3100 after the formation of the sources and drains 3111 and the transistor gates 3108, and also after the optional silicidation 3113 of the sources and drains 3111.
  • the hydrogen releasing layer 3114 may passivate the integrated circuit 3100.
  • the hydrogen releasing layer 3114 may also function as a contact etch stop layer in this embodiment.
  • the hydrogen diffusion barrier layer 3116 is deposited (along with the optional oxide capping layer (not shown), if used).
  • the hydrogen diffusion barrier layer 3116 functions as a passivation trapping layer.
  • the contacts 3120 are formed and the first level of interconnect, metal- 1 3124, is formed over the contacts 3120.
  • the hydrogen diffusion barrier layer 3116 may be deposited directly on top of hydrogen releasing layer 3114 in the embodiment shown in FIG. 3B, or it may be deposited after contact 3120 formation and then used as an etch stop for the metal- 1 3124 etch.
  • the hydrogen releasing film 3114 and the hydrogen barrier film 3116 may be deposited at other points in the integrated circuit manufacturing flow and also be within the scope of the present invention. Some of these other embodiments are illustrated in FIGS. 4A, 4B, and 4C. In these embodiments, 4000, 4100 and 4200, the hydrogen releasing layer is omitted. Therefore, in the embodiments illustrated in FIGS. 4A, 4B, and 4C, the integrated circuit may or may not be passivated prior to a deposition of a passivation trapping layer 4016.
  • the integrated circuit may be passivated through an exposure to a high density plasma ("HDP") containing hydrogen or deuterium, or alternatively to a hydrogen or deuterium anneal at 350° C or more.
  • HDP high density plasma
  • the hydrogen or deuterium containing HDP plasma is used in the best mode of the example embodiments because the HDP plasma usually generates reactive H and D radicals that are especially effective at passivating interface states and crystal defects.
  • the HDP passivation is performed after the formation of the source and drain silicide 4013 and the gate silicide 4015 but prior to the deposition of the passivation tapping layer 4016.
  • the passivation trapping layer 4016 is deposited before the contact 4020 patterning step. If the passivation trapping layer 4016 is SiNxHy then an optional oxide capping layer (not shown) may be deposited on top of the passivation trapping layer 4016 prior to contact patterning (to avoid photoresist poisoning due to residual NH 3 in the SiNxHy). In this example embodiment, the FeCaps 4016 and the second contacts 4038 are formed over the passivation trapping layer 4016.
  • the passivation step is also performed after the formation of the source and drain silicide 4013 and the gate silicide 4015 but prior to the deposition of the passivation trapping layer 4116.
  • the passivation trapping layer is deposited after the formation of the contacts 4020 but before the formation of the metal- 1 interconnects 4124.
  • the passivation step is also performed after prior to deposition of the passivation blocking layer 4216.
  • the passivation trapping layer is deposited before the deposition of the PMD dielectric 4212.
  • the passivation trapping layer in this embodiment may also function as an etch stop layer for the contact 4020 etch step.
  • a passivation trapping layer is deposited over the integrated circuit after the hydrogen or deuterium from a 350° C (or higher) anneal - or from an HDP plasma - passivates the interface and crystal defects.
  • the passivation barrier film is deposited to prevent the hydrogen or deuterium from diffusing away from the transistor interfaces during subsequent thermal processing steps.
  • FIG. 5 shows illustrates the spread threshold voltages ("V t 's") for example n-channel 3.3 Volt transistors processed with no hydrogen passivation anneal 5002, n- channel 3.3 Volt transistors processed with a conventional end-of-process 400° C hydrogen passivation anneal 5004, and n-channel 3.3 Volt transistors processed with a hydrogen releasing film plus a passivation trapping layer (HDP deposited prior to contact patterning) 5006.
  • the V t of the transistors formed with no passivation anneal 5002 is about 0.75 Volts, compared to the V t of the transistors formed with a hydrogen releasing film plus a passivation trapping layer 5006 of about 0.68 Volts. Therefore, a process that forms transistors with a hydrogen releasing film plus a passivation trapping layer may passivate a significant portion of the interface change ("Qit" thereby causing a lowering of the V t .
  • the electrical data illustrated in FIG. 5 also shows that the spread in V t 's for transistors formed with no passivation anneal 5002 is larger (i.e. ⁇ .12 Volts) than the spread in V t 's for transistors formed with a hydrogen releasing film plus a passivation trapping layer 5006 (i.e. ⁇ .03 Volts). Therefore, the uniformity in transistor V t 's has been significantly improved for transistors formed with a hydrogen releasing film plus a passivation trapping layer.
  • V t ( ⁇ .68 Volts) and V t spread (.03 Volts) of transistors formed with a hydrogen releasing film plus a passivation trapping layer 5006 to a baseline sinter process of transistors processed with a conventional end-of-process 400° C hydrogen passivation anneal 5004 with the V t ( ⁇ .69 Volts) and V t spread (.05 Volts) shows that the transistors formed with a hydrogen releasing film plus a passivation trapping layer 5006 may be an improvement over the baseline sinter process 5004.
  • deuterium may also be used instead of hydrogen for the passivation steps of the disclosed embodiments.
  • SiD 4 may be used instead of SiH 4 in the formation of the hydrogen releasing film.
  • a deuterium- containing gas may be added to the HDP during the formation of the hydrogen releasing film.
  • Deuterium usually forms a more stable bond with silicon than hydrogen; therefore, deuterium may improve V t stability (e.g., the V t distribution) over time.
  • deuterium instead of hydrogen in the disclosed embodiments may provide a more cost effective method of passivation than conventional furnace deuterium anneals because the chamber volume is much smaller, the reaction pressure is much lower, the deuterium concentration is much lower, and the process time is much reduced in a single wafer plasma process (in comparison to a batch furnace deuterium anneal process).

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

Description

HYDROGEN PASSIVATION OF INTEGRATED CIRCUITS
[0001] This relates to the field of integrated circuits; and, more particularly, to the hydrogen passivation of integrated circuits.
BRIEF DESCRIPTION OF THE DRAWINGS
[0002] FIG. 1 is a flow diagram of process steps for forming an integrated circuit according to an embodiment.
[0003] FIG. 2A-2E illustrate steps in an integrated circuit process flow according to another embodiment.
[0004] FIGS. 3A-3B illustrate an integrated circuit according to other embodiments.
[0005] FIGS. 4A-4C illustrate an integrated circuit according to alternative embodiments.
[0006] FIG. 5 compares the transistor threshold voltage (Vt) of transistors that are formed according to an example embodiment to the Vt of transistors that are not formed according to the example embodiment.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0007] The example embodiments are described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the example embodiments.
[0008] Several aspects are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the example embodiments. One skilled in the relevant art, however, will readily recognize that the example embodiments can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the embodiment. The example embodiments are not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the example embodiments.
[0009] The threshold voltage ("Vt") of a transistor is generally defined as the gate voltage where an inversion layer forms at the interface between the substrate (body) and the gate dielectric. However, interface states located between the substrate and gate dielectric will generate an interface charge ("Qjt") that contributes to the transistor threshold voltage. Therefore, variations in Qjt may cause variations in Vt. One method for passivating this interface charge is anneal at a temperature of approximately 400° C in a hydrogen ambient that is usually one of the last steps in an integrated circuit process flow.
[0010] An earlier step in an integrated circuit process flow is the formation of the gate dielectric of a CMOS transistor. This step typically begins with an oxidation of the single crystal silicon surface of the substrate. As the oxide is grown on the silicon surface, silicon atoms are removed from the single crystal silicon surface to form an amorphous layer of silicon dioxide. When the oxidation is stopped, some ionic silicon and some incomplete silicon bonds remain at the interface region, thereby forming a sheet of positive charge called interface trap charge or Qjt. The gate dielectric (may be composed of pure silicon dioxide, nitrided silicon dioxide, or a high-k dielectric) is deposited on the thin silicon dioxide layer.
[0011] Other processes in the integrated circuit manufacturing flow (such as plasma depositions and plasma etches) may break the weak bonds at the interface, thereby causing additional Qjt to form. This charge may be variable across a substrate and may also be unstable. Because this charge may contribute to a transistor's Vt, any variability of Qit across a substrate may also cause Vt variability; resulting in transistor instability.
[0012] Moreover, integrated circuit manufacturing processes may also cause crystal defects to occur near the substrate surface. A crystal defect in the depletion region of a transistor's PN junction may cause increased diode leakage.
[0013] One way to reduce the magnitude and instability of the interface charge
(and to passivate crystal defects) is to perform a forming gas (H2 + N2) anneal at approximately 400° C late in the manufacturing flow. The hydrogen may react with the silicon ions and incomplete silicon bonds to form Si-H bonds, thus reducing and stabilizing the interface charge. The spread of a transistor's Vt distribution is typically tightened with the passivation of the interface states, plus the stability of the Vt distribution versus time may be significantly increased. Moreover, diode leakage and integrated circuit standby current may be reduced when the hydrogen reacts with incomplete silicon bonds along a crystal defect to form silicon-hydrogen bonds.
[0014] Hydrogen passivation of integrated circuits is becoming increasingly difficult with new technologies. For example, materials such as TaN that are used in forming interconnect layers may block the diffusion of the hydrogen to the interface. The increased number of interconnect layers also makes the diffusion path longer, thereby requiring more diffusion time to allow the hydrogen to reach the interface. In addition, some integrated circuit process flows (e.g., for ferroelectric memories) involve the formation of hydrogen barrier films (e.g., to prevent hydrogen from degrading the electrical properties of the ferroelectric capacitor). However, these hydrogen barrier films also prevent the hydrogen that is used in the forming gas anneal from reaching the interface.
[0015] Additionally, some materials being used in advanced process flows (such as metal gates and ultra low-k dielectric materials) may be degraded by a hydrogen anneal at 400° C for an hour or more. While some digital integrated circuits may be able to still function with the increased transistor variation if the forming gas anneal is omitted, it may not be possible to omit the anneal from analog process flows (that may require tightly controlled transistor and component matching).
[0016] The term "passivation" refers to the reduction in Qjt and the reduction in diode leakage that may occur during an anneal containing hydrogen or deuterium. A chemical reaction of hydrogen or deuterium with incomplete silicon bonds and silicon ions may occur at the interface between the single crystal silicon substrate and the amorphous layer silicon dioxide and also occur in the crystal defects near the substrate surface to form silicon-hydrogen ("Si-H") or silicon-deuterium ("Si-D") bonds, thereby reducing and stabilizing the interface charge. Prior to a forming gas anneal, the Qit density may be in the low 10 11 cm -"2 eV -" 1 range. After a forming gas anneal, the Qjt density may be reduced to the low 1010 cm"2 eV"1 range. The deuterium isotope of hydrogen may be used instead of hydrogen for passivation to form Si-D bonds (that may be more stable than Si-H bonds).
[0017] FIG. 1 is a flow diagram of process steps for forming an integrated circuit according to an embodiment. After transistors are formed in the substrate 1000, the integrated circuit is passivated with an anneal 1002 and then a passivation trapping layer is deposited 1004. The trapping layer generally prevents the hydrogen or deuterium passivation from diffusing away from the transistors and interface region during subsequent thermal processing steps. An optional capping layer may then be deposited 1006 on top of the passivation trapping layer. In an example embodiment, a silicon nitride passivation trapping layer (formed with NH3) is deposited on top of a substrate (containing transistors). Then an oxide capping layer is deposited on top of the silicon nitride passivation trapping layer. The silicon nitride passivation trapping layer and the oxide capping layer may prevent NH3 from poisoning the photoresist that is used for a subsequent photoresist patterning step (such as the etch of pre-metal dielectric layer located over the transistors). Further processing 1008 - such as forming contacts to the transistors and the back-end steps of forming the metal interconnect layers - then completes the integrated circuit.
[0018] The passivation step 1002 may be performed after silicidation of the transistor gates, sources, and drains but prior to any back-end (post contact formation) processing steps that may be aversely affected by hydrogen. For example, if a ferroelectric capacitor ("FeCap") is to be fabricated after contact formation, the passivation step and passivation trapping layer may be formed after contact formation and prior to FeCap formation. If a FeCap is to be formed after the formation of the first interconnect layer, the passivation step and passivation trapping layer may be formed on top of the first interconnect layer prior to FeCap formation. The passivation step 1002 of an example embodiment may be a hydrogen or deuterium anneal performed at 350° C or higher with a high density plasma containing hydrogen or deuterium, or the passivation step 1002 may be accomplished by depositing a hydrogen or deuterium releasing film. The hydrogen releasing film may be a silicon nitride film, for example, with a high concentration of silicon-hydrogen bonds. The passivation trapping layer formed in step 1004 may be a film such as AlOx, AlONx, SiNx, SiNxHy, A1N, or BN. In addition, the passivation trapping layer formed in step 1004 may be a silicon nitride film with a low concentration of Si-H bonds. Furthermore, the silicon nitride passivation trapping layer may contain a significant concentration of N-H bonds.
[0019] FIGS. 2A-2E illustrate the major processing steps of another embodiment.
Although hydrogen passivation is used to illustrate this embodiment, deuterium passivation may instead be used
[0020] FIG. 2A shows an integrated circuit 2000 that has been partially processed up to, but not including, contact photoresist patterning. The integrated circuit is formed on substrate 2002 and it includes shallow trench isolation regions 2004, transistors 2010 (having a transistor gate dielectric 2006 and a transistor gate 2008), and pre-metal dielectric ("PMD") 2012. A hydrogen releasing layer 2014 has also been deposited over the integrated circuit for the passivation step of the example embodiment. In the example embodiment, the hydrogen releasing film is a SiNxHy film with a high concentration of Si-H bonds that is formed using a high density plasma ("HDP") process (although such a film may also be formed using a low density plasma). SiNxHy films typically contain hydrogen in the form of Si-H and N-H bonds. Si-H bonds are of lower bond energy (e.g., about 3.34 eV) than N-H bonds (e.g., about 4.05 eV). The hydrogen in high Si-H bond containing SiNxHy films may dissociate during back-end (e.g., post contact formation) thermal processing steps (such as copper anneals) and thereafter become available for passivation. An example 8-inch HDP process for forming a SiNxHy hydrogen releasing film is given in Table 1 infra. Those skilled in the art may prepare an equivalent hydrogen releasing film using a different process such as PECVD.
Figure imgf000006_0001
[0021] As shown n FIG. 2B, a hydrogen diffusion barrier layer 2116 is formed on top of the hydrogen releasing layer 2014 of the integrated circuit 2100 to function as a passivation trapping layer. More specifically, the hydrogen diffusion barrier layer 2116 generally prevents hydrogen from diffusing away from the interface and silicon crystal defects during subsequent thermal processing (resulting in degassification). The hydrogen diffusion barrier layer 2116 aids the retention of a high hydrogen concentration in close proximity to the transistor 2010 where it may passivate the interface states and crystal defects. The hydrogen barrier layer may be formed of one or more dielectric thin films, such as AlOx, AlONx, SiNx, SiNxHy, A1N, or BN. In the example embodiment, the hydrogen barrier layer is an SiNxHy film with most of the hydrogen in the form of N-H bonds. An example process for forming such a SiNxHy hydrogen barrier film using an 8- inch plasma enhanced chemical vapor deposition (PECVD) process is given in Table 2 infra. SiNxHy hydrogen barrier films may alternatively be prepared by one skilled in the art using other processes such as HDP.
Figure imgf000007_0001
[0022] As shown in FIG. 2C, the optional capping layer of an oxide film 2218 is formed on the integrated circuit 2200. Next, a contact photoresist pattern 2217 is formed on top of the oxide film 2218. In this embodiment, the oxide film 2218 may prevent an adverse reaction (e.g., resist poisoning) between the residual N¾ that may be present in the PECVD SiNxHy hydrogen barrier film 2116 and the contact photoresist pattern 2217. The adverse reaction may interfere with the patterning and development of the photoresist and it may also interfere with the photoresist removal process.
[0023] FIG. 2D shows the integrated circuit 2300 after contacts 2320 have been formed using conventional processing. Note that the contact etch may be modified to etch the hydrogen releasing 2014 and the hydrogen barrier 2116 SiNxHy films.
[0024] Additional back-end processing may be performed, as shown in FIG. 2E, to add first level interconnects 2424. A first intermetal dielectric layer ("IMD-1") 2422 electrically insulates the first level interconnects ("metal- 1") 2424. IMD-1 2422 may be any suitable dielectric such as a PECVD oxide or a low-k dielectric. The first level interconnects 2424 may be a metal such as copper or an aluminum-copper alloy. Additional processing steps to add additional levels of dielectric and interconnects may be performed to complete the integrated circuit. With this example embodiment, the back-end passivation anneal that is currently commonly used as one of the final processing steps in CMOS process flows may be omitted.
[0025] It is to be noted that although transistors were shown in FIGS. 2A-2E to illustrate the embodiment, other components such as memory cells (SRAM, DRAM, FLASH, FRAM, etc.), resistors, capacitors, analog components, and high voltage components may also benefit using this embodiment. Moreover, the substrate 2002 of the example embodiment is bulk silicon substrate, but other substrates such as silicon-on- insulator may alternatively be used.
[0026] The example embodiment described supra with reference to FIGS. 2A-2E utilizes a hydrogen releasing film 2014. In yet another embodiment, the hydrogen releasing film is omitted, but a hydrogen or deuterium anneal, or a forming gas anneal containing hydrogen or deuterium, is used to passivate the integrated circuit prior to the deposition of the passivation trapping layer 2116. Using this embodiment the passivation anneal that is currently commonly used as one of the final processing steps in CMOS process flows may be omitted.
[0027] In the above embodiment, the hydrogen releasing film is deposited over the planarized PMD dielectric layer subsequent to transistor formation and prior to contact photoresist patterning. However, the passivation step and the deposition of the optional overlying hydrogen barrier film may occur at other points in the process flow, as illustrated in FIGS. 3A and 3B. In FIG. 3A, the hydrogen releasing film 3014 and the hydrogen barrier film 3016 (plus an oxide film (not shown), if used) are deposited over the integrated circuit 3000 after the contacts 3020 have been formed. In this embodiment, the (passivating) hydrogen releasing film 3014 and the (passivation trapping) hydrogen barrier film 3016 also may function as etch stop layers for the metal- 1 3024 etch process. Moreover, the metal- 1 dielectric material 3022 may also be a hydrogen barrier material, such as TiN or TaN. Even though openings for metal- 1 interconnections 3024 have been etched through the hydrogen barrier layer 3016 to enable metal- 1 3024 to make the desired electrical connection to the contacts 3020, the combination of the metal- 1 dielectric material 3022 and the hydrogen barrier layer 3016 may still function as a substantially continuous hydrogen barrier over the integrated circuit 3000.
[0028] In FIG. 3B, the hydrogen releasing layer 3114 is deposited over the integrated circuit 3100 after the formation of the sources and drains 3111 and the transistor gates 3108, and also after the optional silicidation 3113 of the sources and drains 3111. The hydrogen releasing layer 3114 may passivate the integrated circuit 3100. The hydrogen releasing layer 3114 may also function as a contact etch stop layer in this embodiment. After the deposition and planarization of the PMD layer 3112, the hydrogen diffusion barrier layer 3116 is deposited (along with the optional oxide capping layer (not shown), if used). The hydrogen diffusion barrier layer 3116 functions as a passivation trapping layer. Next, the contacts 3120 are formed and the first level of interconnect, metal- 1 3124, is formed over the contacts 3120. Alternatively, the hydrogen diffusion barrier layer 3116 may be deposited directly on top of hydrogen releasing layer 3114 in the embodiment shown in FIG. 3B, or it may be deposited after contact 3120 formation and then used as an etch stop for the metal- 1 3124 etch.
[0029] The hydrogen releasing film 3114 and the hydrogen barrier film 3116 may be deposited at other points in the integrated circuit manufacturing flow and also be within the scope of the present invention. Some of these other embodiments are illustrated in FIGS. 4A, 4B, and 4C. In these embodiments, 4000, 4100 and 4200, the hydrogen releasing layer is omitted. Therefore, in the embodiments illustrated in FIGS. 4A, 4B, and 4C, the integrated circuit may or may not be passivated prior to a deposition of a passivation trapping layer 4016. For embodiments where the integrated circuit is passivated prior to the deposition of the passivation trapping layer 4016, the integrated circuit may be passivated through an exposure to a high density plasma ("HDP") containing hydrogen or deuterium, or alternatively to a hydrogen or deuterium anneal at 350° C or more. The hydrogen or deuterium containing HDP plasma is used in the best mode of the example embodiments because the HDP plasma usually generates reactive H and D radicals that are especially effective at passivating interface states and crystal defects. [0030] In FIG. 4A, the HDP passivation is performed after the formation of the source and drain silicide 4013 and the gate silicide 4015 but prior to the deposition of the passivation tapping layer 4016. In this embodiment, the passivation trapping layer 4016 is deposited before the contact 4020 patterning step. If the passivation trapping layer 4016 is SiNxHy then an optional oxide capping layer (not shown) may be deposited on top of the passivation trapping layer 4016 prior to contact patterning (to avoid photoresist poisoning due to residual NH3 in the SiNxHy). In this example embodiment, the FeCaps 4016 and the second contacts 4038 are formed over the passivation trapping layer 4016.
[0031] In FIG. 4B, the passivation step is also performed after the formation of the source and drain silicide 4013 and the gate silicide 4015 but prior to the deposition of the passivation trapping layer 4116. In this embodiment the passivation trapping layer is deposited after the formation of the contacts 4020 but before the formation of the metal- 1 interconnects 4124.
[0032] In FIG. 4C, the passivation step is also performed after prior to deposition of the passivation blocking layer 4216. However, in this embodiment the passivation trapping layer is deposited before the deposition of the PMD dielectric 4212. The passivation trapping layer in this embodiment may also function as an etch stop layer for the contact 4020 etch step.
[0033] In the embodiments shown and described in FIGS. 4A-4C, a passivation trapping layer is deposited over the integrated circuit after the hydrogen or deuterium from a 350° C (or higher) anneal - or from an HDP plasma - passivates the interface and crystal defects. The passivation barrier film is deposited to prevent the hydrogen or deuterium from diffusing away from the transistor interfaces during subsequent thermal processing steps.
[0034] FIG. 5 shows illustrates the spread threshold voltages ("Vt's") for example n-channel 3.3 Volt transistors processed with no hydrogen passivation anneal 5002, n- channel 3.3 Volt transistors processed with a conventional end-of-process 400° C hydrogen passivation anneal 5004, and n-channel 3.3 Volt transistors processed with a hydrogen releasing film plus a passivation trapping layer (HDP deposited prior to contact patterning) 5006. As shown in FIG. 5, the Vt of the transistors formed with no passivation anneal 5002 is about 0.75 Volts, compared to the Vt of the transistors formed with a hydrogen releasing film plus a passivation trapping layer 5006 of about 0.68 Volts. Therefore, a process that forms transistors with a hydrogen releasing film plus a passivation trapping layer may passivate a significant portion of the interface change ("Qit" thereby causing a lowering of the Vt.
[0035] The electrical data illustrated in FIG. 5 also shows that the spread in Vt's for transistors formed with no passivation anneal 5002 is larger (i.e. ~ .12 Volts) than the spread in Vt's for transistors formed with a hydrogen releasing film plus a passivation trapping layer 5006 (i.e. ~ .03 Volts). Therefore, the uniformity in transistor Vt's has been significantly improved for transistors formed with a hydrogen releasing film plus a passivation trapping layer. Moreover, a comparison of the Vt (~ .68 Volts) and Vt spread (.03 Volts) of transistors formed with a hydrogen releasing film plus a passivation trapping layer 5006 to a baseline sinter process of transistors processed with a conventional end-of-process 400° C hydrogen passivation anneal 5004 with the Vt (~ .69 Volts) and Vt spread (.05 Volts) shows that the transistors formed with a hydrogen releasing film plus a passivation trapping layer 5006 may be an improvement over the baseline sinter process 5004.
[0036] As noted supra, deuterium may also be used instead of hydrogen for the passivation steps of the disclosed embodiments. For example, SiD4 may be used instead of SiH4 in the formation of the hydrogen releasing film. Alternatively, a deuterium- containing gas may be added to the HDP during the formation of the hydrogen releasing film. Deuterium usually forms a more stable bond with silicon than hydrogen; therefore, deuterium may improve Vt stability (e.g., the Vt distribution) over time. The use of deuterium instead of hydrogen in the disclosed embodiments may provide a more cost effective method of passivation than conventional furnace deuterium anneals because the chamber volume is much smaller, the reaction pressure is much lower, the deuterium concentration is much lower, and the process time is much reduced in a single wafer plasma process (in comparison to a batch furnace deuterium anneal process).
[0037] The example process deposition conditions are given for 8-inch deposition equipment. One skilled in the art may use these 8-inch recipes as a guide for developing an equivalent process on a 12-inch (or larger diameter) tool. [0038] While various embodiments have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed embodiments can be made and other embodiments formulated in accordance with the disclosure herein without departing from the scope of the claimed invention.

Claims

CLAIMS What is claimed is:
1. An integrated circuit, comprising:
a substrate;
a transistor coupled to said substrate;
a pre-metal dielectric layer coupled to said substrate; and
a passivation trapping layer overlying said pre-metal dielectric layer.
2. The integrated circuit of claim 1, wherein an interface between said substrate and a gate dielectric of said transistor is passivated, and further wherein said passivation trapping layer is a film selected from the group consisting of AlO, AION, SiNx, and SiNxHy.
3. The integrated circuit of claim 1, further comprising a hydrogen releasing layer that is located under said passivation trapping layer.
4. The integrated circuit of claim 3, wherein said hydrogen releasing layer is a SiNxHy film with more Si-H bonds than N-H bonds.
5. The integrated circuit of claim 1, further comprising a deuterium releasing layer that is located under said passivation layer, and wherein said deuterium releasing layer is a SiNxDy film with more Si-D bonds than N-D bonds.
6. The integrated circuit of claim 3, wherein said hydrogen releasing layer is located under said pre-metal dielectric layer.
7. The integrated circuit of claim 1 wherein an interface between said substrate and a gate dielectric of said transistor is passivated; and further wherein a capping layer is located over said passivation trapping layer.
8. The integrated circuit of claim 1, wherein an interface between said substrate and a gate dielectric of said transistor is passivated; and further wherein said passivation trapping layer is located over contacts formed in said PMD layer.
9. An integrated circuit, comprising:
a substrate;
a transistor coupled to said substrate, wherein an interface between said substrate and a gate dielectric of said transistor is passivated;
a passivation trapping layer overlying said transistor; and
a pre-metal dielectric layer overlying to said passivation trapping layer.
10. A process of forming an integrated circuit, comprising:
providing a partially processed integrated circuit having a transistor and a pre- metal dielectric layer overlying said transistor;
passivating said partially processed integrated circuit; and
after said passivating step, depositing a passivation trapping layer over said pre- metal dielectirc layer.
11. The process of claim 10, wherein said passivating step is a high density plasma process including at least one of hydrogen and deuterium.
12. The process of claim 10, wherein said passivating step comprises depositing a hydrogen releasing layer.
13. The process of claim 12, wherein said hydrogen releasing layer is a SiNxHy film with more Si-H bonds than N-H bonds.
14. The process of claim 12, wherein said passivating step comprises depositing a deuterium releasing layer; and the deuterium releasing layer is a SiNxDy film with more Si-D bonds than N-D bonds.
15. The process of claim 10, wherein said passivating step comprises annealing said integrated circuit in an ambient including at least one of hydrogen or deuterium.
16. The process of claim 10, wherein said passivation trapping layer comprises a film selected from the group consisting of: AlO, AION, SiNx, and SiNxHy.
17. A process of forming an integrated circuit, comprising:
providing a partially processed integrated circuit that includes a transistor;
passivating said partially processed integrated circuit;
after said passivating step, depositing a passivation trapping layer over said transistor; and
forming a pre-metal dielectric layer over said passivation trapping layer.
PCT/US2010/059722 2010-12-09 2010-12-09 Hydrogen passivation of integrated circuits WO2012078163A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2013543143A JP2014501045A (en) 2010-12-09 2010-12-09 Integrated circuit hydrogen passivation
CN2010800706081A CN103262223A (en) 2010-12-09 2010-12-09 Hydrogen passivation of integrated circuits
PCT/US2010/059722 WO2012078163A1 (en) 2010-12-09 2010-12-09 Hydrogen passivation of integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2010/059722 WO2012078163A1 (en) 2010-12-09 2010-12-09 Hydrogen passivation of integrated circuits

Publications (1)

Publication Number Publication Date
WO2012078163A1 true WO2012078163A1 (en) 2012-06-14

Family

ID=46207422

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/059722 WO2012078163A1 (en) 2010-12-09 2010-12-09 Hydrogen passivation of integrated circuits

Country Status (3)

Country Link
JP (1) JP2014501045A (en)
CN (1) CN103262223A (en)
WO (1) WO2012078163A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020257144A1 (en) * 2019-06-17 2020-12-24 Applied Materials, Inc. Deuterium-containing films

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102013218494B4 (en) * 2013-09-16 2021-06-02 Infineon Technologies Ag Semiconductor component with a passivation layer and manufacturing process
TWI548000B (en) * 2014-12-22 2016-09-01 力晶科技股份有限公司 Semiconductor device and method of manufacturing thereof
JP6468886B2 (en) * 2015-03-02 2019-02-13 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method and semiconductor device
KR101914039B1 (en) * 2017-02-03 2018-11-01 주식회사 에이치피에스피 Method for annealing in semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030098497A1 (en) * 2001-11-29 2003-05-29 Symetrix Corporation Barrier layers for protecting metal oxides from hydrogen degradation
US20070134817A1 (en) * 2005-11-29 2007-06-14 Seiko Epson Corporation Method for Manufacturing Ferroelectric Memory
US20090194801A1 (en) * 2008-02-04 2009-08-06 Texas Instruments Inc. ferroelectric capacitor manufacturing process
US20100224961A1 (en) * 2009-03-06 2010-09-09 Texas Instruments Incorporated Passivation of integrated circuits containing ferroelectric capacitors and hydrogen barriers

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0845926A (en) * 1994-07-26 1996-02-16 Sony Corp Semiconductor device and its manufacture
JP2002016249A (en) * 2000-06-30 2002-01-18 Toshiba Corp Semiconductor device and its manufacturing method
JP2003224206A (en) * 2002-01-29 2003-08-08 Fujitsu Ltd Semiconductor device and its fabricating method
EP2032105A2 (en) * 2006-06-23 2009-03-11 Jentec Inc. Superthin wound dressing having folded release sheet
JP4137161B1 (en) * 2007-02-23 2008-08-20 キヤノン株式会社 Method for manufacturing photoelectric conversion device
JP5326361B2 (en) * 2008-05-28 2013-10-30 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
JP2010093064A (en) * 2008-10-08 2010-04-22 Panasonic Corp Semiconductor device and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030098497A1 (en) * 2001-11-29 2003-05-29 Symetrix Corporation Barrier layers for protecting metal oxides from hydrogen degradation
US20070134817A1 (en) * 2005-11-29 2007-06-14 Seiko Epson Corporation Method for Manufacturing Ferroelectric Memory
US20090194801A1 (en) * 2008-02-04 2009-08-06 Texas Instruments Inc. ferroelectric capacitor manufacturing process
US20100224961A1 (en) * 2009-03-06 2010-09-09 Texas Instruments Incorporated Passivation of integrated circuits containing ferroelectric capacitors and hydrogen barriers

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020257144A1 (en) * 2019-06-17 2020-12-24 Applied Materials, Inc. Deuterium-containing films
US11508584B2 (en) 2019-06-17 2022-11-22 Applied Materials, Inc. Deuterium-containing films

Also Published As

Publication number Publication date
JP2014501045A (en) 2014-01-16
CN103262223A (en) 2013-08-21

Similar Documents

Publication Publication Date Title
US9218981B2 (en) Hydrogen passivation of integrated circuits
KR100563748B1 (en) Manufacturing method of semiconductor device
US10211047B2 (en) Multilayer dielectric structures with graded composition for nano-scale semiconductor devices
TW557514B (en) Method for processing a substrate and material for electronic devices
US6297173B1 (en) Process for forming a semiconductor device
WO2012078163A1 (en) Hydrogen passivation of integrated circuits
US20140370621A1 (en) Ferroelectric capacitor encapsulated with a hydrogen barrier
US20070238254A1 (en) Method of etching low dielectric constant films
CN108063117B (en) Interconnect structure and method of forming the same
WO2012078162A1 (en) Ferroelectric capacitor encapsulated with hydrogen barrier
Jamison et al. SiO 2 free HfO 2 gate dielectrics by physical vapor deposition
US9076845B2 (en) Method of forming a high density dielectric etch-stop layer
US20100001353A1 (en) SANOS Memory Cell Structure
Li et al. Blistering induced degradation of thermal stability Al 2 O 3 passivation layer in crystal Si solar cells
KR19980033334A (en) Low Temperature Treatment Method for Deposition of Barrier Thin Films Containing Tungsten and Nitrogen
US20220406606A1 (en) Semiconductor Device and Method of Manufacturing
JP6351079B2 (en) Integrated circuit hydrogen passivation
TW201001550A (en) Adhesion and electromigration improvement between dielectric and conductive layers
US10886168B2 (en) Surface modified dielectric refill structure
US10916431B2 (en) Robust gate cap for protecting a gate from downstream metallization etch operations
US10453797B2 (en) Interconnection structures and fabrication methods thereof
Zhao et al. Impact of BEOL film deposition on poly-Si 3D NAND device characteristics
CN103081064B (en) The preparation method of semiconductor device
JP2006073704A (en) Manufacturing method of semiconductor apparatus
US20200083174A1 (en) Back end of line metallization structure

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10860472

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2013543143

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10860472

Country of ref document: EP

Kind code of ref document: A1