WO2012077606A1 - Liquid crystal panel - Google Patents

Liquid crystal panel Download PDF

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Publication number
WO2012077606A1
WO2012077606A1 PCT/JP2011/077943 JP2011077943W WO2012077606A1 WO 2012077606 A1 WO2012077606 A1 WO 2012077606A1 JP 2011077943 W JP2011077943 W JP 2011077943W WO 2012077606 A1 WO2012077606 A1 WO 2012077606A1
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WO
WIPO (PCT)
Prior art keywords
film
insulating film
photodiode
substrate
liquid crystal
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PCT/JP2011/077943
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French (fr)
Japanese (ja)
Inventor
昇 竹内
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シャープ株式会社
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Publication date
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Publication of WO2012077606A1 publication Critical patent/WO2012077606A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G02F1/13312—Circuits comprising photodetectors for purposes other than feedback
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/38—Anti-reflection arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/042—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means

Definitions

  • the present invention relates to a liquid crystal panel provided with a photodiode.
  • a display device having a liquid crystal panel provided with a photodiode is known (see, for example, JP-A-2009-139597).
  • the display device described in the above publication is provided with a condensing lens that focuses the light from the backlight in the liquid crystal panel while focusing.
  • the display device described in the above publication has a problem that the structure is complicated because it is necessary to separately provide a condenser lens.
  • An object of the present invention is to provide a liquid crystal panel having a simple structure and capable of improving the photodetection sensitivity of a photodiode.
  • a liquid crystal panel of the present invention is formed on a substrate, and includes a photodiode including a semiconductor film for a diode having a p-type semiconductor region, an intrinsic semiconductor region, and an n-type semiconductor region, and so as to cover the photodiode.
  • a coating insulating film, and the coating insulating film is formed on the first coating insulating film, and the first coating insulating film is formed on the first coating insulating film.
  • the light detection sensitivity of the photodiode can be improved with a simple structure.
  • FIG. 2 is a schematic diagram for explaining a photodiode and a thin film transistor included in the liquid crystal panel shown in FIG. 1.
  • FIG. 2 is a schematic diagram for explaining a manufacturing process of an active matrix substrate included in the liquid crystal panel shown in FIG. 1 and shows a state where a light shielding film is formed on the substrate.
  • FIG. 2 is a schematic diagram for explaining a manufacturing process of an active matrix substrate included in the liquid crystal panel shown in FIG. 1, and shows a state where a diode semiconductor film and a transistor semiconductor film are formed on a base layer.
  • FIG. 2 is a schematic diagram for explaining a manufacturing process of an active matrix substrate included in the liquid crystal panel shown in FIG.
  • FIG. 2 is a schematic diagram for explaining a manufacturing process of an active matrix substrate included in the liquid crystal panel shown in FIG. 1 and shows a state where an n-type impurity is implanted.
  • FIG. 2 is a schematic diagram for explaining a manufacturing process of an active matrix substrate included in the liquid crystal panel shown in FIG. 1 and shows a state in which p-type impurities are implanted.
  • FIG. 2 is a schematic diagram for explaining a manufacturing process of an active matrix substrate included in the liquid crystal panel shown in FIG. 1 and shows a state in which contact holes are formed in an interlayer insulating film and a gate insulating film.
  • FIG. 2 is a schematic diagram for explaining a manufacturing process of an active matrix substrate included in the liquid crystal panel shown in FIG. 1 and shows a state in which electrodes and wirings are formed.
  • the schematic diagram for demonstrating the effect of the structure by embodiment of this invention.
  • the graph which shows the result of the optical simulation for verifying the effect of the structure by embodiment of this invention.
  • the schematic diagram which shows the other structure of the thin-film transistor employable with the liquid crystal panel as one Embodiment of this invention.
  • a liquid crystal panel is formed on a substrate, and includes a photodiode including a semiconductor film for a diode having a p-type semiconductor region, an intrinsic semiconductor region, and an n-type semiconductor region, and covers the photodiode A coating insulating film formed on the photodiode, the first coating insulating film formed on the photodiode, and the first coating insulating film. And a second coating insulating film having a refractive index larger than that of the first coating insulating film, and the film thickness of the first coating insulating film is 1 ⁇ 4 of the wavelength of light incident on the photodiode. It is the above magnitude
  • the first configuration light interference can be generated in the first covering insulating film. This makes it possible to create a state in which light is incident on the photodiode many times. As a result, the light detection efficiency of the photodiode can be improved by increasing the light use efficiency.
  • the light detection sensitivity of the photodiode can be improved with a simple structure.
  • the second configuration is a configuration in which, in the first configuration, the film thickness of the first covering insulating film is not more than 1 ⁇ 2 of the wavelength of light incident on the photodiode.
  • the film thickness of the first covering insulating film is not more than 1 ⁇ 2 of the wavelength of light incident on the photodiode.
  • the substrate further includes a thin film transistor provided on a surface of the substrate on which the photodiode is formed, and the thin film transistor is formed on the substrate.
  • a transistor semiconductor film having a channel region, a source region, and a drain region; a gate electrode that controls conductivity of the channel region; and a gate insulation provided between the gate electrode and the transistor semiconductor.
  • the gate insulating film is the first covering insulating film.
  • the first covering insulating film can be realized by skillfully using the gate insulating film included in the thin film transistor. As a result, it becomes easy to simplify the structure.
  • a fourth configuration further includes a gate electrode coating film that is formed on the gate insulating film and covers the gate electrode in the third configuration, and the gate electrode coating film is the second configuration. It is the structure made into the coating insulating film. In such a configuration, the second coating insulating film can be realized by skillfully using the gate electrode coating film. As a result, it becomes easy to simplify the structure.
  • the liquid crystal panel according to the present invention can include arbitrary constituent members not shown in the drawings referred to in this specification.
  • the dimension of the member in each figure does not represent the dimension of an actual structural member, the dimension ratio of each member, etc. faithfully.
  • FIG. 1 shows a liquid crystal panel 10 as an embodiment of the present invention.
  • the liquid crystal panel 10 includes an active matrix substrate 12, a counter substrate 14, and a liquid crystal layer 16 sealed between the substrates 12 and 14.
  • a plurality of pixels are formed on the active matrix substrate 12.
  • Each pixel includes a thin film transistor as an active element and a pixel electrode.
  • a region where a plurality of pixels are formed is a display region (not shown).
  • the counter substrate 14 is arranged at a position facing the display area formed on the active matrix substrate 12. Although not shown, the counter substrate 14 is provided with a counter electrode and a color filter. Note that a color filter is not necessarily required in the counter substrate 14. It is of course possible to provide a color filter on the active matrix substrate 12 side. If the liquid crystal panel 10 does not perform color display, it is not necessary to provide a color filter itself.
  • a liquid crystal layer 16 is sealed between the active matrix substrate 12 and the counter substrate 14.
  • an operation mode of the liquid crystal for example, a TN (twisted nematic) mode or the like can be adopted.
  • a photodiode 18 and a thin film transistor 20 are formed on the active matrix substrate 12.
  • the photodiode 18 include a photodiode for realizing a touch sensor function.
  • the thin film transistor 20 include a thin film transistor as an active element included in each pixel formed on the active matrix substrate 12 and a thin film transistor as an amplifier transistor that amplifies the output of the photodiode 18.
  • the photodiode 18 is formed on a substrate 22 included in the active matrix substrate 12 as shown in FIG.
  • a substrate 22 for example, a low alkali glass substrate or a quartz substrate can be employed.
  • the photodiode 18 includes a semiconductor film for diode 24 provided on the substrate 22.
  • the semiconductor film 24 for a diode is formed on the substrate 22 through the base layer 26 formed on the substrate 22.
  • the underlayer 26 is provided to prevent impurity diffusion from the substrate 22.
  • a silicon oxide film or the like can be employed as the foundation layer 26, for example.
  • the thickness of the underlayer 26 is 100 to 600 nm.
  • the diode semiconductor film 24 for example, an amorphous silicon film or a crystalline silicon film can be employed.
  • a crystalline silicon film for example, a low-temperature polysilicon film, a high-temperature polysilicon film, a continuous grain boundary silicon film, a microcrystalline silicon film, or the like can be employed.
  • the thickness of the diode semiconductor film 24 is 25 to 100 nm.
  • a p-type semiconductor region 24p, an intrinsic semiconductor region 24i, and an n-type semiconductor region 24n are formed so as to be arranged along the base layer 26 in this order.
  • the photodiode 18 is a so-called lateral structure PIN diode.
  • a light shielding film 28 formed on the substrate 22 and covered with the underlayer 26 is provided below the photodiode 18 (diode semiconductor film 24). This prevents light that has passed through the substrate 22 from entering the diode semiconductor film 24.
  • the light shielding film 28 for example, a metal film can be adopted.
  • a metal film formed of a refractory metal such as tantalum, tungsten, or molybdenum as the light shielding film 28.
  • the thickness of the light shielding film 28 is 200 to 300 nm.
  • a gate insulating film 30 as a first covering insulating film is formed on the base layer 26 so as to cover the photodiode 18 (diode semiconductor film 24).
  • the gate insulating film 30 covers not only the photodiode 18 but also a transistor semiconductor film 44 described later.
  • a silicon oxide film, a silicon oxynitrite (SiON) film, a silicon oxynitride hydride (SiONH) film, or the like can be employed as the gate insulating film 30.
  • SiON silicon oxynitrite
  • SiONH silicon oxynitride hydride
  • a silicon oxide film is employed as the gate insulating film 30.
  • the thickness of the gate insulating film 30 is not less than 1/4 of the wavelength of light incident on the photodiode 18.
  • the wavelength range of visible light is 380 to 780 nm, so the thickness of the gate insulating film 30 is set to 95 nm or more.
  • the lower limit value of the wavelength region is 1 ⁇ 4 or more. It is not limited to the method of setting the thickness of the gate insulating film 30 to the size of. For example, a method of examining the spectral characteristics of light incident on the photodiode 18 and setting the thickness of the gate insulating film 30 to a size equal to or larger than 1 ⁇ 4 of the wavelength showing the highest peak value can be adopted. it can.
  • the thickness of the gate insulating film 30 is not more than 1 ⁇ 2 of the wavelength of light incident on the photodiode 18.
  • the thickness of the gate insulating film 30 is preferably set to 390 nm or less, more preferably 190 nm or less.
  • the upper limit value or the lower limit value of the wavelength range is 1 It is not limited to the method of setting the thickness of the gate insulating film 30 to a size of / 2 or less.
  • a method of examining the spectral characteristics of the light incident on the photodiode 18 and setting the thickness of the gate insulating film 30 to a size equal to or smaller than 1 ⁇ 2 of the wavelength having the highest peak value may be adopted. it can.
  • An interlayer insulating film 32 is formed on the gate insulating film 30.
  • the interlayer insulating film 32 of this embodiment is formed by laminating a lower interlayer insulating film 32a as a second covering insulating film and an upper interlayer insulating film 32b in this order. That is, in the present embodiment, a covering insulating film is realized by the gate insulating film 30 and the lower interlayer insulating film 32a.
  • the lower interlayer insulating film 32 a is formed on the gate insulating film 30 so as to cover the gate insulating film 30.
  • the refractive index of the lower interlayer insulating film 32a is made larger than the refractive index of the gate insulating film 30.
  • the thickness of the lower interlayer insulating film 32a is 50 to 800 nm.
  • the lower interlayer insulating film 32a for example, a silicon nitride film, a SiON film, a SiONH film, or the like can be employed.
  • a silicon nitride film having a refractive index larger than that of the silicon oxide film employed as the gate insulating film 30 is employed as the lower interlayer insulating film 32a.
  • the combination of the gate insulating film 30 and the lower interlayer insulating film 32a is not limited to the above combination.
  • the gate insulating film 30 is a silicon oxide film, for example, a SiON film or a SiONH film can be employed as the lower interlayer insulating film 32a in addition to the silicon nitride film.
  • the gate insulating film 30 is a SiON film, for example, a silicon nitride film or a SiONH film can be employed as the lower interlayer insulating film 32a.
  • the gate insulating film 30 is a SiONH film, for example, a silicon nitride film or a SiON film can be employed as the lower interlayer insulating film 32a.
  • the upper interlayer insulating film 32b is formed on the lower interlayer insulating film 32a so as to cover the lower interlayer insulating film 32a.
  • a silicon oxide film or the like can be employed as the upper interlayer insulating film 32b.
  • contact holes 34 and 36 penetrating the interlayer insulating film 32 and the gate insulating film 30 in the thickness direction are formed.
  • the contact hole 34 is formed at a position that overlaps with the p-type semiconductor region 24p in plan view of the substrate 22.
  • the contact hole 36 is formed at a position overlapping the n-type semiconductor region 24n in the plan view of the substrate 22.
  • a planarizing film 42 is formed on the interlayer insulating film 32 so as to cover the electrodes / wirings 38 and 40.
  • the planarizing film 42 for example, a silicon oxide film or the like can be employed in addition to an organic insulating film such as a photosensitive acrylic resin.
  • the thickness of the planarizing film 42 is 1000 to 4000 nm.
  • the thin film transistor 20 includes a transistor semiconductor film 44 provided on the substrate 22.
  • the transistor semiconductor film 44 is formed on the substrate 22 via the base layer 26 formed on the substrate 22. That is, the transistor semiconductor film 44 is formed on the same layer as the diode semiconductor film 24.
  • the transistor semiconductor film 44 for example, an amorphous silicon film or a crystalline silicon film can be employed.
  • a crystalline silicon film for example, a low-temperature polysilicon film, a high-temperature polysilicon film, a continuous grain boundary silicon film, a microcrystalline silicon film, or the like can be employed.
  • the thickness of the transistor semiconductor film 44 is 25 to 100 nm. Incidentally, in the present embodiment, the thickness of the transistor semiconductor film 44 and the thickness of the diode semiconductor film 24 are the same.
  • a source region 44s, a channel region 44c, and a drain region 44d are formed along the base layer 26 in this order.
  • the thin film transistor 20 includes a gate insulating film 30 formed on the base layer 26 so as to cover the transistor semiconductor film 44.
  • the thin film transistor 20 includes a gate electrode 46 formed on the gate insulating film 30.
  • the gate electrode 46 is formed at a position covering the channel region 44 c in plan view of the substrate 22. By applying a gate voltage to the gate electrode 46, the source region 44s and the drain region 44d are connected.
  • the gate electrode 46 for example, a high melting point metal such as tungsten, tantalum, titanium, molybdenum, or an alloy material of these high melting point metals can be employed.
  • the thickness of the gate electrode 46 is 300 to 600 nm.
  • the gate electrode 46 is covered with an interlayer insulating film 32 formed on the gate insulating film 30. That is, in this embodiment, the gate electrode coating film is realized by the lower interlayer insulating film 32a.
  • contact holes 48 and 50 penetrating the interlayer insulating film 32 in the thickness direction are formed.
  • the contact hole 48 is formed at a position overlapping the source region 44 s in plan view of the substrate 22.
  • the contact hole 50 is formed at a position overlapping the drain region 44d when the substrate 22 is viewed in plan.
  • the electrodes / wirings 52 and 54 formed on the interlayer insulating film 32 are connected to the source region 44s and the drain region 44d, respectively. Yes. That is, in this embodiment, the electrodes / wirings 52 and 54 and the electrodes / wirings 38 and 40 are formed on the same layer.
  • electrodes / wirings 52 and 54 for example, those having a two-layer structure of a titanium nitride film and an aluminum film can be employed.
  • a planarizing film 42 is formed on the interlayer insulating film 32 so as to cover the electrodes / wirings 52 and 54.
  • the manufacturing method of the active matrix substrate 12 is not limited to the manufacturing method described below.
  • the light shielding film 28 is formed at a predetermined position on the substrate 22. Specifically, first, a metal film that will later become the light shielding film 28 is formed on the entire upper surface of the substrate 22 by sputtering. Thereafter, this metal film is patterned by photolithography. Thereby, as shown in FIG. 3A, the light shielding film 28 is formed at a predetermined position on the substrate 22.
  • the base layer 26 is formed on the upper surface side of the substrate 22 by CVD (Chemical Vapor Deposition). Thereby, the entire upper surface side of the substrate 22 is covered with the base layer 26.
  • CVD Chemical Vapor Deposition
  • a diode semiconductor film 24 and a transistor semiconductor film 44 are formed on the base layer 26.
  • an amorphous silicon film is formed on the entire upper surface of the base layer 26 by plasma CVD, sputtering, or the like.
  • excimer laser is irradiated to the amorphous silicon film.
  • a polysilicon film covering the entire upper surface of the underlayer 26 is formed.
  • the polysilicon film is patterned by photolithography. As a result, as shown in FIG. 3B, the diode semiconductor film 24 and the transistor semiconductor film 44 are formed at predetermined positions on the base layer 26.
  • the gate insulating film 30 is formed on the upper side of the substrate 22 by plasma CVD or the like. As a result, the entire upper surface side of the substrate 22 is covered with the gate insulating film 30.
  • the gate electrode 46 is formed on the gate insulating film 30. Specifically, first, a conductive film that will later become the gate electrode 46 is formed on the entire upper surface of the gate insulating film 30 by sputtering or CVD. Thereafter, this conductive film is patterned by photolithography. As a result, the gate electrode 46 is formed at a predetermined position on the gate insulating film 30 as shown in FIG. 3C.
  • an n-type impurity such as phosphorus is implanted into the diode semiconductor film 24 and the transistor semiconductor film 44.
  • a mask 56 made of a resist is formed on the gate insulating film 30 so as to cover a part of the semiconductor film 24 for diode.
  • n-type impurities such as phosphorus are ion-doped.
  • the n-type impurity is implanted into a region of the diode semiconductor film 24 that is not covered with the mask 56 and a region of the transistor semiconductor film 44 that is not covered with the gate electrode 46.
  • an n-type semiconductor region 24n is formed in the diode semiconductor film 24.
  • a source region 44s and a drain region 44d are formed in the transistor semiconductor film 44.
  • a region where the n-type impurity is not implanted in the transistor semiconductor film 44 is a channel region 44c formed of an intrinsic semiconductor.
  • a p-type impurity such as boron is implanted into the diode semiconductor film 24.
  • a mask 58 made of resist is applied to the gate insulating film 30 so as to cover a part of the semiconductor film for diode 24 and the entire semiconductor film for transistor 44. Form on top.
  • p-type impurities such as boron are ion-doped.
  • the p-type impurity is implanted into a region of the diode semiconductor film 24 that is not covered with the mask 58.
  • the p-type semiconductor region 24p is formed in the diode semiconductor film 24.
  • the region where neither the n-type impurity nor the p-type impurity is implanted becomes an intrinsic semiconductor region 24i formed of an intrinsic semiconductor.
  • the impurities implanted into the diode semiconductor film 24 and the transistor semiconductor film 44 are activated. Specifically, heat treatment by RTA (Rapid Thermal Annealing) is performed in an inert atmosphere. Thereby, in the n-type semiconductor region 24n and the p-type semiconductor region 24p of the diode semiconductor film 24 and the source region 44s and the drain region 44d of the transistor semiconductor film 44, doping such as crystal defects generated during ion doping is performed. Damage is restored and the implanted impurities are activated.
  • RTA Rapid Thermal Annealing
  • an interlayer insulating film 32 is formed on the upper side of the substrate 22 by plasma CVD or the like. As a result, the entire upper surface side of the substrate 22 is covered with the interlayer insulating film 32.
  • contact holes 34 penetrating the interlayer insulating film 32 and the gate insulating film 30 in the thickness direction, 36, 48 and 50 are formed.
  • the contact holes 34, 36, 48, 50 are formed by photolithography.
  • electrodes / wirings 38, 40, 52, 54 are formed on the interlayer insulating film 32.
  • a conductive film that will later become electrodes / wirings 38, 40, 52, 54 is formed on the upper side of the substrate 22 by sputtering, CVD, or the like. Thereby, the whole upper surface side of the substrate 22 is covered with the conductive film. Thereafter, the conductive film is patterned by photolithography. As a result, electrodes / wirings 38, 40, 52, 54 are formed on the interlayer insulating film 32 as shown in FIG. 3G.
  • a planarizing film 42 is formed on the upper side of the substrate 22.
  • the planarizing film 42 is an organic insulating film such as a photosensitive acrylic resin
  • the planarizing film 42 is formed by a spin coater.
  • the planarizing film 42 is an inorganic insulating film such as a silicon oxide film
  • the planarizing film 42 is formed by plasma CVD or the like. Thereby, the entire upper surface side of the substrate 22 is covered with the planarizing film 42. As a result, the target active matrix substrate 12 is obtained.
  • the thickness of the gate insulating film 30 is set to 1 ⁇ 4 or more of the wavelength of light incident on the photodiode 18, and the refractive index of the lower interlayer insulating film 32a is set to be gate insulating.
  • the refractive index of the film 30 is made larger. Thereby, light interference can be generated in the gate insulating film 30. As a result, as shown in FIG. 4, it is possible to create a state in which light is incident on the photodiode 18 many times.
  • the light utilization efficiency can be increased without providing a condensing lens or the like separately. As a result, it is possible to improve the light detection sensitivity of the photodiode 18.
  • the film thickness of the gate insulating film 30 is set to be smaller than 1 ⁇ 2 of the wavelength of light incident on the photodiode 18. Thereby, the time required for forming the gate insulating film 30 can be shortened.
  • the first covering insulating film is realized by skillfully using the gate insulating film 30 included in the thin film transistor 20. As a result, it becomes easy to simplify the structure.
  • the second covering insulating film is realized by skillfully using the lower interlayer insulating film 32a. As a result, it becomes easy to simplify the structure.
  • optical simulation was performed. The result is shown in FIG.
  • the optical simulation was performed for the case where the wavelength of light incident on the photodiode 18 (light source wavelength) was 400 nm, 500 nm, 600 nm, and 700 nm.
  • the horizontal axis of the graph shown in FIG. 5 plots the thickness of the gate insulating film 30 normalized by 1/4 of the wavelength of light incident on the photodiode 18. For example, when the value of the horizontal axis of the graph shown in FIG. 5 is 1, if the wavelength of light incident on the photodiode 18 is 400 nm, the thickness of the gate insulating film 30 is 100 nm, and the light enters the photodiode 18. If the wavelength of the light to be transmitted is 700 nm, the thickness of the gate insulating film 30 is 175 nm.
  • the vertical axis of the graph shown in FIG. 5 is the photodetection sensitivity of the photodiode 18.
  • the value of the horizontal axis becomes smaller than 1, that is, as the film thickness of the gate insulating film 30 becomes smaller than 1 ⁇ 4 of the wavelength of light incident on the photodiode 18.
  • the value of the horizontal axis of the graph is 1 or more, that is, the thickness of the gate insulating film 30 is the light incident on the photodiode 18. It can be seen that the wavelength should be 1 ⁇ 4 or more of the wavelength.
  • FIG. 6 shows the cumulative frequency distribution of the bright current value of the photodiode 18 in the configuration of the present embodiment and the cumulative frequency distribution of the bright current value of the photodiode in the comparative example.
  • the thickness of the gate insulating film 30 is smaller than 1 ⁇ 4 of the wavelength of light incident on the photodiode 18.
  • the experiment was performed with the thickness of the gate insulating film 30 set to 110 nm or more.
  • the experiment was performed with the thickness of the gate insulating film 30 smaller than 110 nm.
  • the bright current value of the photodiode 18 is increased by about 20% compared to the comparative example, and the photodetection sensitivity of the photodiode 18 is improved. It can be seen that improvement has been realized.
  • a gate protective film that protects the gate electrode 46 may be provided between the gate insulating film 30 and the interlayer insulating film 32.
  • the gate protective film becomes the second covering insulating film.
  • the present invention can be applied to a structure provided with a condenser lens.
  • the so-called top gate thin film transistor 20 in which the gate electrode 46 is positioned on the opposite side of the substrate 22 with the transistor semiconductor film 44 interposed therebetween is employed.
  • a thin film transistor having a so-called bottom gate structure, which is located closer to the substrate than the semiconductor film for a transistor, may be employed.
  • the thin film transistor 60 has a gate electrode 62 formed on the substrate 18.
  • the gate electrode 62 is, for example, a metal film such as tantalum, molybdenum, aluminum, or titanium.
  • a gate insulating film 64 is formed on the gate electrode 62.
  • the gate insulating film 64 is, for example, a silicon nitride film.
  • An intrinsic amorphous silicon film 66 is formed on the gate insulating film 64. On the intrinsic amorphous silicon film 66, n-type amorphous silicon films 67a and 67b are formed.
  • a source electrode 68 is formed on the n-type amorphous silicon film 67a.
  • a drain electrode 70 is formed on the n-type amorphous silicon film 67b.
  • the source electrode 68 and the drain electrode 70 are metal films, such as aluminum and titanium, for example.
  • the source electrode 68 and the drain electrode 70 are covered with a protective film 72.
  • the protective film 72 is, for example, a silicon oxide film.

Abstract

The purpose of the present invention is to provide a liquid crystal panel, wherein optical detection sensitivity of a photodiode is improved with a simple structure. Provided is a liquid crystal panel, which is provided with: a photodiode (18), which is formed on a substrate (22), and is provided with a semiconductor film (24) for a diode, said semiconductor film having a p-type semiconductor region (24p), an intrinsic semiconductor region (24i), and an n-type semiconductor region (24n); and covering insulating films (30, 32a), which are formed to cover the photodiode (18). The covering insulating films (30, 32a) are provided with: a first covering insulating film (30) formed on the photodiode (18); and a second covering insulating film (32a), which is formed on the first covering insulating film (30), and has a refractive index larger than that of the first covering insulating film (30). The thickness of the first covering insulating film (30) is 1/4 or more of the wavelength of light inputted to the photodiode (18).

Description

液晶パネルLCD panel
　本発明は、フォトダイオードを備えた液晶パネルに関する。 The present invention relates to a liquid crystal panel provided with a photodiode.
　従来から、タッチセンサ機能等を実現するために、フォトダイオードを備えた液晶パネルを有する表示装置が知られている（例えば、特開２００９－１３９５９７号公報等を参照）。 Conventionally, in order to realize a touch sensor function and the like, a display device having a liquid crystal panel provided with a photodiode is known (see, for example, JP-A-2009-139597).
　ところで、液晶パネルが備えるフォトダイオードにおいては、操作者の指等を検出する精度を向上させるために、光検出感度を向上させることが望ましい。そこで、上記公報に記載の表示装置においては、バックライトからの光を液晶パネル内で焦点を合わせて集光する集光レンズが設けられている。 Incidentally, in the photodiode provided in the liquid crystal panel, it is desirable to improve the photodetection sensitivity in order to improve the accuracy of detecting an operator's finger or the like. In view of this, the display device described in the above publication is provided with a condensing lens that focuses the light from the backlight in the liquid crystal panel while focusing.
　しかしながら、上記公報に記載の表示装置においては、集光レンズを別途設ける必要があるから、構造が複雑になるという問題があった。 However, the display device described in the above publication has a problem that the structure is complicated because it is necessary to separately provide a condenser lens.
　本発明の目的は、簡単な構造でもって、フォトダイオードの光検出感度を向上させることができる、液晶パネルを提供することにある。 An object of the present invention is to provide a liquid crystal panel having a simple structure and capable of improving the photodetection sensitivity of a photodiode.
　本発明の液晶パネルは、基板上に形成されて、ｐ型半導体領域と真性半導体領域とｎ型半導体領域とを有するダイオード用半導体膜を備えるフォトダイオードと、該フォトダイオードを覆うように形成された被覆絶縁膜とを備えており、前記被覆絶縁膜が、前記フォトダイオード上に形成された第一の被覆絶縁膜と、該第一の被覆絶縁膜上に形成されて、該第一の被覆絶縁膜よりも大きな屈折率を有する第二の被覆絶縁膜とを備えており、前記第一の被覆絶縁膜の膜厚が、前記フォトダイオードに入射する光の波長の１／４以上の大きさである。 A liquid crystal panel of the present invention is formed on a substrate, and includes a photodiode including a semiconductor film for a diode having a p-type semiconductor region, an intrinsic semiconductor region, and an n-type semiconductor region, and so as to cover the photodiode. A coating insulating film, and the coating insulating film is formed on the first coating insulating film, and the first coating insulating film is formed on the first coating insulating film. A second covering insulating film having a refractive index larger than that of the film, and the film thickness of the first covering insulating film is not less than 1/4 of the wavelength of light incident on the photodiode. is there.
　本発明の液晶パネルによれば、簡単な構造でもって、フォトダイオードの光検出感度を向上させることができる。 According to the liquid crystal panel of the present invention, the light detection sensitivity of the photodiode can be improved with a simple structure.
本発明の一実施形態としての液晶パネルを示す模式図。The schematic diagram which shows the liquid crystal panel as one Embodiment of this invention. 図１に示した液晶パネルが備えるフォトダイオード及び薄膜トランジスタを説明するための模式図。FIG. 2 is a schematic diagram for explaining a photodiode and a thin film transistor included in the liquid crystal panel shown in FIG. 1. 図１に示した液晶パネルが備えるアクティブマトリクス基板の製造工程を説明するための模式図であって、遮光膜が基板上に形成された状態を示す模式図。FIG. 2 is a schematic diagram for explaining a manufacturing process of an active matrix substrate included in the liquid crystal panel shown in FIG. 1 and shows a state where a light shielding film is formed on the substrate. 図１に示した液晶パネルが備えるアクティブマトリクス基板の製造工程を説明するための模式図であって、ダイオード用半導体膜とトランジスタ用半導体膜とが下地層上に形成された状態を示す模式図。FIG. 2 is a schematic diagram for explaining a manufacturing process of an active matrix substrate included in the liquid crystal panel shown in FIG. 1, and shows a state where a diode semiconductor film and a transistor semiconductor film are formed on a base layer. 図１に示した液晶パネルが備えるアクティブマトリクス基板の製造工程を説明するための模式図であって、ゲート電極がゲート絶縁膜上に形成された状態を示す模式図。FIG. 2 is a schematic diagram for explaining a manufacturing process of an active matrix substrate included in the liquid crystal panel shown in FIG. 1 and shows a state in which a gate electrode is formed on a gate insulating film. 図１に示した液晶パネルが備えるアクティブマトリクス基板の製造工程を説明するための模式図であって、ｎ型不純物が注入される状態を示す模式図。FIG. 2 is a schematic diagram for explaining a manufacturing process of an active matrix substrate included in the liquid crystal panel shown in FIG. 1 and shows a state where an n-type impurity is implanted. 図１に示した液晶パネルが備えるアクティブマトリクス基板の製造工程を説明するための模式図であって、ｐ型不純物が注入される状態を示す模式図。FIG. 2 is a schematic diagram for explaining a manufacturing process of an active matrix substrate included in the liquid crystal panel shown in FIG. 1 and shows a state in which p-type impurities are implanted. 図１に示した液晶パネルが備えるアクティブマトリクス基板の製造工程を説明するための模式図であって、層間絶縁膜とゲート絶縁膜にコンタクトホールが形成された状態を示す模式図。FIG. 2 is a schematic diagram for explaining a manufacturing process of an active matrix substrate included in the liquid crystal panel shown in FIG. 1 and shows a state in which contact holes are formed in an interlayer insulating film and a gate insulating film. 図１に示した液晶パネルが備えるアクティブマトリクス基板の製造工程を説明するための模式図であって、電極・配線が形成された状態を示す模式図。FIG. 2 is a schematic diagram for explaining a manufacturing process of an active matrix substrate included in the liquid crystal panel shown in FIG. 1 and shows a state in which electrodes and wirings are formed. 本発明の実施の形態による構成の効果を説明するための模式図。The schematic diagram for demonstrating the effect of the structure by embodiment of this invention. 本発明の実施の形態による構成の効果を検証するための光学シミュレーションの結果を示すグラフ。The graph which shows the result of the optical simulation for verifying the effect of the structure by embodiment of this invention. 本実施形態の構成と比較例の構成とにおけるフォトダイオードの明電流値の累積度数分布図。The cumulative frequency distribution diagram of the bright current value of the photodiode in the configuration of the present embodiment and the configuration of the comparative example. 本発明の一実施形態としての液晶パネルで採用可能な薄膜トランジスタの他の構成を示す模式図。The schematic diagram which shows the other structure of the thin-film transistor employable with the liquid crystal panel as one Embodiment of this invention.
　本発明の一実施形態に係る液晶パネルは、基板上に形成されて、ｐ型半導体領域と真性半導体領域とｎ型半導体領域とを有するダイオード用半導体膜を備えるフォトダイオードと、該フォトダイオードを覆うように形成された被覆絶縁膜とを備えており、前記被覆絶縁膜が、前記フォトダイオード上に形成された第一の被覆絶縁膜と、該第一の被覆絶縁膜上に形成されて、該第一の被覆絶縁膜よりも大きな屈折率を有する第二の被覆絶縁膜とを備えており、前記第一の被覆絶縁膜の膜厚が、前記フォトダイオードに入射する光の波長の１／４以上の大きさである（第１の構成）。 A liquid crystal panel according to an embodiment of the present invention is formed on a substrate, and includes a photodiode including a semiconductor film for a diode having a p-type semiconductor region, an intrinsic semiconductor region, and an n-type semiconductor region, and covers the photodiode A coating insulating film formed on the photodiode, the first coating insulating film formed on the photodiode, and the first coating insulating film. And a second coating insulating film having a refractive index larger than that of the first coating insulating film, and the film thickness of the first coating insulating film is ¼ of the wavelength of light incident on the photodiode. It is the above magnitude | size (1st structure).
　第１の構成においては、第一の被覆絶縁膜内で光の干渉を発生させることができる。これにより、光が何度もフォトダイオードに入射する状態を作り出すことが可能となる。その結果、光の利用効率をあげて、フォトダイオードの光検出感度を向上させることができる。 In the first configuration, light interference can be generated in the first covering insulating film. This makes it possible to create a state in which light is incident on the photodiode many times. As a result, the light detection efficiency of the photodiode can be improved by increasing the light use efficiency.
　従って、第１の構成においては、簡単な構造でもって、フォトダイオードの光検出感度を向上させることが可能となる。 Therefore, in the first configuration, the light detection sensitivity of the photodiode can be improved with a simple structure.
　第２の構成は、前記第１の構成において、前記第一の被覆絶縁膜の膜厚が、前記フォトダイオードに入射する光の波長の１／２以下の大きさとされている構成である。このような構成においては、第一の被覆絶縁膜の膜厚が必要以上に大きくなるのを防ぐことができる。その結果、第一の被覆絶縁膜の形成に要する時間を短くすることが可能となる。 The second configuration is a configuration in which, in the first configuration, the film thickness of the first covering insulating film is not more than ½ of the wavelength of light incident on the photodiode. In such a configuration, it is possible to prevent the first coating insulating film from becoming unnecessarily thick. As a result, the time required for forming the first covering insulating film can be shortened.
　第３の構成は、前記第１又は第２の構成において、前記基板において、前記フォトダイオードが形成された側の面に設けられた薄膜トランジスタを更に備えており、前記薄膜トランジスタが、前記基板上に形成されて、チャネル領域とソース領域とドレイン領域とを有するトランジスタ用半導体膜と、前記チャネル領域の導電性を制御するゲート電極と、該ゲート電極と前記トランジスタ用半導体との間に設けられたゲート絶縁膜とを有しており、前記ゲート絶縁膜が前記第一の被覆絶縁膜とされている構成である。このような構成においては、薄膜トランジスタが備えるゲート絶縁膜を巧く利用して、第一の被覆絶縁膜を実現することができる。その結果、構造を簡単にすることが容易になる。 According to a third configuration, in the first or second configuration, the substrate further includes a thin film transistor provided on a surface of the substrate on which the photodiode is formed, and the thin film transistor is formed on the substrate. A transistor semiconductor film having a channel region, a source region, and a drain region; a gate electrode that controls conductivity of the channel region; and a gate insulation provided between the gate electrode and the transistor semiconductor. And the gate insulating film is the first covering insulating film. In such a configuration, the first covering insulating film can be realized by skillfully using the gate insulating film included in the thin film transistor. As a result, it becomes easy to simplify the structure.
　第４の構成は、前記第３の構成において、前記ゲート絶縁膜上に形成されて、前記ゲート電極を被覆するゲート電極被覆膜を更に備えており、前記ゲート電極被覆膜が前記第二の被覆絶縁膜とされている構成である。このような構成においては、ゲート電極被覆膜を巧く利用して、第二の被覆絶縁膜を実現することができる。その結果、構造を簡単にすることが容易になる。 A fourth configuration further includes a gate electrode coating film that is formed on the gate insulating film and covers the gate electrode in the third configuration, and the gate electrode coating film is the second configuration. It is the structure made into the coating insulating film. In such a configuration, the second coating insulating film can be realized by skillfully using the gate electrode coating film. As a result, it becomes easy to simplify the structure.
　以下、本発明のより具体的な実施形態について、図面を参照しながら説明する。なお、以下で参照する各図は、説明の便宜上、本発明の実施形態の構成部材のうち、本発明を説明するために必要な主要部材のみを簡略化して示したものである。従って、本発明に係る液晶パネルは、本明細書が参照する各図に示されていない任意の構成部材を備え得る。また、各図中の部材の寸法は、実際の構成部材の寸法および各部材の寸法比率等を忠実に表したものではない。 Hereinafter, more specific embodiments of the present invention will be described with reference to the drawings. In addition, each figure referred below demonstrates the simplified main component required in order to demonstrate this invention among the structural members of embodiment of this invention for convenience of explanation. Therefore, the liquid crystal panel according to the present invention can include arbitrary constituent members not shown in the drawings referred to in this specification. Moreover, the dimension of the member in each figure does not represent the dimension of an actual structural member, the dimension ratio of each member, etc. faithfully.
　［実施形態］
　図１には、本発明の一実施形態としての液晶パネル１０が示されている。この液晶パネル１０は、アクティブマトリクス基板１２と、対向基板１４と、これらの基板１２，１４の間に封入された液晶層１６とを備えている。 [Embodiment]
FIG. 1 shows a liquid crystal panel 10 as an embodiment of the present invention. The liquid crystal panel 10 includes an active matrix substrate 12, a counter substrate 14, and a liquid crystal layer 16 sealed between the substrates 12 and 14.
　アクティブマトリクス基板１２には、複数の画素（図示せず）が形成されている。各画素は、アクティブ素子としての薄膜トランジスタと、画素電極とを備えている。アクティブマトリクス基板１２において、複数の画素が形成されている領域が、図示しない表示領域となる。 A plurality of pixels (not shown) are formed on the active matrix substrate 12. Each pixel includes a thin film transistor as an active element and a pixel electrode. In the active matrix substrate 12, a region where a plurality of pixels are formed is a display region (not shown).
　アクティブマトリクス基板１２に形成された表示領域と対向する位置において、対向基板１４が配置されている。図示はされていないが、対向基板１４には、対向電極と、カラーフィルタとが設けられている。なお、対向基板１４において、カラーフィルタは必ずしも必要ではない。カラーフィルタをアクティブマトリクス基板１２側に設けることも、勿論、可能である。また、液晶パネル１０において、カラー表示を行わないのであれば、カラーフィルタそのものを設ける必要がない。 The counter substrate 14 is arranged at a position facing the display area formed on the active matrix substrate 12. Although not shown, the counter substrate 14 is provided with a counter electrode and a color filter. Note that a color filter is not necessarily required in the counter substrate 14. It is of course possible to provide a color filter on the active matrix substrate 12 side. If the liquid crystal panel 10 does not perform color display, it is not necessary to provide a color filter itself.
　アクティブマトリクス基板１２と対向基板１４との間には、液晶層１６が封入されている。液晶の動作モードとしては、例えば、ＴＮ（twisted nematic）モード等を採用することができる。 A liquid crystal layer 16 is sealed between the active matrix substrate 12 and the counter substrate 14. As an operation mode of the liquid crystal, for example, a TN (twisted nematic) mode or the like can be adopted.
　アクティブマトリクス基板１２には、図２に示されているように、フォトダイオード１８と、薄膜トランジスタ２０とが形成されている。フォトダイオード１８としては、例えば、タッチセンサ機能を実現するためのフォトダイオード等がある。薄膜トランジスタ２０としては、例えば、アクティブマトリクス基板１２に形成された各画素が備えるアクティブ素子としての薄膜トランジスタや、フォトダイオード１８の出力を増幅するアンプトランジスタとしての薄膜トランジスタ等がある。 As shown in FIG. 2, a photodiode 18 and a thin film transistor 20 are formed on the active matrix substrate 12. Examples of the photodiode 18 include a photodiode for realizing a touch sensor function. Examples of the thin film transistor 20 include a thin film transistor as an active element included in each pixel formed on the active matrix substrate 12 and a thin film transistor as an amplifier transistor that amplifies the output of the photodiode 18.
　フォトダイオード１８は、図２に示されているように、アクティブマトリクス基板１２が備える基板２２上に形成されている。基板２２としては、例えば、低アルカリガラス基板や石英基板等を採用することができる。 The photodiode 18 is formed on a substrate 22 included in the active matrix substrate 12 as shown in FIG. As the substrate 22, for example, a low alkali glass substrate or a quartz substrate can be employed.
　フォトダイオード１８は、基板２２上に設けられたダイオード用半導体膜２４を備えている。本実施形態では、基板２２上に形成された下地層２６を介して、ダイオード用半導体膜２４が基板２２上に形成されている。下地層２６は、基板２２からの不純物拡散を防ぐために設けられている。下地層２６としては、例えば、酸化シリコン膜等を採用することができる。下地層２６の厚さは、１００～６００ｎｍである。 The photodiode 18 includes a semiconductor film for diode 24 provided on the substrate 22. In the present embodiment, the semiconductor film 24 for a diode is formed on the substrate 22 through the base layer 26 formed on the substrate 22. The underlayer 26 is provided to prevent impurity diffusion from the substrate 22. As the foundation layer 26, for example, a silicon oxide film or the like can be employed. The thickness of the underlayer 26 is 100 to 600 nm.
　ダイオード用半導体膜２４としては、例えば、非晶質シリコン膜や結晶質シリコン膜等を採用することができる。結晶質シリコン膜としては、例えば、低温ポリシリコン膜や高温ポリシリコン膜，連続粒界シリコン膜，微結晶シリコン膜等を採用することができる。ダイオード用半導体膜２４の厚さは、２５～１００ｎｍである。 As the diode semiconductor film 24, for example, an amorphous silicon film or a crystalline silicon film can be employed. As the crystalline silicon film, for example, a low-temperature polysilicon film, a high-temperature polysilicon film, a continuous grain boundary silicon film, a microcrystalline silicon film, or the like can be employed. The thickness of the diode semiconductor film 24 is 25 to 100 nm.
　ダイオード用半導体膜２４には、ｐ型半導体領域２４ｐと、真性半導体領域２４ｉと、ｎ型半導体領域２４ｎとが、この順番で下地層２６に沿って並ぶように形成されている。このことから明らかなように、フォトダイオード１８は、いわゆるラテラル構造のＰＩＮダイオードである。 In the diode semiconductor film 24, a p-type semiconductor region 24p, an intrinsic semiconductor region 24i, and an n-type semiconductor region 24n are formed so as to be arranged along the base layer 26 in this order. As is apparent from this, the photodiode 18 is a so-called lateral structure PIN diode.
　このようなフォトダイオード１８（ダイオード用半導体膜２４）の下方には、基板２２上に形成されて且つ下地層２６で覆われた遮光膜２８が設けられている。これにより、基板２２を通過した光が、ダイオード用半導体膜２４に入射するのを防いでいる。 A light shielding film 28 formed on the substrate 22 and covered with the underlayer 26 is provided below the photodiode 18 (diode semiconductor film 24). This prevents light that has passed through the substrate 22 from entering the diode semiconductor film 24.
　遮光膜２８としては、例えば、金属膜を採用することができる。アクティブマトリクス基板１２の製造方法を考慮すると、遮光膜２８としては、高融点金属であるタンタルやタングステン，モリブデン等で形成された金属膜を採用することが望ましい。遮光膜２８の厚さは、２００～３００ｎｍである。 As the light shielding film 28, for example, a metal film can be adopted. Considering the manufacturing method of the active matrix substrate 12, it is desirable to employ a metal film formed of a refractory metal such as tantalum, tungsten, or molybdenum as the light shielding film 28. The thickness of the light shielding film 28 is 200 to 300 nm.
　フォトダイオード１８（ダイオード用半導体膜２４）を覆うようにして、第一の被覆絶縁膜としてのゲート絶縁膜３０が下地層２６上に形成されている。ゲート絶縁膜３０は、フォトダイオード１８だけでなく、後述するトランジスタ用半導体膜４４も覆っている。 A gate insulating film 30 as a first covering insulating film is formed on the base layer 26 so as to cover the photodiode 18 (diode semiconductor film 24). The gate insulating film 30 covers not only the photodiode 18 but also a transistor semiconductor film 44 described later.
　ゲート絶縁膜３０としては、例えば、酸化シリコン膜やシリコンオキシナイトライト（ＳｉＯＮ）膜、シリコンオキシナイトハイドライト（ＳｉＯＮＨ）膜等を採用することができる。因みに、本実施形態では、ゲート絶縁膜３０として、酸化シリコン膜が採用されている。 As the gate insulating film 30, for example, a silicon oxide film, a silicon oxynitrite (SiON) film, a silicon oxynitride hydride (SiONH) film, or the like can be employed. Incidentally, in this embodiment, a silicon oxide film is employed as the gate insulating film 30.
　ゲート絶縁膜３０の厚さは、フォトダイオード１８に入射する光の波長の１／４以上の大きさである。例えば、フォトダイオード１８に入射する光が可視光である場合、可視光の波長域は３８０～７８０ｎｍであるから、ゲート絶縁膜３０の厚さは９５ｎｍ以上に設定される。 The thickness of the gate insulating film 30 is not less than 1/4 of the wavelength of light incident on the photodiode 18. For example, when the light incident on the photodiode 18 is visible light, the wavelength range of visible light is 380 to 780 nm, so the thickness of the gate insulating film 30 is set to 95 nm or more.
　なお、ゲート絶縁膜３０の厚さの下限を設定する方法としては、上述のように、フォトダイオード１８に入射する光がある波長域を有する場合において、当該波長域の下限値の１／４以上の大きさにゲート絶縁膜３０の厚さを設定する方法に限定されない。例えば、フォトダイオード１８に入射する光の分光特性を調べて、最も高いピーク値を示す波長の１／４以上の大きさにゲート絶縁膜３０の厚さを設定する方法等も、採用することができる。 In addition, as a method of setting the lower limit of the thickness of the gate insulating film 30, as described above, when the light incident on the photodiode 18 has a certain wavelength region, the lower limit value of the wavelength region is ¼ or more. It is not limited to the method of setting the thickness of the gate insulating film 30 to the size of. For example, a method of examining the spectral characteristics of light incident on the photodiode 18 and setting the thickness of the gate insulating film 30 to a size equal to or larger than ¼ of the wavelength showing the highest peak value can be adopted. it can.
　また、ゲート絶縁膜３０の厚さは、フォトダイオード１８に入射する光の波長の１／２以下の大きさであることが望ましい。例えば、フォトダイオード１８に入射する光が可視光である場合、ゲート絶縁膜３０の厚さは、好ましくは３９０ｎｍ以下に、より好ましくは１９０ｎｍ以下に設定される。 Further, it is desirable that the thickness of the gate insulating film 30 is not more than ½ of the wavelength of light incident on the photodiode 18. For example, when the light incident on the photodiode 18 is visible light, the thickness of the gate insulating film 30 is preferably set to 390 nm or less, more preferably 190 nm or less.
　なお、ゲート絶縁膜３０の厚さの上限を設定する方法としては、上述のように、フォトダイオード１８に入射する光がある波長域を有する場合において、当該波長域の上限値若しくは下限値の１／２以下の大きさにゲート絶縁膜３０の厚さを設定する方法に限定されない。例えば、フォトダイオード１８に入射する光の分光特性を調べて、最も高いピーク値を有する波長の１／２以下の大きさにゲート絶縁膜３０の厚さを設定する方法等も、採用することができる。 In addition, as a method of setting the upper limit of the thickness of the gate insulating film 30, as described above, when light incident on the photodiode 18 has a certain wavelength range, the upper limit value or the lower limit value of the wavelength range is 1 It is not limited to the method of setting the thickness of the gate insulating film 30 to a size of / 2 or less. For example, a method of examining the spectral characteristics of the light incident on the photodiode 18 and setting the thickness of the gate insulating film 30 to a size equal to or smaller than ½ of the wavelength having the highest peak value may be adopted. it can.
　ゲート絶縁膜３０上には、層間絶縁膜３２が形成されている。本実施形態の層間絶縁膜３２は、第二の被覆絶縁膜としての下側層間絶縁膜３２ａと、上側層間絶縁膜３２ｂとが、この順番で積層されたものである。即ち、本実施形態では、ゲート絶縁膜３０と、下側層間絶縁膜３２ａとによって、被覆絶縁膜が実現されている。 An interlayer insulating film 32 is formed on the gate insulating film 30. The interlayer insulating film 32 of this embodiment is formed by laminating a lower interlayer insulating film 32a as a second covering insulating film and an upper interlayer insulating film 32b in this order. That is, in the present embodiment, a covering insulating film is realized by the gate insulating film 30 and the lower interlayer insulating film 32a.
　下側層間絶縁膜３２ａは、ゲート絶縁膜３０を覆うようにして、ゲート絶縁膜３０上に形成されている。下側層間絶縁膜３２ａの屈折率は、ゲート絶縁膜３０の屈折率よりも大きくされている。下側層間絶縁膜３２ａの厚さは、５０～８００ｎｍである。 The lower interlayer insulating film 32 a is formed on the gate insulating film 30 so as to cover the gate insulating film 30. The refractive index of the lower interlayer insulating film 32a is made larger than the refractive index of the gate insulating film 30. The thickness of the lower interlayer insulating film 32a is 50 to 800 nm.
　下側層間絶縁膜３２ａとしては、例えば、窒化シリコン膜やＳｉＯＮ膜、ＳｉＯＮＨ膜等を採用することができる。因みに、本実施形態では、ゲート絶縁膜３０として採用されている酸化シリコン膜よりも屈折率が大きい窒化シリコン膜が、下側層間絶縁膜３２ａとして、採用されている。 As the lower interlayer insulating film 32a, for example, a silicon nitride film, a SiON film, a SiONH film, or the like can be employed. Incidentally, in this embodiment, a silicon nitride film having a refractive index larger than that of the silicon oxide film employed as the gate insulating film 30 is employed as the lower interlayer insulating film 32a.
　なお、ゲート絶縁膜３０と下側層間絶縁膜３２ａとの組み合わせとしては、上述のような組み合わせに限定されない。ゲート絶縁膜３０が酸化シリコン膜である場合、下側層間絶縁膜３２ａとしては、窒化シリコン膜の他に、例えば、ＳｉＯＮ膜やＳｉＯＮＨ膜等を採用することができる。ゲート絶縁膜３０がＳｉＯＮ膜である場合、下側層間絶縁膜３２ａとしては、例えば、窒化シリコン膜やＳｉＯＮＨ膜等を採用することができる。ゲート絶縁膜３０がＳｉＯＮＨ膜である場合、下側層間絶縁膜３２ａとしては、例えば、窒化シリコン膜やＳｉＯＮ膜等を採用することができる。 It should be noted that the combination of the gate insulating film 30 and the lower interlayer insulating film 32a is not limited to the above combination. When the gate insulating film 30 is a silicon oxide film, for example, a SiON film or a SiONH film can be employed as the lower interlayer insulating film 32a in addition to the silicon nitride film. When the gate insulating film 30 is a SiON film, for example, a silicon nitride film or a SiONH film can be employed as the lower interlayer insulating film 32a. When the gate insulating film 30 is a SiONH film, for example, a silicon nitride film or a SiON film can be employed as the lower interlayer insulating film 32a.
　上側層間絶縁膜３２ｂは、下側層間絶縁膜３２ａを覆うようにして、下側層間絶縁膜３２ａ上に形成されている。上側層間絶縁膜３２ｂとしては、例えば、酸化シリコン膜等を採用することができる。 The upper interlayer insulating film 32b is formed on the lower interlayer insulating film 32a so as to cover the lower interlayer insulating film 32a. For example, a silicon oxide film or the like can be employed as the upper interlayer insulating film 32b.
　層間絶縁膜３２及びゲート絶縁膜３０には、層間絶縁膜３２及びゲート絶縁膜３０を厚さ方向に貫通するコンタクトホール３４，３６が形成されている。コンタクトホール３４は、基板２２の平面視において、ｐ型半導体領域２４ｐと重なる位置に形成されている。コンタクトホール３６は、基板２２の平面視において、ｎ型半導体領域２４ｎと重なる位置に形成されている。このようにして、コンタクトホール３４，３６が形成されていることにより、ｐ型半導体領域２４ｐとｎ型半導体領域２４ｎのそれぞれに対して、層間絶縁膜３２上に形成された電極・配線３８，４０が接続されている。電極・配線３８，４０としては、例えば、窒化チタン膜とアルミニウム膜の二層構造を有するもの等を採用することができる。 In the interlayer insulating film 32 and the gate insulating film 30, contact holes 34 and 36 penetrating the interlayer insulating film 32 and the gate insulating film 30 in the thickness direction are formed. The contact hole 34 is formed at a position that overlaps with the p-type semiconductor region 24p in plan view of the substrate 22. The contact hole 36 is formed at a position overlapping the n-type semiconductor region 24n in the plan view of the substrate 22. By forming the contact holes 34 and 36 in this way, electrodes / wirings 38 and 40 formed on the interlayer insulating film 32 for the p-type semiconductor region 24p and the n-type semiconductor region 24n, respectively. Is connected. As the electrodes / wirings 38 and 40, for example, those having a two-layer structure of a titanium nitride film and an aluminum film can be employed.
　電極・配線３８，４０を覆うようにして、平坦化膜４２が層間絶縁膜３２上に形成されている。平坦化膜４２としては、例えば、感光性アクリル樹脂等の有機絶縁膜の他、酸化シリコン膜等を採用することができる。平坦化膜４２の厚さは、１０００～４０００ｎｍである。 A planarizing film 42 is formed on the interlayer insulating film 32 so as to cover the electrodes / wirings 38 and 40. As the planarizing film 42, for example, a silicon oxide film or the like can be employed in addition to an organic insulating film such as a photosensitive acrylic resin. The thickness of the planarizing film 42 is 1000 to 4000 nm.
　一方、薄膜トランジスタ２０は、基板２２上に設けられたトランジスタ用半導体膜４４を備えている。本実施形態では、基板２２上に形成された下地層２６を介して、トランジスタ用半導体膜４４が基板２２上に形成されている。即ち、トランジスタ用半導体膜４４は、ダイオード用半導体膜２４と同一層上に形成されている。 On the other hand, the thin film transistor 20 includes a transistor semiconductor film 44 provided on the substrate 22. In the present embodiment, the transistor semiconductor film 44 is formed on the substrate 22 via the base layer 26 formed on the substrate 22. That is, the transistor semiconductor film 44 is formed on the same layer as the diode semiconductor film 24.
　トランジスタ用半導体膜４４としては、例えば、非晶質シリコン膜や結晶質シリコン膜等を採用することができる。結晶質シリコン膜としては、例えば、低温ポリシリコン膜や高温ポリシリコン膜，連続粒界シリコン膜，微結晶シリコン膜等を採用することができる。 As the transistor semiconductor film 44, for example, an amorphous silicon film or a crystalline silicon film can be employed. As the crystalline silicon film, for example, a low-temperature polysilicon film, a high-temperature polysilicon film, a continuous grain boundary silicon film, a microcrystalline silicon film, or the like can be employed.
　トランジスタ用半導体膜４４の厚さは、２５～１００ｎｍである。因みに、本実施形態では、トランジスタ用半導体膜４４の厚さと、ダイオード用半導体膜２４の厚さとは同じである。 The thickness of the transistor semiconductor film 44 is 25 to 100 nm. Incidentally, in the present embodiment, the thickness of the transistor semiconductor film 44 and the thickness of the diode semiconductor film 24 are the same.
　トランジスタ用半導体膜４４には、ソース領域４４ｓと、チャネル領域４４ｃと、ドレイン領域４４ｄとが、この順番で下地層２６に沿って並ぶように形成されている。 In the transistor semiconductor film 44, a source region 44s, a channel region 44c, and a drain region 44d are formed along the base layer 26 in this order.
　薄膜トランジスタ２０は、トランジスタ用半導体膜４４を覆うようにして、下地層２６上に形成されたゲート絶縁膜３０を備えている。 The thin film transistor 20 includes a gate insulating film 30 formed on the base layer 26 so as to cover the transistor semiconductor film 44.
　薄膜トランジスタ２０は、ゲート絶縁膜３０上に形成されたゲート電極４６を備えている。ゲート電極４６は、基板２２の平面視において、チャネル領域４４ｃを覆う位置に形成されている。ゲート電極４６にゲート電圧を印加することによって、ソース領域４４ｓとドレイン領域４４ｄが接続されるようになっている。 The thin film transistor 20 includes a gate electrode 46 formed on the gate insulating film 30. The gate electrode 46 is formed at a position covering the channel region 44 c in plan view of the substrate 22. By applying a gate voltage to the gate electrode 46, the source region 44s and the drain region 44d are connected.
　ゲート電極４６としては、例えば、高融点金属であるタングステンやタンタル，チタン，モリブデン、或いは、これら高融点金属の合金材料等で形成された金属膜を採用することができる。ゲート電極４６の厚さは、３００～６００ｎｍである。 As the gate electrode 46, for example, a high melting point metal such as tungsten, tantalum, titanium, molybdenum, or an alloy material of these high melting point metals can be employed. The thickness of the gate electrode 46 is 300 to 600 nm.
　ゲート電極４６は、ゲート絶縁膜３０上に形成された層間絶縁膜３２によって覆われている。即ち、本実施形態では、下側層間絶縁膜３２ａによって、ゲート電極被覆膜が実現されている。 The gate electrode 46 is covered with an interlayer insulating film 32 formed on the gate insulating film 30. That is, in this embodiment, the gate electrode coating film is realized by the lower interlayer insulating film 32a.
　層間絶縁膜３２には、層間絶縁膜３２を厚さ方向に貫通するコンタクトホール４８，５０が形成されている。コンタクトホール４８は、基板２２の平面視において、ソース領域４４ｓと重なる位置に形成されている。コンタクトホール５０は、基板２２の平面視において、ドレイン領域４４ｄと重なる位置に形成されている。このようにして、コンタクトホール４８，５０が形成されていることにより、ソース領域４４ｓとドレイン領域４４ｄのそれぞれに対して、層間絶縁膜３２上に形成された電極・配線５２，５４が接続されている。即ち、本実施形態では、電極・配線５２，５４と、電極・配線３８，４０とが、同一層上に形成されている。 In the interlayer insulating film 32, contact holes 48 and 50 penetrating the interlayer insulating film 32 in the thickness direction are formed. The contact hole 48 is formed at a position overlapping the source region 44 s in plan view of the substrate 22. The contact hole 50 is formed at a position overlapping the drain region 44d when the substrate 22 is viewed in plan. By forming the contact holes 48 and 50 in this way, the electrodes / wirings 52 and 54 formed on the interlayer insulating film 32 are connected to the source region 44s and the drain region 44d, respectively. Yes. That is, in this embodiment, the electrodes / wirings 52 and 54 and the electrodes / wirings 38 and 40 are formed on the same layer.
　電極・配線５２，５４としては、例えば、窒化チタン膜とアルミニウム膜の二層構造を有するもの等を採用することができる。電極・配線５２，５４を覆うようにして、平坦化膜４２が層間絶縁膜３２上に形成されている。 As the electrodes / wirings 52 and 54, for example, those having a two-layer structure of a titanium nitride film and an aluminum film can be employed. A planarizing film 42 is formed on the interlayer insulating film 32 so as to cover the electrodes / wirings 52 and 54.
　続いて、液晶パネル１０が備えるアクティブマトリクス基板１２の製造方法について、説明する。なお、アクティブマトリクス基板１２の製造方法は、以下に記載の製造方法に限定されない。 Subsequently, a method for manufacturing the active matrix substrate 12 included in the liquid crystal panel 10 will be described. The manufacturing method of the active matrix substrate 12 is not limited to the manufacturing method described below.
　先ず、遮光膜２８を基板２２上の所定位置に形成する。具体的には、先ず、後に遮光膜２８となる金属膜をスパッタによって基板２２の上面全体に形成する。その後、この金属膜をフォトリソグラフィによってパターニングする。これにより、図３Ａに示されているように、遮光膜２８が基板２２上の所定位置に形成される。 First, the light shielding film 28 is formed at a predetermined position on the substrate 22. Specifically, first, a metal film that will later become the light shielding film 28 is formed on the entire upper surface of the substrate 22 by sputtering. Thereafter, this metal film is patterned by photolithography. Thereby, as shown in FIG. 3A, the light shielding film 28 is formed at a predetermined position on the substrate 22.
　次に、下地層２６をＣＶＤ（Chemical Vapor Deposition）によって基板２２の上面側に形成する。これにより、基板２２の上面側全体が下地層２６で覆われる。 Next, the base layer 26 is formed on the upper surface side of the substrate 22 by CVD (Chemical Vapor Deposition). Thereby, the entire upper surface side of the substrate 22 is covered with the base layer 26.
　続いて、ダイオード用半導体膜２４とトランジスタ用半導体膜４４とを下地層２６上に形成する。具体的には、先ず、アモルファスシリコン膜をプラズマＣＶＤやスパッタ等によって下地層２６の上面全体に形成する。続いて、アモルファスシリコン膜にエキシマレーザーを照射する。これにより、下地層２６の上面全体を覆うポリシリコン膜が形成される。その後、ポリシリコン膜をフォトリソグラフィによってパターニングする。これにより、図３Ｂに示されているように、ダイオード用半導体膜２４とトランジスタ用半導体膜４４が下地層２６上の所定位置に形成される。 Subsequently, a diode semiconductor film 24 and a transistor semiconductor film 44 are formed on the base layer 26. Specifically, first, an amorphous silicon film is formed on the entire upper surface of the base layer 26 by plasma CVD, sputtering, or the like. Subsequently, excimer laser is irradiated to the amorphous silicon film. Thereby, a polysilicon film covering the entire upper surface of the underlayer 26 is formed. Thereafter, the polysilicon film is patterned by photolithography. As a result, as shown in FIG. 3B, the diode semiconductor film 24 and the transistor semiconductor film 44 are formed at predetermined positions on the base layer 26.
　次に、ゲート絶縁膜３０をプラズマＣＶＤ等によって基板２２の上側に形成する。これにより、基板２２の上面側全体がゲート絶縁膜３０で覆われる。 Next, the gate insulating film 30 is formed on the upper side of the substrate 22 by plasma CVD or the like. As a result, the entire upper surface side of the substrate 22 is covered with the gate insulating film 30.
　続いて、ゲート電極４６をゲート絶縁膜３０上に形成する。具体的には、先ず、後にゲート電極４６となる導電膜をスパッタ又はＣＶＤ等によってゲート絶縁膜３０の上面全体に形成する。その後、この導電膜をフォトリソグラフィによってパターニングする。これにより、図３Ｃに示されているように、ゲート電極４６がゲート絶縁膜３０上の所定位置に形成される。 Subsequently, the gate electrode 46 is formed on the gate insulating film 30. Specifically, first, a conductive film that will later become the gate electrode 46 is formed on the entire upper surface of the gate insulating film 30 by sputtering or CVD. Thereafter, this conductive film is patterned by photolithography. As a result, the gate electrode 46 is formed at a predetermined position on the gate insulating film 30 as shown in FIG. 3C.
　次に、リン等のｎ型不純物をダイオード用半導体膜２４とトランジスタ用半導体膜４４とに注入する。具体的には、先ず、図３Ｄに示されているように、ダイオード用半導体膜２４の一部を覆うようにして、レジストからなるマスク５６をゲート絶縁膜３０上に形成する。その後、リン等のｎ型不純物をイオンドーピングする。これにより、ダイオード用半導体膜２４においてマスク５６で覆われていない領域とトランジスタ用半導体膜４４においてゲート電極４６で覆われていない領域とにｎ型不純物が注入される。その結果、ダイオード用半導体膜２４には、ｎ型半導体領域２４ｎが形成される。トランジスタ用半導体膜４４には、ソース領域４４ｓとドレイン領域４４ｄとが形成される。トランジスタ用半導体膜４４においてｎ型不純物が注入されていない領域は、真性半導体で形成されたチャネル領域４４ｃとなる。ダイオード用半導体膜２４及びトランジスタ用半導体膜４４へのｎ型不純物の注入が終了したら、マスク５６を除去する。 Next, an n-type impurity such as phosphorus is implanted into the diode semiconductor film 24 and the transistor semiconductor film 44. Specifically, first, as shown in FIG. 3D, a mask 56 made of a resist is formed on the gate insulating film 30 so as to cover a part of the semiconductor film 24 for diode. Thereafter, n-type impurities such as phosphorus are ion-doped. As a result, the n-type impurity is implanted into a region of the diode semiconductor film 24 that is not covered with the mask 56 and a region of the transistor semiconductor film 44 that is not covered with the gate electrode 46. As a result, an n-type semiconductor region 24n is formed in the diode semiconductor film 24. In the transistor semiconductor film 44, a source region 44s and a drain region 44d are formed. A region where the n-type impurity is not implanted in the transistor semiconductor film 44 is a channel region 44c formed of an intrinsic semiconductor. When the implantation of the n-type impurity into the diode semiconductor film 24 and the transistor semiconductor film 44 is completed, the mask 56 is removed.
　続いて、ボロン等のｐ型不純物をダイオード用半導体膜２４に注入する。具体的には、先ず、図３Ｅに示されているように、ダイオード用半導体膜２４の一部とトランジスタ用半導体膜４４の全体とを覆うようにして、レジストからなるマスク５８をゲート絶縁膜３０上に形成する。その後、ボロン等のｐ型不純物をイオンドーピングする。これにより、ダイオード用半導体膜２４においてマスク５８で覆われていない領域にｐ型不純物が注入される。その結果、ｐ型半導体領域２４ｐがダイオード用半導体膜２４に形成される。ダイオード用半導体膜２４においてｎ型不純物もｐ型不純物も注入されなかった領域は、真性半導体で形成された真性半導体領域２４ｉとなる。ダイオード用半導体膜２４へのｐ型不純物の注入が終了したら、マスク５８を除去する。 Subsequently, a p-type impurity such as boron is implanted into the diode semiconductor film 24. Specifically, first, as shown in FIG. 3E, a mask 58 made of resist is applied to the gate insulating film 30 so as to cover a part of the semiconductor film for diode 24 and the entire semiconductor film for transistor 44. Form on top. Thereafter, p-type impurities such as boron are ion-doped. As a result, the p-type impurity is implanted into a region of the diode semiconductor film 24 that is not covered with the mask 58. As a result, the p-type semiconductor region 24p is formed in the diode semiconductor film 24. In the diode semiconductor film 24, the region where neither the n-type impurity nor the p-type impurity is implanted becomes an intrinsic semiconductor region 24i formed of an intrinsic semiconductor. When the implantation of the p-type impurity into the diode semiconductor film 24 is completed, the mask 58 is removed.
　次に、ダイオード用半導体膜２４及びトランジスタ用半導体膜４４へ注入した不純物を活性化させる。具体的には、不活性雰囲気下で、ＲＴＡ（Rapid Thermal Annealing）による熱処理を行う。これにより、ダイオード用半導体膜２４のｎ型半導体領域２４ｎ及びｐ型半導体領域２４ｐと、トランジスタ用半導体膜４４のソース領域４４ｓ及びドレイン領域４４ｄとにおいて、イオンドーピングの際に生じた結晶欠陥等のドーピングダメージが回復し、注入された不純物が活性化される。 Next, the impurities implanted into the diode semiconductor film 24 and the transistor semiconductor film 44 are activated. Specifically, heat treatment by RTA (Rapid Thermal Annealing) is performed in an inert atmosphere. Thereby, in the n-type semiconductor region 24n and the p-type semiconductor region 24p of the diode semiconductor film 24 and the source region 44s and the drain region 44d of the transistor semiconductor film 44, doping such as crystal defects generated during ion doping is performed. Damage is restored and the implanted impurities are activated.
　続いて、層間絶縁膜３２をプラズマＣＶＤ等によって基板２２の上側に形成する。これにより、基板２２の上面側全体が層間絶縁膜３２で覆われる。 Subsequently, an interlayer insulating film 32 is formed on the upper side of the substrate 22 by plasma CVD or the like. As a result, the entire upper surface side of the substrate 22 is covered with the interlayer insulating film 32.
　このようにして形成された層間絶縁膜３２及びゲート絶縁膜３０に対して、図３Ｆに示されているように、層間絶縁膜３２及びゲート絶縁膜３０を厚さ方向に貫通するコンタクトホール３４，３６，４８，５０を形成する。コンタクトホール３４，３６，４８，５０は、フォトリソグラフィによって形成される。 With respect to the interlayer insulating film 32 and the gate insulating film 30 thus formed, as shown in FIG. 3F, contact holes 34 penetrating the interlayer insulating film 32 and the gate insulating film 30 in the thickness direction, 36, 48 and 50 are formed. The contact holes 34, 36, 48, 50 are formed by photolithography.
　次に、電極・配線３８，４０，５２，５４を層間絶縁膜３２上に形成する。具体的には、先ず、後に電極・配線３８，４０，５２，５４となる導電膜をスパッタやＣＶＤ等によって基板２２の上側に形成する。これにより、基板２２の上面側全体が導電膜で覆われる。その後、導電膜をフォトリソグラフィによってパターニングする。これにより、図３Ｇに示されているように、電極・配線３８，４０，５２，５４が層間絶縁膜３２上に形成される。 Next, electrodes / wirings 38, 40, 52, 54 are formed on the interlayer insulating film 32. Specifically, first, a conductive film that will later become electrodes / wirings 38, 40, 52, 54 is formed on the upper side of the substrate 22 by sputtering, CVD, or the like. Thereby, the whole upper surface side of the substrate 22 is covered with the conductive film. Thereafter, the conductive film is patterned by photolithography. As a result, electrodes / wirings 38, 40, 52, 54 are formed on the interlayer insulating film 32 as shown in FIG. 3G.
　続いて、平坦化膜４２を基板２２の上側に形成する。平坦化膜４２が感光性アクリル樹脂等の有機絶縁膜である場合、平坦化膜４２をスピンコータによって形成する。平坦化膜４２が酸化シリコン膜等の無機絶縁膜である場合、平坦化膜４２をプラズマＣＶＤ等によって形成する。これにより、基板２２の上面側全体が平坦化膜４２で覆われる。その結果、目的とするアクティブマトリクス基板１２が得られる。 Subsequently, a planarizing film 42 is formed on the upper side of the substrate 22. When the planarizing film 42 is an organic insulating film such as a photosensitive acrylic resin, the planarizing film 42 is formed by a spin coater. When the planarizing film 42 is an inorganic insulating film such as a silicon oxide film, the planarizing film 42 is formed by plasma CVD or the like. Thereby, the entire upper surface side of the substrate 22 is covered with the planarizing film 42. As a result, the target active matrix substrate 12 is obtained.
　このような液晶パネル１０においては、ゲート絶縁膜３０の膜厚がフォトダイオード１８に入射する光の波長の１／４以上に設定されていると共に、下側層間絶縁膜３２ａの屈折率がゲート絶縁膜３０の屈折率よりも大きくされている。これにより、ゲート絶縁膜３０内で光の干渉を発生させることができる。その結果、図４に示されているように、光が何度もフォトダイオード１８に入射する状態を作り出すことが可能となる。 In such a liquid crystal panel 10, the thickness of the gate insulating film 30 is set to ¼ or more of the wavelength of light incident on the photodiode 18, and the refractive index of the lower interlayer insulating film 32a is set to be gate insulating. The refractive index of the film 30 is made larger. Thereby, light interference can be generated in the gate insulating film 30. As a result, as shown in FIG. 4, it is possible to create a state in which light is incident on the photodiode 18 many times.
　従って、液晶パネル１０においては、集光レンズ等を別途設けなくても、光の利用効率を上げることができる。その結果、フォトダイオード１８の光検出感度の向上を図ることが可能となる。 Therefore, in the liquid crystal panel 10, the light utilization efficiency can be increased without providing a condensing lens or the like separately. As a result, it is possible to improve the light detection sensitivity of the photodiode 18.
　また、ゲート絶縁膜３０の膜厚がフォトダイオード１８に入射する光の波長の１／２よりも小さくされている。これにより、ゲート絶縁膜３０の形成に要する時間を短くすることができる。 The film thickness of the gate insulating film 30 is set to be smaller than ½ of the wavelength of light incident on the photodiode 18. Thereby, the time required for forming the gate insulating film 30 can be shortened.
　また、薄膜トランジスタ２０が有するゲート絶縁膜３０を巧く利用して、第一の被覆絶縁膜が実現されている。その結果、構造を簡単にすることが容易になる。 Further, the first covering insulating film is realized by skillfully using the gate insulating film 30 included in the thin film transistor 20. As a result, it becomes easy to simplify the structure.
　また、下側層間絶縁膜３２ａを巧く利用して、第二の被覆絶縁膜が実現されている。その結果、構造を簡単にすることが容易になる。 Further, the second covering insulating film is realized by skillfully using the lower interlayer insulating film 32a. As a result, it becomes easy to simplify the structure.
　本実施形態の構成の効果を検証するために、光学シミュレーションを行った。その結果を、図５に示す。光学シミュレーションは、フォトダイオード１８に入射する光の波長（光源波長）が、４００ｎｍの場合と、５００ｎｍの場合と、６００ｎｍの場合と、７００ｎｍの場合とについて、行った。 In order to verify the effect of the configuration of the present embodiment, an optical simulation was performed. The result is shown in FIG. The optical simulation was performed for the case where the wavelength of light incident on the photodiode 18 (light source wavelength) was 400 nm, 500 nm, 600 nm, and 700 nm.
　図５に示すグラフの横軸は、ゲート絶縁膜３０の膜厚をフォトダイオード１８へ入射する光の波長の１／４で正規化した値でプロットしている。例えば、図５に示すグラフの横軸の値が１というのは、フォトダイオード１８へ入射する光の波長が４００ｎｍであれば、ゲート絶縁膜３０の膜厚は１００ｎｍであり、フォトダイオード１８へ入射する光の波長が７００ｎｍであれば、ゲート絶縁膜３０の膜厚は１７５ｎｍである。図５に示すグラフの縦軸は、フォトダイオード１８の光検出感度である。 The horizontal axis of the graph shown in FIG. 5 plots the thickness of the gate insulating film 30 normalized by 1/4 of the wavelength of light incident on the photodiode 18. For example, when the value of the horizontal axis of the graph shown in FIG. 5 is 1, if the wavelength of light incident on the photodiode 18 is 400 nm, the thickness of the gate insulating film 30 is 100 nm, and the light enters the photodiode 18. If the wavelength of the light to be transmitted is 700 nm, the thickness of the gate insulating film 30 is 175 nm. The vertical axis of the graph shown in FIG. 5 is the photodetection sensitivity of the photodiode 18.
　図５のグラフより、横軸の値が１よりも小さくなる、即ち、ゲート絶縁膜３０の膜厚がフォトダイオード１８へ入射する光の波長の１／４よりも小さくなるに従って、フォトダイオード１８の光検出感度が減少する傾向を、フォトダイオード１８へ入射する光の波長が何れの場合であっても、確認することができる。換言すれば、フォトダイオード１８の光検出感度を向上させるためには、グラフの横軸の値が１以上となるように、即ち、ゲート絶縁膜３０の膜厚がフォトダイオード１８に入射する光の波長の１／４以上となるようにすれば良いことが判る。 From the graph of FIG. 5, as the value of the horizontal axis becomes smaller than 1, that is, as the film thickness of the gate insulating film 30 becomes smaller than ¼ of the wavelength of light incident on the photodiode 18, The tendency for the light detection sensitivity to decrease can be confirmed regardless of the wavelength of light incident on the photodiode 18. In other words, in order to improve the light detection sensitivity of the photodiode 18, the value of the horizontal axis of the graph is 1 or more, that is, the thickness of the gate insulating film 30 is the light incident on the photodiode 18. It can be seen that the wavelength should be ¼ or more of the wavelength.
　また、本実施形態の構成でのフォトダイオード１８の明電流値の累積度数分布と、比較例でのフォトダイオードの明電流値の累積度数分布を、図６に示す。比較例とは、ゲート絶縁膜３０の膜厚がフォトダイオード１８に入射する光の波長の１／４よりも小さい構成である。この実験においては、光源が発する光の分光特性を予め調べた。その結果、光源が発する光は、４４０ｎｍ付近に鋭いピークを有することが判った。そこで、本実施形態の構成においては、ゲート絶縁膜３０の厚さを１１０ｎｍ以上に設定して、実験を行った。比較例においては、ゲート絶縁膜３０の厚さを１１０ｎｍよりも小さくして、実験を行った。 Further, FIG. 6 shows the cumulative frequency distribution of the bright current value of the photodiode 18 in the configuration of the present embodiment and the cumulative frequency distribution of the bright current value of the photodiode in the comparative example. In the comparative example, the thickness of the gate insulating film 30 is smaller than ¼ of the wavelength of light incident on the photodiode 18. In this experiment, the spectral characteristics of light emitted from the light source were examined in advance. As a result, it was found that the light emitted from the light source has a sharp peak near 440 nm. Therefore, in the configuration of the present embodiment, the experiment was performed with the thickness of the gate insulating film 30 set to 110 nm or more. In the comparative example, the experiment was performed with the thickness of the gate insulating film 30 smaller than 110 nm.
　図６に示す累積度数分布図から明らかなように、本実施形態の構成は、比較例よりも、フォトダイオード１８の明電流値が約２０％増加しており、フォトダイオード１８の光検出感度の向上が実現できているのが判る。 As is clear from the cumulative frequency distribution diagram shown in FIG. 6, in the configuration of this embodiment, the bright current value of the photodiode 18 is increased by about 20% compared to the comparative example, and the photodetection sensitivity of the photodiode 18 is improved. It can be seen that improvement has been realized.
　以上、本発明の実施形態について、詳述してきたが、これはあくまでも例示であって、本発明は、上述の実施形態によって、何等、限定されない。 As mentioned above, although embodiment of this invention has been explained in full detail, this is an illustration to the last, Comprising: This invention is not limited at all by the above-mentioned embodiment.
　例えば、ゲート絶縁膜３０と、層間絶縁膜３２との間において、ゲート電極４６を保護するゲート保護膜を設けるようにしても良い。このような態様においては、ゲート保護膜が第二の被覆絶縁膜となる。 For example, a gate protective film that protects the gate electrode 46 may be provided between the gate insulating film 30 and the interlayer insulating film 32. In such an embodiment, the gate protective film becomes the second covering insulating film.
　また、本発明は、集光レンズが設けられた構造に対しても、勿論、適用可能である。 Of course, the present invention can be applied to a structure provided with a condenser lens.
　また、前記実施形態では、ゲート電極４６がトランジスタ半導体膜４４を挟んで基板２２とは反対側に位置する、いわゆるトップゲート構造の薄膜トランジスタ２０が採用されていたが、前記実施形態において、ゲート電極がトランジスタ用半導体膜よりも基板側に位置する、いわゆるボトムゲート構造の薄膜トランジスタを採用しても良い。 In the above embodiment, the so-called top gate thin film transistor 20 in which the gate electrode 46 is positioned on the opposite side of the substrate 22 with the transistor semiconductor film 44 interposed therebetween is employed. A thin film transistor having a so-called bottom gate structure, which is located closer to the substrate than the semiconductor film for a transistor, may be employed.
　この場合、図７に示すように、薄膜トランジスタ６０は、基板１８上に形成されたゲート電極６２を有する。ゲート電極６２は、例えば、タンタル、モリブデン、アルミニウム、チタン等の金属膜である。 In this case, as shown in FIG. 7, the thin film transistor 60 has a gate electrode 62 formed on the substrate 18. The gate electrode 62 is, for example, a metal film such as tantalum, molybdenum, aluminum, or titanium.
　ゲート電極６２上には、ゲート絶縁膜６４が形成されている。ゲート絶縁膜６４は、例えば、窒化シリコン膜である。 A gate insulating film 64 is formed on the gate electrode 62. The gate insulating film 64 is, for example, a silicon nitride film.
　ゲート絶縁膜６４上には、真性のアモルファスシリコン膜６６が形成されている。真性のアモルファスシリコン膜６６上には、ｎ型のアモルファスシリコン膜６７ａ，６７ｂが形成されている。 An intrinsic amorphous silicon film 66 is formed on the gate insulating film 64. On the intrinsic amorphous silicon film 66, n-type amorphous silicon films 67a and 67b are formed.
　ｎ型のアモルファスシリコン膜６７ａ上には、ソース電極６８が形成されている。ｎ型のアモルファスシリコン膜６７ｂ上には、ドレイン電極７０が形成されている。ソース電極６８と、ドレイン電極７０とは、例えば、アルミニウム、チタン等の金属膜である。 A source electrode 68 is formed on the n-type amorphous silicon film 67a. A drain electrode 70 is formed on the n-type amorphous silicon film 67b. The source electrode 68 and the drain electrode 70 are metal films, such as aluminum and titanium, for example.
　ソース電極６８と、ドレイン電極７０とは、保護膜７２によって覆われている。保護膜７２は、例えば、酸化シリコン膜である。 The source electrode 68 and the drain electrode 70 are covered with a protective film 72. The protective film 72 is, for example, a silicon oxide film.

Claims (4)

  1. 　基板上に形成されて、ｐ型半導体領域と真性半導体領域とｎ型半導体領域とを有するダイオード用半導体膜を備えるフォトダイオードと、
    　該フォトダイオードを覆うように形成された被覆絶縁膜と
    を備えており、
    　前記被覆絶縁膜が、
    　前記フォトダイオード上に形成された第一の被覆絶縁膜と、
    　該第一の被覆絶縁膜上に形成されて、該第一の被覆絶縁膜よりも大きな屈折率を有する第二の被覆絶縁膜と
    を備えており、
    　前記第一の被覆絶縁膜の膜厚が、前記フォトダイオードに入射する光の波長の１／４以上の大きさである、液晶パネル。     A photodiode comprising a semiconductor film for a diode formed on a substrate and having a p-type semiconductor region, an intrinsic semiconductor region, and an n-type semiconductor region;
    A coating insulating film formed so as to cover the photodiode,
    The covering insulating film is
    A first covering insulating film formed on the photodiode;
    A second covering insulating film formed on the first covering insulating film and having a higher refractive index than the first covering insulating film;
    A liquid crystal panel, wherein the film thickness of the first covering insulating film is not less than 1/4 of the wavelength of light incident on the photodiode.
  2. 　前記第一の被覆絶縁膜の膜厚が、前記フォトダイオードに入射する光の波長の１／２以下の大きさである、請求項１に記載の液晶パネル。 2. The liquid crystal panel according to claim 1, wherein the film thickness of the first covering insulating film is not more than 1/2 of the wavelength of light incident on the photodiode.
  3. 　前記基板において、前記フォトダイオードが形成された側の面に設けられた薄膜トランジスタを更に備えており、
    　前記薄膜トランジスタが、
    　前記基板上に形成されて、チャネル領域とソース領域とドレイン領域とを有するトランジスタ用半導体膜と、
    　前記チャネル領域の導電性を制御するゲート電極と、
    　該ゲート電極と前記トランジスタ用半導体膜との間に設けられたゲート絶縁膜と
    を有しており、
    　前記ゲート絶縁膜が前記第一の被覆絶縁膜である、請求項１又は２に記載の液晶パネル。     The substrate further includes a thin film transistor provided on a surface on which the photodiode is formed,
    The thin film transistor is
    A transistor semiconductor film formed on the substrate and having a channel region, a source region, and a drain region;
    A gate electrode for controlling the conductivity of the channel region;
    A gate insulating film provided between the gate electrode and the transistor semiconductor film;
    The liquid crystal panel according to claim 1, wherein the gate insulating film is the first covering insulating film.
  4. 　前記ゲート絶縁膜上に形成されて、前記ゲート電極を被覆するゲート電極被覆膜を更に備えており、
    　前記ゲート電極被覆膜が前記第二の被覆絶縁膜である、請求項３に記載の液晶パネル。     A gate electrode coating film formed on the gate insulating film and covering the gate electrode;
    The liquid crystal panel according to claim 3, wherein the gate electrode coating film is the second coating insulating film.
PCT/JP2011/077943 2010-12-07 2011-12-02 Liquid crystal panel WO2012077606A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9466938B2 (en) 2012-12-04 2016-10-11 Commissariat A L'energie Atomique Et Aux Energies Alternatives Device for measuring and controlling the wave-front of a coherent light beam

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008158273A (en) * 2006-12-25 2008-07-10 Seiko Epson Corp Electrooptical device
JP2009282361A (en) * 2008-05-23 2009-12-03 Seiko Epson Corp Electrooptical apparatus and electronic device
WO2010047086A1 (en) * 2008-10-23 2010-04-29 シャープ株式会社 Semiconductor device, method for manufacturing same, and display device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008158273A (en) * 2006-12-25 2008-07-10 Seiko Epson Corp Electrooptical device
JP2009282361A (en) * 2008-05-23 2009-12-03 Seiko Epson Corp Electrooptical apparatus and electronic device
WO2010047086A1 (en) * 2008-10-23 2010-04-29 シャープ株式会社 Semiconductor device, method for manufacturing same, and display device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"`Hikari Usumaku Gijutsu Manual enlarged", OPTRONICS, 31 August 1992 (1992-08-31), pages 276 - 283 *
SAISHIN KOGAKU GIJUTSU HANDBOOK, 20 September 2002 (2002-09-20), pages 522 - 531 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9466938B2 (en) 2012-12-04 2016-10-11 Commissariat A L'energie Atomique Et Aux Energies Alternatives Device for measuring and controlling the wave-front of a coherent light beam

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