WO2012075725A9 - 电容器组的谐波保护方法 - Google Patents

电容器组的谐波保护方法 Download PDF

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WO2012075725A9
WO2012075725A9 PCT/CN2011/070796 CN2011070796W WO2012075725A9 WO 2012075725 A9 WO2012075725 A9 WO 2012075725A9 CN 2011070796 W CN2011070796 W CN 2011070796W WO 2012075725 A9 WO2012075725 A9 WO 2012075725A9
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capacitor bank
harmonic
current
cpu unit
capacitor
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PCT/CN2011/070796
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French (fr)
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WO2012075725A1 (zh
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曹良
何昊
虞坚阳
罗皎虹
许箴
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江苏省电力公司常州供电公司
江苏省电力公司
国家电网公司
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Priority to US13/806,752 priority Critical patent/US8810976B2/en
Publication of WO2012075725A1 publication Critical patent/WO2012075725A1/zh
Publication of WO2012075725A9 publication Critical patent/WO2012075725A9/zh

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02HEMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/16Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for capacitors
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02HEMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/08Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current

Definitions

  • the present invention relates to a method of harmonic protection of a power capacitor in a power system. Background technique
  • capacitor protection generally sets differential voltage, differential current, overcurrent protection, and overvoltage and undervoltage protection.
  • these protections only measure the fundamental of voltage and current, do not reflect harmonics, and have no harmonic protection.
  • DFT discrete harmonic Fourier algorithm
  • N is the number of sampling points per fundamental frequency period.
  • n takes different values, the real and imaginary parts of harmonic components of different frequencies can be obtained.
  • the effective value of the "second harmonic" can be obtained. It is generally believed that
  • the current rms calculation formula for the capacitor bank is: In actual operation, it is found that the result of the algorithm is often lower than the actual current effective value, which causes the protection device to fail to act in time to cut off the capacitor bank, thereby expanding the fault. Summary of the invention
  • the technical problem to be solved by the present invention is to provide a harmonic protection method for a capacitor bank suitable for real-time and accurate measurement of the effective value of the actual current on the capacitor bank, so that the protection device can cut off the capacitor bank more accurately and in time.
  • the present invention provides a harmonic protection method for a capacitor bank, which comprises a capacitor unit harmonic protection device comprising: a CPU unit, connected to the CPU unit for current and voltage sampling of the capacitor bank. Current and voltage sampling unit, which is controlled by the CPU unit to cut off the capacitor bank
  • is the power consumption equivalent resistance of the capacitor bank at the fundamental frequency; the specific value of r B is provided by the manufacturer of the capacitor bank or by laboratory test; I is the effective value of the fundamental current on the capacitor bank; 1 fatigue is the effective value of the nth harmonic current on the capacitor bank; when I> 1. 3I N , the CPU unit controls the protection device to cut off the capacitor bank; I N is the rated current of the capacitor bank.
  • the capacitor group harmonic protection device further includes: a relay connected to the CPU unit, the correction page (Article 91) A relay is used to control the circuit breaker and the isolating knife to disconnect the capacitor bank from the bus.
  • the CPU unit includes: an analog-to-digital conversion module; the analog-to-digital conversion module uses a second-order RC passive anti-aliasing low-pass filter and a synchronous sampling A/D converter to form an analog quantity acquisition system.
  • FIG. 1 is a schematic diagram showing the circuit structure of a device for harmonic protection in an embodiment. Concrete
  • a harmonic protection method for a capacitor bank of the present embodiment includes a capacitor unit harmonic protection device including: a CPU unit 20, a communication interface 22 connected to the CPU unit 20, and a CPU unit 20 connected thereto. a current voltage sampling unit 21 for sampling current and voltage of the capacitor bank, a protection device 23 for shutting off the capacitor group controlled by the CPU unit 20 connected to the CPU unit 20, and a circuit breaker for detecting the circuit breaker connected to the CPU unit A switching amount input unit 24 that isolates position information such as a knife gate.
  • the protection device includes a relay connected to the CPU unit for controlling the circuit breaker and the isolating knife to disconnect the capacitor bank from the bus bar.
  • CPU unit 20 includes: analog to digital conversion module, microprocessor module, 10 drive, protection algorithm, fixed value event management, fault recording, Features such as man-machine interface, background communication and USB HOST interface.
  • the module provides a real-time clock and GPS timing input interface as the clock source for the entire device.
  • the analog-to-digital conversion module uses a second-order RC passive anti-aliasing low-pass filter plus a 16-bit, six-channel synchronous sampling A/D converter to form an analog acquisition system.
  • a total of 15 AC acquisition channels are provided.
  • the 13-15th channel acts as a complex recovery channel.
  • the error detection mechanism of the data channel between the A/D chip and the CPU is designed to prevent misjudgment caused by the failure of this part of the data channel.
  • the microprocessor module uses the MPC8247 of Freescale's PowerQuicc II series, with a CPU frequency of up to 400MHz and low power consumption (0.88 at 266 MHz).
  • the MPC8247 features a dual-core architecture: a PowerPC 603e core and a separate Communications Processor Module (CPM).
  • the core (1. 5V) and I/O (3.3V) are powered separately.
  • the 60x BUS for 64-bit data lines and 32-bit address lines supports 64, 32, 16 and 8-bit devices.
  • the invention can not only realize the conventional overcurrent, overvoltage and other protection functions, but also calculate the 2 ⁇ 13th harmonics in the current and voltage in real time, and provide the single harmonic current, the single harmonic voltage, Full current, full voltage and other harmonic protection functions to better protect the capacitor bank.
  • the harmonic protection method of the capacitor bank of the present invention is based on the difference of the resistance of the capacitor and the reactor group under different harmonics, and the formula: D r 2 D * r 2 d is proposed in the case of different harmonics, the reactor work
  • the consumed equivalent resistance exhibits a changing law.
  • This concept is introduced into the capacitor bank harmonic protection device, which is suitable for calculating the power consumption of the capacitor bank or the reactor group under different harmonic components, and according to the "Parallel Capacitor Device Design Specification" (GB50227-1995)
  • the regulation requires that when the sampling current of the protection device exceeds 1.3 times of the rated current, the protection device acts to cut off the capacitor bank or the reactor group.
  • the invention can not only realize the conventional overcurrent, overvoltage and other protection functions, but also calculate the 2 ⁇ 13th harmonics in the current and voltage in real time, and provide the single harmonic current, the single harmonic voltage, Full current, full voltage and other harmonic protection functions to better protect the capacitor bank.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Supply And Distribution Of Alternating Current (AREA)
  • Protection Of Static Devices (AREA)

Abstract

一种电容器组的谐波保护方法,其采用的电容器组谐波保护装置包括:CPU单元(20)、电流电压采样单元(21)和保护装置(23)。CPU单元(20)获取电容器组上的基波电流有效值I1和谐波电流有效值In,然后根据公式(I)计算电容器组上的电流真有效值I。式(I)中,kn为n次谐波系数,n为谐波次数。当I≤1.3IN时,CPU单元(20)控制保护装置(23)切断电容器组,其中IN为电容器组的额定电流。

Description

电容器组的谐波保护方法 技术领域
本发明涉及电力系统中的电力电容器的谐波保护方法。 背景技术
近年来, 随着电力系统的发展和电力电子技术的广泛应用, 用电负荷的结构 发生了重大的变化。 大量的非线性负荷如电弧炉、 电气化铁路、 晶闸管调压及变 频调整装置的运行, 成为电网中主要谐波源, 向电力系统注入大量谐波电流, 导 致电网的电压波形畸变。 谐波对电网中的各种电气设备的正常运行产生了不同程 度的影响, 其中对电容器组的影响尤其严重。 主要表现在以下几个方面: 加大了 电容器组回路的电能损耗; 电容器组回路产生谐振; 谐波电流放大; 缩短电容器 组的使用寿命。
运行经验证明, 电容器组及串联电抗器受电网谐波危害的程度有快速上升的 趋势, 变电所的电容器组及串联电抗器着火事故频繁发生。 目前电容器保护一般 设置差压、 差流、 过电流保护及过压、 欠压等保护, 但这些保护均只测量电压和 电流的基波, 不反应谐波, 没有谐波保护功能。 如何实现谐波测量, 并在谐波危 害较严重时发出告警信号或切断电容器组, 从而实现电容器谐波保护, 以避免电 容器组的损坏, 防止事故蔓延或扩大, 是本领域要解决的技术难题。
电容器谐波保护的关键在于谐波的密集精确采样、 ·快速准确计算。 当前对于 谐波计算通常采用离散傅立叶算法 (DFT ):
x(t)二 ^ (Xp^ cosnwt - XlK sin nwt) 式中 n为第 n次谐波分量的实部, Χ为第 η次谐波分量的虚部。
Figure imgf000003_0001
更正页 (细则第 91条) 式中 N为每基频周期内的采样点数, 当 n取不同的数值, 可求出不同频次谐 波分量的实部和虚部。
Figure imgf000004_0001
根据公式: ,可求得第"次谐波的有效值。 一般认为,
电容器组的电流真有效值计算公式为:
Figure imgf000004_0002
实际运行中发现, 该算法得出的结果往往低于实际的电流有效值, 导致保护 装置不能及时动作以切断电容器组, 进而使故障扩大。 发明内容
本发明所要解决的技术问题是提供一种适于实时、 准确测量电容器组上的实 际电流的有效值的电容器组的谐波保护方法, 以使保护装置能较准确并及时切断 电容器组。
为解决上述技术问题, 本发明提供了一种电容器组的谐波保护方法, 其采用 的电容器组谐波保护装置包括: CPU单元, 与 CPU单元相连的用于对电容器组进行 电流、 电压采样的电流电压采样单元, 由 CPU单元控制的用于切断电容器组的保
CPU单元通过电流电压采样单元获取电容器组上的基波电流有效值 I,和各次 谐波有效值 1„, 其中: n为谐波次数, n的范围为 2〜∞; 然后, 根据如下公式计 算电容器组上的电流真有效值 I:
Figure imgf000004_0003
其中, k„ =r„/r, , 1„为 η次谐波系数, r„为电容器组在 n次谐波下的功耗等 值电阻, !^为电容器组在基波频率下的功耗等值电阻; r B 的具体数值, 由电 容器组的生产厂家提供或通过实验室检测得出; I,为电容器组上的基波电流有效 值; 1„为电容器组上的 n次谐波电流有效值; 当 I> 1. 3IN时, CPU单元控制保护装 置切断电容器组; IN为电容器组的额定电流。
进一步, 所述电容器组谐波保护装置还包括: 与 CPU单元相连的继电器, 该 更正页 (细则第 91条) 继电器用于控制断路器及隔离刀闸, 以将所述电容器组从母线上断开。 进一步, 所述 CPU单元包括: 模数转换模块; 所述模数转换模块采用二阶 RC 无源抗混叠低通滤波和同步采样 A/D转换器构成模拟量采集系统。 附图说明
为了使本发明的内容更容易被清楚的理解, 下面根据的具体实施例并结合附 图, 对本发明作进一步详细的说明, 其中
图 1为实施例中的谐波保护的装置的电路结构示意图。 具体实 »式
见图 1-3, 本实施例的一种电容器组的谐波保护方法, 其采用的电容器组谐 波保护装置包括: CPU单元 20, 与 CPU单 20相连的通讯接口 22、 与 CPU单 20相 连的用于对电容器组进行电流、 电压采样的电流电压采样单元 21, 与 CPU单 20相 连的由 CPU单 20控制的用于切断电容器组的保护装置 23、与 CPU单元相连的用于 检测断路器、隔离刀闸器等位置信息的开关量输入单元 24。保护装置包括:与 CPU 单元相连的继电器, 该继电器用于控制断路器及隔离刀闸, 以将电容器组从母线 上断开。
CPU单元通过电流电压采样单元获取电容器组上的基波电流有效值 I,和各次 谐波有效值 1。, 其中: n为谐波次数, n的范围为 2〜∞; 然后, 根据如下公式计 算电容器组上的电流真有效值 I:
Figure imgf000005_0001
其中, kn =rn/r,, 1„为 η次谐波系数, r„为电容器组在 n次谐波下的功耗等 值电阻, r,为电容器组在基波频率下的功耗等值电阻; I,为电容器组上的基波电流 有效值; 1„为电容器组上的 n次谐波电流有效值; 当 1> 1. 3^时, CPU单元控制 保护装置切断电容器组; IN为电容器组的额定电流。
通过对 66千伏的电抗器的谐波过载试验发现, 在 3次谐波时, 谐波系数 K3的值 就达到了 1. 218347; 在 13次谐波时, 谐波系数 Κ13的值就达到了 3. 15, 可见常规 的含谐波分量的电流真有效值计算误差较大, 应当采用本发明的电容器谐波保护 更正页 (细则第 91条) 的算法, 才能准确测量电容器组上的实际电流的有效值, 以使保护装置能较准确 并及时切断电容器组。 . 谐波
2 3 4 5 6 7 次数 n
kn 1. 06548 1. 16043 1. 28399 1. 425691 1. 57317 1. 73326 谐波
8 9 10 11 12 13 次数 n
k„ 1. 91285 2. 10560 2. 31538 2. 52262 2. 76192 3. 00258 CPU单元 20包括: 模数转换模块、 微处理器模块、 10驱动、 保护算法、 定值 事件管理、 故障录波、 人机界面、 后台通信和 USB HOST接口等功能。 模件提供实 时时钟和 GPS对时输入接口, 作为整个装置的时钟源。
所述模数转换模块采用二阶 RC无源抗混叠低通滤波加 16bit、 6路同步采样 A/D转换器构成模拟量采集系统。 共提供 15路交流采集通道。 在交流采样通道路 数允许情况下, 第 13-15通道作为复采通道。 并设计有 A/D芯片到 CPU间数据通 道的检错机制, 防止因这部分数据通道故障导致的误判。
所述的微处理器模块,采用 Freescale公司的 PowerQuicc II系列的 MPC8247, CPU频率最高达 400MHz, 低功耗 (0. 8 W at 266 MHz)。 MPC8247采用双核结构: 一个 PowerPC 603e核和一个单独的通信处理机模块 (CPM)。 内核 (1. 5V)和 I/O ( 3. 3V) 分开供电。 64位数据线和 32位地址线的 60x BUS支持 64、 32、 16和 8 位的器件。
在此基础上, 本发明不仅可以实现常规的过流, 过压等保护功能, 而且实时 计算电流和电压中的 2〜13次谐波, 全面提供单次谐波电流, 单次谐波电压, 全 电流, 全电压等谐波保护功能, 更好地提供电容器组的保护。
显然, 上述实施案例仅是为清楚地说明本发明所作的举例, 而并非是对本发 明的实施方式的限定。 对于所属领域的普通技术人员来说, 在上述说明的基础上 还可以做出其它不同形式的变化或变动。 这里无需也无法对所有的实施方式予以 穷举。 而这些属于本发明的精神所引伸出的显而易见的变化或变动仍处于本发明 的保护范围之中。 更正页 (细则第 91条) IDIk应用性
本发明的电容器组的谐波保护方法根据不同谐波下, 电容器、 电抗器组阻值 的不同, 以及公式: D r 2 D * r 2 d 提出在不同次谐波的情况下, 电抗器功耗的等值电阻呈现一变化规律。 将此 理念引入至电容器组谐波保护装置中, 其适于在不同次谐波分量的情况下计算电 容器组或电抗器组的功耗, 并根据《并联电容器装置设计规范》(GB50227— 1995) 规定要求确定当保护装置采样电流超过额定电流的 1. 3倍后, 保护装置动作切除 电容器组或电抗器组。 在此基础上, 本发明不仅可以实现常规的过流, 过压等保 护功能, 而且实时计算电流和电压中的 2〜13次谐波, 全面提供单次谐波电流, 单次谐波电压, 全电流, 全电压等谐波保护功能, 更好地提供电容器组的保护。
更正页 (细则第 91条)

Claims

权利要求书
1、一种电容器组的谐波保护方法, 其特征在于: 采用的电容器组谐波保护装 置包括: CPU单元, 与 CPU单元相连的用于对电容器组进行电流、 电压采样的电流 电压采样单元, 由 CPU单元控制的用于切断电容器组的保护装置; CPU单元通过电 流电压采样单元获取电容器组上的基波电流有效值 L和各次谐波有效值 IN,其中: n为谐波次数, n的范围为 2〜∞; 然后, 根据如下公式计算电容器组上的电流真 有效值 I:
Figure imgf000008_0001
其中, k„ =r„/r,, 1^为 n次谐波系数, rn为电容器组在 n次谐波下的功耗等 值电阻, ΙΊ为电容器组在基波频率下的功耗等值电阻; I ,为电容器组上的基波电流 有效值; L为电容器组上的 n次谐波电流有效值;
当 I > 1. 3IN时, CPU单元控制保护装置切断电容器组; IN为电容器组的额定电
2、 根据权利要求 1所述的电容器组的谐波保护方法, 其特征在于: 所述电容 器组谐波保护装置还包括: 与 CPU单元相连的继电器, 该继电器用于控制断路器 及隔离刀闸, 以将所述电容器组从母线上断开。
3、 根据权利要求 2所述的电容器组的谐波保护方法, 其特征在于: 所述 CPU 单元包括: 模数转换模块; 所述模数转换模块采用二阶 RC无源抗混叠低通滤波和 同步采样 A/D转换器构成模拟量采集系统。
更正页 (细则第 91条)
PCT/CN2011/070796 2010-12-10 2011-01-30 电容器组的谐波保护方法 WO2012075725A1 (zh)

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